<feed xmlns='http://www.w3.org/2005/Atom'>
<title>litmus-rt-imx6.git/include/linux/spi, branch master</title>
<subtitle>LITMUS^RT and MC^2 V1 support for the i.MX6 processor family.</subtitle>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt-imx6.git/'/>
<entry>
<title>spi: Provide common spi_message processing loop</title>
<updated>2014-04-16T13:05:55+00:00</updated>
<author>
<name>Mark Brown</name>
<email>broonie@linaro.org</email>
</author>
<published>2013-10-05T10:50:40+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt-imx6.git/commit/?id=85e894237dcdb0557e5cdd1dba5d0cbfe4027d45'/>
<id>85e894237dcdb0557e5cdd1dba5d0cbfe4027d45</id>
<content type='text'>
The loops which SPI controller drivers use to process the list of transfers
in a spi_message are typically very similar and have some error prone areas
such as the handling of /CS. Help simplify drivers by factoring this code
out into the core - if drivers provide a transfer_one() function instead
of a transfer_one_message() function the core will handle processing at the
message level.

/CS can be controlled by either setting cs_gpio or providing a set_cs
function. If this is not possible for hardware reasons then both can be
omitted and the driver should continue to implement manual /CS handling.

This is a first step in refactoring and it is expected that there will be
further enhancements, for example factoring out of the mapping of transfers
for DMA and the initiation and completion of interrupt driven transfers.

Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The loops which SPI controller drivers use to process the list of transfers
in a spi_message are typically very similar and have some error prone areas
such as the handling of /CS. Help simplify drivers by factoring this code
out into the core - if drivers provide a transfer_one() function instead
of a transfer_one_message() function the core will handle processing at the
message level.

/CS can be controlled by either setting cs_gpio or providing a set_cs
function. If this is not possible for hardware reasons then both can be
omitted and the driver should continue to implement manual /CS handling.

This is a first step in refactoring and it is expected that there will be
further enhancements, for example factoring out of the mapping of transfers
for DMA and the initiation and completion of interrupt driven transfers.

Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: Provide per-message prepare and unprepare operations</title>
<updated>2014-04-16T13:05:55+00:00</updated>
<author>
<name>Mark Brown</name>
<email>broonie@linaro.org</email>
</author>
<published>2013-10-04T23:23:12+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt-imx6.git/commit/?id=de6a76d78ecf38eb77079e303c2c1b842737bd96'/>
<id>de6a76d78ecf38eb77079e303c2c1b842737bd96</id>
<content type='text'>
Many SPI drivers perform setup and tear down on every message, usually
doing things like DMA mapping the message. Provide hooks for them to use
to provide such operations.

This is of limited value for drivers that implement transfer_one_message()
but will be of much greater utility with future factoring out of standard
implementations of that function.

Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Many SPI drivers perform setup and tear down on every message, usually
doing things like DMA mapping the message. Provide hooks for them to use
to provide such operations.

This is of limited value for drivers that implement transfer_one_message()
but will be of much greater utility with future factoring out of standard
implementations of that function.

Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: core: Add devm_spi_register_master()</title>
<updated>2014-04-16T13:05:54+00:00</updated>
<author>
<name>Mark Brown</name>
<email>broonie@linaro.org</email>
</author>
<published>2013-08-31T17:50:52+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt-imx6.git/commit/?id=732c1b3904cb71f4347670e0702ddb40beec9f42'/>
<id>732c1b3904cb71f4347670e0702ddb40beec9f42</id>
<content type='text'>
Help simplify the cleanup code for SPI master drivers by providing a
managed master registration function, ensuring that the master is
automatically unregistered whenever the device is unbound.

Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Help simplify the cleanup code for SPI master drivers by providing a
managed master registration function, ensuring that the master is
automatically unregistered whenever the device is unbound.

Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: DUAL and QUAD support</title>
<updated>2014-04-16T13:05:53+00:00</updated>
<author>
<name>wangyuhang</name>
<email>wangyuhang2014@gmail.com</email>
</author>
<published>2013-08-11T10:15:17+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt-imx6.git/commit/?id=8cf27f4979551c626540ec68e6cc219b26440799'/>
<id>8cf27f4979551c626540ec68e6cc219b26440799</id>
<content type='text'>
fix the previous patch some mistake below:
1. DT in slave node, use "spi-tx-nbits = &lt;1/2/4&gt;" in place of using
   "spi-tx-dual, spi-tx-quad" directly, same to rx. So correct the
   previous way to get the property in @of_register_spi_devices().
2. Change the value of transfer bit macro(SPI_NBITS_SINGLE, SPI_NBITS_DUAL
   SPI_NBITS_QUAD) to 0x01, 0x02 and 0x04 to match the actual wires.
3. Add the following check
   (1)keep the tx_nbits and rx_nbits in spi_transfer is not beyond the
      single, dual and quad.
   (2)keep tx_nbits and rx_nbits are contained by @spi_device-&gt;mode
      example: if @spi_device-&gt;mode = DUAL, then tx/rx_nbits can not be set
               to QUAD(SPI_NBITS_QUAD)
   (3)if "@spi_device-&gt;mode &amp; SPI_3WIRE", then tx/rx_nbits should be in
      single(SPI_NBITS_SINGLE)

Signed-off-by: wangyuhang &lt;wangyuhang2014@gmail.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
fix the previous patch some mistake below:
1. DT in slave node, use "spi-tx-nbits = &lt;1/2/4&gt;" in place of using
   "spi-tx-dual, spi-tx-quad" directly, same to rx. So correct the
   previous way to get the property in @of_register_spi_devices().
2. Change the value of transfer bit macro(SPI_NBITS_SINGLE, SPI_NBITS_DUAL
   SPI_NBITS_QUAD) to 0x01, 0x02 and 0x04 to match the actual wires.
3. Add the following check
   (1)keep the tx_nbits and rx_nbits in spi_transfer is not beyond the
      single, dual and quad.
   (2)keep tx_nbits and rx_nbits are contained by @spi_device-&gt;mode
      example: if @spi_device-&gt;mode = DUAL, then tx/rx_nbits can not be set
               to QUAD(SPI_NBITS_QUAD)
   (3)if "@spi_device-&gt;mode &amp; SPI_3WIRE", then tx/rx_nbits should be in
      single(SPI_NBITS_SINGLE)

Signed-off-by: wangyuhang &lt;wangyuhang2014@gmail.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: fix SPI_BIT_MASK so it always fits into 32-bits</title>
<updated>2014-04-16T13:05:53+00:00</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2013-08-01T22:08:57+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt-imx6.git/commit/?id=f72ac71f4cee27e2077d2da79bd46ec631a3db6d'/>
<id>f72ac71f4cee27e2077d2da79bd46ec631a3db6d</id>
<content type='text'>
On a 64-bit platform, ~0UL fills 64-bits, which causes SPI_BIT_MASK(32)
not to fit into 32 bits. This causes a warning when the result is assigned
to a 32-bit variable. Use ~0U instead to prevent this. This fixes:

drivers/spi/spi-gpio.c: In function 'spi_gpio_probe':
drivers/spi/spi-gpio.c:446:2: warning: large integer implicitly truncated to unsigned type [-Woverflow]

Reported-by: kbuild test robot &lt;fengguang.wu@intel.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
On a 64-bit platform, ~0UL fills 64-bits, which causes SPI_BIT_MASK(32)
not to fit into 32 bits. This causes a warning when the result is assigned
to a 32-bit variable. Use ~0U instead to prevent this. This fixes:

drivers/spi/spi-gpio.c: In function 'spi_gpio_probe':
drivers/spi/spi-gpio.c:446:2: warning: large integer implicitly truncated to unsigned type [-Woverflow]

Reported-by: kbuild test robot &lt;fengguang.wu@intel.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: Provide core support for runtime PM during transfers</title>
<updated>2014-04-16T13:05:53+00:00</updated>
<author>
<name>Mark Brown</name>
<email>broonie@linaro.org</email>
</author>
<published>2013-07-28T13:47:02+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt-imx6.git/commit/?id=5a42f567433f9b870f98049b73f5a76d77c97aa0'/>
<id>5a42f567433f9b870f98049b73f5a76d77c97aa0</id>
<content type='text'>
Most SPI drivers that implement runtime PM support use identical code to
do so: they acquire a runtime PM lock in prepare_transfer_hardware() and
then they release it in unprepare_transfer_hardware(). The variations in
this are mostly missing error checking and the choice to use autosuspend.

Since these runtime PM calls are normally the only thing in the prepare
and unprepare callbacks and the autosuspend API transparently does the
right thing on devices with autosuspend disabled factor all of this out
into the core with a flag to enable the behaviour.

Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Reviewed-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Most SPI drivers that implement runtime PM support use identical code to
do so: they acquire a runtime PM lock in prepare_transfer_hardware() and
then they release it in unprepare_transfer_hardware(). The variations in
this are mostly missing error checking and the choice to use autosuspend.

Since these runtime PM calls are normally the only thing in the prepare
and unprepare callbacks and the autosuspend API transparently does the
right thing on devices with autosuspend disabled factor all of this out
into the core with a flag to enable the behaviour.

Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Reviewed-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>driver: spi: Modify core to compute the message length</title>
<updated>2014-04-16T13:05:52+00:00</updated>
<author>
<name>Sourav Poddar</name>
<email>sourav.poddar@ti.com</email>
</author>
<published>2013-07-18T10:01:25+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt-imx6.git/commit/?id=f09cb87e6cab90b9345eb7eb4a91277f6b903969'/>
<id>f09cb87e6cab90b9345eb7eb4a91277f6b903969</id>
<content type='text'>
Make spi core calculate the message length while
populating the other transfer parameters.

Usecase, driver can use it to populate framelength filed in their
controller.

Signed-off-by: Sourav Poddar &lt;sourav.poddar@ti.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Make spi core calculate the message length while
populating the other transfer parameters.

Usecase, driver can use it to populate framelength filed in their
controller.

Signed-off-by: Sourav Poddar &lt;sourav.poddar@ti.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: Support transfer speed checking in the core</title>
<updated>2014-04-16T13:05:52+00:00</updated>
<author>
<name>Mark Brown</name>
<email>broonie@linaro.org</email>
</author>
<published>2013-07-10T13:57:26+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt-imx6.git/commit/?id=c33bf5459e629df19f1ae522662bdf1b86756372'/>
<id>c33bf5459e629df19f1ae522662bdf1b86756372</id>
<content type='text'>
Allow drivers to avoid implementing their own checks for simple rates by
specifying the limits in the master structure.

Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Allow drivers to avoid implementing their own checks for simple rates by
specifying the limits in the master structure.

Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: fix incorrect handling of min param in SPI_BPW_RANGE_MASK</title>
<updated>2014-04-16T13:05:52+00:00</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2013-05-30T15:59:40+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt-imx6.git/commit/?id=c424eddc810dee0030b719e07ef96342c051a562'/>
<id>c424eddc810dee0030b719e07ef96342c051a562</id>
<content type='text'>
SPI_BPW_RANGE_MASK is intended to work by calculating two masks; one
representing support for all bits up-to-and-including the "max" supported
value, and one representing support for all bits up-to-but-not-including
the "min" supported value, and then taking the difference between the
two, resulting in a mask representing support for all bits between
(inclusive) the min and max values.

However, the second mask ended up representing all bits up-to-and-
including rather up-to-but-not-including. Fix this bug.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
SPI_BPW_RANGE_MASK is intended to work by calculating two masks; one
representing support for all bits up-to-and-including the "max" supported
value, and one representing support for all bits up-to-but-not-including
the "min" supported value, and then taking the difference between the
two, resulting in a mask representing support for all bits between
(inclusive) the min and max values.

However, the second mask ended up representing all bits up-to-and-
including rather up-to-but-not-including. Fix this bug.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: fix undefined behaviour in SPI_BPW_RANGE_MASK</title>
<updated>2014-04-16T13:05:52+00:00</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2013-05-30T15:59:39+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt-imx6.git/commit/?id=631ab50c109d2779d5b09d5c20bfcc5e35b65c11'/>
<id>631ab50c109d2779d5b09d5c20bfcc5e35b65c11</id>
<content type='text'>
The parameters to SPI_BPW_RANGE_MASK() are in the range 1..32. If 32 is
used as a parameter, part of the expression is "1 &lt;&lt; 32". Since 32 is &gt;=
the size of the type in use, such a shift is undefined behaviour. Add
macro SPI_BIT_MASK to Implement a special case and thus avoid undefined
behaviour. Use this new macro rather than BIT() when implementing
SPI_BPW_RANGE_MASK().

This fixes build warnings such as:
drivers/spi/spi-gpio.c:446:2: warning: left shift count &gt;= width of type [enabled by default]

SPI_BPW_MASK() already avoids this, since its parameter is also in range
1..32, yet it only shifts by up to one less than the input parameter.

Reported-by: Fengguang Wu &lt;fengguang.wu@intel.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The parameters to SPI_BPW_RANGE_MASK() are in the range 1..32. If 32 is
used as a parameter, part of the expression is "1 &lt;&lt; 32". Since 32 is &gt;=
the size of the type in use, such a shift is undefined behaviour. Add
macro SPI_BIT_MASK to Implement a special case and thus avoid undefined
behaviour. Use this new macro rather than BIT() when implementing
SPI_BPW_RANGE_MASK().

This fixes build warnings such as:
drivers/spi/spi-gpio.c:446:2: warning: left shift count &gt;= width of type [enabled by default]

SPI_BPW_MASK() already avoids this, since its parameter is also in range
1..32, yet it only shifts by up to one less than the input parameter.

Reported-by: Fengguang Wu &lt;fengguang.wu@intel.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Signed-off-by: Huang Shijie &lt;b32955@freescale.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
