From 995d3fdeb2f2d362b1b6bf26656c417452939a1a Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 19 Apr 2016 21:07:01 +0200 Subject: clk: rockchip: reign in some overly long lines in the rk3399 controller We allow overlong lines in the array portitions describing the clock trees to ease readability by having each element always at the same position. But the rest of the code should honor the 80 char limit. Fix the newly added rk3399 clock code to respect that. Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk-rk3399.c | 139 ++++++++++++++++++++++---------------- 1 file changed, 81 insertions(+), 58 deletions(-) (limited to 'drivers/clk/rockchip') diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 356e13256242..e8f040be3fea 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -117,73 +117,96 @@ PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src", "gpll_aclk_cci_src", "npll_aclk_cci_src", "vpll_aclk_cci_src" }; -PNAME(mux_cci_trace_p) = { "cpll_cci_trace", "gpll_cci_trace" }; -PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs", "npll_cs"}; -PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src", "gpll_aclk_perihp_src" }; +PNAME(mux_cci_trace_p) = { "cpll_cci_trace", + "gpll_cci_trace" }; +PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs", + "npll_cs"}; +PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src", + "gpll_aclk_perihp_src" }; PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" }; PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" }; PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" }; PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" }; -PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll", "ppll" }; -PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll", "xin24m" }; -PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll", "clk_usbphy_480m" }; -PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll", "npll", "upll" }; -PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll", "upll", "xin24m" }; -PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" }; +PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll", + "ppll" }; +PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll", + "xin24m" }; +PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll", + "clk_usbphy_480m" }; +PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll", + "npll", "upll" }; +PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll", + "upll", "xin24m" }; +PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", + "ppll", "upll", "xin24m" }; PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" }; -PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll", "npll" }; -PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll", "xin24m" }; - -PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div", "dclk_vop0_frac" }; -PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div", "dclk_vop1_frac" }; - -PNAME(mux_clk_cif_p) = { "clk_cifout_div", "xin24m" }; - -PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" }; -PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" }; -PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k", "cpll", "gpll" }; -PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru", "clk_pcie_core_phy" }; - -PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src", "gpll_aclk_emmc_src" }; - -PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src" }; - -PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src", "gpll_fclk_cm0s_src" }; - -PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src", "gpll_hclk_perilp1_src" }; - -PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" }; -PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" }; - -PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src", "clk_usbphy1_480m_src" }; -PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src", "gpll_aclk_gmac_src" }; -PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" }; -PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac", - "clkin_i2s", "xin12m" }; -PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac", - "clkin_i2s", "xin12m" }; -PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac", - "clkin_i2s", "xin12m" }; -PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac", - "clkin_i2s", "xin12m" }; -PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1", "clk_i2s2" }; -PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" }; - -PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; -PNAME(mux_uart1_p) = { "clk_uart1_div", "clk_uart1_frac", "xin24m" }; -PNAME(mux_uart2_p) = { "clk_uart2_div", "clk_uart2_frac", "xin24m" }; -PNAME(mux_uart3_p) = { "clk_uart3_div", "clk_uart3_frac", "xin24m" }; +PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll", + "npll" }; +PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll", + "xin24m" }; + +PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div", + "dclk_vop0_frac" }; +PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div", + "dclk_vop1_frac" }; + +PNAME(mux_clk_cif_p) = { "clk_cifout_div", "xin24m" }; + +PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" }; +PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" }; +PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k", + "cpll", "gpll" }; +PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru", + "clk_pcie_core_phy" }; + +PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src", + "gpll_aclk_emmc_src" }; + +PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src", + "gpll_aclk_perilp0_src" }; + +PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src", + "gpll_fclk_cm0s_src" }; + +PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src", + "gpll_hclk_perilp1_src" }; + +PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" }; +PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" }; + +PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src", + "clk_usbphy1_480m_src" }; +PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src", + "gpll_aclk_gmac_src" }; +PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" }; +PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac", + "clkin_i2s", "xin12m" }; +PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac", + "clkin_i2s", "xin12m" }; +PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac", + "clkin_i2s", "xin12m" }; +PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac", + "clkin_i2s", "xin12m" }; +PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1", + "clk_i2s2" }; +PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" }; + +PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; +PNAME(mux_uart1_p) = { "clk_uart1_div", "clk_uart1_frac", "xin24m" }; +PNAME(mux_uart2_p) = { "clk_uart2_div", "clk_uart2_frac", "xin24m" }; +PNAME(mux_uart3_p) = { "clk_uart3_div", "clk_uart3_frac", "xin24m" }; /* PMU CRU parents */ -PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" }; -PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" }; -PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" }; -PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" }; -PNAME(mux_uart4_pmu_p) = { "clk_uart4_div", "clk_uart4_frac", "xin24m" }; -PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" }; +PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" }; +PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" }; +PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" }; +PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" }; +PNAME(mux_uart4_pmu_p) = { "clk_uart4_div", "clk_uart4_frac", + "xin24m" }; +PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" }; static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = { [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0), @@ -1530,7 +1553,7 @@ static void __init rk3399_pmu_clk_init(struct device_node *np) ARRAY_SIZE(rk3399_clk_pmu_branches)); rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks, - ARRAY_SIZE(rk3399_pmucru_critical_clocks)); + ARRAY_SIZE(rk3399_pmucru_critical_clocks)); rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0), ROCKCHIP_SOFTRST_HIWORD_MASK); -- cgit v1.2.2 From 2b4e6286484c3eeae2c80063c510166c63d7cb85 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 19 Apr 2016 21:17:55 +0200 Subject: clk: rockchip: drop unnecessary header comment The internal clk header did contain a comment indicating that some of the defined registers were shared over multiple clock controller variants. In recent times, it was simply extended all the time and stopped providing any meaningful information, so drop it and it's overlong line. Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk.h | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/clk/rockchip') diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 880349f6d3d7..4a355bf1d69a 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -34,7 +34,6 @@ struct clk; #define HIWORD_UPDATE(val, mask, shift) \ ((val) << (shift) | (mask) << ((shift) + 16)) -/* register positions shared by RK2928, RK3036, RK3066, RK3188, RK3228, RK3399 */ #define RK2928_PLL_CON(x) ((x) * 0x4) #define RK2928_MODE_CON 0x40 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44) -- cgit v1.2.2 From 03ae1747869437a8e4d0d4e79d4c88c25c6df39c Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 19 Apr 2016 21:29:27 +0200 Subject: clk: rockchip: fix checkpatch warning in core code We seem to have accumulated a bunch of checkpatch warnings, with mainly overlong lines and two unnecessary allocation error messages. Most were introduced with the recent multi-controller-support but some were quite a bit older. Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk-mmc-phase.c | 3 ++- drivers/clk/rockchip/clk.c | 44 ++++++++++++++++++++---------------- drivers/clk/rockchip/clk.h | 2 +- 3 files changed, 27 insertions(+), 22 deletions(-) (limited to 'drivers/clk/rockchip') diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c index e0dc7e83403a..bc856f21f6b2 100644 --- a/drivers/clk/rockchip/clk-mmc-phase.c +++ b/drivers/clk/rockchip/clk-mmc-phase.c @@ -123,7 +123,8 @@ static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees) raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; raw_value |= nineties; - writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), mmc_clock->reg); + writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), + mmc_clock->reg); pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n", clk_hw_get_name(hw), degrees, delay_num, diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 277f9270bf72..f0a8be1553b0 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -42,7 +42,8 @@ * sometimes without one of those components. */ static struct clk *rockchip_clk_register_branch(const char *name, - const char *const *parent_names, u8 num_parents, void __iomem *base, + const char *const *parent_names, u8 num_parents, + void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, @@ -139,9 +140,11 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb, pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n", __func__, event, ndata->old_rate, ndata->new_rate); if (event == PRE_RATE_CHANGE) { - frac->rate_change_idx = frac->mux_ops->get_parent(&frac_mux->hw); + frac->rate_change_idx = + frac->mux_ops->get_parent(&frac_mux->hw); if (frac->rate_change_idx != frac->mux_frac_idx) { - frac->mux_ops->set_parent(&frac_mux->hw, frac->mux_frac_idx); + frac->mux_ops->set_parent(&frac_mux->hw, + frac->mux_frac_idx); frac->rate_change_remuxed = 1; } } else if (event == POST_RATE_CHANGE) { @@ -152,7 +155,8 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb, * reaches the mux itself. */ if (frac->rate_change_remuxed) { - frac->mux_ops->set_parent(&frac_mux->hw, frac->rate_change_idx); + frac->mux_ops->set_parent(&frac_mux->hw, + frac->rate_change_idx); frac->rate_change_remuxed = 0; } } @@ -326,18 +330,12 @@ struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np, int i; ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL); - if (!ctx) { - pr_err("%s: Could not allocate clock provider context\n", - __func__); + if (!ctx) return ERR_PTR(-ENOMEM); - } clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); - if (!clk_table) { - pr_err("%s: Could not allocate clock lookup table\n", - __func__); + if (!clk_table) goto err_free; - } for (i = 0; i < nr_clks; ++i) clk_table[i] = ERR_PTR(-ENOENT); @@ -367,7 +365,8 @@ void __init rockchip_clk_of_add_provider(struct device_node *np, struct regmap *rockchip_clk_get_grf(struct rockchip_clk_provider *ctx) { if (IS_ERR(ctx->grf)) - ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node, "rockchip,grf"); + ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node, + "rockchip,grf"); return ctx->grf; } @@ -427,7 +426,8 @@ void __init rockchip_clk_register_branches( if (list->div_table) clk = clk_register_divider_table(NULL, list->name, list->parent_names[0], - flags, ctx->reg_base + list->muxdiv_offset, + flags, + ctx->reg_base + list->muxdiv_offset, list->div_shift, list->div_width, list->div_flags, list->div_table, &ctx->lock); @@ -441,7 +441,8 @@ void __init rockchip_clk_register_branches( case branch_fraction_divider: clk = rockchip_clk_register_frac_branch(ctx, list->name, list->parent_names, list->num_parents, - ctx->reg_base, list->muxdiv_offset, list->div_flags, + ctx->reg_base, list->muxdiv_offset, + list->div_flags, list->gate_offset, list->gate_shift, list->gate_flags, flags, list->child, &ctx->lock); @@ -457,7 +458,8 @@ void __init rockchip_clk_register_branches( case branch_composite: clk = rockchip_clk_register_branch(list->name, list->parent_names, list->num_parents, - ctx->reg_base, list->muxdiv_offset, list->mux_shift, + ctx->reg_base, list->muxdiv_offset, + list->mux_shift, list->mux_width, list->mux_flags, list->div_shift, list->div_width, list->div_flags, list->div_table, @@ -517,8 +519,8 @@ void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, struct clk *clk; clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents, - reg_data, rates, nrates, ctx->reg_base, - &ctx->lock); + reg_data, rates, nrates, + ctx->reg_base, &ctx->lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s: %ld\n", __func__, name, PTR_ERR(clk)); @@ -560,8 +562,10 @@ static struct notifier_block rockchip_restart_handler = { .priority = 128, }; -void __init rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx, - unsigned int reg, void (*cb)(void)) +void __init +rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx, + unsigned int reg, + void (*cb)(void)) { int ret; diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 4a355bf1d69a..1abb7d05d1c7 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -252,7 +252,7 @@ struct rockchip_cpuclk_rate_table { }; /** - * struct rockchip_cpuclk_reg_data - describes register offsets and masks of the cpuclock + * struct rockchip_cpuclk_reg_data - register offsets and masks of the cpuclock * @core_reg: register offset of the core settings register * @div_core_shift: core divider offset used to divide the pll value * @div_core_mask: core divider mask -- cgit v1.2.2