From 06f3008a6a7454389a82495eb1fc132c2b0710f6 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 2 Dec 2015 22:27:03 +0100 Subject: ARM: orion: move watchdog setup to mach-orion5x The watchdog device node is created in plat-orion/common.c but depends on the bridge address that is platform specific, so as a preparation for orion multiplatform support, we move it out of the common code into orion5x and dove. At the moment, dove does not use the watchdog, so I'm marking the function as __maybe_unused for the moment. The compiler will be able to compile out the device definition this way, and we can easily add it later. Signed-off-by: Arnd Bergmann Acked-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/mach-dove/common.c | 17 +++++++++++++++++ arch/arm/mach-orion5x/common.c | 14 +++++++++++++- arch/arm/plat-orion/common.c | 21 --------------------- arch/arm/plat-orion/include/plat/common.h | 2 -- 4 files changed, 30 insertions(+), 24 deletions(-) diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 0d1a89298ece..25a682fd444f 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -375,6 +375,23 @@ void __init dove_setup_cpu_wins(void) DOVE_SCRATCHPAD_SIZE); } +static struct resource orion_wdt_resource[] = { + DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04), + DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04), +}; + +static struct platform_device orion_wdt_device = { + .name = "orion_wdt", + .id = -1, + .num_resources = ARRAY_SIZE(orion_wdt_resource), + .resource = orion_wdt_resource, +}; + +static void __init __maybe_unused orion_wdt_init(void) +{ + platform_device_register(&orion_wdt_device); +} + void __init dove_init(void) { pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 6bbb7b55c6d1..2b7889e3b7bc 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -184,9 +184,21 @@ static void __init orion5x_crypto_init(void) /***************************************************************************** * Watchdog ****************************************************************************/ +static struct resource orion_wdt_resource[] = { + DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04), + DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04), +}; + +static struct platform_device orion_wdt_device = { + .name = "orion_wdt", + .id = -1, + .num_resources = ARRAY_SIZE(orion_wdt_resource), + .resource = orion_wdt_resource, +}; + static void __init orion5x_wdt_init(void) { - orion_wdt_init(); + platform_device_register(&orion_wdt_device); } diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 8861c367d061..78c8bf4043c0 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -21,7 +21,6 @@ #include #include #include -#include #include /* Create a clkdev entry for a given device/clk */ @@ -588,26 +587,6 @@ void __init orion_spi_1_init(unsigned long mapbase) platform_device_register(&orion_spi_1); } -/***************************************************************************** - * Watchdog - ****************************************************************************/ -static struct resource orion_wdt_resource[] = { - DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04), - DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04), -}; - -static struct platform_device orion_wdt_device = { - .name = "orion_wdt", - .id = -1, - .num_resources = ARRAY_SIZE(orion_wdt_resource), - .resource = orion_wdt_resource, -}; - -void __init orion_wdt_init(void) -{ - platform_device_register(&orion_wdt_device); -} - /***************************************************************************** * XOR ****************************************************************************/ diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index d9a24f605a2b..9e6d76ad48a9 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -75,8 +75,6 @@ void __init orion_spi_init(unsigned long mapbase); void __init orion_spi_1_init(unsigned long mapbase); -void __init orion_wdt_init(void); - void __init orion_xor0_init(unsigned long mapbase_low, unsigned long mapbase_high, unsigned long irq_0, -- cgit v1.2.2 From b8cd337c8e0330f4a29b3d1f69b7c73b324b1f8d Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 2 Dec 2015 22:27:04 +0100 Subject: ARM: orion: always use MULTI_IRQ_HANDLER As a preparation for multiplatform support, this enables the MULTI_IRQ_HANDLER code unconditionally on dove and orion5x, and introduces the respective code on mv78xx0, which did not have it so far. The classic entry-macro.S files are removed as they are now obsolete. Signed-off-by: Arnd Bergmann Acked-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/Kconfig | 3 ++ arch/arm/mach-dove/include/mach/entry-macro.S | 33 ------------------- arch/arm/mach-dove/irq.c | 12 +------ arch/arm/mach-mv78xx0/include/mach/entry-macro.S | 41 ------------------------ arch/arm/mach-mv78xx0/irq.c | 33 +++++++++++++++++++ arch/arm/mach-orion5x/include/mach/entry-macro.S | 25 --------------- arch/arm/mach-orion5x/irq.c | 11 ------- arch/arm/plat-orion/irq.c | 1 - arch/arm/plat-orion/mpp.c | 1 - 9 files changed, 37 insertions(+), 123 deletions(-) delete mode 100644 arch/arm/mach-dove/include/mach/entry-macro.S delete mode 100644 arch/arm/mach-mv78xx0/include/mach/entry-macro.S delete mode 100644 arch/arm/mach-orion5x/include/mach/entry-macro.S diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0365cbbc9179..76f2526f86b9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -510,6 +510,7 @@ config ARCH_DOVE select CPU_PJ4 select GENERIC_CLOCKEVENTS select MIGHT_HAVE_PCI + select MULTI_IRQ_HANDLER select MVEBU_MBUS select PINCTRL select PINCTRL_DOVE @@ -523,6 +524,7 @@ config ARCH_MV78XX0 select CPU_FEROCEON select GENERIC_CLOCKEVENTS select MVEBU_MBUS + select MULTI_IRQ_HANDLER select PCI select PLAT_ORION_LEGACY help @@ -536,6 +538,7 @@ config ARCH_ORION5X select CPU_FEROCEON select GENERIC_CLOCKEVENTS select MVEBU_MBUS + select MULTI_IRQ_HANDLER select PCI select PLAT_ORION_LEGACY select MULTI_IRQ_HANDLER diff --git a/arch/arm/mach-dove/include/mach/entry-macro.S b/arch/arm/mach-dove/include/mach/entry-macro.S deleted file mode 100644 index 72d622baaad3..000000000000 --- a/arch/arm/mach-dove/include/mach/entry-macro.S +++ /dev/null @@ -1,33 +0,0 @@ -/* - * arch/arm/mach-dove/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for Marvell Dove platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include - - .macro get_irqnr_preamble, base, tmp - ldr \base, =IRQ_VIRT_BASE - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - @ check low interrupts - ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF] - ldr \tmp, [\base, #IRQ_MASK_LOW_OFF] - mov \irqnr, #31 - ands \irqstat, \irqstat, \tmp - - @ if no low interrupts set, check high interrupts - ldreq \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF] - ldreq \tmp, [\base, #IRQ_MASK_HIGH_OFF] - moveq \irqnr, #63 - andeqs \irqstat, \irqstat, \tmp - - @ find first active interrupt source - clzne \irqstat, \irqstat - subne \irqnr, \irqnr, \irqstat - .endm diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c index bfb3703357c5..b1c7cae1486b 100644 --- a/arch/arm/mach-dove/irq.c +++ b/arch/arm/mach-dove/irq.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -109,14 +110,6 @@ static int __initdata gpio2_irqs[4] = { 0, }; -#ifdef CONFIG_MULTI_IRQ_HANDLER -/* - * Compiling with both non-DT and DT support enabled, will - * break asm irq handler used by non-DT boards. Therefore, - * we provide a C-style irq handler even for non-DT boards, - * if MULTI_IRQ_HANDLER is set. - */ - static void __iomem *dove_irq_base = IRQ_VIRT_BASE; static asmlinkage void @@ -139,7 +132,6 @@ __exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs) return; } } -#endif void __init dove_init_irq(void) { @@ -148,9 +140,7 @@ void __init dove_init_irq(void) orion_irq_init(1, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); orion_irq_init(33, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); -#ifdef CONFIG_MULTI_IRQ_HANDLER set_handle_irq(dove_legacy_handle_irq); -#endif /* * Initialize gpiolib for GPIOs 0-71. diff --git a/arch/arm/mach-mv78xx0/include/mach/entry-macro.S b/arch/arm/mach-mv78xx0/include/mach/entry-macro.S deleted file mode 100644 index 6b1f088e0597..000000000000 --- a/arch/arm/mach-mv78xx0/include/mach/entry-macro.S +++ /dev/null @@ -1,41 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for Marvell MV78xx0 platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include - - .macro get_irqnr_preamble, base, tmp - ldr \base, =IRQ_VIRT_BASE - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - @ check low interrupts - ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF] - ldr \tmp, [\base, #IRQ_MASK_LOW_OFF] - mov \irqnr, #31 - ands \irqstat, \irqstat, \tmp - bne 1001f - - @ if no low interrupts set, check high interrupts - ldr \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF] - ldr \tmp, [\base, #IRQ_MASK_HIGH_OFF] - mov \irqnr, #63 - ands \irqstat, \irqstat, \tmp - bne 1001f - - @ if no high interrupts set, check error interrupts - ldr \irqstat, [\base, #IRQ_CAUSE_ERR_OFF] - ldr \tmp, [\base, #IRQ_MASK_ERR_OFF] - mov \irqnr, #95 - ands \irqstat, \irqstat, \tmp - - @ find first active interrupt source -1001: clzne \irqstat, \irqstat - subne \irqnr, \irqnr, \irqstat - .endm diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c index 32073444024b..2453c33faccf 100644 --- a/arch/arm/mach-mv78xx0/irq.c +++ b/arch/arm/mach-mv78xx0/irq.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -23,12 +24,44 @@ static int __initdata gpio0_irqs[4] = { IRQ_MV78XX0_GPIO_24_31, }; +static void __iomem *mv78xx0_irq_base = IRQ_VIRT_BASE; + +static asmlinkage void +__exception_irq_entry mv78xx0_legacy_handle_irq(struct pt_regs *regs) +{ + u32 stat; + + stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_LOW_OFF); + stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_LOW_OFF); + if (stat) { + unsigned int hwirq = __fls(stat); + handle_IRQ(hwirq, regs); + return; + } + stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_HIGH_OFF); + stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_HIGH_OFF); + if (stat) { + unsigned int hwirq = 32 + __fls(stat); + handle_IRQ(hwirq, regs); + return; + } + stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_ERR_OFF); + stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_ERR_OFF); + if (stat) { + unsigned int hwirq = 64 + __fls(stat); + handle_IRQ(hwirq, regs); + return; + } +} + void __init mv78xx0_init_irq(void) { orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF); + set_handle_irq(mv78xx0_legacy_handle_irq); + /* * Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask * registers for core #1 are at an offset of 0x18 from those of diff --git a/arch/arm/mach-orion5x/include/mach/entry-macro.S b/arch/arm/mach-orion5x/include/mach/entry-macro.S deleted file mode 100644 index 79eb502a1e64..000000000000 --- a/arch/arm/mach-orion5x/include/mach/entry-macro.S +++ /dev/null @@ -1,25 +0,0 @@ -/* - * arch/arm/mach-orion5x/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for Orion platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include - - .macro get_irqnr_preamble, base, tmp - ldr \base, =MAIN_IRQ_CAUSE - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqstat, [\base, #0] @ main cause - ldr \tmp, [\base, #(MAIN_IRQ_MASK - MAIN_IRQ_CAUSE)] @ main mask - mov \irqnr, #0 @ default irqnr - @ find cause bits that are unmasked - ands \irqstat, \irqstat, \tmp @ clear Z flag if any - clzne \irqnr, \irqstat @ calc irqnr - rsbne \irqnr, \irqnr, #31 - .endm diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index 086ecb87d885..8678db1eb1bd 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c @@ -26,14 +26,6 @@ static int __initdata gpio0_irqs[4] = { IRQ_ORION5X_GPIO_24_31, }; -#ifdef CONFIG_MULTI_IRQ_HANDLER -/* - * Compiling with both non-DT and DT support enabled, will - * break asm irq handler used by non-DT boards. Therefore, - * we provide a C-style irq handler even for non-DT boards, - * if MULTI_IRQ_HANDLER is set. - */ - asmlinkage void __exception_irq_entry orion5x_legacy_handle_irq(struct pt_regs *regs) { @@ -47,15 +39,12 @@ __exception_irq_entry orion5x_legacy_handle_irq(struct pt_regs *regs) return; } } -#endif void __init orion5x_init_irq(void) { orion_irq_init(1, MAIN_IRQ_MASK); -#ifdef CONFIG_MULTI_IRQ_HANDLER set_handle_irq(orion5x_legacy_handle_irq); -#endif /* * Initialize gpiolib for GPIOs 0-31. diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c index 8c1fc06007c0..5b63b28b00ac 100644 --- a/arch/arm/plat-orion/irq.c +++ b/arch/arm/plat-orion/irq.c @@ -18,7 +18,6 @@ #include #include #include -#include void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) { diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c index 7310bcfb299f..5b4ff9373c89 100644 --- a/arch/arm/plat-orion/mpp.c +++ b/arch/arm/plat-orion/mpp.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include -- cgit v1.2.2 From 5cdbe5d23a8a0d7274d628bb9d5ff018d25075ca Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 2 Dec 2015 22:27:05 +0100 Subject: ARM: orion: use SPARSE_IRQ everywhere As a preparation for multiplatform support, this moves all the code using plat-orion over to use sparse irq support, which is enabled implicitly for multiplatform. In particular, the hardcoded NR_IRQS macro gets replaced with a machine specific one that is set in the machine descriptor in order to set up a static mapping for all legacy interrupts. Signed-off-by: Arnd Bergmann Acked-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/Kconfig | 3 +++ arch/arm/mach-dove/cm-a510.c | 1 + arch/arm/mach-dove/dove-db-setup.c | 1 + arch/arm/mach-dove/include/mach/dove.h | 2 ++ arch/arm/mach-dove/include/mach/irqs.h | 2 +- arch/arm/mach-dove/include/mach/pm.h | 2 +- arch/arm/mach-dove/irq.c | 2 +- arch/arm/mach-mv78xx0/buffalo-wxl-setup.c | 1 + arch/arm/mach-mv78xx0/db78x00-bp-setup.c | 1 + arch/arm/mach-mv78xx0/include/mach/irqs.h | 2 +- arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | 2 ++ arch/arm/mach-mv78xx0/rd78x00-masa-setup.c | 1 + arch/arm/mach-orion5x/db88f5281-setup.c | 1 + arch/arm/mach-orion5x/dns323-setup.c | 1 + arch/arm/mach-orion5x/include/mach/irqs.h | 2 +- arch/arm/mach-orion5x/include/mach/orion5x.h | 2 ++ arch/arm/mach-orion5x/kurobox_pro-setup.c | 2 ++ arch/arm/mach-orion5x/ls-chl-setup.c | 1 + arch/arm/mach-orion5x/ls_hgl-setup.c | 1 + arch/arm/mach-orion5x/mv2120-setup.c | 1 + arch/arm/mach-orion5x/net2big-setup.c | 1 + arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c | 1 + arch/arm/mach-orion5x/rd88f5181l-ge-setup.c | 1 + arch/arm/mach-orion5x/rd88f5182-setup.c | 1 + arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c | 1 + arch/arm/mach-orion5x/terastation_pro2-setup.c | 1 + arch/arm/mach-orion5x/ts209-setup.c | 1 + arch/arm/mach-orion5x/ts409-setup.c | 1 + arch/arm/mach-orion5x/ts78xx-setup.c | 1 + arch/arm/mach-orion5x/wnr854t-setup.c | 1 + arch/arm/mach-orion5x/wrt350n-v2-setup.c | 1 + 31 files changed, 37 insertions(+), 5 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 76f2526f86b9..567c83380128 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -515,6 +515,7 @@ config ARCH_DOVE select PINCTRL select PINCTRL_DOVE select PLAT_ORION_LEGACY + select SPARSE_IRQ help Support for the Marvell Dove SoC 88AP510 @@ -527,6 +528,7 @@ config ARCH_MV78XX0 select MULTI_IRQ_HANDLER select PCI select PLAT_ORION_LEGACY + select SPARSE_IRQ help Support for the following Marvell MV78xx0 series SoCs: MV781x0, MV782x0. @@ -542,6 +544,7 @@ config ARCH_ORION5X select PCI select PLAT_ORION_LEGACY select MULTI_IRQ_HANDLER + select SPARSE_IRQ help Support for the following Marvell Orion 5x series SoCs: Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c index 0dc39cf30fdd..b9a7c33db29a 100644 --- a/arch/arm/mach-dove/cm-a510.c +++ b/arch/arm/mach-dove/cm-a510.c @@ -88,6 +88,7 @@ static void __init cm_a510_init(void) MACHINE_START(CM_A510, "Compulab CM-A510 Board") .atag_offset = 0x100, + .nr_irqs = DOVE_NR_IRQS, .init_machine = cm_a510_init, .map_io = dove_map_io, .init_early = dove_init_early, diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c index 76e26f949c27..bcb678fd2415 100644 --- a/arch/arm/mach-dove/dove-db-setup.c +++ b/arch/arm/mach-dove/dove-db-setup.c @@ -94,6 +94,7 @@ static void __init dove_db_init(void) MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board") .atag_offset = 0x100, + .nr_irqs = DOVE_NR_IRQS, .init_machine = dove_db_init, .map_io = dove_map_io, .init_early = dove_init_early, diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h index 0c4b35f4ee5b..00f45458b3ec 100644 --- a/arch/arm/mach-dove/include/mach/dove.h +++ b/arch/arm/mach-dove/include/mach/dove.h @@ -11,6 +11,8 @@ #ifndef __ASM_ARCH_DOVE_H #define __ASM_ARCH_DOVE_H +#include + /* * Marvell Dove address maps. * diff --git a/arch/arm/mach-dove/include/mach/irqs.h b/arch/arm/mach-dove/include/mach/irqs.h index 3f29e6bca058..8ff0fa8b4fcd 100644 --- a/arch/arm/mach-dove/include/mach/irqs.h +++ b/arch/arm/mach-dove/include/mach/irqs.h @@ -90,7 +90,7 @@ #define NR_PMU_IRQS 7 #define IRQ_DOVE_RTC (IRQ_DOVE_PMU_START + 5) -#define NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS) +#define DOVE_NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS) #endif diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h index b47f75038686..9834ba10cd13 100644 --- a/arch/arm/mach-dove/include/mach/pm.h +++ b/arch/arm/mach-dove/include/mach/pm.h @@ -63,7 +63,7 @@ static inline int pmu_to_irq(int pin) static inline int irq_to_pmu(int irq) { - if (IRQ_DOVE_PMU_START <= irq && irq < NR_IRQS) + if (IRQ_DOVE_PMU_START <= irq && irq < DOVE_NR_IRQS) return irq - IRQ_DOVE_PMU_START; return -EINVAL; diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c index b1c7cae1486b..ad785d34c1e7 100644 --- a/arch/arm/mach-dove/irq.c +++ b/arch/arm/mach-dove/irq.c @@ -160,7 +160,7 @@ void __init dove_init_irq(void) writel(0, PMU_INTERRUPT_MASK); writel(0, PMU_INTERRUPT_CAUSE); - for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { + for (i = IRQ_DOVE_PMU_START; i < DOVE_NR_IRQS; i++) { irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); irq_clear_status_flags(i, IRQ_NOREQUEST); diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c index 1f2ef98b37c6..1607fd5e206e 100644 --- a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c +++ b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c @@ -146,6 +146,7 @@ subsys_initcall(wxl_pci_init); MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL") /* Maintainer: Sebastien Requiem */ .atag_offset = 0x100, + .nr_irqs = MV78XX0_NR_IRQS, .init_machine = wxl_init, .map_io = mv78xx0_map_io, .init_early = mv78xx0_init_early, diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c index 4e0f22b30bc8..0c5dd6fceb6b 100644 --- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c +++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c @@ -94,6 +94,7 @@ subsys_initcall(db78x00_pci_init); MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board") /* Maintainer: Lennert Buytenhek */ .atag_offset = 0x100, + .nr_irqs = MV78XX0_NR_IRQS, .init_machine = db78x00_init, .map_io = mv78xx0_map_io, .init_early = mv78xx0_init_early, diff --git a/arch/arm/mach-mv78xx0/include/mach/irqs.h b/arch/arm/mach-mv78xx0/include/mach/irqs.h index fa1d422196c2..ac96bcf3d268 100644 --- a/arch/arm/mach-mv78xx0/include/mach/irqs.h +++ b/arch/arm/mach-mv78xx0/include/mach/irqs.h @@ -88,7 +88,7 @@ #define IRQ_MV78XX0_GPIO_START 96 #define NR_GPIO_IRQS 32 -#define NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS) +#define MV78XX0_NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS) #endif diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index 723748d8ba7d..0972d5f9b46d 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h @@ -12,6 +12,8 @@ #ifndef __ASM_ARCH_MV78XX0_H #define __ASM_ARCH_MV78XX0_H +#include "irqs.h" + /* * Marvell MV78xx0 address maps. * diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c index d2d06f3957f3..a0a3debf8c21 100644 --- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c +++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c @@ -79,6 +79,7 @@ subsys_initcall(rd78x00_pci_init); MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board") /* Maintainer: Lennert Buytenhek */ .atag_offset = 0x100, + .nr_irqs = MV78XX0_NR_IRQS, .init_machine = rd78x00_masa_init, .map_io = mv78xx0_map_io, .init_early = mv78xx0_init_early, diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index dc01c4ffc9a8..698528fee39d 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c @@ -369,6 +369,7 @@ static void __init db88f5281_init(void) MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") /* Maintainer: Tzachi Perelstein */ .atag_offset = 0x100, + .nr_irqs = ORION5X_NR_IRQS, .init_machine = db88f5281_init, .map_io = orion5x_map_io, .init_early = orion5x_init_early, diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index bc279a853075..96a8c50e7223 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -666,6 +666,7 @@ static void __init dns323_init(void) MACHINE_START(DNS323, "D-Link DNS-323") /* Maintainer: Herbert Valerio Riedel */ .atag_offset = 0x100, + .nr_irqs = ORION5X_NR_IRQS, .init_machine = dns323_init, .map_io = orion5x_map_io, .init_early = orion5x_init_early, diff --git a/arch/arm/mach-orion5x/include/mach/irqs.h b/arch/arm/mach-orion5x/include/mach/irqs.h index 2431d9923427..4b8703cd1ccb 100644 --- a/arch/arm/mach-orion5x/include/mach/irqs.h +++ b/arch/arm/mach-orion5x/include/mach/irqs.h @@ -54,7 +54,7 @@ #define IRQ_ORION5X_GPIO_START 33 #define NR_GPIO_IRQS 32 -#define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) +#define ORION5X_NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) #endif diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index b78ff3248868..7be7c2e05465 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h @@ -14,6 +14,8 @@ #ifndef __ASM_ARCH_ORION5X_H #define __ASM_ARCH_ORION5X_H +#include + /***************************************************************************** * Orion Address Maps * diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c index fe6a48a325e8..b1ebb3721638 100644 --- a/arch/arm/mach-orion5x/kurobox_pro-setup.c +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c @@ -383,6 +383,7 @@ static void __init kurobox_pro_init(void) MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") /* Maintainer: Ronen Shitrit */ .atag_offset = 0x100, + .nr_irqs = ORION5X_NR_IRQS, .init_machine = kurobox_pro_init, .map_io = orion5x_map_io, .init_early = orion5x_init_early, @@ -397,6 +398,7 @@ MACHINE_END MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live") /* Maintainer: Byron Bradley */ .atag_offset = 0x100, + .nr_irqs = ORION5X_NR_IRQS, .init_machine = kurobox_pro_init, .map_io = orion5x_map_io, .init_early = orion5x_init_early, diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c index 028ea038d404..cb8720e6d02b 100644 --- a/arch/arm/mach-orion5x/ls-chl-setup.c +++ b/arch/arm/mach-orion5x/ls-chl-setup.c @@ -320,6 +320,7 @@ static void __init lschl_init(void) MACHINE_START(LINKSTATION_LSCHL, "Buffalo Linkstation LiveV3 (LS-CHL)") /* Maintainer: Ash Hughes */ .atag_offset = 0x100, + .nr_irqs = ORION5X_NR_IRQS, .init_machine = lschl_init, .map_io = orion5x_map_io, .init_early = orion5x_init_early, diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c index 32b7129b767d..0ddfa23821ec 100644 --- a/arch/arm/mach-orion5x/ls_hgl-setup.c +++ b/arch/arm/mach-orion5x/ls_hgl-setup.c @@ -267,6 +267,7 @@ static void __init ls_hgl_init(void) MACHINE_START(LINKSTATION_LS_HGL, "Buffalo Linkstation LS-HGL") /* Maintainer: Zhu Qingsen */ .atag_offset = 0x100, + .nr_irqs = ORION5X_NR_IRQS, .init_machine = ls_hgl_init, .map_io = orion5x_map_io, .init_early = orion5x_init_early, diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c index e032f01da49e..11985dc45c47 100644 --- a/arch/arm/mach-orion5x/mv2120-setup.c +++ b/arch/arm/mach-orion5x/mv2120-setup.c @@ -232,6 +232,7 @@ static void __init mv2120_init(void) MACHINE_START(MV2120, "HP Media Vault mv2120") /* Maintainer: Martin Michlmayr */ .atag_offset = 0x100, + .nr_irqs = ORION5X_NR_IRQS, .init_machine = mv2120_init, .map_io = orion5x_map_io, .init_early = orion5x_init_early, diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c index ba73dc7ffb9e..e91abcc2213d 100644 --- a/arch/arm/mach-orion5x/net2big-setup.c +++ b/arch/arm/mach-orion5x/net2big-setup.c @@ -423,6 +423,7 @@ static void __init net2big_init(void) /* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */ MACHINE_START(NET2BIG, "LaCie 2Big Network") .atag_offset = 0x100, + .nr_irqs = ORION5X_NR_IRQS, .init_machine = net2big_init, .map_io = orion5x_map_io, .init_early = orion5x_init_early, diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c index 213b3e143c57..69a6e5b20b0b 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c @@ -169,6 +169,7 @@ subsys_initcall(rd88f5181l_fxo_pci_init); MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design") /* Maintainer: Nicolas Pitre */ .atag_offset = 0x100, + .nr_irqs = ORION5X_NR_IRQS, .init_machine = rd88f5181l_fxo_init, .map_io = orion5x_map_io, .init_early = orion5x_init_early, diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c index 594800e1d691..e19f8b7f87b3 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c @@ -181,6 +181,7 @@ subsys_initcall(rd88f5181l_ge_pci_init); MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design") /* Maintainer: Lennert Buytenhek */ .atag_offset = 0x100, + .nr_irqs = ORION5X_NR_IRQS, .init_machine = rd88f5181l_ge_init, .map_io = orion5x_map_io, .init_early = orion5x_init_early, diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index b576ef5f18a1..180a4f972d3d 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c @@ -281,6 +281,7 @@ static void __init rd88f5182_init(void) MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") /* Maintainer: Ronen Shitrit */ .atag_offset = 0x100, + .nr_irqs = ORION5X_NR_IRQS, .init_machine = rd88f5182_init, .map_io = orion5x_map_io, .init_early = orion5x_init_early, diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c index 78a1e6ab1b9d..cc5bdbe70fa9 100644 --- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c +++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c @@ -119,6 +119,7 @@ subsys_initcall(rd88f6183ap_ge_pci_init); MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design") /* Maintainer: Lennert Buytenhek */ .atag_offset = 0x100, + .nr_irqs = ORION5X_NR_IRQS, .init_machine = rd88f6183ap_ge_init, .map_io = orion5x_map_io, .init_early = orion5x_init_early, diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c index 12086745c9fd..ad2057514deb 100644 --- a/arch/arm/mach-orion5x/terastation_pro2-setup.c +++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c @@ -359,6 +359,7 @@ static void __init tsp2_init(void) MACHINE_START(TERASTATION_PRO2, "Buffalo Terastation Pro II/Live") /* Maintainer: Sylver Bruneau */ .atag_offset = 0x100, + .nr_irqs = ORION5X_NR_IRQS, .init_machine = tsp2_init, .map_io = orion5x_map_io, .init_early = orion5x_init_early, diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index c725b7cb9875..1cfc364c9b1e 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c @@ -324,6 +324,7 @@ static void __init qnap_ts209_init(void) MACHINE_START(TS209, "QNAP TS-109/TS-209") /* Maintainer: Byron Bradley */ .atag_offset = 0x100, + .nr_irqs = ORION5X_NR_IRQS, .init_machine = qnap_ts209_init, .map_io = orion5x_map_io, .init_early = orion5x_init_early, diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c index cf2ab531cabc..bc985cf44625 100644 --- a/arch/arm/mach-orion5x/ts409-setup.c +++ b/arch/arm/mach-orion5x/ts409-setup.c @@ -313,6 +313,7 @@ static void __init qnap_ts409_init(void) MACHINE_START(TS409, "QNAP TS-409") /* Maintainer: Sylver Bruneau */ .atag_offset = 0x100, + .nr_irqs = ORION5X_NR_IRQS, .init_machine = qnap_ts409_init, .map_io = orion5x_map_io, .init_early = orion5x_init_early, diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c index 1b704d35cf5b..5a61a66ce012 100644 --- a/arch/arm/mach-orion5x/ts78xx-setup.c +++ b/arch/arm/mach-orion5x/ts78xx-setup.c @@ -615,6 +615,7 @@ static void __init ts78xx_init(void) MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC") /* Maintainer: Alexander Clouter */ .atag_offset = 0x100, + .nr_irqs = ORION5X_NR_IRQS, .init_machine = ts78xx_init, .map_io = ts78xx_map_io, .init_early = orion5x_init_early, diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c index 80a56ee245b3..bcc6e12dcdac 100644 --- a/arch/arm/mach-orion5x/wnr854t-setup.c +++ b/arch/arm/mach-orion5x/wnr854t-setup.c @@ -174,6 +174,7 @@ subsys_initcall(wnr854t_pci_init); MACHINE_START(WNR854T, "Netgear WNR854T") /* Maintainer: Imre Kaloz */ .atag_offset = 0x100, + .nr_irqs = ORION5X_NR_IRQS, .init_machine = wnr854t_init, .map_io = orion5x_map_io, .init_early = orion5x_init_early, diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c index 670e30dc0d1b..4068d7a3e466 100644 --- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c +++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c @@ -262,6 +262,7 @@ subsys_initcall(wrt350n_v2_pci_init); MACHINE_START(WRT350N_V2, "Linksys WRT350N v2") /* Maintainer: Lennert Buytenhek */ .atag_offset = 0x100, + .nr_irqs = ORION5X_NR_IRQS, .init_machine = wrt350n_v2_init, .map_io = orion5x_map_io, .init_early = orion5x_init_early, -- cgit v1.2.2 From 4c811b99b4de975f6c624efb269ed719e75a3035 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 2 Dec 2015 22:27:06 +0100 Subject: ARM: mv78xx0: clean up mach/*.h headers This is a simple move of all header files that are no longer included by anything else from the include/mach directory to the platform directory itself as preparation for multiplatform support. The mach/uncompress.h headers are left in place for now, and are mildly modified to be independent of the other headers. They will be removed entirely when ARCH_MULTIPLATFORM gets enabled and they become obsolete. Rather than updating the path names inside of the comments of each header, I delete those comments to avoid having to update them again, should they get moved or copied another time. Signed-off-by: Arnd Bergmann Acked-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/mach-mv78xx0/bridge-regs.h | 35 ++++++ arch/arm/mach-mv78xx0/buffalo-wxl-setup.c | 2 +- arch/arm/mach-mv78xx0/common.c | 4 +- arch/arm/mach-mv78xx0/db78x00-bp-setup.c | 2 +- arch/arm/mach-mv78xx0/include/mach/bridge-regs.h | 37 ------- arch/arm/mach-mv78xx0/include/mach/hardware.h | 14 --- arch/arm/mach-mv78xx0/include/mach/irqs.h | 94 ----------------- arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | 129 ----------------------- arch/arm/mach-mv78xx0/include/mach/uncompress.h | 4 +- arch/arm/mach-mv78xx0/irq.c | 2 +- arch/arm/mach-mv78xx0/irqs.h | 92 ++++++++++++++++ arch/arm/mach-mv78xx0/mpp.c | 2 +- arch/arm/mach-mv78xx0/mv78xx0.h | 127 ++++++++++++++++++++++ arch/arm/mach-mv78xx0/pcie.c | 2 +- arch/arm/mach-mv78xx0/rd78x00-masa-setup.c | 2 +- 15 files changed, 263 insertions(+), 285 deletions(-) create mode 100644 arch/arm/mach-mv78xx0/bridge-regs.h delete mode 100644 arch/arm/mach-mv78xx0/include/mach/bridge-regs.h delete mode 100644 arch/arm/mach-mv78xx0/include/mach/hardware.h delete mode 100644 arch/arm/mach-mv78xx0/include/mach/irqs.h delete mode 100644 arch/arm/mach-mv78xx0/include/mach/mv78xx0.h create mode 100644 arch/arm/mach-mv78xx0/irqs.h create mode 100644 arch/arm/mach-mv78xx0/mv78xx0.h diff --git a/arch/arm/mach-mv78xx0/bridge-regs.h b/arch/arm/mach-mv78xx0/bridge-regs.h new file mode 100644 index 000000000000..2f54e1753d45 --- /dev/null +++ b/arch/arm/mach-mv78xx0/bridge-regs.h @@ -0,0 +1,35 @@ +/* + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_BRIDGE_REGS_H +#define __ASM_ARCH_BRIDGE_REGS_H + +#include "mv78xx0.h" + +#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) +#define L2_WRITETHROUGH 0x00020000 + +#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) +#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108) +#define SOFT_RESET_OUT_EN 0x00000004 + +#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) +#define SOFT_RESET 0x00000001 + +#define BRIDGE_INT_TIMER1_CLR (~0x0004) + +#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) +#define IRQ_CAUSE_ERR_OFF 0x0000 +#define IRQ_CAUSE_LOW_OFF 0x0004 +#define IRQ_CAUSE_HIGH_OFF 0x0008 +#define IRQ_MASK_ERR_OFF 0x000c +#define IRQ_MASK_LOW_OFF 0x0010 +#define IRQ_MASK_HIGH_OFF 0x0014 + +#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) +#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) + +#endif diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c index 1607fd5e206e..e112f2e7cc9a 100644 --- a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c +++ b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c @@ -17,9 +17,9 @@ #include #include #include -#include #include #include +#include "mv78xx0.h" #include "common.h" #include "mpp.h" diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index e6ac679bece9..a1a04df9c05c 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -18,13 +18,13 @@ #include #include #include -#include -#include #include #include #include #include #include +#include "mv78xx0.h" +#include "bridge-regs.h" #include "common.h" static int get_tclk(void); diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c index 0c5dd6fceb6b..cf16e08d4cf5 100644 --- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c +++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c @@ -15,9 +15,9 @@ #include #include #include -#include #include #include +#include "mv78xx0.h" #include "common.h" static struct mv643xx_eth_platform_data db78x00_ge00_data = { diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h deleted file mode 100644 index e20d6da234a6..000000000000 --- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/bridge-regs.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_BRIDGE_REGS_H -#define __ASM_ARCH_BRIDGE_REGS_H - -#include - -#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) -#define L2_WRITETHROUGH 0x00020000 - -#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) -#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108) -#define SOFT_RESET_OUT_EN 0x00000004 - -#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) -#define SOFT_RESET 0x00000001 - -#define BRIDGE_INT_TIMER1_CLR (~0x0004) - -#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) -#define IRQ_CAUSE_ERR_OFF 0x0000 -#define IRQ_CAUSE_LOW_OFF 0x0004 -#define IRQ_CAUSE_HIGH_OFF 0x0008 -#define IRQ_MASK_ERR_OFF 0x000c -#define IRQ_MASK_LOW_OFF 0x0010 -#define IRQ_MASK_HIGH_OFF 0x0014 - -#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) -#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) - -#endif diff --git a/arch/arm/mach-mv78xx0/include/mach/hardware.h b/arch/arm/mach-mv78xx0/include/mach/hardware.h deleted file mode 100644 index 67cab0a08e07..000000000000 --- a/arch/arm/mach-mv78xx0/include/mach/hardware.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/hardware.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include "mv78xx0.h" - -#endif diff --git a/arch/arm/mach-mv78xx0/include/mach/irqs.h b/arch/arm/mach-mv78xx0/include/mach/irqs.h deleted file mode 100644 index ac96bcf3d268..000000000000 --- a/arch/arm/mach-mv78xx0/include/mach/irqs.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/irqs.h - * - * IRQ definitions for Marvell MV78xx0 SoCs - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -/* - * MV78xx0 Low Interrupt Controller - */ -#define IRQ_MV78XX0_ERR 0 -#define IRQ_MV78XX0_SPI 1 -#define IRQ_MV78XX0_I2C_0 2 -#define IRQ_MV78XX0_I2C_1 3 -#define IRQ_MV78XX0_IDMA_0 4 -#define IRQ_MV78XX0_IDMA_1 5 -#define IRQ_MV78XX0_IDMA_2 6 -#define IRQ_MV78XX0_IDMA_3 7 -#define IRQ_MV78XX0_TIMER_0 8 -#define IRQ_MV78XX0_TIMER_1 9 -#define IRQ_MV78XX0_TIMER_2 10 -#define IRQ_MV78XX0_TIMER_3 11 -#define IRQ_MV78XX0_UART_0 12 -#define IRQ_MV78XX0_UART_1 13 -#define IRQ_MV78XX0_UART_2 14 -#define IRQ_MV78XX0_UART_3 15 -#define IRQ_MV78XX0_USB_0 16 -#define IRQ_MV78XX0_USB_1 17 -#define IRQ_MV78XX0_USB_2 18 -#define IRQ_MV78XX0_CRYPTO 19 -#define IRQ_MV78XX0_SDIO_0 20 -#define IRQ_MV78XX0_SDIO_1 21 -#define IRQ_MV78XX0_XOR_0 22 -#define IRQ_MV78XX0_XOR_1 23 -#define IRQ_MV78XX0_I2S_0 24 -#define IRQ_MV78XX0_I2S_1 25 -#define IRQ_MV78XX0_SATA 26 -#define IRQ_MV78XX0_TDMI 27 - -/* - * MV78xx0 High Interrupt Controller - */ -#define IRQ_MV78XX0_PCIE_00 32 -#define IRQ_MV78XX0_PCIE_01 33 -#define IRQ_MV78XX0_PCIE_02 34 -#define IRQ_MV78XX0_PCIE_03 35 -#define IRQ_MV78XX0_PCIE_10 36 -#define IRQ_MV78XX0_PCIE_11 37 -#define IRQ_MV78XX0_PCIE_12 38 -#define IRQ_MV78XX0_PCIE_13 39 -#define IRQ_MV78XX0_GE00_SUM 40 -#define IRQ_MV78XX0_GE00_RX 41 -#define IRQ_MV78XX0_GE00_TX 42 -#define IRQ_MV78XX0_GE00_MISC 43 -#define IRQ_MV78XX0_GE01_SUM 44 -#define IRQ_MV78XX0_GE01_RX 45 -#define IRQ_MV78XX0_GE01_TX 46 -#define IRQ_MV78XX0_GE01_MISC 47 -#define IRQ_MV78XX0_GE10_SUM 48 -#define IRQ_MV78XX0_GE10_RX 49 -#define IRQ_MV78XX0_GE10_TX 50 -#define IRQ_MV78XX0_GE10_MISC 51 -#define IRQ_MV78XX0_GE11_SUM 52 -#define IRQ_MV78XX0_GE11_RX 53 -#define IRQ_MV78XX0_GE11_TX 54 -#define IRQ_MV78XX0_GE11_MISC 55 -#define IRQ_MV78XX0_GPIO_0_7 56 -#define IRQ_MV78XX0_GPIO_8_15 57 -#define IRQ_MV78XX0_GPIO_16_23 58 -#define IRQ_MV78XX0_GPIO_24_31 59 -#define IRQ_MV78XX0_DB_IN 60 -#define IRQ_MV78XX0_DB_OUT 61 - -/* - * MV78xx0 Error Interrupt Controller - */ -#define IRQ_MV78XX0_GE_ERR 70 - -/* - * MV78XX0 General Purpose Pins - */ -#define IRQ_MV78XX0_GPIO_START 96 -#define NR_GPIO_IRQS 32 - -#define MV78XX0_NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS) - - -#endif diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h deleted file mode 100644 index 0972d5f9b46d..000000000000 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/mv78xx0.h - * - * Generic definitions for Marvell MV78xx0 SoC flavors: - * MV781x0 and MV782x0. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_MV78XX0_H -#define __ASM_ARCH_MV78XX0_H - -#include "irqs.h" - -/* - * Marvell MV78xx0 address maps. - * - * phys - * c0000000 PCIe Memory space - * f0800000 PCIe #0 I/O space - * f0900000 PCIe #1 I/O space - * f0a00000 PCIe #2 I/O space - * f0b00000 PCIe #3 I/O space - * f0c00000 PCIe #4 I/O space - * f0d00000 PCIe #5 I/O space - * f0e00000 PCIe #6 I/O space - * f0f00000 PCIe #7 I/O space - * f1000000 on-chip peripheral registers - * - * virt phys size - * fe400000 f102x000 16K core-specific peripheral registers - * fee00000 f0800000 64K PCIe #0 I/O space - * fee10000 f0900000 64K PCIe #1 I/O space - * fee20000 f0a00000 64K PCIe #2 I/O space - * fee30000 f0b00000 64K PCIe #3 I/O space - * fee40000 f0c00000 64K PCIe #4 I/O space - * fee50000 f0d00000 64K PCIe #5 I/O space - * fee60000 f0e00000 64K PCIe #6 I/O space - * fee70000 f0f00000 64K PCIe #7 I/O space - * fd000000 f1000000 1M on-chip peripheral registers - */ -#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 -#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 -#define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000) -#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 -#define MV78XX0_CORE_REGS_SIZE SZ_16K - -#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) -#define MV78XX0_PCIE_IO_SIZE SZ_1M - -#define MV78XX0_REGS_PHYS_BASE 0xf1000000 -#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfd000000) -#define MV78XX0_REGS_SIZE SZ_1M - -#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 -#define MV78XX0_PCIE_MEM_SIZE 0x30000000 - -/* - * Core-specific peripheral registers. - */ -#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) -#define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE) -#define BRIDGE_WINS_CPU0_BASE (MV78XX0_CORE0_REGS_PHYS_BASE) -#define BRIDGE_WINS_CPU1_BASE (MV78XX0_CORE1_REGS_PHYS_BASE) -#define BRIDGE_WINS_SZ (0xA000) - -/* - * Register Map - */ -#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000) -#define DDR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x00000) -#define DDR_WINDOW_CPU0_BASE (DDR_PHYS_BASE + 0x1500) -#define DDR_WINDOW_CPU1_BASE (DDR_PHYS_BASE + 0x1570) -#define DDR_WINDOW_CPU_SZ (0x20) - -#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000) -#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000) -#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030) -#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034) -#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100) -#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000) -#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100) -#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000) -#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000) -#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100) -#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100) -#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200) -#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200) -#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300) -#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300) - -#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000) -#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000) - -#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000) -#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000) -#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000) -#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000) - -#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000) -#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000) -#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000) - -#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000) -#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000) - -#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000) -#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000) -#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000) -#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000) - -#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000) - -/* - * Supported devices and revisions. - */ -#define MV78X00_Z0_DEV_ID 0x6381 -#define MV78X00_REV_Z0 1 - -#define MV78100_DEV_ID 0x7810 -#define MV78100_REV_A0 1 -#define MV78100_REV_A1 2 - -#define MV78200_DEV_ID 0x7820 -#define MV78200_REV_A0 1 - -#endif diff --git a/arch/arm/mach-mv78xx0/include/mach/uncompress.h b/arch/arm/mach-mv78xx0/include/mach/uncompress.h index 6a761c44a296..2787ef392262 100644 --- a/arch/arm/mach-mv78xx0/include/mach/uncompress.h +++ b/arch/arm/mach-mv78xx0/include/mach/uncompress.h @@ -1,14 +1,12 @@ /* - * arch/arm/mach-mv78xx0/include/mach/uncompress.h - * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ #include -#include +#define UART0_PHYS_BASE (0xf1000000 + 0x12000) #define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE) static void putc(const char c) diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c index 2453c33faccf..788569e960e1 100644 --- a/arch/arm/mach-mv78xx0/irq.c +++ b/arch/arm/mach-mv78xx0/irq.c @@ -12,9 +12,9 @@ #include #include #include -#include #include #include +#include "bridge-regs.h" #include "common.h" static int __initdata gpio0_irqs[4] = { diff --git a/arch/arm/mach-mv78xx0/irqs.h b/arch/arm/mach-mv78xx0/irqs.h new file mode 100644 index 000000000000..67e0fe730a13 --- /dev/null +++ b/arch/arm/mach-mv78xx0/irqs.h @@ -0,0 +1,92 @@ +/* + * IRQ definitions for Marvell MV78xx0 SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +/* + * MV78xx0 Low Interrupt Controller + */ +#define IRQ_MV78XX0_ERR 0 +#define IRQ_MV78XX0_SPI 1 +#define IRQ_MV78XX0_I2C_0 2 +#define IRQ_MV78XX0_I2C_1 3 +#define IRQ_MV78XX0_IDMA_0 4 +#define IRQ_MV78XX0_IDMA_1 5 +#define IRQ_MV78XX0_IDMA_2 6 +#define IRQ_MV78XX0_IDMA_3 7 +#define IRQ_MV78XX0_TIMER_0 8 +#define IRQ_MV78XX0_TIMER_1 9 +#define IRQ_MV78XX0_TIMER_2 10 +#define IRQ_MV78XX0_TIMER_3 11 +#define IRQ_MV78XX0_UART_0 12 +#define IRQ_MV78XX0_UART_1 13 +#define IRQ_MV78XX0_UART_2 14 +#define IRQ_MV78XX0_UART_3 15 +#define IRQ_MV78XX0_USB_0 16 +#define IRQ_MV78XX0_USB_1 17 +#define IRQ_MV78XX0_USB_2 18 +#define IRQ_MV78XX0_CRYPTO 19 +#define IRQ_MV78XX0_SDIO_0 20 +#define IRQ_MV78XX0_SDIO_1 21 +#define IRQ_MV78XX0_XOR_0 22 +#define IRQ_MV78XX0_XOR_1 23 +#define IRQ_MV78XX0_I2S_0 24 +#define IRQ_MV78XX0_I2S_1 25 +#define IRQ_MV78XX0_SATA 26 +#define IRQ_MV78XX0_TDMI 27 + +/* + * MV78xx0 High Interrupt Controller + */ +#define IRQ_MV78XX0_PCIE_00 32 +#define IRQ_MV78XX0_PCIE_01 33 +#define IRQ_MV78XX0_PCIE_02 34 +#define IRQ_MV78XX0_PCIE_03 35 +#define IRQ_MV78XX0_PCIE_10 36 +#define IRQ_MV78XX0_PCIE_11 37 +#define IRQ_MV78XX0_PCIE_12 38 +#define IRQ_MV78XX0_PCIE_13 39 +#define IRQ_MV78XX0_GE00_SUM 40 +#define IRQ_MV78XX0_GE00_RX 41 +#define IRQ_MV78XX0_GE00_TX 42 +#define IRQ_MV78XX0_GE00_MISC 43 +#define IRQ_MV78XX0_GE01_SUM 44 +#define IRQ_MV78XX0_GE01_RX 45 +#define IRQ_MV78XX0_GE01_TX 46 +#define IRQ_MV78XX0_GE01_MISC 47 +#define IRQ_MV78XX0_GE10_SUM 48 +#define IRQ_MV78XX0_GE10_RX 49 +#define IRQ_MV78XX0_GE10_TX 50 +#define IRQ_MV78XX0_GE10_MISC 51 +#define IRQ_MV78XX0_GE11_SUM 52 +#define IRQ_MV78XX0_GE11_RX 53 +#define IRQ_MV78XX0_GE11_TX 54 +#define IRQ_MV78XX0_GE11_MISC 55 +#define IRQ_MV78XX0_GPIO_0_7 56 +#define IRQ_MV78XX0_GPIO_8_15 57 +#define IRQ_MV78XX0_GPIO_16_23 58 +#define IRQ_MV78XX0_GPIO_24_31 59 +#define IRQ_MV78XX0_DB_IN 60 +#define IRQ_MV78XX0_DB_OUT 61 + +/* + * MV78xx0 Error Interrupt Controller + */ +#define IRQ_MV78XX0_GE_ERR 70 + +/* + * MV78XX0 General Purpose Pins + */ +#define IRQ_MV78XX0_GPIO_START 96 +#define NR_GPIO_IRQS 32 + +#define MV78XX0_NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS) + + +#endif diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c index df50342179e2..72843c02e95a 100644 --- a/arch/arm/mach-mv78xx0/mpp.c +++ b/arch/arm/mach-mv78xx0/mpp.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include "mv78xx0.h" #include "common.h" #include "mpp.h" diff --git a/arch/arm/mach-mv78xx0/mv78xx0.h b/arch/arm/mach-mv78xx0/mv78xx0.h new file mode 100644 index 000000000000..2db1265ec121 --- /dev/null +++ b/arch/arm/mach-mv78xx0/mv78xx0.h @@ -0,0 +1,127 @@ +/* + * Generic definitions for Marvell MV78xx0 SoC flavors: + * MV781x0 and MV782x0. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_MV78XX0_H +#define __ASM_ARCH_MV78XX0_H + +#include "irqs.h" + +/* + * Marvell MV78xx0 address maps. + * + * phys + * c0000000 PCIe Memory space + * f0800000 PCIe #0 I/O space + * f0900000 PCIe #1 I/O space + * f0a00000 PCIe #2 I/O space + * f0b00000 PCIe #3 I/O space + * f0c00000 PCIe #4 I/O space + * f0d00000 PCIe #5 I/O space + * f0e00000 PCIe #6 I/O space + * f0f00000 PCIe #7 I/O space + * f1000000 on-chip peripheral registers + * + * virt phys size + * fe400000 f102x000 16K core-specific peripheral registers + * fee00000 f0800000 64K PCIe #0 I/O space + * fee10000 f0900000 64K PCIe #1 I/O space + * fee20000 f0a00000 64K PCIe #2 I/O space + * fee30000 f0b00000 64K PCIe #3 I/O space + * fee40000 f0c00000 64K PCIe #4 I/O space + * fee50000 f0d00000 64K PCIe #5 I/O space + * fee60000 f0e00000 64K PCIe #6 I/O space + * fee70000 f0f00000 64K PCIe #7 I/O space + * fd000000 f1000000 1M on-chip peripheral registers + */ +#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 +#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 +#define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000) +#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 +#define MV78XX0_CORE_REGS_SIZE SZ_16K + +#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) +#define MV78XX0_PCIE_IO_SIZE SZ_1M + +#define MV78XX0_REGS_PHYS_BASE 0xf1000000 +#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfd000000) +#define MV78XX0_REGS_SIZE SZ_1M + +#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 +#define MV78XX0_PCIE_MEM_SIZE 0x30000000 + +/* + * Core-specific peripheral registers. + */ +#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) +#define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE) +#define BRIDGE_WINS_CPU0_BASE (MV78XX0_CORE0_REGS_PHYS_BASE) +#define BRIDGE_WINS_CPU1_BASE (MV78XX0_CORE1_REGS_PHYS_BASE) +#define BRIDGE_WINS_SZ (0xA000) + +/* + * Register Map + */ +#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000) +#define DDR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x00000) +#define DDR_WINDOW_CPU0_BASE (DDR_PHYS_BASE + 0x1500) +#define DDR_WINDOW_CPU1_BASE (DDR_PHYS_BASE + 0x1570) +#define DDR_WINDOW_CPU_SZ (0x20) + +#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000) +#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000) +#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030) +#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034) +#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100) +#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000) +#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100) +#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000) +#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000) +#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100) +#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100) +#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200) +#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200) +#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300) +#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300) + +#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000) +#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000) + +#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000) +#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000) +#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000) +#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000) + +#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000) +#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000) +#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000) + +#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000) +#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000) + +#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000) +#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000) +#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000) +#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000) + +#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000) + +/* + * Supported devices and revisions. + */ +#define MV78X00_Z0_DEV_ID 0x6381 +#define MV78X00_REV_Z0 1 + +#define MV78100_DEV_ID 0x7810 +#define MV78100_REV_A0 1 +#define MV78100_REV_A1 2 + +#define MV78200_DEV_ID 0x7820 +#define MV78200_REV_A0 1 + +#endif diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index 097ea4cb1136..13a7d72ee0c4 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include "mv78xx0.h" #include "common.h" #define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4) diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c index a0a3debf8c21..308ab71ec822 100644 --- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c +++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c @@ -14,9 +14,9 @@ #include #include #include -#include #include #include +#include "mv78xx0.h" #include "common.h" static struct mv643xx_eth_platform_data rd78x00_masa_ge00_data = { -- cgit v1.2.2 From 43dad399a107ecffdba97454ca4cdf8c7271b228 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 2 Dec 2015 22:27:07 +0100 Subject: ARM: mv78xx0: multiplatform support The mv78xx0 platform is now ready to be enabled for multiplatform support, this patch does the switch over by modifying the Kconfig file, the defconfig and removing the last mach/*.h header that becomes obsolete with this. Signed-off-by: Arnd Bergmann Acked-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/Kconfig | 14 -------- arch/arm/configs/mv78xx0_defconfig | 3 ++ arch/arm/mach-mv78xx0/Kconfig | 15 ++++++--- arch/arm/mach-mv78xx0/Makefile | 2 ++ arch/arm/mach-mv78xx0/include/mach/uncompress.h | 44 ------------------------- 5 files changed, 16 insertions(+), 62 deletions(-) delete mode 100644 arch/arm/mach-mv78xx0/include/mach/uncompress.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 567c83380128..90494e9d8ebb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -519,20 +519,6 @@ config ARCH_DOVE help Support for the Marvell Dove SoC 88AP510 -config ARCH_MV78XX0 - bool "Marvell MV78xx0" - select ARCH_REQUIRE_GPIOLIB - select CPU_FEROCEON - select GENERIC_CLOCKEVENTS - select MVEBU_MBUS - select MULTI_IRQ_HANDLER - select PCI - select PLAT_ORION_LEGACY - select SPARSE_IRQ - help - Support for the following Marvell MV78xx0 series SoCs: - MV781x0, MV782x0. - config ARCH_ORION5X bool "Marvell Orion" depends on MMU diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig index 85d10d2e3d66..fcdffa7d9d78 100644 --- a/arch/arm/configs/mv78xx0_defconfig +++ b/arch/arm/configs/mv78xx0_defconfig @@ -11,6 +11,9 @@ CONFIG_KPROBES=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_MULTI_V5=y +# CONFIG_ARCH_MULTI_V6 is not set +# CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_MV78XX0=y CONFIG_MACH_DB78X00_BP=y CONFIG_MACH_RD78X00_MASA=y diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig index f2d309d0619e..a32575fa3fba 100644 --- a/arch/arm/mach-mv78xx0/Kconfig +++ b/arch/arm/mach-mv78xx0/Kconfig @@ -1,6 +1,15 @@ -if ARCH_MV78XX0 +menuconfig ARCH_MV78XX0 + bool "Marvell MV78xx0" if ARCH_MULTI_V5 + select ARCH_REQUIRE_GPIOLIB + select CPU_FEROCEON + select MVEBU_MBUS + select PCI + select PLAT_ORION_LEGACY + help + Support for the following Marvell MV78xx0 series SoCs: + MV781x0, MV782x0. -menu "Marvell MV78xx0 Implementations" +if ARCH_MV78XX0 config MACH_DB78X00_BP bool "Marvell DB-78x00-BP Development Board" @@ -20,6 +29,4 @@ config MACH_TERASTATION_WXL Say 'Y' here if you want your kernel to support the Buffalo WXL Nas. -endmenu - endif diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile index 7cd04634d302..ddb3aa98a3c7 100644 --- a/arch/arm/mach-mv78xx0/Makefile +++ b/arch/arm/mach-mv78xx0/Makefile @@ -1,3 +1,5 @@ +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-orion/include + obj-y += common.o mpp.o irq.o pcie.o obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o diff --git a/arch/arm/mach-mv78xx0/include/mach/uncompress.h b/arch/arm/mach-mv78xx0/include/mach/uncompress.h deleted file mode 100644 index 2787ef392262..000000000000 --- a/arch/arm/mach-mv78xx0/include/mach/uncompress.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include - -#define UART0_PHYS_BASE (0xf1000000 + 0x12000) -#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE) - -static void putc(const char c) -{ - unsigned char *base = SERIAL_BASE; - int i; - - for (i = 0; i < 0x1000; i++) { - if (base[UART_LSR << 2] & UART_LSR_THRE) - break; - barrier(); - } - - base[UART_TX << 2] = c; -} - -static void flush(void) -{ - unsigned char *base = SERIAL_BASE; - unsigned char mask; - int i; - - mask = UART_LSR_TEMT | UART_LSR_THRE; - - for (i = 0; i < 0x1000; i++) { - if ((base[UART_LSR << 2] & mask) == mask) - break; - barrier(); - } -} - -/* - * nothing to do - */ -#define arch_decomp_setup() -- cgit v1.2.2 From c22c2c6008d69ff2632f8a69c62782468c2bb5a0 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 2 Dec 2015 22:27:08 +0100 Subject: ARM: orion5x: clean up mach/*.h headers This is a simple move of all header files that are no longer included by anything else from the include/mach directory to the platform directory itself as preparation for multiplatform support. The mach/uncompress.h headers are left in place for now, and are mildly modified to be independent of the other headers. They will be removed entirely when ARCH_MULTIPLATFORM gets enabled and they become obsolete. Rather than updating the path names inside of the comments of each header, I delete those comments to avoid having to update them again, should they get moved or copied another time. Signed-off-by: Arnd Bergmann Acked-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/mach-orion5x/board-d2net.c | 2 +- arch/arm/mach-orion5x/board-dt.c | 4 +- arch/arm/mach-orion5x/board-mss2.c | 4 +- arch/arm/mach-orion5x/board-rd88f5182.c | 2 +- arch/arm/mach-orion5x/bridge-regs.h | 35 ++++++ arch/arm/mach-orion5x/common.c | 6 +- arch/arm/mach-orion5x/db88f5281-setup.c | 2 +- arch/arm/mach-orion5x/dns323-setup.c | 2 +- arch/arm/mach-orion5x/include/mach/bridge-regs.h | 37 ------ arch/arm/mach-orion5x/include/mach/hardware.h | 14 --- arch/arm/mach-orion5x/include/mach/irqs.h | 60 --------- arch/arm/mach-orion5x/include/mach/orion5x.h | 148 ----------------------- arch/arm/mach-orion5x/include/mach/uncompress.h | 4 +- arch/arm/mach-orion5x/irq.c | 2 +- arch/arm/mach-orion5x/irqs.h | 58 +++++++++ arch/arm/mach-orion5x/kurobox_pro-setup.c | 2 +- arch/arm/mach-orion5x/ls-chl-setup.c | 2 +- arch/arm/mach-orion5x/ls_hgl-setup.c | 2 +- arch/arm/mach-orion5x/mpp.c | 2 +- arch/arm/mach-orion5x/mv2120-setup.c | 2 +- arch/arm/mach-orion5x/net2big-setup.c | 2 +- arch/arm/mach-orion5x/orion5x.h | 146 ++++++++++++++++++++++ arch/arm/mach-orion5x/pci.c | 2 +- arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c | 2 +- arch/arm/mach-orion5x/rd88f5181l-ge-setup.c | 2 +- arch/arm/mach-orion5x/rd88f5182-setup.c | 2 +- arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c | 2 +- arch/arm/mach-orion5x/terastation_pro2-setup.c | 2 +- arch/arm/mach-orion5x/ts209-setup.c | 2 +- arch/arm/mach-orion5x/ts409-setup.c | 2 +- arch/arm/mach-orion5x/ts78xx-setup.c | 2 +- arch/arm/mach-orion5x/tsx09-common.c | 2 +- arch/arm/mach-orion5x/wnr854t-setup.c | 2 +- arch/arm/mach-orion5x/wrt350n-v2-setup.c | 2 +- 34 files changed, 270 insertions(+), 292 deletions(-) create mode 100644 arch/arm/mach-orion5x/bridge-regs.h delete mode 100644 arch/arm/mach-orion5x/include/mach/bridge-regs.h delete mode 100644 arch/arm/mach-orion5x/include/mach/hardware.h delete mode 100644 arch/arm/mach-orion5x/include/mach/irqs.h delete mode 100644 arch/arm/mach-orion5x/include/mach/orion5x.h create mode 100644 arch/arm/mach-orion5x/irqs.h create mode 100644 arch/arm/mach-orion5x/orion5x.h diff --git a/arch/arm/mach-orion5x/board-d2net.c b/arch/arm/mach-orion5x/board-d2net.c index 8a7284124153..a89376a5cd92 100644 --- a/arch/arm/mach-orion5x/board-d2net.c +++ b/arch/arm/mach-orion5x/board-d2net.c @@ -20,9 +20,9 @@ #include #include #include -#include #include #include "common.h" +#include "orion5x.h" /***************************************************************************** * LaCie d2 Network Info diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c index d0871786dd8a..6f4c2c4ae2a5 100644 --- a/arch/arm/mach-orion5x/board-dt.c +++ b/arch/arm/mach-orion5x/board-dt.c @@ -20,10 +20,10 @@ #include #include #include -#include -#include #include #include +#include "orion5x.h" +#include "bridge-regs.h" #include "common.h" static struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = { diff --git a/arch/arm/mach-orion5x/board-mss2.c b/arch/arm/mach-orion5x/board-mss2.c index 66f9c3ba86cc..79202fd626df 100644 --- a/arch/arm/mach-orion5x/board-mss2.c +++ b/arch/arm/mach-orion5x/board-mss2.c @@ -17,8 +17,8 @@ #include #include #include -#include -#include +#include "orion5x.h" +#include "bridge-regs.h" #include "common.h" /***************************************************************************** diff --git a/arch/arm/mach-orion5x/board-rd88f5182.c b/arch/arm/mach-orion5x/board-rd88f5182.c index 270824b0e50f..b7b0f52f4c0a 100644 --- a/arch/arm/mach-orion5x/board-rd88f5182.c +++ b/arch/arm/mach-orion5x/board-rd88f5182.c @@ -18,8 +18,8 @@ #include #include #include -#include #include "common.h" +#include "orion5x.h" /***************************************************************************** * RD-88F5182 Info diff --git a/arch/arm/mach-orion5x/bridge-regs.h b/arch/arm/mach-orion5x/bridge-regs.h new file mode 100644 index 000000000000..305598eaaee1 --- /dev/null +++ b/arch/arm/mach-orion5x/bridge-regs.h @@ -0,0 +1,35 @@ +/* + * Orion CPU Bridge Registers + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_BRIDGE_REGS_H +#define __ASM_ARCH_BRIDGE_REGS_H + +#include "orion5x.h" + +#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100) + +#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104) + +#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108) +#define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108) + +#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c) + +#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110) + +#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C) + +#define BRIDGE_INT_TIMER1_CLR (~0x0004) + +#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200) + +#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204) + +#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300) +#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300) +#endif diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 2b7889e3b7bc..70c3366c8d03 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -27,14 +27,14 @@ #include #include #include -#include -#include -#include #include #include #include #include + +#include "bridge-regs.h" #include "common.h" +#include "orion5x.h" /***************************************************************************** * I/O Address Mapping diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index 698528fee39d..12f74b46e2ff 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c @@ -23,10 +23,10 @@ #include #include #include -#include #include #include "common.h" #include "mpp.h" +#include "orion5x.h" /***************************************************************************** * DB-88F5281 on board devices diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 96a8c50e7223..cd483bfb5ca8 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -33,8 +33,8 @@ #include #include #include -#include #include +#include "orion5x.h" #include "common.h" #include "mpp.h" diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h deleted file mode 100644 index 5766e3fbff69..000000000000 --- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * arch/arm/mach-orion5x/include/mach/bridge-regs.h - * - * Orion CPU Bridge Registers - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_BRIDGE_REGS_H -#define __ASM_ARCH_BRIDGE_REGS_H - -#include - -#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100) - -#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104) - -#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108) -#define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108) - -#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c) - -#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110) - -#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C) - -#define BRIDGE_INT_TIMER1_CLR (~0x0004) - -#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200) - -#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204) - -#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300) -#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300) -#endif diff --git a/arch/arm/mach-orion5x/include/mach/hardware.h b/arch/arm/mach-orion5x/include/mach/hardware.h deleted file mode 100644 index 395735482473..000000000000 --- a/arch/arm/mach-orion5x/include/mach/hardware.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * arch/arm/mach-orion5x/include/mach/hardware.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include "orion5x.h" - -#endif diff --git a/arch/arm/mach-orion5x/include/mach/irqs.h b/arch/arm/mach-orion5x/include/mach/irqs.h deleted file mode 100644 index 4b8703cd1ccb..000000000000 --- a/arch/arm/mach-orion5x/include/mach/irqs.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * arch/arm/mach-orion5x/include/mach/irqs.h - * - * IRQ definitions for Orion SoC - * - * Maintainer: Tzachi Perelstein - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -/* - * Orion Main Interrupt Controller - */ -#define IRQ_ORION5X_BRIDGE (1 + 0) -#define IRQ_ORION5X_DOORBELL_H2C (1 + 1) -#define IRQ_ORION5X_DOORBELL_C2H (1 + 2) -#define IRQ_ORION5X_UART0 (1 + 3) -#define IRQ_ORION5X_UART1 (1 + 4) -#define IRQ_ORION5X_I2C (1 + 5) -#define IRQ_ORION5X_GPIO_0_7 (1 + 6) -#define IRQ_ORION5X_GPIO_8_15 (1 + 7) -#define IRQ_ORION5X_GPIO_16_23 (1 + 8) -#define IRQ_ORION5X_GPIO_24_31 (1 + 9) -#define IRQ_ORION5X_PCIE0_ERR (1 + 10) -#define IRQ_ORION5X_PCIE0_INT (1 + 11) -#define IRQ_ORION5X_USB1_CTRL (1 + 12) -#define IRQ_ORION5X_DEV_BUS_ERR (1 + 14) -#define IRQ_ORION5X_PCI_ERR (1 + 15) -#define IRQ_ORION5X_USB_BR_ERR (1 + 16) -#define IRQ_ORION5X_USB0_CTRL (1 + 17) -#define IRQ_ORION5X_ETH_RX (1 + 18) -#define IRQ_ORION5X_ETH_TX (1 + 19) -#define IRQ_ORION5X_ETH_MISC (1 + 20) -#define IRQ_ORION5X_ETH_SUM (1 + 21) -#define IRQ_ORION5X_ETH_ERR (1 + 22) -#define IRQ_ORION5X_IDMA_ERR (1 + 23) -#define IRQ_ORION5X_IDMA_0 (1 + 24) -#define IRQ_ORION5X_IDMA_1 (1 + 25) -#define IRQ_ORION5X_IDMA_2 (1 + 26) -#define IRQ_ORION5X_IDMA_3 (1 + 27) -#define IRQ_ORION5X_CESA (1 + 28) -#define IRQ_ORION5X_SATA (1 + 29) -#define IRQ_ORION5X_XOR0 (1 + 30) -#define IRQ_ORION5X_XOR1 (1 + 31) - -/* - * Orion General Purpose Pins - */ -#define IRQ_ORION5X_GPIO_START 33 -#define NR_GPIO_IRQS 32 - -#define ORION5X_NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) - - -#endif diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h deleted file mode 100644 index 7be7c2e05465..000000000000 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * arch/arm/mach-orion5x/include/mach/orion5x.h - * - * Generic definitions of Orion SoC flavors: - * Orion-1, Orion-VoIP, Orion-NAS, Orion-2, and Orion-1-90. - * - * Maintainer: Tzachi Perelstein - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_ORION5X_H -#define __ASM_ARCH_ORION5X_H - -#include - -/***************************************************************************** - * Orion Address Maps - * - * phys - * e0000000 PCIe MEM space - * e8000000 PCI MEM space - * f0000000 PCIe WA space (Orion-1/Orion-NAS only) - * f1000000 on-chip peripheral registers - * f2000000 PCIe I/O space - * f2100000 PCI I/O space - * f2200000 SRAM dedicated for the crypto unit - * f4000000 device bus mappings (boot) - * fa000000 device bus mappings (cs0) - * fa800000 device bus mappings (cs2) - * fc000000 device bus mappings (cs0/cs1) - * - * virt phys size - * fe000000 f1000000 1M on-chip peripheral registers - * fee00000 f2000000 64K PCIe I/O space - * fee10000 f2100000 64K PCI I/O space - * fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) - ****************************************************************************/ -#define ORION5X_REGS_PHYS_BASE 0xf1000000 -#define ORION5X_REGS_VIRT_BASE IOMEM(0xfe000000) -#define ORION5X_REGS_SIZE SZ_1M - -#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 -#define ORION5X_PCIE_IO_BUS_BASE 0x00000000 -#define ORION5X_PCIE_IO_SIZE SZ_64K - -#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 -#define ORION5X_PCI_IO_BUS_BASE 0x00010000 -#define ORION5X_PCI_IO_SIZE SZ_64K - -#define ORION5X_SRAM_PHYS_BASE (0xf2200000) -#define ORION5X_SRAM_SIZE SZ_8K - -/* Relevant only for Orion-1/Orion-NAS */ -#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 -#define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000) -#define ORION5X_PCIE_WA_SIZE SZ_16M - -#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 -#define ORION5X_PCIE_MEM_SIZE SZ_128M - -#define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000 -#define ORION5X_PCI_MEM_SIZE SZ_128M - -/******************************************************************************* - * Orion Registers Map - ******************************************************************************/ - -#define ORION5X_DDR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x00000) -#define ORION5X_DDR_WINS_BASE (ORION5X_DDR_PHYS_BASE + 0x1500) -#define ORION5X_DDR_WINS_SZ (0x10) -#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x00000) -#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x10000) -#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x10000) -#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE + (x)) -#define GPIO_VIRT_BASE ORION5X_DEV_BUS_REG(0x0100) -#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x0600) -#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x1000) -#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2000) -#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2000) -#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2100) -#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2100) - -#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000) -#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x20000) -#define ORION5X_BRIDGE_WINS_BASE (ORION5X_BRIDGE_PHYS_BASE) -#define ORION5X_BRIDGE_WINS_SZ (0x80) - -#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x30000) - -#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x40000) - -#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x50000) -#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x50000) - -#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x60900) -#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x60900) - -#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x70000) -#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x70000) - -#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x80000) -#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x80000) - -#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x90000) - -#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0xa0000) -#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0xa0000) - -/******************************************************************************* - * Device Bus Registers - ******************************************************************************/ -#define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000) -#define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004) -#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050) -#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008) -#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010) -#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c) -#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460) -#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464) -#define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c) -#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0) -#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) -#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) - -/******************************************************************************* - * Supported Devices & Revisions - ******************************************************************************/ -/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ -#define MV88F5181_DEV_ID 0x5181 -#define MV88F5181_REV_B1 3 -#define MV88F5181L_REV_A0 8 -#define MV88F5181L_REV_A1 9 -/* Orion-NAS (88F5182) */ -#define MV88F5182_DEV_ID 0x5182 -#define MV88F5182_REV_A2 2 -/* Orion-2 (88F5281) */ -#define MV88F5281_DEV_ID 0x5281 -#define MV88F5281_REV_D0 4 -#define MV88F5281_REV_D1 5 -#define MV88F5281_REV_D2 6 -/* Orion-1-90 (88F6183) */ -#define MV88F6183_DEV_ID 0x6183 -#define MV88F6183_REV_B0 3 - -#endif diff --git a/arch/arm/mach-orion5x/include/mach/uncompress.h b/arch/arm/mach-orion5x/include/mach/uncompress.h index abd26b542c3c..25e5cb98fecc 100644 --- a/arch/arm/mach-orion5x/include/mach/uncompress.h +++ b/arch/arm/mach-orion5x/include/mach/uncompress.h @@ -1,6 +1,4 @@ /* - * arch/arm/mach-orion5x/include/mach/uncompress.h - * * Tzachi Perelstein * * This file is licensed under the terms of the GNU General Public @@ -9,8 +7,8 @@ */ #include -#include +#define UART0_PHYS_BASE (0xf1000000 + 0x12000) #define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE) static void putc(const char c) diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index 8678db1eb1bd..de980ef9cda1 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c @@ -13,10 +13,10 @@ #include #include #include -#include #include #include #include +#include "bridge-regs.h" #include "common.h" static int __initdata gpio0_irqs[4] = { diff --git a/arch/arm/mach-orion5x/irqs.h b/arch/arm/mach-orion5x/irqs.h new file mode 100644 index 000000000000..506c8e0b30c4 --- /dev/null +++ b/arch/arm/mach-orion5x/irqs.h @@ -0,0 +1,58 @@ +/* + * IRQ definitions for Orion SoC + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +/* + * Orion Main Interrupt Controller + */ +#define IRQ_ORION5X_BRIDGE (1 + 0) +#define IRQ_ORION5X_DOORBELL_H2C (1 + 1) +#define IRQ_ORION5X_DOORBELL_C2H (1 + 2) +#define IRQ_ORION5X_UART0 (1 + 3) +#define IRQ_ORION5X_UART1 (1 + 4) +#define IRQ_ORION5X_I2C (1 + 5) +#define IRQ_ORION5X_GPIO_0_7 (1 + 6) +#define IRQ_ORION5X_GPIO_8_15 (1 + 7) +#define IRQ_ORION5X_GPIO_16_23 (1 + 8) +#define IRQ_ORION5X_GPIO_24_31 (1 + 9) +#define IRQ_ORION5X_PCIE0_ERR (1 + 10) +#define IRQ_ORION5X_PCIE0_INT (1 + 11) +#define IRQ_ORION5X_USB1_CTRL (1 + 12) +#define IRQ_ORION5X_DEV_BUS_ERR (1 + 14) +#define IRQ_ORION5X_PCI_ERR (1 + 15) +#define IRQ_ORION5X_USB_BR_ERR (1 + 16) +#define IRQ_ORION5X_USB0_CTRL (1 + 17) +#define IRQ_ORION5X_ETH_RX (1 + 18) +#define IRQ_ORION5X_ETH_TX (1 + 19) +#define IRQ_ORION5X_ETH_MISC (1 + 20) +#define IRQ_ORION5X_ETH_SUM (1 + 21) +#define IRQ_ORION5X_ETH_ERR (1 + 22) +#define IRQ_ORION5X_IDMA_ERR (1 + 23) +#define IRQ_ORION5X_IDMA_0 (1 + 24) +#define IRQ_ORION5X_IDMA_1 (1 + 25) +#define IRQ_ORION5X_IDMA_2 (1 + 26) +#define IRQ_ORION5X_IDMA_3 (1 + 27) +#define IRQ_ORION5X_CESA (1 + 28) +#define IRQ_ORION5X_SATA (1 + 29) +#define IRQ_ORION5X_XOR0 (1 + 30) +#define IRQ_ORION5X_XOR1 (1 + 31) + +/* + * Orion General Purpose Pins + */ +#define IRQ_ORION5X_GPIO_START 33 +#define NR_GPIO_IRQS 32 + +#define ORION5X_NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) + + +#endif diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c index b1ebb3721638..9dc3f59bed9c 100644 --- a/arch/arm/mach-orion5x/kurobox_pro-setup.c +++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c @@ -23,10 +23,10 @@ #include #include #include -#include #include #include "common.h" #include "mpp.h" +#include "orion5x.h" /***************************************************************************** * KUROBOX-PRO Info diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c index cb8720e6d02b..dfdaa8a498a4 100644 --- a/arch/arm/mach-orion5x/ls-chl-setup.c +++ b/arch/arm/mach-orion5x/ls-chl-setup.c @@ -22,9 +22,9 @@ #include #include #include -#include #include "common.h" #include "mpp.h" +#include "orion5x.h" /***************************************************************************** * Linkstation LS-CHL Info diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c index 0ddfa23821ec..47ba6e0502f5 100644 --- a/arch/arm/mach-orion5x/ls_hgl-setup.c +++ b/arch/arm/mach-orion5x/ls_hgl-setup.c @@ -21,9 +21,9 @@ #include #include #include -#include #include "common.h" #include "mpp.h" +#include "orion5x.h" /***************************************************************************** * Linkstation LS-HGL Info diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c index 5b70026f478c..19ef18594415 100644 --- a/arch/arm/mach-orion5x/mpp.c +++ b/arch/arm/mach-orion5x/mpp.c @@ -11,8 +11,8 @@ #include #include #include -#include #include +#include "orion5x.h" #include "mpp.h" #include "common.h" diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c index 11985dc45c47..2bf8ec75e908 100644 --- a/arch/arm/mach-orion5x/mv2120-setup.c +++ b/arch/arm/mach-orion5x/mv2120-setup.c @@ -21,9 +21,9 @@ #include #include #include -#include #include "common.h" #include "mpp.h" +#include "orion5x.h" #define MV2120_NOR_BOOT_BASE 0xf4000000 #define MV2120_NOR_BOOT_SIZE SZ_512K diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c index e91abcc2213d..bf6be4cfd238 100644 --- a/arch/arm/mach-orion5x/net2big-setup.c +++ b/arch/arm/mach-orion5x/net2big-setup.c @@ -24,10 +24,10 @@ #include #include #include -#include #include #include "common.h" #include "mpp.h" +#include "orion5x.h" /***************************************************************************** * LaCie 2Big Network Info diff --git a/arch/arm/mach-orion5x/orion5x.h b/arch/arm/mach-orion5x/orion5x.h new file mode 100644 index 000000000000..3364df331f01 --- /dev/null +++ b/arch/arm/mach-orion5x/orion5x.h @@ -0,0 +1,146 @@ +/* + * Generic definitions of Orion SoC flavors: + * Orion-1, Orion-VoIP, Orion-NAS, Orion-2, and Orion-1-90. + * + * Maintainer: Tzachi Perelstein + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_ORION5X_H +#define __ASM_ARCH_ORION5X_H + +#include "irqs.h" + +/***************************************************************************** + * Orion Address Maps + * + * phys + * e0000000 PCIe MEM space + * e8000000 PCI MEM space + * f0000000 PCIe WA space (Orion-1/Orion-NAS only) + * f1000000 on-chip peripheral registers + * f2000000 PCIe I/O space + * f2100000 PCI I/O space + * f2200000 SRAM dedicated for the crypto unit + * f4000000 device bus mappings (boot) + * fa000000 device bus mappings (cs0) + * fa800000 device bus mappings (cs2) + * fc000000 device bus mappings (cs0/cs1) + * + * virt phys size + * fe000000 f1000000 1M on-chip peripheral registers + * fee00000 f2000000 64K PCIe I/O space + * fee10000 f2100000 64K PCI I/O space + * fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) + ****************************************************************************/ +#define ORION5X_REGS_PHYS_BASE 0xf1000000 +#define ORION5X_REGS_VIRT_BASE IOMEM(0xfe000000) +#define ORION5X_REGS_SIZE SZ_1M + +#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 +#define ORION5X_PCIE_IO_BUS_BASE 0x00000000 +#define ORION5X_PCIE_IO_SIZE SZ_64K + +#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 +#define ORION5X_PCI_IO_BUS_BASE 0x00010000 +#define ORION5X_PCI_IO_SIZE SZ_64K + +#define ORION5X_SRAM_PHYS_BASE (0xf2200000) +#define ORION5X_SRAM_SIZE SZ_8K + +/* Relevant only for Orion-1/Orion-NAS */ +#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 +#define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000) +#define ORION5X_PCIE_WA_SIZE SZ_16M + +#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 +#define ORION5X_PCIE_MEM_SIZE SZ_128M + +#define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000 +#define ORION5X_PCI_MEM_SIZE SZ_128M + +/******************************************************************************* + * Orion Registers Map + ******************************************************************************/ + +#define ORION5X_DDR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x00000) +#define ORION5X_DDR_WINS_BASE (ORION5X_DDR_PHYS_BASE + 0x1500) +#define ORION5X_DDR_WINS_SZ (0x10) +#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x00000) +#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x10000) +#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x10000) +#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE + (x)) +#define GPIO_VIRT_BASE ORION5X_DEV_BUS_REG(0x0100) +#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x0600) +#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x1000) +#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2000) +#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2000) +#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2100) +#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2100) + +#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000) +#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x20000) +#define ORION5X_BRIDGE_WINS_BASE (ORION5X_BRIDGE_PHYS_BASE) +#define ORION5X_BRIDGE_WINS_SZ (0x80) + +#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x30000) + +#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x40000) + +#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x50000) +#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x50000) + +#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x60900) +#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x60900) + +#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x70000) +#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x70000) + +#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x80000) +#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x80000) + +#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x90000) + +#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0xa0000) +#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0xa0000) + +/******************************************************************************* + * Device Bus Registers + ******************************************************************************/ +#define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000) +#define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004) +#define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050) +#define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008) +#define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010) +#define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c) +#define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460) +#define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464) +#define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c) +#define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0) +#define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) +#define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) + +/******************************************************************************* + * Supported Devices & Revisions + ******************************************************************************/ +/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ +#define MV88F5181_DEV_ID 0x5181 +#define MV88F5181_REV_B1 3 +#define MV88F5181L_REV_A0 8 +#define MV88F5181L_REV_A1 9 +/* Orion-NAS (88F5182) */ +#define MV88F5182_DEV_ID 0x5182 +#define MV88F5182_REV_A2 2 +/* Orion-2 (88F5281) */ +#define MV88F5281_DEV_ID 0x5281 +#define MV88F5281_REV_D0 4 +#define MV88F5281_REV_D1 5 +#define MV88F5281_REV_D2 6 +/* Orion-1-90 (88F6183) */ +#define MV88F6183_DEV_ID 0x6183 +#define MV88F6183_REV_B0 3 + +#endif diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index b02f3947be51..ecb998e7f8dc 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -19,8 +19,8 @@ #include #include #include -#include #include "common.h" +#include "orion5x.h" /***************************************************************************** * Orion has one PCIe controller and one PCI controller. diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c index 69a6e5b20b0b..c742e7b40b0d 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c @@ -20,9 +20,9 @@ #include #include #include -#include #include "common.h" #include "mpp.h" +#include "orion5x.h" /***************************************************************************** * RD-88F5181L FXO Info diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c index e19f8b7f87b3..7e977b794b0c 100644 --- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c +++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c @@ -21,9 +21,9 @@ #include #include #include -#include #include "common.h" #include "mpp.h" +#include "orion5x.h" /***************************************************************************** * RD-88F5181L GE Info diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index 180a4f972d3d..fe3e67c81fb8 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c @@ -23,9 +23,9 @@ #include #include #include -#include #include "common.h" #include "mpp.h" +#include "orion5x.h" /***************************************************************************** * RD-88F5182 Info diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c index cc5bdbe70fa9..4bf80dd5478c 100644 --- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c +++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c @@ -22,8 +22,8 @@ #include #include #include -#include #include "common.h" +#include "orion5x.h" static struct mv643xx_eth_platform_data rd88f6183ap_ge_eth_data = { .phy_addr = -1, diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c index ad2057514deb..deb5e29ac669 100644 --- a/arch/arm/mach-orion5x/terastation_pro2-setup.c +++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c @@ -22,9 +22,9 @@ #include #include #include -#include #include "common.h" #include "mpp.h" +#include "orion5x.h" /***************************************************************************** * Terastation Pro 2/Live Info diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index 1cfc364c9b1e..7bd671b2854c 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c @@ -25,9 +25,9 @@ #include #include #include -#include #include "common.h" #include "mpp.h" +#include "orion5x.h" #include "tsx09-common.h" #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000 diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c index bc985cf44625..a77613b14db5 100644 --- a/arch/arm/mach-orion5x/ts409-setup.c +++ b/arch/arm/mach-orion5x/ts409-setup.c @@ -27,9 +27,9 @@ #include #include #include -#include #include "common.h" #include "mpp.h" +#include "orion5x.h" #include "tsx09-common.h" /***************************************************************************** diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c index 5a61a66ce012..b67ace446576 100644 --- a/arch/arm/mach-orion5x/ts78xx-setup.c +++ b/arch/arm/mach-orion5x/ts78xx-setup.c @@ -23,9 +23,9 @@ #include #include #include -#include #include "common.h" #include "mpp.h" +#include "orion5x.h" #include "ts78xx-fpga.h" /***************************************************************************** diff --git a/arch/arm/mach-orion5x/tsx09-common.c b/arch/arm/mach-orion5x/tsx09-common.c index d42e006597c7..89774985d380 100644 --- a/arch/arm/mach-orion5x/tsx09-common.c +++ b/arch/arm/mach-orion5x/tsx09-common.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include "orion5x.h" #include "tsx09-common.h" #include "common.h" diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c index bcc6e12dcdac..4e1e5c8f6111 100644 --- a/arch/arm/mach-orion5x/wnr854t-setup.c +++ b/arch/arm/mach-orion5x/wnr854t-setup.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include "orion5x.h" #include "common.h" #include "mpp.h" diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c index 4068d7a3e466..61e9027ef224 100644 --- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c +++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include "orion5x.h" #include "common.h" #include "mpp.h" -- cgit v1.2.2 From 63cddd25fa02dbba294fb09f78ea24d7a9f1c7d9 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 2 Dec 2015 22:27:09 +0100 Subject: ARM: orion5x: multiplatform support The orion5x platform is now ready to be enabled for multiplatform support, this patch does the switch over by modifying the Kconfig file, the defconfig and removing the last mach/*.h header that becomes obsolete with this. Signed-off-by: Arnd Bergmann Acked-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/Kconfig | 17 --------- arch/arm/configs/orion5x_defconfig | 3 ++ arch/arm/mach-orion5x/Kconfig | 18 +++++++--- arch/arm/mach-orion5x/Makefile | 2 ++ arch/arm/mach-orion5x/include/mach/uncompress.h | 46 ------------------------- 5 files changed, 19 insertions(+), 67 deletions(-) delete mode 100644 arch/arm/mach-orion5x/include/mach/uncompress.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 90494e9d8ebb..473c1417968a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -519,23 +519,6 @@ config ARCH_DOVE help Support for the Marvell Dove SoC 88AP510 -config ARCH_ORION5X - bool "Marvell Orion" - depends on MMU - select ARCH_REQUIRE_GPIOLIB - select CPU_FEROCEON - select GENERIC_CLOCKEVENTS - select MVEBU_MBUS - select MULTI_IRQ_HANDLER - select PCI - select PLAT_ORION_LEGACY - select MULTI_IRQ_HANDLER - select SPARSE_IRQ - help - Support for the following Marvell Orion 5x series SoCs: - Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), - Orion-2 (5281), Orion-1-90 (6183). - config ARCH_MMP bool "Marvell PXA168/910/MMP2" depends on MMU diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig index 8099417a9466..6ddca8875cb5 100644 --- a/arch/arm/configs/orion5x_defconfig +++ b/arch/arm/configs/orion5x_defconfig @@ -13,6 +13,9 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y CONFIG_BSD_DISKLABEL=y +CONFIG_ARCH_MULTI_V5=y +# CONFIG_ARCH_MULTI_V6 is not set +# CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_ORION5X=y CONFIG_ARCH_ORION5X_DT=y CONFIG_MACH_DB88F5281=y diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 66f1c952c048..a9ad95f000a1 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -1,6 +1,18 @@ -if ARCH_ORION5X +menuconfig ARCH_ORION5X + bool "Marvell Orion" + depends on MMU && ARCH_MULTI_V5 + select ARCH_REQUIRE_GPIOLIB + select CPU_FEROCEON + select GENERIC_CLOCKEVENTS + select MVEBU_MBUS + select PCI + select PLAT_ORION_LEGACY + help + Support for the following Marvell Orion 5x series SoCs: + Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), + Orion-2 (5281), Orion-1-90 (6183). -menu "Orion Implementations" +if ARCH_ORION5X config ARCH_ORION5X_DT bool "Marvell Orion5x Flattened Device Tree" @@ -163,6 +175,4 @@ config MACH_RD88F6183AP_GE Say 'Y' here if you want your kernel to support the Marvell Orion-1-90 (88F6183) AP GE RD. -endmenu - endif diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index a1e0fbe6a7a1..4b2502b4ca0d 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -1,3 +1,5 @@ +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-orion/include + obj-y += common.o pci.o irq.o mpp.o obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o diff --git a/arch/arm/mach-orion5x/include/mach/uncompress.h b/arch/arm/mach-orion5x/include/mach/uncompress.h deleted file mode 100644 index 25e5cb98fecc..000000000000 --- a/arch/arm/mach-orion5x/include/mach/uncompress.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Tzachi Perelstein - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include - -#define UART0_PHYS_BASE (0xf1000000 + 0x12000) -#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE) - -static void putc(const char c) -{ - unsigned char *base = SERIAL_BASE; - int i; - - for (i = 0; i < 0x1000; i++) { - if (base[UART_LSR << 2] & UART_LSR_THRE) - break; - barrier(); - } - - base[UART_TX << 2] = c; -} - -static void flush(void) -{ - unsigned char *base = SERIAL_BASE; - unsigned char mask; - int i; - - mask = UART_LSR_TEMT | UART_LSR_THRE; - - for (i = 0; i < 0x1000; i++) { - if ((base[UART_LSR << 2] & mask) == mask) - break; - barrier(); - } -} - -/* - * nothing to do - */ -#define arch_decomp_setup() -- cgit v1.2.2 From 67098119abeb596823ed0a74dd8cdcfbee4c2210 Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 8 Dec 2015 10:43:28 +0000 Subject: soc: dove: add legacy support to PMU driver Add support for legacy non-DT Dove to the PMU driver, so that we can transition the legacy support over. [gregory.clement@free-electrons.com: removed pm_genpd_poweroff_unused] Acked-by: Arnd Bergmann Signed-off-by: Russell King Signed-off-by: Gregory CLEMENT --- drivers/soc/Makefile | 1 + drivers/soc/dove/pmu.c | 43 +++++++++++++++++++++++++++++++++++++++++++ include/linux/soc/dove/pmu.h | 19 +++++++++++++++++++ 3 files changed, 63 insertions(+) diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index f2ba2e932ae1..d52872680f86 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_SOC_BRCMSTB) += brcmstb/ +obj-$(CONFIG_ARCH_DOVE) += dove/ obj-$(CONFIG_MACH_DOVE) += dove/ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ obj-$(CONFIG_ARCH_QCOM) += qcom/ diff --git a/drivers/soc/dove/pmu.c b/drivers/soc/dove/pmu.c index abd087917f80..039374e9fdc0 100644 --- a/drivers/soc/dove/pmu.c +++ b/drivers/soc/dove/pmu.c @@ -305,6 +305,49 @@ static int __init dove_init_pmu_irq(struct pmu_data *pmu, int irq) return 0; } +int __init dove_init_pmu_legacy(const struct dove_pmu_initdata *initdata) +{ + const struct dove_pmu_domain_initdata *domain_initdata; + struct pmu_data *pmu; + int ret; + + pmu = kzalloc(sizeof(*pmu), GFP_KERNEL); + if (!pmu) + return -ENOMEM; + + spin_lock_init(&pmu->lock); + pmu->pmc_base = initdata->pmc_base; + pmu->pmu_base = initdata->pmu_base; + + pmu_reset_init(pmu); + for (domain_initdata = initdata->domains; domain_initdata->name; + domain_initdata++) { + struct pmu_domain *domain; + + domain = kzalloc(sizeof(*domain), GFP_KERNEL); + if (domain) { + domain->pmu = pmu; + domain->pwr_mask = domain_initdata->pwr_mask; + domain->rst_mask = domain_initdata->rst_mask; + domain->iso_mask = domain_initdata->iso_mask; + domain->base.name = domain_initdata->name; + + __pmu_domain_register(domain, NULL); + } + } + + ret = dove_init_pmu_irq(pmu, initdata->irq); + if (ret) + pr_err("dove_init_pmu_irq() failed: %d\n", ret); + + if (pmu->irq_domain) + irq_domain_associate_many(pmu->irq_domain, + initdata->irq_domain_start, + 0, NR_PMU_IRQS); + + return 0; +} + /* * pmu: power-manager@d0000 { * compatible = "marvell,dove-pmu"; diff --git a/include/linux/soc/dove/pmu.h b/include/linux/soc/dove/pmu.h index 9c99f84bcc0e..765386972b55 100644 --- a/include/linux/soc/dove/pmu.h +++ b/include/linux/soc/dove/pmu.h @@ -1,6 +1,25 @@ #ifndef LINUX_SOC_DOVE_PMU_H #define LINUX_SOC_DOVE_PMU_H +#include + +struct dove_pmu_domain_initdata { + u32 pwr_mask; + u32 rst_mask; + u32 iso_mask; + const char *name; +}; + +struct dove_pmu_initdata { + void __iomem *pmc_base; + void __iomem *pmu_base; + int irq; + int irq_domain_start; + const struct dove_pmu_domain_initdata *domains; +}; + +int dove_init_pmu_legacy(const struct dove_pmu_initdata *); + int dove_init_pmu(void); #endif -- cgit v1.2.2 From c5d431e8c511788556651b91debd7d77d4508f4b Mon Sep 17 00:00:00 2001 From: Russell King Date: Tue, 8 Dec 2015 10:58:09 +0000 Subject: ARM: dove: convert legacy dove to PMU support Since Dove has non-DT support for various facilities in the PMU, convert the legacy support to use the new PMU driver. Acked-by: Arnd Bergmann Signed-off-by: Russell King Signed-off-by: Gregory CLEMENT --- arch/arm/Kconfig | 1 + arch/arm/mach-dove/common.c | 26 +++++++++++ arch/arm/mach-dove/include/mach/pm.h | 20 +++----- arch/arm/mach-dove/irq.c | 88 ------------------------------------ 4 files changed, 33 insertions(+), 102 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 473c1417968a..72af9d6f8c13 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -516,6 +516,7 @@ config ARCH_DOVE select PINCTRL_DOVE select PLAT_ORION_LEGACY select SPARSE_IRQ + select PM_GENERIC_DOMAINS if PM help Support for the Marvell Dove SoC 88AP510 diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 25a682fd444f..0cdaa3851d2e 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -392,6 +393,30 @@ static void __init __maybe_unused orion_wdt_init(void) platform_device_register(&orion_wdt_device); } +static const struct dove_pmu_domain_initdata pmu_domains[] __initconst = { + { + .pwr_mask = PMU_PWR_VPU_PWR_DWN_MASK, + .rst_mask = PMU_SW_RST_VIDEO_MASK, + .iso_mask = PMU_ISO_VIDEO_MASK, + .name = "vpu-domain", + }, { + .pwr_mask = PMU_PWR_GPU_PWR_DWN_MASK, + .rst_mask = PMU_SW_RST_GPU_MASK, + .iso_mask = PMU_ISO_GPU_MASK, + .name = "gpu-domain", + }, { + /* sentinel */ + }, +}; + +static const struct dove_pmu_initdata pmu_data __initconst = { + .pmc_base = DOVE_PMU_VIRT_BASE, + .pmu_base = DOVE_PMU_VIRT_BASE + 0x8000, + .irq = IRQ_DOVE_PMU, + .irq_domain_start = IRQ_DOVE_PMU_START, + .domains = pmu_domains, +}; + void __init dove_init(void) { pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n", @@ -406,6 +431,7 @@ void __init dove_init(void) dove_clk_init(); /* internal devices that every board has */ + dove_init_pmu_legacy(&pmu_data); dove_rtc_init(); dove_xor0_init(); dove_xor1_init(); diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h index 9834ba10cd13..d22b9b174007 100644 --- a/arch/arm/mach-dove/include/mach/pm.h +++ b/arch/arm/mach-dove/include/mach/pm.h @@ -51,22 +51,14 @@ #define CLOCK_GATING_GIGA_PHY_MASK (1 << CLOCK_GATING_BIT_GIGA_PHY) #define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50) -#define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54) -static inline int pmu_to_irq(int pin) -{ - if (pin < NR_PMU_IRQS) - return pin + IRQ_DOVE_PMU_START; +#define PMU_SW_RST_VIDEO_MASK BIT(16) +#define PMU_SW_RST_GPU_MASK BIT(18) - return -EINVAL; -} +#define PMU_PWR_GPU_PWR_DWN_MASK BIT(2) +#define PMU_PWR_VPU_PWR_DWN_MASK BIT(3) -static inline int irq_to_pmu(int irq) -{ - if (IRQ_DOVE_PMU_START <= irq && irq < DOVE_NR_IRQS) - return irq - IRQ_DOVE_PMU_START; - - return -EINVAL; -} +#define PMU_ISO_VIDEO_MASK BIT(0) +#define PMU_ISO_GPU_MASK BIT(1) #endif diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c index ad785d34c1e7..d6627c1f7f30 100644 --- a/arch/arm/mach-dove/irq.c +++ b/arch/arm/mach-dove/irq.c @@ -7,88 +7,15 @@ * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ - -#include #include #include -#include #include #include -#include #include -#include -#include #include #include #include "common.h" -static void pmu_irq_mask(struct irq_data *d) -{ - int pin = irq_to_pmu(d->irq); - u32 u; - - u = readl(PMU_INTERRUPT_MASK); - u &= ~(1 << (pin & 31)); - writel(u, PMU_INTERRUPT_MASK); -} - -static void pmu_irq_unmask(struct irq_data *d) -{ - int pin = irq_to_pmu(d->irq); - u32 u; - - u = readl(PMU_INTERRUPT_MASK); - u |= 1 << (pin & 31); - writel(u, PMU_INTERRUPT_MASK); -} - -static void pmu_irq_ack(struct irq_data *d) -{ - int pin = irq_to_pmu(d->irq); - u32 u; - - /* - * The PMU mask register is not RW0C: it is RW. This means that - * the bits take whatever value is written to them; if you write - * a '1', you will set the interrupt. - * - * Unfortunately this means there is NO race free way to clear - * these interrupts. - * - * So, let's structure the code so that the window is as small as - * possible. - */ - u = ~(1 << (pin & 31)); - u &= readl_relaxed(PMU_INTERRUPT_CAUSE); - writel_relaxed(u, PMU_INTERRUPT_CAUSE); -} - -static struct irq_chip pmu_irq_chip = { - .name = "pmu_irq", - .irq_mask = pmu_irq_mask, - .irq_unmask = pmu_irq_unmask, - .irq_ack = pmu_irq_ack, -}; - -static void pmu_irq_handler(struct irq_desc *desc) -{ - unsigned long cause = readl(PMU_INTERRUPT_CAUSE); - unsigned int irq; - - cause &= readl(PMU_INTERRUPT_MASK); - if (cause == 0) { - do_bad_IRQ(desc); - return; - } - - for (irq = 0; irq < NR_PMU_IRQS; irq++) { - if (!(cause & (1 << irq))) - continue; - irq = pmu_to_irq(irq); - generic_handle_irq(irq); - } -} - static int __initdata gpio0_irqs[4] = { IRQ_DOVE_GPIO_0_7, IRQ_DOVE_GPIO_8_15, @@ -135,8 +62,6 @@ __exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs) void __init dove_init_irq(void) { - int i; - orion_irq_init(1, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); orion_irq_init(33, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); @@ -153,17 +78,4 @@ void __init dove_init_irq(void) orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0, IRQ_DOVE_GPIO_START + 64, gpio2_irqs); - - /* - * Mask and clear PMU interrupts - */ - writel(0, PMU_INTERRUPT_MASK); - writel(0, PMU_INTERRUPT_CAUSE); - - for (i = IRQ_DOVE_PMU_START; i < DOVE_NR_IRQS; i++) { - irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq); - irq_set_status_flags(i, IRQ_LEVEL); - irq_clear_status_flags(i, IRQ_NOREQUEST); - } - irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); } -- cgit v1.2.2