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| | * | PCI: mvebu: Use resource_size() to remap I/O spaceThomas Petazzoni2018-08-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of hardcoding the remapping of IO_SPACE_LIMIT - SZ_64K, use resource_size(). However, we cannot use just IO_SPACE_LIMIT, because pci_ioremap_io() has a bug and doesn't allow remapping the last 64 KB before IO_SPACE_LIMIT, so we ensure that we do not exceed this limit. When the pci_ioremap_io() issue is fixed, this work around can be dropped. Note that this workaround already existed, since we were mapping only up to IO_SPACE_LIMIT - SZ_64K. Suggested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> [lorenzo.pieralisi@arm.com: tweaked the commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: mvebu: Only remap I/O space if configuredThomas Petazzoni2018-08-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If there is no PCI I/O aperture configured in the Device Tree, it does not make sense to create the virtual mapping for the PCI I/O space, since we will anyway not create the MBus window that will allow to access it. Therefore, do the pci_ioremap_io() only if necessary. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: mvebu: Fix I/O space end address calculationThomas Petazzoni2018-08-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pcie->realio.end should be the address of last byte of the area, therefore using resource_size() of another resource is not correct, we must substract 1 to get the address of the last byte. Fixes: 11be65472a427 ("PCI: mvebu: Adapt to the new device tree layout") Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: mvebu: Remove redundant platform_set_drvdata() callThomas Petazzoni2018-08-08
| | |/ | | | | | | | | | | | | | | | | | | This is already done earlier in mvebu_pcie_probe(). Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | Merge branch 'remotes/lorenzo/pci/mobiveil'Bjorn Helgaas2018-08-15
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Fix mobiveil iomem/phys_addr_t type usage (Lorenzo Pieralisi) - Fix mobiveil missing include file (Lorenzo Pieralisi) - Add mobiveil Kconfig/Makefile support (Lorenzo Pieralisi) * remotes/lorenzo/pci/mobiveil: PCI: mobiveil: Add Kconfig/Makefile entries PCI: mobiveil: Add missing ../pci.h include PCI: mobiveil: Fix struct mobiveil_pcie.pcie_reg_base address type PCI: mobiveil: Integer overflow in IB_WIN_SIZE
| | * | PCI: mobiveil: Add Kconfig/Makefile entriesLorenzo Pieralisi2018-07-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") did not add the configuration and build infrastructure to configure and build the mobiveil controller driver, so at present the driver code is in the kernel but cannot be compiled. Add the mobiveil controller driver Kconfig/Makefile infrastructure. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
| | * | PCI: mobiveil: Add missing ../pci.h includeLorenzo Pieralisi2018-07-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI mobiveil host controller driver currently fails to compile with the following error: drivers/pci/controller/pcie-mobiveil.c: In function 'mobiveil_pcie_probe': drivers/pci/controller/pcie-mobiveil.c:788:8: error: implicit declaration of function 'devm_of_pci_get_host_bridge_resources'; did you mean 'pci_get_host_bridge_device'? [-Werror=implicit-function-declaration] ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ pci_get_host_bridge_device Add the missing include file to pull in the required function declaration. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
| | * | PCI: mobiveil: Fix struct mobiveil_pcie.pcie_reg_base address typeLorenzo Pieralisi2018-07-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The field pcie_reg_base in struct mobiveil_pcie represents a physical address so it should be of phys_addr_t type rather than void __iomem*; this results in the following compilation warnings: drivers/pci/controller/pcie-mobiveil.c: In function 'mobiveil_pcie_parse_dt': drivers/pci/controller/pcie-mobiveil.c:326:22: warning: assignment makes pointer from integer without a cast [-Wint-conversion] pcie->pcie_reg_base = res->start; ^ drivers/pci/controller/pcie-mobiveil.c: In function 'mobiveil_pcie_enable_msi': drivers/pci/controller/pcie-mobiveil.c:485:25: warning: initialization makes integer from pointer without a cast [-Wint-conversion] phys_addr_t msg_addr = pcie->pcie_reg_base; ^~~~ drivers/pci/controller/pcie-mobiveil.c: In function 'mobiveil_compose_msi_msg': drivers/pci/controller/pcie-mobiveil.c:640:21: warning: initialization makes integer from pointer without a cast [-Wint-conversion] phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int)); Fix the type and with it the compilation warnings. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
| | * | PCI: mobiveil: Integer overflow in IB_WIN_SIZEDan Carpenter2018-07-26
| | |/ | | | | | | | | | | | | | | | | | | | | | IB_WIN_SIZE is larger than INT_MAX so we need to cast it to u64. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | Merge branch 'remotes/lorenzo/pci/iproc'Bjorn Helgaas2018-08-15
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add more devices to Broadcom PAXC quirk (Ray Jui) - Work around corrupted Broadcom PAXC config space to enable SMMU and GICv3 ITS (Ray Jui) - Disable MSI parsing to work around broken Broadcom PAXC logic in some devices (Ray Jui) - Hide unconfigured functions to work around a Broadcom PAXC defect (Ray Jui) - Lower iproc log level to reduce console output during boot (Ray Jui) * remotes/lorenzo/pci/iproc: PCI: iproc: Reduce inbound/outbound mapping print level PCI: iproc: Reject unconfigured physical functions from PAXC PCI: iproc: Disable MSI parsing in certain PAXC blocks PCI: iproc: Fix up corrupted PAXC root complex config registers PCI: iproc: Activate PAXC bridge quirk for more devices
| | * | PCI: iproc: Reduce inbound/outbound mapping print levelRay Jui2018-07-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reduce inbound/outbound mapping print level from dev_info() to dev_dbg(). This reduces the console logs during Linux boot process. Signed-off-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Reviewed-by: Oza Pawandeep <poza@codeaurora.org>
| | * | PCI: iproc: Reject unconfigured physical functions from PAXCRay Jui2018-07-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PAXC is an emulated PCIe root complex internally in various Broadcom based SoCs. PAXC internally connects to the embedded network processor within these SoCs, with the embedeed network processor exposed as an endpoint device. The number of physical functions from the embedded network processor that can be accessed depends on the firmware configuration. Unfortunately, due to an ASIC bug, unconfigured physical functions cannot be properly hidden from the root complex during enumerattion. As a result, config write access to these unconfigured physical functions during enumeration will cause a bus lock up on the embedded network processor. Fortunately, these unconfigured physical functions contain a very specific, staled PCIe device ID 0x168e. By making use of this device ID, one is able to terminate the enumeration early in the vendor/device ID config read. Signed-off-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Reviewed-by: Oza Pawandeep <poza@codeaurora.org>
| | * | PCI: iproc: Disable MSI parsing in certain PAXC blocksRay Jui2018-07-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The internal MSI parsing logic in certain revisions of PAXC root complexes does not work properly and can cause corruptions on the writes transactions so they need to be disabled. Signed-off-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Reviewed-by: Oza Pawandeep <poza@codeaurora.org>
| | * | PCI: iproc: Fix up corrupted PAXC root complex config registersRay Jui2018-07-13
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On certain versions of Broadcom PAXC based root complexes, certain regions of the configuration space are corrupted. As a result, it prevents the Linux PCIe stack from traversing the linked list of the capability registers completely and therefore the root complex is not advertised as "PCIe capable". This prevents the correct PCIe RID from being parsed in the kernel PCIe stack. A correct RID is required for mapping to a stream ID from the SMMU or the device ID from the GICv3 ITS. This patch fixes up the issue by manually populating the related PCIe capabilities. Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Oza Pawandeep <poza@codeaurora.org>
| * | Merge branch 'remotes/lorenzo/pci/hv'Bjorn Helgaas2018-08-15
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Remove unnecessary GFP_ATOMIC from Hyper-V "new child" allocation (Jia-Ju Bai) * remotes/lorenzo/pci/hv: PCI: hv: Replace GFP_ATOMIC with GFP_KERNEL in new_pcichild_device()
| | * | PCI: hv: Replace GFP_ATOMIC with GFP_KERNEL in new_pcichild_device()Jia-Ju Bai2018-06-29
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | new_pcichild_device() is not called in atomic context. The call chain ending up at new_pcichild_device() is: [1] new_pcichild_device() <- pci_devices_present_work() pci_devices_present_work() is only set in INIT_WORK(). Despite never getting called from atomic context, new_pcichild_device() calls kzalloc with GFP_ATOMIC, which waits busily for allocation. GFP_ATOMIC is not necessary and can be replaced with GFP_KERNEL to avoid busy waiting. Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com> [lorenzo.pieralisi@arm.com: reworked commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Michael Kelley <mikelley@microsoft.com>
| * | Merge branch 'remotes/lorenzo/pci/dwc'Bjorn Helgaas2018-08-15
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add Kirin MSI support (Xiaowei Song) - Drop unnecessary root_bus_nr setting from exynos, imx6, keystone, armada8k, artpec6, designware-plat, histb, qcom, spear13xx (Shawn Guo) - Move link notification settings from DesignWare core to individual drivers (Gustavo Pimentel) - Add endpoint library MSI-X interfaces (Gustavo Pimentel) - Correct signature of endpoint library IRQ interfaces (Gustavo Pimentel) - Add DesignWare endpoint library MSI-X callbacks (Gustavo Pimentel) - Add endpoint library MSI-X test support (Gustavo Pimentel) * remotes/lorenzo/pci/dwc: PCI: endpoint: Add MSI set maximum restriction tools: PCI: Add MSI-X support pci_endpoint_test: Add 2 ioctl commands pci-epf-test/pci_endpoint_test: Add MSI-X support pci-epf-test/pci_endpoint_test: Use irq_type module parameter pci-epf-test/pci_endpoint_test: Cleanup PCI_ENDPOINT_TEST memspace PCI: dwc: Add legacy interrupt callback handler PCI: dwc: Rework MSI callbacks handler PCI: dwc: Add MSI-X callbacks handler PCI: Update xxx_pcie_ep_raise_irq() and pci_epc_raise_irq() signatures PCI: endpoint: Add MSI-X interfaces PCI: dwc: Fix EP link notification implementation PCI: spear13xx: Drop unnecessary root_bus_nr setting PCI: qcom: Drop unnecessary root_bus_nr setting PCI: histb: Drop unnecessary root_bus_nr setting PCI: designware-plat: Drop unnecessary root_bus_nr setting PCI: artpec6: Drop unnecessary root_bus_nr setting PCI: armada8k: Drop unnecessary root_bus_nr setting PCI: keystone: Drop unnecessary root_bus_nr setting PCI: imx6: Drop unnecessary root_bus_nr setting PCI: exynos: Drop unnecessary root_bus_nr setting PCI: kirin: Add MSI support
| | * | pci-epf-test/pci_endpoint_test: Add MSI-X supportGustavo Pimentel2018-07-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MSI-X support and update driver documentation accordingly. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * | PCI: dwc: Add legacy interrupt callback handlerGustavo Pimentel2018-07-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently DesignWare IP does not handle legacy interrupts. Add a legacy interrupt callback handler. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * | PCI: dwc: Rework MSI callbacks handlerGustavo Pimentel2018-07-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove duplicate defines located on pcie-designware.h file already available on /include/uapi/linux/pci-regs.h file. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * | PCI: dwc: Add MSI-X callbacks handlerGustavo Pimentel2018-07-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PCIe config space capability search function. Add sysfs set/get interface to allow the change of EP MSI-X maximum number. Add EP MSI-X callback for triggering interruptions. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * | PCI: Update xxx_pcie_ep_raise_irq() and pci_epc_raise_irq() signaturesGustavo Pimentel2018-07-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change {cdns, dra7xx, artpec6, dw, rockchip}_pcie_ep_raise_irq() and pci_epc_raise_irq() signature, namely the interrupt_num variable type from u8 to u16 to accommodate 2048 maximum MSI-X interrupts. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Alan Douglas <adouglas@cadence.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Joao Pinto <jpinto@synopsys.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * | PCI: dwc: Fix EP link notification implementationGustavo Pimentel2018-07-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move specific features settings from EP shared code (pcie-designware-ep.c) to the driver (pcie-designware-plat.c). Previous implementation disables the EP link notification by default for all SoCs that uses EP DesignWare IP, which affects directly the dra7xx and artpec6 SoCs. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| | * | PCI: spear13xx: Drop unnecessary root_bus_nr settingShawn Guo2018-07-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function dw_pcie_host_init() already initializes the root_bus_nr field of 'struct pcie_port', so the -1 assignment prior to calling dw_pcie_host_init() in platform specific driver is not really needed. Drop it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
| | * | PCI: qcom: Drop unnecessary root_bus_nr settingShawn Guo2018-07-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function dw_pcie_host_init() already initializes the root_bus_nr field of 'struct pcie_port', so the -1 assignment prior to calling dw_pcie_host_init() in platform specific driver is not really needed. Drop it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
| | * | PCI: histb: Drop unnecessary root_bus_nr settingShawn Guo2018-07-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function dw_pcie_host_init() already initializes the root_bus_nr field of 'struct pcie_port', so the -1 assignment prior to calling dw_pcie_host_init() in platform specific driver is not really needed. Drop it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Jianguo Sun <sunjianguo1@huawei.com>
| | * | PCI: designware-plat: Drop unnecessary root_bus_nr settingShawn Guo2018-07-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function dw_pcie_host_init() already initializes the root_bus_nr field of 'struct pcie_port', so the -1 assignment prior to calling dw_pcie_host_init() in platform specific driver is not really needed. Drop it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
| | * | PCI: artpec6: Drop unnecessary root_bus_nr settingShawn Guo2018-07-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function dw_pcie_host_init() already initializes the root_bus_nr field of 'struct pcie_port', so the -1 assignment prior to calling dw_pcie_host_init() in platform specific driver is not really needed. Drop it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Cc: Jesper Nilsson <jesper.nilsson@axis.com>
| | * | PCI: armada8k: Drop unnecessary root_bus_nr settingShawn Guo2018-07-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function dw_pcie_host_init() already initializes the root_bus_nr field of 'struct pcie_port', so the -1 assignment prior to calling dw_pcie_host_init() in platform specific driver is not really needed. Drop it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
| | * | PCI: keystone: Drop unnecessary root_bus_nr settingShawn Guo2018-07-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function dw_pcie_host_init() already initializes the root_bus_nr field of 'struct pcie_port', so the -1 assignment prior to calling dw_pcie_host_init() in platform specific driver is not really needed. Drop it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Murali Karicheri <m-karicheri2@ti.com>
| | * | PCI: imx6: Drop unnecessary root_bus_nr settingShawn Guo2018-07-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function dw_pcie_host_init() already initializes the root_bus_nr field of 'struct pcie_port', so the -1 assignment prior to calling dw_pcie_host_init() in platform specific driver is not really needed. Drop it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Lucas Stach <l.stach@pengutronix.de>
| | * | PCI: exynos: Drop unnecessary root_bus_nr settingShawn Guo2018-07-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function dw_pcie_host_init() already initializes the root_bus_nr field of 'struct pcie_port', so the -1 assignment prior to calling dw_pcie_host_init() in platform specific driver is not really needed. Drop it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Jingoo Han <jingoohan1@gmail.com>
| | * | PCI: kirin: Add MSI supportXiaowei Song2018-07-11
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for MSI to the kirin host controller driver, based on the generic dwc infrastructure. Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com> Signed-off-by: Yao Chen <chenyao11@huawei.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
| * | Merge branch 'remotes/lorenzo/pci/cadence'Bjorn Helgaas2018-08-15
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Correct the Cadence cdns_pcie_writel() signature (Alan Douglas) - Add Cadence support for optional generic PHYs (Alan Douglas) - Add Cadence power management ops (Alan Douglas) - Remove redundant variable from Cadence driver (Colin Ian King) * remotes/lorenzo/pci/cadence: PCI: pcie-cadence-ep: Remove redundant variable mmc PCI: cadence: Add shutdown callback to host driver PCI: cadence: Add Power Management ops for host and EP dt-bindings: PCI: cadence: Add DT bindings for optional PHYs PCI: cadence: Add generic PHY support to host and EP drivers PCI: cadence: Update cdns_pcie_writel() function signature
| | * | PCI: pcie-cadence-ep: Remove redundant variable mmcColin Ian King2018-07-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Variable mmc is being assigned but is never used hence it is redundant and can be removed. Cleans up clang warning: warning: variable 'mmc' set but not used [-Wunused-but-set-variable] Signed-off-by: Colin Ian King <colin.king@canonical.com> [lorenzo.pieralisi@arm.com: reworked commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Alan Douglas <adouglas@cadence.com>
| | * | PCI: cadence: Add shutdown callback to host driverAlan Douglas2018-07-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add shutdown callback to host driver which will disable PHY and PM runtime. Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: cadence: Add Power Management ops for host and EPAlan Douglas2018-07-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These PM ops will enable/disable the optional PHYs if present. The AXI link-down register in the host driver is now cleared in cdns_pci_map_bus() since the link-down bit will be set if the PHY has been disabled. It is not cleared when enabling the PHY, since the link will not yet be up (e.g. when an EP controller is connected back-to-back to the host controller and its PHY is still disabled). Link: http://lkml.kernel.org/r/1529915453-4633-5-git-send-email-adouglas@cadence.com Signed-off-by: Alan Douglas <adouglas@cadence.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: cadence: Add generic PHY support to host and EP driversAlan Douglas2018-07-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If PHYs are present, initialize and enable them at driver probe. Signed-off-by: Alan Douglas <adouglas@cadence.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: cadence: Update cdns_pcie_writel() function signatureAlan Douglas2018-07-11
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | cdns_pcie_writel() writes a long value; change the value parameter type from u16 to u32 to rectify the function signature and related behaviour. Signed-off-by: Alan Douglas <adouglas@cadence.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | Merge branch 'remotes/lorenzo/pci/aardvark'Bjorn Helgaas2018-08-15
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Remove Aardvark outbound window configuration (Evan Wang) - Fix Aardvark bridge window sizing issue (Zachary Zhang) - Convert Aardvark to use pci_host_probe() to reduce code duplication (Thomas Petazzoni) * remotes/lorenzo/pci/aardvark: PCI: aardvark: Convert to use pci_host_probe() PCI: aardvark: Size bridges before resources allocation PCI: aardvark: Remove PCIe outbound window configuration PCI: aardvark: Introduce an advk_pcie_valid_device() helper # Conflicts: # drivers/pci/controller/pci-aardvark.c
| | * | PCI: aardvark: Convert to use pci_host_probe()Thomas Petazzoni2018-07-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Part of advk_pcie_probe() is exactly an open-coded version of pci_host_probe(). So instead of duplicating this code, use pci_host_probe() directly. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI: aardvark: Size bridges before resources allocationZachary Zhang2018-07-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCIE I/O and MEM resource allocation mechanism is that root bus goes through the following steps: 1. Check PCI bridges' range and computes I/O and Mem base/limits. 2. Sort all subordinate devices I/O and MEM resource requirements and allocate the resources and writes/updates subordinate devices' requirements to PCI bridges I/O and Mem MEM/limits registers. Currently, PCI Aardvark driver only handles the second step and lacks the first step, so there is an I/O and MEM resource allocation failure when using a PCI switch. This commit fixes that by sizing bridges before doing the resource allocation. Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver") Signed-off-by: Zachary Zhang <zhangzg@marvell.com> [Thomas: edit commit log.] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: <stable@vger.kernel.org>
| | * | PCI: aardvark: Remove PCIe outbound window configurationEvan Wang2018-06-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Outbound window is used to translate CPU space addresses to PCIe space addresses when the CPU initiates PCIe transactions. According to the suggestion of the HW designers, the recommended solution is to use the default outbound parameters, even though the current outbound window setting does not cause any known functional issue. This patch doesn't address any known functional issue, but aligns to HW design guidelines, and removes code that isn't needed. Signed-off-by: Evan Wang <xswang@marvell.com> [Thomas: tweak commit log.] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> [lorenzo.pieralisi@arm.com: handled host->controller dir move] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Victor Gu <xigu@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
| | * | PCI: aardvark: Introduce an advk_pcie_valid_device() helperThomas Petazzoni2018-06-27
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | In other to mimic other PCIe host controller drivers, introduce an advk_pcie_valid_device() helper, used in the configuration read/write functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> [lorenzo.pieralisi@arm.com: updated host->controller dir move] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | Merge branch 'remotes/lorenzo/pci/controller/misc'Bjorn Helgaas2018-08-15
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | - Remove Xilinx AXI-PCIe host bridge arch dependency (Palmer Dabbelt) * remotes/lorenzo/pci/controller/misc: PCI/xilinx: Depend on OF instead of the ARCH
| | * | PCI/xilinx: Depend on OF instead of the ARCHChristoph Hellwig2018-08-06
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There isn't a hard dependency of the Xilinx AXI-PCIe host bridge on any architecture. For example: at SiFive we map RISC-V cores to Xilinx FPGAs and connect the Xilinx IP via a TileLink adapter, so the RISC-V Linux port will need to be able to enable PCIE_XILINX in order to have PCIe support. This patch decouples the PCIE_XILINX support from ARCH. Instead it just depends on OF, which is the only true dependency. Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> [hch: switch to OF instead of OF_PCI now that the latter is gone] Signed-off-by: Christoph Hellwig <hch@lst.de> [lorenzo.pieralisi@arm.com: trimmed the commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
* | | Merge branch 'l1tf-final' of ↵Linus Torvalds2018-08-14
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Merge L1 Terminal Fault fixes from Thomas Gleixner: "L1TF, aka L1 Terminal Fault, is yet another speculative hardware engineering trainwreck. It's a hardware vulnerability which allows unprivileged speculative access to data which is available in the Level 1 Data Cache when the page table entry controlling the virtual address, which is used for the access, has the Present bit cleared or other reserved bits set. If an instruction accesses a virtual address for which the relevant page table entry (PTE) has the Present bit cleared or other reserved bits set, then speculative execution ignores the invalid PTE and loads the referenced data if it is present in the Level 1 Data Cache, as if the page referenced by the address bits in the PTE was still present and accessible. While this is a purely speculative mechanism and the instruction will raise a page fault when it is retired eventually, the pure act of loading the data and making it available to other speculative instructions opens up the opportunity for side channel attacks to unprivileged malicious code, similar to the Meltdown attack. While Meltdown breaks the user space to kernel space protection, L1TF allows to attack any physical memory address in the system and the attack works across all protection domains. It allows an attack of SGX and also works from inside virtual machines because the speculation bypasses the extended page table (EPT) protection mechanism. The assoicated CVEs are: CVE-2018-3615, CVE-2018-3620, CVE-2018-3646 The mitigations provided by this pull request include: - Host side protection by inverting the upper address bits of a non present page table entry so the entry points to uncacheable memory. - Hypervisor protection by flushing L1 Data Cache on VMENTER. - SMT (HyperThreading) control knobs, which allow to 'turn off' SMT by offlining the sibling CPU threads. The knobs are available on the kernel command line and at runtime via sysfs - Control knobs for the hypervisor mitigation, related to L1D flush and SMT control. The knobs are available on the kernel command line and at runtime via sysfs - Extensive documentation about L1TF including various degrees of mitigations. Thanks to all people who have contributed to this in various ways - patches, review, testing, backporting - and the fruitful, sometimes heated, but at the end constructive discussions. There is work in progress to provide other forms of mitigations, which might be less horrible performance wise for a particular kind of workloads, but this is not yet ready for consumption due to their complexity and limitations" * 'l1tf-final' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (75 commits) x86/microcode: Allow late microcode loading with SMT disabled tools headers: Synchronise x86 cpufeatures.h for L1TF additions x86/mm/kmmio: Make the tracer robust against L1TF x86/mm/pat: Make set_memory_np() L1TF safe x86/speculation/l1tf: Make pmd/pud_mknotpresent() invert x86/speculation/l1tf: Invert all not present mappings cpu/hotplug: Fix SMT supported evaluation KVM: VMX: Tell the nested hypervisor to skip L1D flush on vmentry x86/speculation: Use ARCH_CAPABILITIES to skip L1D flush on vmentry x86/speculation: Simplify sysfs report of VMX L1TF vulnerability Documentation/l1tf: Remove Yonah processors from not vulnerable list x86/KVM/VMX: Don't set l1tf_flush_l1d from vmx_handle_external_intr() x86/irq: Let interrupt handlers set kvm_cpu_l1tf_flush_l1d x86: Don't include linux/irq.h from asm/hardirq.h x86/KVM/VMX: Introduce per-host-cpu analogue of l1tf_flush_l1d x86/irq: Demote irq_cpustat_t::__softirq_pending to u16 x86/KVM/VMX: Move the l1tf_flush_l1d test to vmx_l1d_flush() x86/KVM/VMX: Replace 'vmx_l1d_flush_always' with 'vmx_l1d_flush_cond' x86/KVM/VMX: Don't set l1tf_flush_l1d to true from vmx_l1d_flush() cpu/hotplug: detect SMT disabled by BIOS ...
| * | Merge 4.18-rc7 into master to pick up the KVM dependcyThomas Gleixner2018-08-05
| |\ \ | | | | | | | | | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * | | x86: Don't include linux/irq.h from asm/hardirq.hNicolai Stange2018-08-05
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The next patch in this series will have to make the definition of irq_cpustat_t available to entering_irq(). Inclusion of asm/hardirq.h into asm/apic.h would cause circular header dependencies like asm/smp.h asm/apic.h asm/hardirq.h linux/irq.h linux/topology.h linux/smp.h asm/smp.h or linux/gfp.h linux/mmzone.h asm/mmzone.h asm/mmzone_64.h asm/smp.h asm/apic.h asm/hardirq.h linux/irq.h linux/irqdesc.h linux/kobject.h linux/sysfs.h linux/kernfs.h linux/idr.h linux/gfp.h and others. This causes compilation errors because of the header guards becoming effective in the second inclusion: symbols/macros that had been defined before wouldn't be available to intermediate headers in the #include chain anymore. A possible workaround would be to move the definition of irq_cpustat_t into its own header and include that from both, asm/hardirq.h and asm/apic.h. However, this wouldn't solve the real problem, namely asm/harirq.h unnecessarily pulling in all the linux/irq.h cruft: nothing in asm/hardirq.h itself requires it. Also, note that there are some other archs, like e.g. arm64, which don't have that #include in their asm/hardirq.h. Remove the linux/irq.h #include from x86' asm/hardirq.h. Fix resulting compilation errors by adding appropriate #includes to *.c files as needed. Note that some of these *.c files could be cleaned up a bit wrt. to their set of #includes, but that should better be done from separate patches, if at all. Signed-off-by: Nicolai Stange <nstange@suse.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* | | PCI: mobiveil: Avoid integer overflow in IB_WIN_SIZEDan Carpenter2018-07-27
| |/ |/| | | | | | | | | | | | | IB_WIN_SIZE is larger than INT_MAX so we need to cast it to u64. Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-07 00:09:33 -0400