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path: root/drivers/net/wireless/ath/ath10k/pci.c
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* ath10k: fix erroneous return valueAnton Protopopov2016-03-03
| | | | | | | | The ath10k_pci_hif_exchange_bmi_msg() function may return the positive value EIO instead of -EIO in case of error. Signed-off-by: Anton Protopopov <a.s.protopopov@gmail.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: add basic skeleton to support ahbRaja Mani2016-01-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | qca4019 uses ahb instead of pci where it slightly differs in device enumeration, clock control, reset control, etc. Good thing is that ahb also uses copy engine for the data transaction. So, the most of the stuff implemented in pci.c/ce.c are reusable in ahb case too. Device enumeration in ahb case comes through platform driver/device model. All resource details like irq, memory map, clocks, etc for qca4019 can be fetched from of_node of platform device. Simply flow would look like, device tree => platform device (kernel) => platform driver (ath10k) Device tree entry will have all qca4019 resource details and the same info will be passed to kernel. Kernel will prepare new platform device for that entry and expose DT info to of_node in platform device. Later, ath10k would register platform driver with unique compatible name and then kernels binds to corresponding compatible entry & calls ath10k ahb probe functions. From there onwards, ath10k will take control of it and move forward. New bool flag CONFIG_ATH10K_AHB is added in Kconfig to conditionally enable ahb support in ath10k. On enabling this flag, ath10k_pci.ko will have ahb support. This patch adds only basic skeleton and few macros to support ahb in the context of qca4019. Signed-off-by: Raja Mani <rmani@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: pull reusable code from pci probe and remove for ahbRaja Mani2016-01-28
| | | | | | | | | | Some of the code present in ath10k_pci_{probe|remove} are reusable in ahb case too. To avoid code duplication, move reusable code to new functions. Later, those new functions can be called from ahb module's probe and exit functions. Signed-off-by: Raja Mani <rmani@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: make ath10k_pci_read32/write32() ops more genericRaja Mani2016-01-28
| | | | | | | | | | | | | | | | | | | | | | | | | | ath10k_pci_read32/write32() does work more specific to PCI by ensuring pci wake/sleep for every read and write. There is a plan to use most of stuff available in pci.c (irq stuff, copy engine, etc) for AHB case. Such kind of pci wake/sleep for every read/write is not required in AHB case (qca4019). All those reusable areas in pci.c and ce.c calls ath10k_pci_read32/write32() for low level read and write. In fact, ath10k_pci_read32/write32() should do what it does today for PCI case. But for AHB, it has to do differently. To make ath10k_pci_read32/write32() more generic, new function pointers are added in ar_pci for the function which does operation more close to the bus. Later, corresponding bus specific read and write function will be mapped to that. ath10k_pci_read32/write32() are changed to call directly those function pointers without worrying which bus underlying to it. Also, the function to get number of bank is changed in the same way. Signed-off-by: Raja Mani <rmani@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: make some of ath10k_pci_* func reusableRaja Mani2016-01-28
| | | | | | | | | | | | Some of static functions present in pci.c file are reusable in ahb (qca4019) case. Remove static word for those reusable functions and have those function prototype declaration in pci.h file. So that, pci.h header file can be included in ahb module and reused. There is no functionality changes done in this patch. Signed-off-by: Raja Mani <rmani@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: reduce indentation by moving powersave check within functionRajkumar Manoharan2015-12-31
| | | | | | | | | For devices that does not support PCI power save, force wake up API is used. So move powersave check inside force wakeup to reduce one level indentation. Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: wake up device before accessing registersRajkumar Manoharan2015-12-31
| | | | | | | | | | | | | | commit 1aaf8efba0ae ("ath10k: disable PCI PS for QCA988X and QCA99X0") partially reverts pci soc powersave support added by commit 77258d409ce4 ("ath10k: enable pci soc powersaving"). While reverting the change, pci wake up function is called after accessing pci registers instead of prior to access. The assumption is that chip is woken up before accessing its registers.Though this change does not fix any known issues, this might help to avoid unknown or low power platform specific issues. Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* Merge tag 'wireless-drivers-next-for-davem-2015-12-07' of ↵David S. Miller2015-12-08
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next Kalle Vallo says: ==================== brcfmac * support bcm4359 which can operate in two bands concurrently * disable runtime pm for USB avoiding issues * use generic pm callback in PCIe driver * support wowlan wake indication reporting * add beamforming support * unified handling of firmware files ath10k * support Manegement Frame Protection (MFP) * add thermal throttling support for 10.4 firmware * add support for pktlog in QCA99X0 * add debugfs file to enable Bluetooth coexistence feature * use firmware's native mesh interface type instead of raw mode iwlwifi * BT coex improvements * D3 operation bugfixes * rate control improvements * firmware debugging infra improvements * ground work for multi Rx * various security fixes ==================== Conflicts: drivers/net/wireless/ath/ath10k/pci.c The conflict resolution at: http://article.gmane.org/gmane.linux.kernel.next/37391 by Stephen Rothwell was used. Signed-off-by: David S. Miller <davem@davemloft.net>
| * ath10k: add support for pktlog in QCA99X0Vivek Natarajan2015-11-04
| | | | | | | | | | | | | | This patch adds pktlog support for 10.4 fw versions. Signed-off-by: Vivek Natarajan <nataraja@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* | ath10k: poll HTT send completion when CE 5 is unusedRajkumar Manoharan2015-11-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | commit a70587b3389a ("ath10k: configure copy engine 5 for HTT messages") moved send completion polling under HTT Rx (CE 5) service routine. For QCA6174 based devices copy engine 1 (CE 1) is used for HTT Rx instead of CE 5. So send completion never be called. This is causing "failed to transmit packet, dropping: -105" errors. Fix this by processing send completion from CE 1 service routine instead of CE 5. Fixes: a70587b3389a ("ath10k: configure copy engine 5 for HTT messages") Tested-by: Ryan Hsu <ryanhsu@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* | ath10k: override CE5 configuration for QCA6147 deviceRyan Hsu2015-11-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit a70587b3389a ("ath10k: configure copy engine 5 for HTT messages") introduced to use the unused CE5 for target to host message. For the device like QCA6174, CE5 already assigned for other feature. So for QCA6174, override the CE5 configuration and use the CE1 instead. This patch is based on Rajkumar's earlier patch. Fixes: a70587b3389a ("ath10k: configure copy engine 5 for HTT messages") Signed-off-by: Ryan Hsu <ryanhsu@qca.qualcomm.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* | ath10k: add QCA9377 hw1.0 supportBartosz Markowski2015-11-12
| | | | | | | | | | | | | | | | Add new BMI target version and chip id revision. Register it on supported chips list. Signed-off-by: Bartosz Markowski <bartosz.markowski@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* | ath10k: introduce dev_id to hw_paramsBartosz Markowski2015-11-12
| | | | | | | | | | | | | | | | | | | | | | A follow up patch introducing a QCA9377 hw1.0 support will need this device identification helper for an explicit distinction of HWs, as apparently both QCA6174 hw3.0 and QCA9377 share the same BMI target version (0x0502000x). For the QCA9377 hw1.1 previously added we were just lucky we did not overlap with the same chip_id_rev. Signed-off-by: Bartosz Markowski <bartosz.markowski@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* | ath10k: fix the currently supported QCA9377 target version nameBartosz Markowski2015-11-12
|/ | | | | | | | | | When introducing the original QCA9377 support, the chip target version was wrongly picked. The chip advertising itself with bmi target value equal to 0x05020001 is in fact a 1.1 revision. I realized this once I got a real 1.1 hw to play with. Signed-off-by: Bartosz Markowski <bartosz.markowski@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: add QCA9377 chipset supportBartosz Markowski2015-10-29
| | | | | | | | | | | | | | Add the hardware name, revision and update the pci_id table. Currently there're two HW ref. designs available I'm aware of, with 1.0.2 and 1.1 chip revisions. I've access and been using the first one so far and this patch cover only it. QCA9377 inherits most of the stuff (e.g. fw interfaces) from QCA61x4 design, so the integration was pretty straightforward. Signed-off-by: Bartosz Markowski <bartosz.markowski@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: remove shadow copy of CE descriptors for source ringRajkumar Manoharan2015-10-29
| | | | | | | | | | | | For the messages from host to target, shadow copy of CE descriptors are maintained in source ring. Before writing actual CE descriptor, first shadow copy is filled and then it is copied to CE address space. To optimize in download path and to reduce d-cache pressure, removing shadow copy of CE descriptors. This will also reduce driver memory consumption by 33KB during on device probing. Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: cleanup copy engine send completionRajkumar Manoharan2015-10-29
| | | | | | | | | | | | The physical address necessary to unmap DMA ('bufferp') is stored in ath10k_skb_cb as 'paddr'. ath10k doesn't rely on the meta/transfer_id when handling send completion (htc ep id is stored in sk_buff control buffer). So the unused output arguments {bufferp, nbytesp and transfer_idp} are removed from CE send completion. This change is needed before removing the shadow copy of copy engine (CE) descriptors in follow up patch. Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: remove send completion validation in diag read/writeRajkumar Manoharan2015-10-29
| | | | | | | | | CE diag window access is serialized (it has to be by design) so there's no way to get a different send completion. so there's no need for post completion validation. Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: disable PCI PS for QCA988X and QCA99X0Anilkumar Kolli2015-10-19
| | | | | | | | | | | | | | | | | | This patch disables PCI PS for QCA988X and QCA99X0, Since PCI PS is validated for QCA6174, let it be enabled only for QCA6174. It would be better to execute PCI PS related functions only for the supported devices. PCI time out issue is observed with QCA99X0 on x86 platform, We will disable PCI PS for QCA988X and QCA99X0 until PCI PS is properly implemented. Taking and releasing ps_lock is causing higher CPU consumption. Michal Kazior suggested ps_lock overhead to be reworked so that ath10k_pci_wake/sleep functions are called less often, i.e. move the powersave logic up (only during irq handling, tx path, submitting fw commands) but that's a bigger change and can be implemented later. Signed-off-by: Anilkumar Kolli <akolli@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: remove htc polling for tx completionRajkumar Manoharan2015-10-16
| | | | | | | | | | Since polling for tx completion is handled whenever target to host messages are received, removing the unnecessary polling mechanism for send completion at HTC level. Reviewed-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: remove unused dl_is_polledRajkumar Manoharan2015-10-16
| | | | | | | | | Since polling for received messages not supported, remove unused dl_is_polled. Reviewed-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: configure copy engine 5 for HTT messagesRajkumar Manoharan2015-10-16
| | | | | | | | | | | | | | | | | | | | | | Currently target to host (T2H) HTT messages are received at copy engine 1. These messages are processed by HTC layer in both host and target. To avoid HTC level processing overhead in both host and target, the unused copy engine 5 is being used for receiving HTT T2H messages. This will speedup the receive data processing as well as htt tx completion. Hence host and target copy engine configuration tables are updated to enable CE5 pipe. The in-direction HTT mapping is now pointing to CE5 for all HTT T2H. Moreover HTT send completion messages are polled from HTC handler as CE 4 is not interrupt-driven. For faster tx completion, CE4 polling needs to be done whenever CE pipe which transports HTT Rx (target->host) is processed. This avoids overhead of polling HTT messages from HTC layer. Servicing CE 4 faster is helping to solve "failed to transmit packet, dropping: -105". Reviewed-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: register per copy engine receive callbacksRajkumar Manoharan2015-10-16
| | | | | | | | | | | | Register receive callbacks for every copy engines (CE) separately instead of having common receive handler. Some of the copy engines receives different type of messages (i.e HTT/HTC/pktlog) from target. Hence to service them accordingly, register per copy engine receive callbacks. Reviewed-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: register per copy engine send completion callbacksRajkumar Manoharan2015-10-16
| | | | | | | | | | | Register send completion callbacks for every copy engines (CE) separately instead of having common completion handler. Since some of the copy engines delivers different type of messages, per-CE callbacks help to service them differently. Reviewed-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: add board 2 API supportManikanta Pubbisetty2015-10-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | QCA6174 needs different board files based on board type. To make it easier to distribute multiple board files and automatically choose correct board file create a simple TLV file format following the same principles as with FW IEs. The file is named board-2.bin and contain multiple board files. Each board file then can have multiple names. ath10k searches for file board-N.bin (where N is the interface version number for the board file, just like we for firmware files) in /lib/firmware/*, for example for qca99x0 it will try to find it here: /lib/firmware/ath10k/QCA99X0/hw2.0/board-2.bin If ath10k doesn't find board-2.bin then it will fallback to the old board.bin file. This patch adds a simple name scheme using pci device id which for now will be used by qca6174: bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x This removes the old method of having subsystem ids in ar->spec_board_id and using that in the board file name. Signed-off-by: Manikanta Pubbisetty <c_mpubbi@qti.qualcomm.com> [kvalo@qca.qualcomm.com: simplified the file format, rewrote commit log, other smaller changes] Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: optimize ce_lock on post rx buffer processingRajkumar Manoharan2015-10-09
| | | | | | | | | | | | | | | | | | | After processing received packets from copy engine, host will allocate new buffer and queue them back to copy engine ring for further packet reception. On post rx processing path, skb allocation and dma mapping are unnecessarily handled within ce_lock. This is affecting peak throughput and also causing more CPU consumption. Optimize this by acquiring ce_lock only when accessing copy engine ring and moving skb allocation out of ce_lock. In AP148 platform with QCA99x0 in conducted environment, UDP uplink peak throughput is improved from ~1320 Mbps to ~1450 Mbps and TCP uplink peak throughput is increased from ~1240 Mbps (70% host CPU load) to ~1300 Mbps (71% CPU load). Similarly ~40Mbps improvement is observed in downlink path. Signed-off-by: Rajkumar Manoharan <rmanohar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: increase pci wakeup timeout to 30 msMaharaja Kennadyrajan2015-10-09
| | | | | | | | | It is noticed that pci wakeup time is exceeding current timeout (10ms) randomly which is tested on QCA988x. So, the wake up time is increased to 30 ms and added debug prints to log total timeout. Signed-off-by: Maharaja Kennadyrajan <c_mkenna@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: fix whitespace usageKalle Valo2015-10-06
| | | | | | | | | | | | checkpatch found: drivers/net/wireless/ath/ath10k/core.c:574: Blank lines aren't necessary before a close brace '}' drivers/net/wireless/ath/ath10k/mac.c:4067: Missing a blank line after declarations drivers/net/wireless/ath/ath10k/mac.c:4083: Missing a blank line after declarations drivers/net/wireless/ath/ath10k/mac.c:4084: spaces required around that '>>=' (ctx:WxV) drivers/net/wireless/ath/ath10k/pci.c:1507: Missing a blank line after declarations Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: indentation fixesKalle Valo2015-10-06
| | | | | | | | | | | | | | | | checkpatch found: drivers/net/wireless/ath/ath10k/core.c:513: Alignment should match open parenthesis drivers/net/wireless/ath/ath10k/core.c:1266: code indent should use tabs where possible drivers/net/wireless/ath/ath10k/core.c:1267: code indent should use tabs where possible drivers/net/wireless/ath/ath10k/core.c:1268: code indent should use tabs where possible drivers/net/wireless/ath/ath10k/core.c:1269: code indent should use tabs where possible drivers/net/wireless/ath/ath10k/mac.c:4659: Alignment should match open parenthesis drivers/net/wireless/ath/ath10k/mac.c:6271: Alignment should match open parenthesis drivers/net/wireless/ath/ath10k/pci.c:2260: Alignment should match open parenthesis drivers/net/wireless/ath/ath10k/wmi.c:3510: Alignment should match open parenthesis Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: fix MSI-X registering for qca99x0Janusz Dziedzic2015-09-27
| | | | | | | | | | | | In case of qca99x0 and MSI-X supported/enabled we failed during interrupts registering with message: ath10k_pci 0000:04:00.0: failed to request MSI-X ce irq 50: -22 Issue/fix was reproduced/tested using Dell Latitude E6430 laptop. Signed-off-by: Janusz Dziedzic <janusz.dziedzic@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: add qca6164 supportMichal Kazior2015-08-26
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds additional 0x0041 PCI Device ID definition to ath10k for QCA6164 which is a 1 spatial stream sibling of the QCA6174 (which is 2 spatial stream chip). The QCA6164 needs a dedicated board.bin file which is different than the one used for QCA6174. If the board.bin is wrong the device will crash early while trying to boot firmware. The register dump will look like this: ath10k_pci 0000:02:00.0: firmware register dump: ath10k_pci 0000:02:00.0: [00]: 0x05010000 0x000015B3 0x000A012D 0x00955B31 ... Note the value 0x000A012D. Special credit goes to Alan Liu <alanliu@qca.qualcomm.com> for providing support help which enabled me to come up with this patch. Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: fix dma_mapping_error() handlingMichal Kazior2015-08-26
| | | | | | | | | | | The function returns 1 when DMA mapping fails. The driver would return bogus values and could possibly confuse itself if DMA failed. Fixes: 767d34fc67af ("ath10k: remove DMA mapping wrappers") Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: add QCA99X0 to supported device listVasanthakumar Thiagarajan2015-07-30
| | | | | | | | | | | | Add vendor/device id of QCA99X0 V2.0 to pci id table and QCA99X0_HW_2_0_CHIP_ID_REV to ath10k_pci_supp_chips[] for QCA99X0 to get detected by the driver. kvalo: now QCA99X0 family of chipsets is supported by ath10k. Tested client, AP and monitor mode with QCA9990. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: delay device access after cold resetVasanthakumar Thiagarajan2015-07-24
| | | | | | | | | | | | | | It is observed that during cold reset pcie access right after a write operation to SOC_GLOBAL_RESET_ADDRESS causes Data Bus Error and system hard lockup. The reason for bus error is that pcie needs some time to get back to stable state for any transaction during cold reset. Add delay of 20 msecs after write of SOC_GLOBAL_RESET_ADDRESS to fix this issue. This patch is tested on QCA988X. This is also tested on QCA99X0 which is WIP. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: Fix target to cpu address conversion logicVasanthakumar Thiagarajan2015-07-11
| | | | | | | | | | In commit 418ca5992e2f ("ath10k: Make target cpu address to CE address conversion chip specific") mask 0x7fff is added by mistake instead of 0x7ff. Fix this regression. Fixes: 418ca5992e2f ("ath10k: Make target cpu address to CE address conversion chip specific") Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: Add chip reset sequence for QCA99X0Vasanthakumar Thiagarajan2015-06-30
| | | | | | | | | | QCA99X0 supports only cold reset. Also, made ath10k_pci_irq_msi_fw_mask() and ath10k_pci_irq_msi_fw_unmask() non-99X0 specific till we get proper register configuration to mask/unmask irq/MSI. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: Make target cpu address to CE address conversion chip specificVasanthakumar Thiagarajan2015-06-30
| | | | | | | | | Make the helper converting target virtual address space to CE address space a target type specific to support QCA99X0. Also make this as function instead of macro. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: Copy Engine related changes for QCA99X0Vasanthakumar Thiagarajan2015-06-30
| | | | | | | | | | QCA99X0 supports upto 12 Copy engines. Host and target CE configuration table is updated to support new copy engine pipes. This also fixes the assumption of diagnostic CE by making CE_7 as the one instead of CE_COUNT - 1. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: Add hw register/values for QCA99X0 chipVasanthakumar Thiagarajan2015-06-30
| | | | | | | | | | | This is to prepare the driver for QCA99X0 chip support. This commit adds hw_params, hw register table and hw_values table for QCA99X0 chip. Please note this is only a partial patch adding support for QCA99X0, so the device id is not yet added to pci device table. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: prevent debugfs mmio access crash kernelMichal Kazior2015-06-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It was possible to force an out of bounds MMIO read/write via debugfs. E.g. on QCA988X this could be triggered with: echo 0x2080e0 | tee /sys/kernel/debug/ieee80211/*/ath10k/reg_addr cat /sys/kernel/debug/ieee80211/*/ath10k/reg_value BUG: unable to handle kernel paging request at ffffc90001e080e0 IP: [<ffffffff8135c860>] ioread32+0x40/0x50 ... Call Trace: [<ffffffffa00d0c7f>] ? ath10k_pci_read32+0x4f/0x70 [ath10k_pci] [<ffffffffa0080f50>] ath10k_reg_value_read+0x90/0xf0 [ath10k_core] [<ffffffff8115c2c1>] ? handle_mm_fault+0xa91/0x1050 [<ffffffff81189758>] __vfs_read+0x28/0xe0 [<ffffffff812e4694>] ? security_file_permission+0x84/0xa0 [<ffffffff81189ce3>] ? rw_verify_area+0x53/0x100 [<ffffffff81189e1a>] vfs_read+0x8a/0x140 [<ffffffff8118acb9>] SyS_read+0x49/0xb0 [<ffffffff8104e39c>] ? trace_do_page_fault+0x3c/0xc0 [<ffffffff8196596e>] system_call_fastpath+0x12/0x71 Reported-by: Ben Greear <greearb@candelatech.com> Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: remove unused variable 'id' in ath10k_pci_tx_pipe_cleanup()Raja Mani2015-06-09
| | | | | | | | | | mete_data is extracted from ce descriptor and stored in variable 'id'. later, id is not used anywhere in the same function. Fixes: d84a512dca23 ("ath10k: remove transfer_id from ath10k_hif_cb::tx_completion") Signed-off-by: Raja Mani <rmani@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: fix possible ps sleep crashMichal Kazior2015-06-01
| | | | | | | | | | | | | | | | | | | | | | | | | If probing failed pci sleep timer could remain running and trigger after ath10k structures were freed causing invalid pointer dereference: BUG: unable to handle kernel paging request at ffffc90001c80004 IP: [<ffffffff81354728>] iowrite32+0x38/0x40 ... Call Trace: <IRQ> [<ffffffffa00da048>] ? __ath10k_pci_sleep+0x48/0x60 [ath10k_pci] [<ffffffffa00da44e>] ath10k_pci_ps_timer+0x5e/0x80 [ath10k_pci] [<ffffffff810b210e>] call_timer_fn+0x3e/0x120 [<ffffffffa00da3f0>] ? ath10k_pci_wake+0x150/0x150 [ath10k_pci] [<ffffffff810b3d11>] run_timer_softirq+0x201/0x2e0 [<ffffffff8105d73f>] __do_softirq+0xaf/0x290 [<ffffffff8105da95>] irq_exit+0x95/0xa0 [<ffffffff81950406>] smp_apic_timer_interrupt+0x46/0x60 [<ffffffff8194e77e>] apic_timer_interrupt+0x6e/0x80 Fixes: 77258d409ce4 ("ath10k: enable pci soc powersaving") Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: add missing firmware declarationsMichal Kazior2015-05-29
| | | | | | | | | | This could lead userspace initram images getting built without necessary firmware files included leading to probing failures of ath10k on boot with QCA61X4. Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: enable pci soc powersavingMichal Kazior2015-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By using SOC_WAKE register it is possible to bring down power consumption of QCA61X4 from 36mA to 16mA when associated and idle. Currently the sleep threshold/grace period is at a very conservative value of 60ms. Contrary to QCA61X4 the QCA988X firmware doesn't have Rx/beacon filtering available for client mode and SWBA events are used for beaconing in AP/IBSS so the SoC needs to be woken up at least every ~100ms in most cases. This means that QCA988X is at a disadvantage and the power consumption won't drop as much as for QCA61X4. Due to putting irq-safe spinlocks on every MMIO read/write it is expected this can cause a little performance regression on some systems. I haven't done any thorough measurements but some of my tests don't show any extreme degradation. The patch removes some explicit pci_wake calls that were added in 320e14b8db51aa ("ath10k: fix some pci wake/sleep issues"). This is safe because all MMIO accesses are now wrapped and the device is woken up automatically if necessary. Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: enable ASPMJanusz Dziedzic2015-05-22
| | | | | | | | | | | | | | It is actually safe to enable ASPM after the device is booted up. This reduces power drain of QCA61X4 when driver is simply loaded (no interface is up) from 31mA to 14mA. QCA988X wasn't measured but doesn't seem to regress in any other way. Signed-off-by: Janusz Dziedzic <janusz.dziedzic@tieto.com> Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: fix qca61x4 hw2.1 supportMichal Kazior2015-04-21
| | | | | | | | | | | | | | During initialization firmware does some sort of memory switch between DRAM and IRAM. If configuration value for bank switching isn't correct device crashes during init. The new value prevents firmware 11.0.0.302 (and possibly others) for qca61x4 hw2.1 from crashing during init. Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: allow loading device specific board filesMichal Kazior2015-04-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some devices differ slightly and require different board files. If wrong board data is used they crash or behave incorrectly. These devices can be differentiated by looking at PCI subsystem device id. That is the case for qca61x4 devices at least. The board specific filename is constructed as: board-<bus>-<id>.bin For PCI in particular it is: board-pci-<vendor>:<dev>:<subsys_vendor>:<subsys_dev>.bin These files are looked in device/hw specific directories. Hence for Killer 1525 (qca6174 hw2.1) ath10k will request: /lib/firmware/ath10k/QCA6174/hw2.1/board-pci-168c:003e:1a56:1525.bin To not break any existing setups (e.g. in case some devices in the wild already have subsys ids) if a board specific file isn't found a generic one is used which is the one which would be used until now. This guarantees that after upgrading a driver device will not suddenly stop working due to now-missing specific board file. If this is the case a "fallback" string is appended to the info string when driver boots. Keep in mind this is distinct from cal-pci-*.bin files which contain full calibration data and MAC address. Cal data is aimed at systems where calibration data is stored out of band, e.g. on nand flash instead of device EEPROM - an approach taken by some AP/router vendors. Board files are more of a template and needs some bits to be filled in by the OTP program using device EEPROM contents. One could argue to map subsystem ids to some board design codename strings instead of using raw ids when building the board filename. Using a mapping however would make it a lot more cumbersome and time consuming (due to how patches propagate over various kernel trees) to add support for some new device board designs. Adding a board file is a lot quicker and doesn't require recompilation. Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: fix error handling in pci_probeMichal Kazior2015-04-17
| | | | | | | | | | | If chip_id wasn't recognized clean up code wasn't executed properly. It would skip freeing memory causing a leak and irqs causing possibly MSI warning splats later or even kernel crashes. Fixes: 1a7fecb766c8 ("ath10k: reset chip before reading chip_id in probe") Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: bump up FW API to 5Kalle Valo2015-03-30
| | | | | | | | | | Firmware 10.2.4.48-3 now supports management frames over HTT feature and has ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX. But as 10.2.4 branch has conflicting HTT ids patch "ath10k: add ATH10K_FW_IE_HTT_OP_VERSION" is needed to fix the issue. Older ath10k versions don't have support that support and to maintain backwards compatibility we need bump up the FW API to 5 not break older versions. Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath10k: save/restore pci config space properlyMichal Kazior2015-03-07
| | | | | | | | | | | | | | | | The check was't really necessary and couldn't even work to begin with because pci_restore_state() restores only first 64 bytes of PCI configuration space. Actually the PCI subsystem takes care of this so there's no need for explicit calls to save PCI state in ath10k. This is necessary for future WoWLAN support. Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
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