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path: root/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
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* amd-xgbe: Fix maximum GPIO value checkLendacky, Thomas2016-11-16
| | | | | | | | | | | The GPIO support in the hardware allows for up to 16 GPIO pins, enumerated from 0 to 15. The driver uses the wrong value (16) to validate the GPIO pin range in the routines to set and clear the GPIO output pins. Update the code to use the correct value (15). Reported-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add support for MDIO attached PHYsLendacky, Thomas2016-11-13
| | | | | | | | | Use the phylib support in the kernel to communicate with and control an MDIO attached PHY. Use the hardware's MDIO communication mechanism to communicate with the PHY. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add ECC status support for the device memoryLendacky, Thomas2016-11-13
| | | | | | | | | Some versions of the amd-xgbe device are capable of reporting ECC error information back to the driver. Add support to process, track and report on this information. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add support for new DMA interrupt modeLendacky, Thomas2016-11-13
| | | | | | | | | | | | | The current per channel DMA interrupt support is based on an edge triggered interrupt that is not maskable. This results in having to call the disable_irq/enable_irq functions in order to prevent interrupts during napi processing. The hardware now has a way to configure the per channel DMA interrupt that will allow for masking the interrupt which prevents calling disable_irq/enable_irq now. This patch makes use of this support. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add a workaround for Tx timestamp issueLendacky, Thomas2016-11-13
| | | | | | | | | | | | | | | Update the reading of the Tx timestamp to account for a hardware issue on how the fields and interrupt are cleared. The "seconds" portion of the timestamp should be read first, followed by the "nanoseconds" portion. Reading the "nanoseconds" portion should clear the timestamp data and the interrupt. Because of an issue with the hardware this order is reversed and reading the "seconds" portion actually clears the timestamp. The code currently follows this workaround, but to guard against future versions where this is fixed add a field to the version data to indicate if the workaround is required or not. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Guard against incorrectly generated interruptsLendacky, Thomas2016-11-13
| | | | | | | | | Due to a hardware issue, it is possible for interrupt events to be incorrectly generated when performing a soft reset. To guard against this, perform the soft reset twice. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Prepare for supporting PCI devicesLendacky, Thomas2016-11-04
| | | | | | | | | Update the driver framework to separate out platform/ACPI specific code from general code during device initialization. This will allow for the introduction of PCI device support. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Update how to determine DMA channel statusLendacky, Thomas2016-11-04
| | | | | | | | | | Tx and Rx DMA channel status determiniation is different depending on the version of the hardware. Update the channel status processing code to account for the change. Also, reduce the timeout value used when stopping the channels. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Support for 64-bit management counter registersLendacky, Thomas2016-11-04
| | | | | | | | | Add support for reading all management counter registers as 64-bit values. The indication of whether to read the high 32-bits to form a 64-bit value is indicated in the version data. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Prepare for a new PCS register access methodLendacky, Thomas2016-11-04
| | | | | | | | | Prepare the code to be able to support accessing of the PCS registers in a new way, while maintaining the current access method. Provide a version specific field that indicates the method to use. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Prepare for working with more than one type of phyLendacky, Thomas2016-11-04
| | | | | | | | | Prepare the code to be able to work with more than one type of phy by adding additional callable functions into the phy interface and removing phy specific settings/functions from non-phy related files. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Perform priority-based hardware FIFO allocationLendacky, Thomas2016-11-04
| | | | | | | | | | Allocate the FIFO across the hardware Rx queues based on the priority of the queues. Giving more FIFO resources to queues with a higher priority. If PFC is active but not enabled for a queue, then less resources can allocated to the queue. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Prepare for priority-based FIFO allocationLendacky, Thomas2016-11-04
| | | | | | | | | | | | | Currently, the Rx and Tx fifos are evenly allocated between the hardware queues of the device. As more queues are instantiated, the fifo memory needs to be able to be allocated based on queue priority. This allows for higher priority queues to have more fifo memory than lower priority queues. Prepare for this by modifying the current fifo calculation to assign the fifo queue allocation in an array that is then used to program the hardware. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Mask auto-negotiation interrupts in ISRLendacky, Thomas2016-02-17
| | | | | | | | | | | | | | Currently the auto-negotiation interrupt handling disables the irq instead of masking off the interrupts. This was done because the phy library was originally used to read and write the PCS registers, which could not be performed in interrupt context. Now that the phy library is no longer used to read and write the PCS registers the interrupts can be masked off in the interrupt service routine eliminating the need to call disable_irq/enable_irq. This also requires changing the protection mutex to a spinlock. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Check Rx queue fifos before stopping Rx DMALendacky, Thomas2016-02-17
| | | | | | | | Check to be sure that the Rx queue fifos are empty before stopping the Rx DMA channels. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Do traffic class setup when called through dcbnlLendacky, Thomas2016-02-17
| | | | | | | | | | | Currently the netdev traffic class setup is only performed when invoked through the ndo_setup_tc interface. However, the same setup should be performed when the dcbnl interface (ieee_setets) is invoked. Rework the netdev traffic class setup to be invokable through either interface and also provide the priority to traffic class mapping if available. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Fix the mapping of priorities to traffic classesLendacky, Thomas2016-02-17
| | | | | | | | | | | | | | | | The driver is checking the pfc_en field of the ieee_pfc structure to determine whether to associate a priority with a traffic class. This is incorrect since the pfc_en field is for determining if PFC is enabled for a traffic class. The association of priority to traffic class does not depend on whether the traffic class is enabled for PFC, so remove that check. Also, the mapping of priorities to traffic classes should be done when configuring the traffic classes and not the PFC support so move the priority to traffic class association from xgbe_config_dcb_pfc to xgbe_config_dcb_tc. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Enable/disable PFC per traffic classLendacky, Thomas2016-02-17
| | | | | | | | | | Currently the PFC flow control is enabled on all traffic classes if one or more traffic classes request it. The PFC enable setting of the traffic class should be used to determine whether to enable or disable flow control for the traffic class. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Disable VLAN filtering when in promiscuous modeLendacky, Thomas2016-02-17
| | | | | | | | | | | | | When the hardware is placed in promiscuous mode it will still perform VLAN filtering and therefore may not pass all packets to the driver. Disable all VLAN filtering when entering promiscuous mode and restore VLAN filtering upon exit from promiscuous mode. In order to avoid adding forward declarations, move the VLAN related functions earlier in the file. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: fix a couple timeout loopsDan Carpenter2015-12-15
| | | | | | | | | | At the end of the loop we test "if (!count)" but because "count--" is a post-op then the loop will end with count set to -1. I have fixed this by changing it to --count. Fixes: c5aa9e3b8156 ('amd-xgbe: Initial AMD 10GbE platform driver') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller2015-11-01
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| * amd-xgbe: Fix race between access of desc and desc indexLendacky, Thomas2015-10-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During Tx cleanup it's still possible for the descriptor data to be read ahead of the descriptor index. A memory barrier is required between the read of the descriptor index and the start of the Tx cleanup loop. This allows a change to a lighter-weight barrier in the Tx transmit routine just before updating the current descriptor index. Since the memory barrier does result in extra overhead on arm64, keep the previous change to not chase the current descriptor value. This prevents the execution of the barrier for each loop performed. Suggested-by: Alexander Duyck <alexander.duyck@gmail.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller2015-10-24
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: net/ipv6/xfrm6_output.c net/openvswitch/flow_netlink.c net/openvswitch/vport-gre.c net/openvswitch/vport-vxlan.c net/openvswitch/vport.c net/openvswitch/vport.h The openvswitch conflicts were overlapping changes. One was the egress tunnel info fix in 'net' and the other was the vport ->send() op simplification in 'net-next'. The xfrm6_output.c conflicts was also a simplification overlapping a bug fix. Signed-off-by: David S. Miller <davem@davemloft.net>
| * amd-xgbe: Use wmb before updating current descriptor countLendacky, Thomas2015-10-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code currently uses the lightweight dma_wmb barrier before updating the current descriptor count. Under heavy load, the Tx cleanup routine was seeing the updated current descriptor count before the updated descriptor information. As a result, the Tx descriptor was being cleaned up before it was used because it was not "owned" by the hardware yet, resulting in a Tx queue hang. Using the wmb barrier insures that the descriptor is updated before the descriptor counter preventing the Tx queue hang. For extra insurance, the Tx cleanup routine is changed to grab the current decriptor count on entry and uses that initial value in the processing loop rather than trying to chase the current value. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Tested-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* | amd-xgbe: Simplify calculation and setting of queue fifosLendacky, Thomas2015-10-05
| | | | | | | | | | | | | | | | | | | | | | | | | | The calculation of the Tx and Rx fifo sizes can be calculated rather than hardcoded in a switch statement. Additionally, the per-queue fifo sizes can be calculated rather than hardcoded using if/else if statements that can possibly underutilize the available fifo area. Change the code to calculate the fifo sizes and the per-queue fifo sizes to simplify the code and make best use of the available fifo. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | amd-xgbe: Remove an unneeded semicolon on a switch statementLendacky, Thomas2015-10-05
|/ | | | | | | | Remove an unneeded semicolon at the end of a switch statement block. Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Fix DMA API debug warningLendacky, Thomas2015-07-08
| | | | | | | | | | | | | | | | When running a kernel configured with CONFIG_DMA_API_DEBUG=y a warning is issued: DMA-API: device driver tries to sync DMA memory it has not allocated This warning is the result of mapping the full range of the Rx buffer pages allocated and then performing a dma_sync_single_for_cpu against a calculated DMA address. The proper thing to do is to use the dma_sync_single_range_for_cpu with a base DMA address and an offset. Reported-by: Kim Phillips <kim.phillips@arm.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Tested-by: Kim Phillips <kim.phillips@arm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Move the PHY support into amd-xgbeLendacky, Thomas2015-05-15
| | | | | | | | | | | | | The AMD XGBE device is intended to work with a specific integrated PHY and that PHY is not meant to be a standalone PHY for use by other devices. As such this patch removes the phylib driver and implements the PHY support in the amd-xgbe driver (the majority of the logic from the phylib driver is moved into the amd-xgbe driver). Update the driver version to 1.0.1. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add netif_* message support to the driverLendacky, Thomas2015-05-15
| | | | | | | | | Add support for the network interface message level settings for determining whether to issue some of the driver messages. Make use of the netif_* interface where appropriate. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add additional stats to be reported via ethtoolLendacky, Thomas2015-05-15
| | | | | | | | | Add additional/extended statistics beyond what is provided by the hardware to be reported via ethtool. The new stats focus on the calls into ndo_start_xmit and the napi_poll routine. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Move Rx mode configuration into initLendacky, Thomas2015-04-09
| | | | | | | | | | | Currently a call to configure the Rx mode (promiscuous mode, all multicast mode, etc.) is made in xgbe_start separate from the xgbe_init function. This call to set the Rx mode should be part of the xgbe_init function so that calls to the init function don't have to be preceded with calls to configure the Rx mode. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Allow rx-frames coalescing to be changed anytimeLendacky, Thomas2015-04-09
| | | | | | | | | | | | Currently the device must be down in order to update the rx-frames coalescing setting because the interrupt indicator is set in the descriptor data during initialization. Allow this setting to be changed while the device is up by moving the interrupt decision into the descriptor reset function and base the decision off of the supplied descriptor index value. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Remove Tx coalescingLendacky, Thomas2015-03-20
| | | | | | | | | | | | | | | The Tx coalescing support in the driver was a software implementation for something lacking in the hardware. Using hrtimers, the idea was to trigger a timer interrupt after having queued a packet for transmit. Unfortunately, as the timer value was lowered, the timer expired before the hardware actually did the transmit and so it was racey and resulted in unnecessary interrupts. Remove the Tx coalescing support and hrtimer and replace with a Tx timer that is used as a reclaim timer in case of inactivity. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Use the new DMA memory barriers where appropriateLendacky, Thomas2015-03-20
| | | | | | | | Use the new lighter weight memory barriers when working with the device descriptors. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Clarify output message about queuesLendacky, Thomas2015-03-20
| | | | | | | | | Clarify that the queues referred to in a message when the device is brought up are hardware queues and not necessarily related to the Linux network queues. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller2015-01-27
|\ | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/boot/dts/imx6sx-sdb.dts net/sched/cls_bpf.c Two simple sets of overlapping changes. Signed-off-by: David S. Miller <davem@davemloft.net>
| * amd-xgbe: Use proper Rx flow control registerLendacky, Thomas2015-01-24
| | | | | | | | | | | | | | | | | | | | | | Updated hardware documention shows the Rx flow control settings were moved from the Rx queue operation mode register to a new Rx queue flow control register. The old flow control settings are now reserved areas of the Rx queue operation mode register. Update the code to use the new register. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | amd-xgbe: Add ACPI supportLendacky, Thomas2015-01-16
| | | | | | | | | | | | | | | | | | Add support for ACPI to the amd-xgbe and amd-xgbe-phy drivers. This support converts many of the device tree APIs to the new device_property APIs. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | amd-xgbe-phy: Change auto-negotiation logicLendacky, Thomas2015-01-16
| | | | | | | | | | | | | | | | | | | | | | | | The auto negotiation logic was geared to being the initiator of the auto negotiation. This presented problems when auto negotiation was initiated by the remote end. Change the auto negotiation logic to make use of the auto negotiation event interrupt thus allowing the auto negotiation state machine to function properly in either scenario. This also removes the polling during auto-negotiation. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | amd-xgbe: Remove need for Tx path spinlockLendacky, Thomas2015-01-16
| | | | | | | | | | | | | | | | | | | | | | | | Since the Tx ring cleanup can run at the same time that data is being transmitted, a spin lock was used to protect the ring. This patch eliminates the need for Tx spinlocks by updating the current ring position only after all ownership bits for data being transmitted have been set. This will insure that ring operations in the Tx cleanup path do not interfere with the ring operations in the Tx transmit path. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | amd-xgbe: Clear all state during a device restartLendacky, Thomas2015-01-16
|/ | | | | | | | | | | When performing a device restart, like during an MTU change, sometimes the device queues still have data and get hung up trying to flush resulting in the device becoming unresponsive until brought down and back up. To prevent this, always perform a device reset during a restart. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add support for the skb->xmit_more flagLendacky, Thomas2014-11-21
| | | | | | | | Add support to delay telling the hardware about data that is ready to be transmitted if the skb->xmit_more flag is set. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Perform Tx coalescing on a packet basisLendacky, Thomas2014-11-21
| | | | | | | | | | | The current form of Tx coalescing works on a descriptor basis instead of on a packet basis and doesn't take into account TSO packets. Update the Tx coalescing support to work on a packet basis, taking into account the number of packets associated with a TSO transmit. Also, only activate the Tx timer if a timer value is set. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add BQL supportLendacky, Thomas2014-11-21
| | | | | | | | | Call the appropriate BQL functions to track the number of bytes queued during Tx processing and to track the number of packets and bytes that have been transmitted during Tx complete processing. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Separate Tx/Rx ring data fields into new structsLendacky, Thomas2014-11-21
| | | | | | | | | Move the Tx and Rx related fields within the xgbe_ring_data struct into their own structs in order to more easily see what fields are used for each operation. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Incorporate Smatch coding suggestionLendacky, Thomas2014-11-21
| | | | | | | | | | | | The Smatch tool indicated that one of the if statements in xgbe-dev.c could be rewritten to remove a redundant check for the 'err' variable in an if statement. Change the statement as suggested and add a comment to help clarify. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Tx engine must not be active before stopping itLendacky, Thomas2014-11-21
| | | | | | | | | | | | | | | If the Tx engine is told to stop while it is actively processing Tx descriptors it is possible that the Tx descriptor(s) will not be closed out properly. When the Tx engine is restarted this could result in the driver being stuck on the improperly closed descriptor. Update the driver to wait for the Tx engine to be in a stopped or suspended state before issuing the stop command. This has not been an issue to date, but it's a good safe-guard to have. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add a read memory barrier to Tx/Rx pathLendacky, Thomas2014-11-21
| | | | | | | | | | | Add a read memory barrier to the Tx and Rx paths where the ownership bit is checked to be sure that all descriptor fields are read after having read the ownership bit for the descriptor. This has not been an issue to date, but it's a good safe-guard to have. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: fix ->rss_hash_typeDan Carpenter2014-11-13
| | | | | | | | | There was a missing break statement so we set everything to PKT_HASH_TYPE_L3 even when we intended to use PKT_HASH_TYPE_L4. Fixes: 5b9dfe299e55 ('amd-xgbe: Provide support for receive side scaling') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* amd-xgbe: Add receive side scaling ethtool supportLendacky, Thomas2014-11-05
| | | | | | | | This patch adds support for ethtool receive side scaling (RSS) commands. Support is added to get/set the RSS hash key and the RSS lookup table. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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