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* mtd: spi-nor: re-name OPCODE_* to SPINOR_OP_*Brian Norris2014-04-14
| | | | | | | | | Qualify these with a better namespace, and prepare them for use in more drivers. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Huang Shijie <b32955@freescale.com>
* mtd: spi-nor: add the copyright informationHuang Shijie2014-04-14
| | | | | | | Add the copyright information for spi-nor.c and spi-nor.h. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Add support for Macronix MX25L3255EAngus Clark2014-04-14
| | | | | | | | | | | | This patch adds support for the Macronix MX25L3255E device. Unlike the other Macronix devices we have seen, this device supports WRITE_1_4_4 at reasonable frequencies. Rather than masking out WRITE_1_4_4 support altogether, we now rely on the table parameters to indicate whether or not WRITE_1_4_4 should be used. Signed-off-by: Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Add Spansion S25FL032P to device tableAngus Clark2014-04-14
| | | | | | | | Add Spansion S25FL032P to the list of known devices. Signed-off-by: Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Refactor status register operationsAngus Clark2014-04-14
| | | | | | | | | | | | | | | | This patch refactors the fsm_read_status() and fsm_write_status() code to support 1 or 2 byte operations, with a specified command. This allows us to remove device/register specific code, such as the N25Q fsm_wrvcr() function. The 'QE' configuration code is updated accordingly, with minor tweaks to ensure the register values are only written if actually required. One notable change in this area is that the 'W25Q_STATUS_QE' bit-field is now defined with respect to the 'SR2' register, rather than the combined 'SR1+SR2' register which is only used for write operations. Signed-off-by: Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Update Macronix 'QE' configurationAngus Clark2014-04-14
| | | | | | | | | Update the configuration of the Macronix 'QE' bit, such that we only set or clear the bit if required. Signed-off-by: Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Update Macronix 32-bit addressing supportAngus Clark2014-04-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support for the Macronix 32-bit addressing scheme was originally developed using the MX25L25635E device. As is often the case, it was found that the presence of a "WAIT" instruction was required for the "EN4B/EX4B" FSM Sequence to complete. (It is known that the SPI FSM Controller makes certain undocumented assumptions regarding what constitutes a valid sequence.) However, further testing suggested that a small delay was required after issuing the "EX4B" command; without this delay, data corruptions were observed, consistent with the device not being ready to retrieve data. Although the issue was not fully understood, the workaround of adding a small delay was implemented, while awaiting clarification from Macronix. The same behaviour has now been found with a second Macronix device, the MX25L25655E. However, with this device, it seems that the delay is also required after the 'EN4B' commands. This discovery has prompted us to revisit the issue. Although still not conclusive, further tests have suggested that the issue is down to the SPI FSM Controller, rather than the Macronix devices. Furthermore, an alternative workaround has emerged which is to set the WAIT time to 0x00000001, rather then 0x00000000. (Note, the WAIT instruction is used purely for the purpose of achieving "sequence validity", rather than actually implementing a delay!) The issue is now being investigated by the Design and Validation teams. In the meantime, we implement the alternative workaround, which reduces the effective delay from 1us to 1ns. Signed-off-by: Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: st_spi_fsm: Add Macronix MX25L25655E deviceAngus Clark2014-04-14
| | | | | | | | Add Macronix MX25L25655E to the list of known devices. Signed-off-by: Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: spi-nor: EXPORT symbols which could be used by module driversBrian Norris2014-04-14
| | | | | | | | | | | Fix errors like this: ERROR: "spi_nor_ids" [drivers/mtd/devices/m25p80.ko] undefined! ERROR: "spi_nor_scan" [drivers/mtd/devices/m25p80.ko] undefined! make[1]: *** [__modpost] Error 1 make: *** [modules] Error 2 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: spi-nor: Add Freescale QuadSPI driverHuang Shijie2014-04-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (0) What is the QuadSPI controller? The QuadSPI(Quad Serial Peripheral Interface) acts as an interface to one single or two external serial flash devices, each with up to 4 bidirectional data lines. (1) The QuadSPI controller is driven by the LUT(Look-up Table) registers. The LUT registers are a look-up-table for sequences of instructions. A valid sequence consists of four LUT registers. (2) The definition of the LUT register shows below: --------------------------------------------------- | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | --------------------------------------------------- There are several types of INSTRx, such as: CMD : the SPI NOR command. ADDR : the address for the SPI NOR command. DUMMY : the dummy cycles needed by the SPI NOR command. .... There are several types of PADx, such as: PAD1 : use a singe I/O line. PAD2 : use two I/O lines. PAD4 : use quad I/O lines. .... (3) Test this driver with the JFFS2 and UBIFS: For jffs2: ------------- #flash_eraseall /dev/mtd0 #mount -t jffs2 /dev/mtdblock0 tmp #bonnie++ -d tmp -u 0 -s 10 -r 5 For ubifs: ------------- #flash_eraseall /dev/mtd0 #ubiattach /dev/ubi_ctrl -m 0 #ubimkvol /dev/ubi0 -N test -m #mount -t ubifs ubi0:test tmp #bonnie++ -d tmp -u 0 -s 10 -r 5 Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: spi-nor: add a helper to find the spi_device_idHuang Shijie2014-04-14
| | | | | | | | | Add the spi_nor_match_id() to find the proper spi_device_id with the NOR flash's name in the spi_nor_ids table. Signed-off-by: Huang Shijie <b32955@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: m25p80: use the SPI nor frameworkBrian Norris2014-04-14
| | | | | | | | | | | | | Use the new SPI nor framework, and rewrite the m25p80: (0) remove all the NOR comands. (1) change the m25p->command to an array. (2) implement the necessary hooks, such as m25p80_read/m25p80_write. Tested with the m25p32. Signed-off-by: Huang Shijie <b32955@freescale.com> Acked-by: Marek Vasut <marex@denx.de> [Brian: rebased] Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* mtd: spi-nor: add the framework for SPI NORHuang Shijie2014-04-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch cloned most of the m25p80.c. In theory, it adds a new spi-nor layer. Before this patch, the layer is like: MTD ------------------------ m25p80 ------------------------ spi bus driver ------------------------ SPI NOR chip After this patch, the layer is like: MTD ------------------------ spi-nor ------------------------ m25p80 ------------------------ spi bus driver ------------------------ SPI NOR chip With the spi-nor controller driver(Freescale Quadspi), it looks like: MTD ------------------------ spi-nor ------------------------ fsl-quadspi ------------------------ SPI NOR chip New APIs: spi_nor_scan: used to scan a spi-nor flash. Signed-off-by: Huang Shijie <b32955@freescale.com> Acked-by: Marek Vasut <marex@denx.de> [Brian: rebased to include additional m25p_ids[] entry] Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* Merge tag 'for-linus-20140405' of git://git.infradead.org/linux-mtdLinus Torvalds2014-04-07
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MTD updates from Brian Norris: - A few SPI NOR ID definitions - Kill the NAND "max pagesize" restriction - Fix some x16 bus-width NAND support - Add NAND JEDEC parameter page support - DT bindings for NAND ECC - GPMI NAND updates (subpage reads) - More OMAP NAND refactoring - New STMicro SPI NOR driver (now in 40 patches!) - A few other random bugfixes * tag 'for-linus-20140405' of git://git.infradead.org/linux-mtd: (120 commits) Fix index regression in nand_read_subpage mtd: diskonchip: mem resource name is not optional mtd: nand: fix mention to CONFIG_MTD_NAND_ECC_BCH mtd: nand: fix GET/SET_FEATURES address on 16-bit devices mtd: omap2: Use devm_ioremap_resource() mtd: denali_dt: Use devm_ioremap_resource() mtd: devices: elm: update DRIVER_NAME as "omap-elm" mtd: devices: elm: configure parallel channels based on ecc_steps mtd: devices: elm: clean elm_load_syndrome mtd: devices: elm: check for hardware engine's design constraints mtd: st_spi_fsm: Succinctly reorganise .remove() mtd: st_spi_fsm: Allow loop to run at least once before giving up CPU mtd: st_spi_fsm: Correct vendor name spelling issue - missing "M" mtd: st_spi_fsm: Avoid duplicating MTD core code mtd: st_spi_fsm: Remove useless consts from function arguments mtd: st_spi_fsm: Convert ST SPI FSM (NOR) Flash driver to new DT partitions mtd: st_spi_fsm: Move runtime configurable msg sequences into device's struct mtd: st_spi_fsm: Supply the W25Qxxx chip specific configuration call-back mtd: st_spi_fsm: Supply the S25FLxxx chip specific configuration call-back mtd: st_spi_fsm: Supply the MX25xxx chip specific configuration call-back ...
| * Fix index regression in nand_read_subpageRon2014-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 7351d3a5dbf42ba3299af71db3296be447bc1516 added an index variable as part of fixing checkpatch warnings, presumably as a tool to make some long lines shorter, however it only set that index in the case of there being no gaps in eccpos for the fragment being read. Which means the later step of filling ecccode from oob_poi will use the wrong indexing into eccpos in that case. This patch restores the behaviour that existed prior to that change. Signed-off-by: Ron Lee <ron@debian.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: diskonchip: mem resource name is not optionalSasha Levin2014-03-31
| | | | | | | | | | | | | | | | | | | | | | Passing a name to request_mem_region() isn't optional and can't just be NULL. Passing NULL causes a NULL ptr deref later in the boot process. Signed-off-by: Sasha Levin <sasha.levin@oracle.com> Tested-by: Alexander Shiyan <shc_work@mail.ru> Cc: <stable@vger.kernel.org> # 3.14 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: nand: fix mention to CONFIG_MTD_NAND_ECC_BCHErico Nunes2014-03-26
| | | | | | | | | | | | | | | | | | | | | | | | Mention to CONFIG_MTD_ECC_BCH in the warning message can be confusing as this doesn't match the exact name of the configuration option. This warning showed up once to me when I was starting to set up BCH. After checking my .config file, it took a moment before realizing it is CONFIG_MTD_NAND_ECC_BCH instead of CONFIG_MTD_ECC_BCH. Signed-off-by: Erico Nunes <nunes.erico@gmail.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: omap2: Use devm_ioremap_resource()Jingoo Han2014-03-26
| | | | | | | | | | | | | | | | | | | | | | Use devm_ioremap_resource() in order to make the code simpler, and remove redundant return value check of platform_get_resource() because the value is checked by devm_ioremap_resource(). Also, 'unsigned long mem_size' is removed from 'struct omap_nand_info', because the 'mem_size' variable is not necessary anymore. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: denali_dt: Use devm_ioremap_resource()Jingoo Han2014-03-26
| | | | | | | | | | | | | | | | | | | | | | Use devm_ioremap_resource() in order to make the code simpler, and remove redundant return value check of platform_get_resource_byname() because the value is checked by devm_ioremap_resource(). Signed-off-by: Jingoo Han <jg1.han@samsung.com> Tested-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: devices: elm: update DRIVER_NAME as "omap-elm"Pekon Gupta2014-03-26
| | | | | | | | | | | | | | | | use "omap-elm" as DRIVER_NAME Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: devices: elm: configure parallel channels based on ecc_stepsPekon Gupta2014-03-26
| | | | | | | | | | | | | | | | | | | | | | | | ELM hardware can process up to maximum of 8 hannels in parallel for ECC error detection. Currently the number of channels getting configured for processing is static determined by macro ERROR_VECTOR_MAX. However, the actual number of channels that need to be processed is the ECC step number. This patch just avoids configuring extra unused channels. Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: devices: elm: clean elm_load_syndromePekon Gupta2014-03-26
| | | | | | | | | | | | | | | | | | | | This patch refactors elm_load_syndrome() to make it scalable for newer ECC schemes by removing scheme specific macros (like ECC_BYTES*xx), and instead using ECC control information passed during elm_config. Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: devices: elm: check for hardware engine's design constraintsPekon Gupta2014-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ELM hardware engine is used by BCH ecc-schemes for detecting and locating ECC errors. This patch adds the following checks for ELM hardware engine: - ELM internal buffers are of 1K, so it cannot process data with ecc-step-size > 1K. - ELM engine can execute upto maximum of 8 threads in parallel, so in *page-mode* (when complete page is processed in single iteration), ELM cannot support ecc-steps > 8. Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Succinctly reorganise .remove()Lee Jones2014-03-20
| | | | | | | | | | | | Reported-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Allow loop to run at least once before giving up CPULee Jones2014-03-20
| | | | | | | | | | | | Reported-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Correct vendor name spelling issue - missing "M"Lee Jones2014-03-20
| | | | | | | | | | | | Reported-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Avoid duplicating MTD core codeLee Jones2014-03-20
| | | | | | | | | | | | Reported-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Remove useless consts from function argumentsLee Jones2014-03-20
| | | | | | | | | | | | | | Reported-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> [Brian: tweaked a bit] Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Convert ST SPI FSM (NOR) Flash driver to new DT partitionsLee Jones2014-03-20
| | | | | | | | | | | | | | | | | | | | | | The old API expected a "partitions" property provided a phandle to a separate partitions node, which itself contained yet more nodes each representing one partition. The new API rids the requirement for the superfluous intermediary partitions node. This patch provides the added information required for automatic parsing by the core. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Move runtime configurable msg sequences into device's structLee Jones2014-03-20
| | | | | | | | | | | | | | | | | | | | | | | | | | Until now the dynamically configurable message sequences for read, write and enable 32bit addressing have been global. Brian makes a good point why this should not be the case. If there are ever two FSM's located on the same platform, we could be potentially introducing a race condition on "needlessly shared data". Suggested-by: Brian Norris <computersforpeace@gmail.com> Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Supply the W25Qxxx chip specific configuration call-backLee Jones2014-03-20
| | | | | | | | | | | | Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Supply the S25FLxxx chip specific configuration call-backLee Jones2014-03-20
| | | | | | | | | | | | | | | | | | | | | | This patch allows us to prepare some of the message sequences which will be required to talk to the S25FLxxx family of Serial Flash devices. It also allows us to do some required extra operations after any busy wait failures. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Supply the MX25xxx chip specific configuration call-backLee Jones2014-03-20
| | | | | | | | | | | | Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Add the ability to write to FSM's status registerLee Jones2014-03-20
| | | | | | | | | | | | Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Add the ability to read the FSM's statusLee Jones2014-03-20
| | | | | | | | | | | | Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Erase partly or as a whole a Serial Flash deviceLee Jones2014-03-20
| | | | | | | | | | | | | | | | | | | | | | When an erase is requested by userspace the MTD framework calls back into the driver to conduct the actual command issue. Here we provide the routines which do exactly that. We can choose to either do an entire chip erase or by sector. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Supply a busy wait for post-write statusLee Jones2014-03-20
| | | | | | | | | | | | | | | | | | | | When we write data to the Serial Flash chip we'll wait a predetermined period of time before giving up. During that period of time we poll the status register until completion. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Write to Flash via the FSM FIFOLee Jones2014-03-20
| | | | | | | | | | | | | | | | | | When we write data to the FIFO the FSM Controller subsequently writes that data out to the Serial Flash chip. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Add the ability to read from a Serial Flash deviceLee Jones2014-03-20
| | | | | | | | | | | | | | | | | | | | When a read is issued by userspace the MTD framework calls back into the driver to conduct the actual command issue and data extraction. Here we provide the routines which do exactly that. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Prepare default sequences for read/write/eraseLee Jones2014-03-20
| | | | | | | | | | | | | | | | | | | | | | Most chips require a predefined set of FSM message sequences for read, write and erase operations. This patch provides a way to set them up, which it will do so if a chip specific initialisation routine isn't been provided. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Supply the N25Qxxx chip specific configuration call-backLee Jones2014-03-20
| | | | | | | | | | | | | | | | | | | | | | | | | | In the FSM driver we handle chip differences by providing the possibility of calling back into a chip specific initialisation routine. In this patch we provide one for the N25Qxxx series, which endeavours to setup things like the read, write and erase sequences, as they differ from the default. We also configure 32bit support and the amount of dummy cycles to use. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Supply the N25Qxxx specific read configurationsLee Jones2014-03-20
| | | | | | | | | | | | | | | | | | | | The N25Qxxx Serial Flash devices required different sequence configurations depending on whether they're running in 24bit (3Byte) or 32bit (4Byte) mode. We provide those here. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Provide the default read/write configurationsLee Jones2014-03-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Message sequences can vary depending on how many pads (lines) are required to address the chip (mode & dummy), how many data pads (lines) are required to write out to the chip which will determine speed amongst other things which are detailed by the SFDP specification. We are able to use multiple configurations for each chip, but they need to me matched to a device's capabilities. These configurations are listed in preference order - most preferred first. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Update the flash Volatile Configuration RegisterLee Jones2014-03-20
| | | | | | | | | | | | | | | | | | | | The FSM Serial Flash Controller is driven by issuing a standard set of register writes we call a message sequence. This patch supplies a method to prepare the message sequence responsible for updating a chip's VCR. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Provide a method to put the chip into 32bit addressing modeLee Jones2014-03-20
| | | | | | | | | | | | | | | | | | | | | | | | Most Serial Flash chips support 24bit addressing as a default but more recent incarnations can support 32bit. Based on information provided though platform specific data and capabilities we can determine whether or not our current chip can. This patch provides a means to setup the FSM message sequence to put the chip into 32bit mode. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Add a check to if the chip can handle an SoC resetLee Jones2014-03-20
| | | | | | | | | | | | | | | | | | | | | | Based on information we can obtain though platform specific data and/or chip capabilities we are able to determine whether or not we can handle a SoC reset or not. To find out why this is important please read the comment provided in the patch. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Prepare read/write sequences according to configurationLee Jones2014-03-20
| | | | | | | | | | | | | | | | | | | | Firstly we search for our preference read/write configuration based on a given chip's capabilities. Then we actually set up the message sequence accordingly. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Provide the sequence for enabling 32bit addressing modeLee Jones2014-03-20
| | | | | | | | | | | | | | | | | | | | | | The FSM Serial Flash Controller is driven by issuing a standard set of register writes we call a message sequence. This patch supplies a method to prepare the message sequence responsible for setting 32bit addressing mode on the Flash chip. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Provide the erase one sector sequenceLee Jones2014-03-20
| | | | | | | | | | | | | | | | | | | | The FSM Serial Flash Controller is driven by issuing a standard set of register writes we call a message sequence. This patch supplies a method to prepare the message sequence responsible for erasing a single sector. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: st_spi_fsm: Fetch boot-device from mode pinsLee Jones2014-03-20
| | | | | | | | | | | | | | | | | | | | | | | | It's important for us to determine which device was used to boot from in order to make some correct decisions surrounding Power Management. On each of the platforms which support the FSM this is communicated via a set of mode pins held in the system configuration area. This patch determine the boot device and stores the result. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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