aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/mmc/host
Commit message (Collapse)AuthorAge
...
| * mmc: sdhci: Add sdhci_read_caps()Adrian Hunter2016-07-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add sdhci_read_caps() and __sdhci_read_caps() to make it easier for drivers to fix the version and capabilities registers. Pedantically, the SDHCI specification states that the capabilities registers are valid when the host controller resets the Software Reset For All bit. That requirement has always been satisfied by performing a reset at the start of initialization, and consequently that is now part of the new functions. Although the SDHCI_QUIRK_MISSING_CAPS quirk has not yet been removed, drivers that want to provide their own caps can now use these functions instead of that quirk. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci: Tidy caps variables in sdhci_setup_host()Adrian Hunter2016-07-25
| | | | | | | | | | | | | | In preparation for adding a function to read the capability registers. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci: Make signal voltage support explicitAdrian Hunter2016-07-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signal voltage support is not a quirk, it is a capability. According to the SDHCI specification, support for 1.8V signaling is determined by the presence of one of the capability bits SDHCI_SUPPORT_SDR50, SDHCI_SUPPORT_SDR104, or SDHCI_SUPPORT_DDR50. This is complicated by also supporting eMMC which has 1.8V modes and 1.2V modes. It would be possible to use the transfer mode to determine signal voltage support, except for eMMC DDR52 mode which uses the same capability (MMC_CAP_1_8V_DDR) for 1.8V signaling and 3V signaling. In addition, the mmc core will fail over from one signaling voltage to the next (refer mmc_power_up()) which means SDHCI really needs to validate which voltages are actually supported. Introduce SDHCI flags for signal voltage support and set them based on the supported transfer modes. In general, drivers should prefer to set the supported transfer modes correctly rather than change the signal voltage capability, except in the case where 3V DDR52 is supported but 1.8V is not. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci: Split sdhci_add_host()Adrian Hunter2016-07-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split sdhci-add_host() in order to further our objective to make sdhci into a library. The split divides code that sets up mmc and sdhci parameters, from code that actually activates things - such as tasklet initialization, requesting the irq, and adding (and starting) the host. This gives drivers an opportunity to change various settings before committing to start the host. Drivers can continue to call sdhci_add_host() but drivers that want to take advantage of the split instead call sdhci_setup_host() followed by __sdhci_add_host(). Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci: Do not call implementations of mmc host ops directlyAdrian Hunter2016-07-25
| | | | | | | | | | | | | | | | | | | | Drivers must be able to provide their own implementations for mmc host operations. Consequently, SDHCI should call those not the default implementations. Do that by calling indirectly through the mmc host ops function pointers. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: mediatek: perfer to use rise edge latchingChaotian Jing2016-07-25
| | | | | | | | | | | | | | | | in our host design, rise edge latching is more stable than fall edge latching. so that if rise edge has enough margin, no need scan fall edge. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: mediatek: fix CMD21/CMD19 timeout issueChaotian Jing2016-07-25
| | | | | | | | | | | | | | | | | | | | | | | | | | we did not deal with the read data of CMD21/CMD19 if there is response CRC error of CMD21/CMD19, in this case, eMMC/SD may still in send-data state. therefore, all of next commands cannot get response as device is not in transfer state. for resolving this issue, still need deal with the data receive to make device back to transfer state. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: mediatek: fix CRC error when calling mmc_select_hs400()Chaotian Jing2016-07-25
| | | | | | | | | | | | | | | | | | the tune result of hs200 mode at 200Mhz is not suitable for 50Mhz, mmc_select_hs400() will set clock frequency to 50Mhz, use defalut tune setting for 50Mhz to avoid CRC error. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: mediatek: do not tune data for HS400 modeChaotian Jing2016-07-25
| | | | | | | | | | | | | | | | | | | | for hs400 mode, should only tune DS delay, should not tune PAD_TUNE for data path. if eMMC will run at hs400 mode, do not tune data while call ops->execute_tuning(). Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: dw_mmc: fix unmap sg twice when finding data errShawn Lin2016-07-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DATA_OVER(the same for RI/TI of IDMAC) interrupt may come up together with data error interrupts. If so, the interrupt routine set EVENT_DATA_ERR to the pending_events and schedule the tasklet but we may still fallback to the IDMAC interrupt case as the tasklet may come up a little late, namely right after the IDMAC interrupt checking. This will casue dw_mmc unmap sg twice. We can easily see it with CONFIG_DMA_API_DEBUG enabled. WARNING: CPU: 0 PID: 0 at lib/dma-debug.c:1096 check_unmap+0x7bc/0xb38 dwmmc_exynos 12200000.mmc: DMA-API: device driver tries to free DMA memory it has not allocated [device address=0x000000006d9d2200] [size=128 bytes] Modules linked in: CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.7.0-rc4 #26 Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) [<c0112b4c>] (unwind_backtrace) from [<c010d888>] (show_stack+0x20/0x24) [<c010d888>] (show_stack) from [<c03fab0c>] (dump_stack+0x80/0x94) [<c03fab0c>] (dump_stack) from [<c0123548>] (__warn+0xf8/0x110) [<c0123548>] (__warn) from [<c01235a8>] (warn_slowpath_fmt+0x48/0x50) [<c01235a8>] (warn_slowpath_fmt) from [<c042ac90>] (check_unmap+0x7bc/0xb38) [<c042ac90>] (check_unmap) from [<c042b25c>] (debug_dma_unmap_sg+0x118/0x148) [<c042b25c>] (debug_dma_unmap_sg) from [<c077512c>] (dw_mci_dma_cleanup+0x7c/0xb8) [<c077512c>] (dw_mci_dma_cleanup) from [<c0773f24>] (dw_mci_stop_dma+0x40/0x50) [<c0773f24>] (dw_mci_stop_dma) from [<c0777d04>] (dw_mci_tasklet_func+0x130/0x3b4) [<c0777d04>] (dw_mci_tasklet_func) from [<c0129760>] (tasklet_action+0xb4/0x150) ..[snip].. ---[ end trace 256f83eed365daf0 ]--- Reported-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: dw_mmc: add the card write threshold for HS400 modeJaehoon Chung2016-07-25
| | | | | | | | | | | | | | | | | | | | | | | | | | Since v2.80a, dwmmc controller introduced the card write threshold for HS400 mode. So CardThrCtl can be supported during write operation, not only read operation. (Note: Only use the write threshold when mode is HS400.) To use more compatible, removed "_rd_" from function name. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: dw_mmc: remove the quirks flagsJaehoon Chung2016-07-25
| | | | | | | | | | | | | | | | | | | | | | Remove the quirks flag. (DW_MCI_QUIRK_BROKEN_DTO) For removing this, enabled the dto_timer by defaults. It doesn't see any I/O performance degression. In future, dwmmc controller should not use the quirks flag. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: dw_mmc: exynos: fix the NULL pointer dereference errorJaehoon Chung2016-07-25
| | | | | | | | | | | | | | | | "host->cur_slot" should be assigned to start the request. So it can be the NULL pointer. This patch fixed this error. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: dw_mmc: remove UBSAN warning in dw_mci_setup_bus()Seung-Woo Kim2016-07-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes following UBSAN warnings in dw_mci_setup_bus(). UBSAN: Undefined behaviour in drivers/mmc/host/dw_mmc.c:1102:14 shift exponent 250 is too large for 32-bit type 'unsigned int' Call trace: [<ffffff90080908a8>] dump_backtrace+0x0/0x380 [<ffffff9008090c3c>] show_stack+0x14/0x20 [<ffffff90087457b8>] dump_stack+0xe0/0x120 [<ffffff90087b1360>] ubsan_epilogue+0x18/0x68 [<ffffff90087b1a94>] __ubsan_handle_shift_out_of_bounds+0x18c/0x1bc [<ffffff9008d89cb8>] dw_mci_setup_bus+0x3a0/0x438 [...] UBSAN: Undefined behaviour in drivers/mmc/host/dw_mmc.c:1132:27 shift exponent 250 is too large for 32-bit type 'unsigned int' Call trace: [<ffffff90080908a8>] dump_backtrace+0x0/0x380 [<ffffff9008090c3c>] show_stack+0x14/0x20 [<ffffff90087457b8>] dump_stack+0xe0/0x120 [<ffffff90087b1360>] ubsan_epilogue+0x18/0x68 [<ffffff90087b1a94>] __ubsan_handle_shift_out_of_bounds+0x18c/0x1bc [<ffffff9008d89c9c>] dw_mci_setup_bus+0x384/0x438 [...] The warnings are caused because of bit shift which is used to filter spamming message for CONFIG_MMC_CLKGATE, but the config is already removed. So this patch just removes the shift. Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: dw_mmc: Wait for data transfer after response errors.Doug Anderson2016-07-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the DesignWare state machine description, after we get a "response error" or "response CRC error" we move into data transfer mode. That means that we don't necessarily need to special case trying to deal with the failure right away. We can wait until we are notified that the data transfer is complete (with or without errors) and then we can deal with the failure. It may sound strange to defer dealing with a command that we know will fail anyway, but this appears to fix a bug. During tuning (CMD19) on a specific card on an rk3288-based system, we found that we could get a "response CRC error". Sending the stop command after the "response CRC error" would then throw the system into a confused state causing all future tuning phases to report failure. When in the confused state, the controller would show these (hex codes are interrupt status register): CMD ERR: 0x00000046 (cmd=19) CMD ERR: 0x0000004e (cmd=12) DATA ERR: 0x00000208 DATA ERR: 0x0000020c CMD ERR: 0x00000104 (cmd=19) CMD ERR: 0x00000104 (cmd=12) DATA ERR: 0x00000208 DATA ERR: 0x0000020c ... ... It is inherently difficult to deal with the complexity of trying to correctly send a stop command while a data transfer is taking place since you need to deal with different corner cases caused by the fact that the data transfer could complete (with errors or without errors) during various places in sending the stop command (dw_mci_stop_dma, send_stop_abort, etc) Instead of adding a bunch of extra complexity to deal with this, it seems much simpler to just use the more straightforward (and less error-prone) path of letting the data transfer finish. There shouldn't be any huge benefit to sending the stop command slightly earlier, anyway. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Cc: Alim Akhtar <alim.akhtar@gmail.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: dw_mmc: fix 32bit little-endian access of des1 fieldBen Dooks2016-07-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IDMAC_SET_BUFFER1_SIZE() macro modifies des1, but does not check if the value being passed is big or little endian desptire the des1 field being marked as __le32. Fix the issue by ensuring the values are changed from the cpu endian to the descriptor endian by using cpu_to_le32. Spotted whilst doing big endian conversion work on Exynos, and stops the mmc worker thread from stalling. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Tested-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: dw_mmc: Consider HLE errors to be data and command errorsDoug Anderson2016-07-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dw_mmc driver enables HLE errors as part of DW_MCI_ERROR_FLAGS but nothing in the interrupt handler actually handles them and ACKs them. That means that if we ever get an HLE error we'll just keep getting interrupts and we'll wedge things. We really don't expect HLE errors but if we ever get them we shouldn't silently ignore them. Note that I have seen HLE errors while constantly ejecting and inserting cards (ejecting while inserting, etc). Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: dw_mmc: k3: add MMC_CAP_CMD23Jérôme Forissier2016-07-25
| | | | | | | | | | | | | | | | | | Enables RPMB support for the on-board eMMC of the HiKey board as well as for eMMC modules connected to the microSD slot. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: dw_mmc: check card present before starting requestShawn Lin2016-07-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The main reason to add this check is to avoid unnecessary mmc_request like the on-going cmd and the corresponding sbc if the card is removed. Although we have already checked this in dw_mci_handle_cd for runtime usage of sd card and dw_mci_init_slot for noremovable devices, but there is a timing gap before it really calls dw_mci_get_cd as mmc_detect_change needs some delay here. Another gain here is that we could save some checkings of card status after sd card been removed. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: dw_mmc: remove redundant of set_bit and clear_bitShawn Lin2016-07-25
| | | | | | | | | | | | | | | | | | dw_mci_get_cd have already dealt with these for both of internal card-detect and gpio card-detect. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sh_mmcif: Use a 10s timeout in the error recovery pathUlf Hansson2016-07-25
| | | | | | | | | | | | | | | | | | The current value means an mdelay(1) may execute up to 10000000 times, which translates to around ~2.8 hours. This is probably not what the orignal author had in mind. Let's instead use 10s, which is the same value sh_mmcif is using for other timeouts. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sh_mmcif: Inform the mmc core about the max busy timeoutUlf Hansson2016-07-25
| | | | | | | | | | | | | | | | The sh_mmcif driver is already using a 10s request timeout. Let's also inform the mmc core about this value, as there are situations when it needs to know about it. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sh_mmcif: Use response type to know when to enable busy detectionUlf Hansson2016-07-25
| | | | | | | | | | | | | | | | | | | | | | | | | | The sh_mmcif explicity checks for certain commands to decide when to enable HW busy detection. Instead, it should only check the response type as it tells if busy detection is needed. In this way, the mmc core also gets full control whether it thinks busy detection should be done or not. In some specific scenarios, like for ERASE and STOP commands it may decide to fall back to use a CMD13 to poll the card status instead. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sh_mmcif: Enable MMC_CAP2_NO_SD and MMC_CAP2_NO_SDIOUlf Hansson2016-07-25
| | | | | | | | | | | | | | | | Enable the capabilities which tells the mmc core to prevent sending SD and SDIO commands during card initialization. In this way, we can also remove the validation of non-supported commands in the ->request() callback. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-msm: fix spelling mistake: "Perpheral" -> "Peripheral"Colin Ian King2016-07-25
| | | | | | | | | | | | | | | | trivial fix to spelling mistake in dev_err message Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci: use pr_err for sdhci_dumpregsChuanxiao Dong2016-07-25
| | | | | | | | | | | | | | | | | | | | sdhci_dumpregs is used to dump registers when error happens. Thus it should use pr_err instead of pr_debug to show more information about the hardware. Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> [Fix whitespace and checkpatch warnings] Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: host: use the defined function to check whether card is removableJaehoon Chung2016-07-25
| | | | | | | | | | | | | | | | | | In linux/mmc/host.h, mmc_card_is_removable() is already defined. It should be maintainted more easier than now. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-of-arasan: Add ability to export card clockDouglas Anderson2016-07-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SD/eMMC PHYs (like the PHY from Arasan that is designed to work with arasan,sdhci-5.1) need to know the card clock in order to function properly. Let's add the ability to expose this clock. Any PHY that needs to know the clock rate can add a reference and query the clock rate. At the moment we register a CLK_GET_RATE_NOCACHE clock that simply allows querying the clock. This allows us to be less intrusive with regards to the main SDHCI driver, which has complex logic for adjusting the SD clock. Right now we always fully power cycle the PHY when the clock changes and that gives the PHY a good chance to query our clock. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3399Douglas Anderson2016-07-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the the earlier change in this series ("Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg regs") we can see the mechansim for specifying a syscon to properly set corecfg registers in sdhci-of-arasan. Now let's use this mechanism to properly set corecfg_baseclkfreq on rk3399. >From [1] the corecfg_baseclkfreq is supposed to be set to: Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. This is a relatively easy thing to do. Note that we assume that xin_clk is not dynamic and we can check the clock at probe time. If any real devices have a dynamic xin_clk future patches could register for notifiers for the clock. At the moment, setting corecfg_baseclkfreq is only supported for rk3399 since we need a specific map for each implementation. The code is written in a generic way that should make this easy to extend to other SoCs. Note that a specific compatible string for rk3399 is already in use and so we add that to the table to match rk3399. [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-of-arasan: Always power the PHY off/on when clock changesDouglas Anderson2016-07-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit 802ac39a5566 ("mmc: sdhci-of-arasan: fix set_clock when a phy is supported") we added code to power the PHY off and on whenever the clock was changed but we avoided doing the power cycle code when the clock was low speed. Let's now do it always. Although there may be other reasons for power cycling the PHY when the clock changes, one of the main reasons is that we need to give the DLL a chance to re-lock with the new clock. One of the things that the DLL is for is tuning the Receive Clock in HS200 mode and STRB in HS400 mode. Thus it is clear that we should make sure we power cycle the PHY (and wait for the DLL to lock) when we know we'll be in one of these two speed modes. That's what the original code did, though it used the clock rate rather than the speed mode. However, even in speed modes other than HS200,/HS400 the DLL is used for something since it can be clearly observed that the PHY doesn't function properly if you leave the DLL off. Although it appears less important to power cycle the PHY and wait for the DLL to lock when not in HS200/HS400 modes (no bugs were reported), it still seems wise to let the locking always happen nevertheless. Note: as part of this, we make sure that we never try to turn the PHY on when the clock is off (when the clock rate is 0). The PHY cannot work when the clock is off since its DLL can't lock. This change requires ("phy: rockchip-emmc: Increase lock time allowance") and will cause problems if picked without that change. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-brcmstb: Add driver for Broadcom BRCMSTB SoCsAl Cooper2016-07-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SDHCI driver for Broadcom BRCMSTB SoCs. This driver works with all ARM based SoCs and the 7425, 7429 and 7435 MIPS based SoCs. The driver disables all UHS speed modes by default and relies on the Device Tree node properties to enable these modes for SoC/Board combinations that support them. Signed-off-by: Al Cooper <alcooperx@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-bcm2835: remove driverStefan Wahren2016-07-25
| | | | | | | | | | | | | | | | | | The sdhci-bcm2835 is no more needed since it has been replaced by sdhci-iproc. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci: Fix sdhci_card_busy()Adrian Hunter2016-07-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | host->card_busy() was introduced for SD voltage switching which checks all 4 data lines. Increasingly, host->card_busy is being used to poll the the busy signal which is only data line 0 (DAT[0]). The current logic in sdhci_card_busy() does not work in that case because it returns false if any of the data lines is high. It also ignores possibilities: - data lines 1-3 are not connected and could show at any level - data lines 1-2 can be used by SDIO for other purposes According to the SD specification, it is OK to check any of the data lines for voltage switching, so change to use DAT[0] only. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: tmio: make a cast explicitWolfram Sang2016-07-25
| | | | | | | | | | | | | | | | Sparse complains about the implicit cast. Making it explicit is indeed better coding style. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci-of-arasan: implement enhanced strobe callbackShawn Lin2016-07-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently sdhci-arasan 5.1 can support enhanced strobe function, and we now limit it just for "arasan,sdhci-5.1". Add mmc-hs400-enhanced-strobe in DT to enable the function if we're sure our controller can support it. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci: fix wakeup configurationLudovic Desroches2016-07-25
| | | | | | | | | | | | | | | | | | | | | | Activating wakeup event is not enough to get a wakeup signal. The corresponding events have to be enabled in the Interrupt Status Enable Register too. It follows the specification and is needed at least by sdhci-of-at91. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sdhci: remove comment regarding timeout during tuningSimon Horman2016-07-25
| | | | | | | | | | | | | | | | | | Since commit 7ce45e950624 ("mmc: sdhci: SD tuning is broken for some controllers") sdhci_execute_tuning() no longer includes a timeout in its loop counter(s) so remove portion of the comment regarding this. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * mmc: sh_mobile_sdhi: properly document R-Car versionsWolfram Sang2016-07-25
| | | | | | | | | | | | | | | | | | Replace hardcoded values with meaningful names and document what we know. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | Merge branch 'timers-core-for-linus' of ↵Linus Torvalds2016-07-25
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull timer updates from Thomas Gleixner: "This update provides the following changes: - The rework of the timer wheel which addresses the shortcomings of the current wheel (cascading, slow search for next expiring timer, etc). That's the first major change of the wheel in almost 20 years since Finn implemted it. - A large overhaul of the clocksource drivers init functions to consolidate the Device Tree initialization - Some more Y2038 updates - A capability fix for timerfd - Yet another clock chip driver - The usual pile of updates, comment improvements all over the place" * 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (130 commits) tick/nohz: Optimize nohz idle enter clockevents: Make clockevents_subsys static clocksource/drivers/time-armada-370-xp: Fix return value check timers: Implement optimization for same expiry time in mod_timer() timers: Split out index calculation timers: Only wake softirq if necessary timers: Forward the wheel clock whenever possible timers/nohz: Remove pointless tick_nohz_kick_tick() function timers: Optimize collect_expired_timers() for NOHZ timers: Move __run_timers() function timers: Remove set_timer_slack() leftovers timers: Switch to a non-cascading wheel timers: Reduce the CPU index space to 256k timers: Give a few structs and members proper names hlist: Add hlist_is_singular_node() helper signals: Use hrtimer for sigtimedwait() timers: Remove the deprecated mod_timer_pinned() API timers, net/ipv4/inet: Initialize connection request timers as pinned timers, drivers/tty/mips_ejtag: Initialize the poll timer as pinned timers, drivers/tty/metag_da: Initialize the poll timer as pinned ...
| * | timers: Remove set_timer_slack() leftoversThomas Gleixner2016-07-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We now have implicit batching in the timer wheel. The slack API is no longer used, so remove it. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Alan Stern <stern@rowland.harvard.edu> Cc: Andrew F. Davis <afd@ti.com> Cc: Arjan van de Ven <arjan@infradead.org> Cc: Chris Mason <clm@fb.com> Cc: David S. Miller <davem@davemloft.net> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Cc: Eric Dumazet <edumazet@google.com> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: George Spelvin <linux@sciencehorizons.net> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Jens Axboe <axboe@kernel.dk> Cc: John Stultz <john.stultz@linaro.org> Cc: Josh Triplett <josh@joshtriplett.org> Cc: Len Brown <lenb@kernel.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mathias Nyman <mathias.nyman@intel.com> Cc: Pali Rohár <pali.rohar@gmail.com> Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rik van Riel <riel@redhat.com> Cc: Sebastian Reichel <sre@kernel.org> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: linux-block@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mmc@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-usb@vger.kernel.org Cc: netdev@vger.kernel.org Cc: rt@linutronix.de Link: http://lkml.kernel.org/r/20160704094342.189813118@linutronix.de Signed-off-by: Ingo Molnar <mingo@kernel.org>
* | | Merge branch 'x86-platform-for-linus' of ↵Linus Torvalds2016-07-25
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 platform updates from Ingo Molnar: "The main changes in this cycle were: - Intel-SoC enhancements (Andy Shevchenko) - Intel CPU symbolic model definition rework (Dave Hansen) - ... other misc changes" * 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits) x86/sfi: Enable enumeration of SD devices x86/pci: Use MRFLD abbreviation for Merrifield x86/platform/intel-mid: Make vertical indentation consistent x86/platform/intel-mid: Mark regulators explicitly defined x86/platform/intel-mid: Rename mrfl.c to mrfld.c x86/platform/intel-mid: Enable spidev on Intel Edison boards x86/platform/intel-mid: Extend PWRMU to support Penwell x86/pci, x86/platform/intel_mid_pci: Remove duplicate power off code x86/platform/intel-mid: Add pinctrl for Intel Merrifield x86/platform/intel-mid: Enable GPIO expanders on Edison x86/platform/intel-mid: Add Power Management Unit driver x86/platform/atom/punit: Enable support for Merrifield x86/platform/intel_mid_pci: Rework IRQ0 workaround x86, thermal: Clean up and fix CPU model detection for intel_soc_dts_thermal x86, mmc: Use Intel family name macros for mmc driver x86/intel_telemetry: Use Intel family name macros for telemetry driver x86/acpi/lss: Use Intel family name macros for the acpi_lpss driver x86/cpufreq: Use Intel family name macros for the intel_pstate cpufreq driver x86/platform: Use new Intel model number macros x86/intel_idle: Use Intel family macros for intel_idle ...
| * | x86, mmc: Use Intel family name macros for mmc driverDave Hansen2016-06-08
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Another straightforward replacement of magic numbers. Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Dave Hansen <dave@sr71.net> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: jacob.jun.pan@intel.com Cc: linux-mmc@vger.kernel.org Link: http://lkml.kernel.org/r/20160603001951.9EEA53D8@viggo.jf.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
* / mmc: pxamci: fix potential oopsRobert Jarzmik2016-07-18
|/ | | | | | | | | | | | | | | | | | | | | | | | As reported by Dan in his report in [1], there is a potential NULL pointer derefence if these conditions are met : - there is no platform_data provided, ie. host->pdata = NULL Fix this by only using the platform data ro_invert when a gpio for read-only is provided by the platform data. This doesn't appear yet as every pxa board provides a platform_data, and calls pxa_set_mci_info() with a non NULL pointer. [1] [bug report] mmc: pxamci: fix card detect with slot-gpio API. The commit fd546ee6a7dc ("mmc: pxamci: fix card detect with slot-gpio API") from Sep 26, 2015, leads to the following static checker warning: drivers/mmc/host/pxamci.c:809 pxamci_probe() warn: variable dereferenced before check 'host->pdata' (see line 798) Fixes: fd546ee6a7dc ("mmc: pxamci: fix card detect with slot-gpio API") Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sunxi: Re-enable eMMC HS-DDR modes on Allwinner A80Chen-Yu Tsai2016-06-02
| | | | | | | | | Now the the HS-DDR mode clock timings have been corrected, we can re-enable these modes on the A80. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sunxi: Fix DDR MMC timings for A80Chen-Yu Tsai2016-06-02
| | | | | | | | | | | | | | | | | The MMC clock timings were incorrectly calculated, when the conversion from delay value to delay phase was done. The 50M DDR and 50M DDR 8bit timings are off, and make eMMC DDR unusable. Unfortunately it seems different controllers on the same SoC have different timings. The new settings are taken from mmc2, which is commonly used with eMMC. The settings for the slower timing modes seem to work despite being wrong, so leave them be. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* remove lots of IS_ERR_VALUE abusesArnd Bergmann2016-05-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most users of IS_ERR_VALUE() in the kernel are wrong, as they pass an 'int' into a function that takes an 'unsigned long' argument. This happens to work because the type is sign-extended on 64-bit architectures before it gets converted into an unsigned type. However, anything that passes an 'unsigned short' or 'unsigned int' argument into IS_ERR_VALUE() is guaranteed to be broken, as are 8-bit integers and types that are wider than 'unsigned long'. Andrzej Hajda has already fixed a lot of the worst abusers that were causing actual bugs, but it would be nice to prevent any users that are not passing 'unsigned long' arguments. This patch changes all users of IS_ERR_VALUE() that I could find on 32-bit ARM randconfig builds and x86 allmodconfig. For the moment, this doesn't change the definition of IS_ERR_VALUE() because there are probably still architecture specific users elsewhere. Almost all the warnings I got are for files that are better off using 'if (err)' or 'if (err < 0)'. The only legitimate user I could find that we get a warning for is the (32-bit only) freescale fman driver, so I did not remove the IS_ERR_VALUE() there but changed the type to 'unsigned long'. For 9pfs, I just worked around one user whose calling conventions are so obscure that I did not dare change the behavior. I was using this definition for testing: #define IS_ERR_VALUE(x) ((unsigned long*)NULL == (typeof (x)*)NULL && \ unlikely((unsigned long long)(x) >= (unsigned long long)(typeof(x))-MAX_ERRNO)) which ends up making all 16-bit or wider types work correctly with the most plausible interpretation of what IS_ERR_VALUE() was supposed to return according to its users, but also causes a compile-time warning for any users that do not pass an 'unsigned long' argument. I suggested this approach earlier this year, but back then we ended up deciding to just fix the users that are obviously broken. After the initial warning that caused me to get involved in the discussion (fs/gfs2/dir.c) showed up again in the mainline kernel, Linus asked me to send the whole thing again. [ Updated the 9p parts as per Al Viro - Linus ] Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Andrzej Hajda <a.hajda@samsung.com> Cc: Andrew Morton <akpm@linux-foundation.org> Link: https://lkml.org/lkml/2016/1/7/363 Link: https://lkml.org/lkml/2016/5/27/486 Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> # For nvmem part Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* mmc: sdhci-acpi: Remove MMC_CAP_BUS_WIDTH_TEST for Intel controllersAdrian Hunter2016-05-23
| | | | | | | | | The CMD19/CMD14 bus width test has been found to be unreliable in some cases. It is not essential, so simply remove it. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-pci: Remove MMC_CAP_BUS_WIDTH_TEST for Intel controllersAdrian Hunter2016-05-23
| | | | | | | | | The CMD19/CMD14 bus width test has been found to be unreliable in some cases. It is not essential, so simply remove it. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: dw_mmc: rockchip: Set the drive phase properlyDouglas Anderson2016-05-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Historically for Rockchip devices we've relied on the power-on default (or perhaps the firmware setting) to get the correct drive phase for dw_mmc devices. This worked OK for the most part, but: * Relying on the setting just "being right" is a bit fragile. * As soon as there is an instance where the power on default is wrong or where the firmware didn't configure this properly then we'll get a mysterious failure. In commit 7a03fe6f48f3 ("clk: rockchip: reset init state before mmc card initialization") we actually started setting this explicitly in the kernel, but that commit wasn't quite right and also wasn't quite enough. See <https://patchwork.kernel.org/patch/9085311/> for some details. Let's explicitly set this phase in dw_mmc. The comments inside this patch try to explain the situation quite throughly, but the high level overview of this is: Before this patch on rk3288 devices tested (after revert of the clock patch described above): * eMMC: 180 degrees * SDMMC/SDIO0/SDIO1: 90 degrees After this patch: * Use 90 degree phase offset usually. * Use 180 degree phase offset for MMC_DDR52, SDR104, HS200. That means we are _changing_ behavior for those devices in this way: * If we have HS200 eMMC or DDR52 eMMC, we'll run ID mode at 90 degrees (vs 180) but otherwise have no change. * For any non-HS200 / non-DDR52 eMMC devices we'll now _always_ run at 90 degrees (vs 180). It seems fairly unlikely that building modern hardware is using an eMMC that isn't using DDR52 or HS200, of course. * For SDR104 cards we'll now run with 180 degree phase offset (vs 90). It's expected that 90 degree phase offset would have worked OK, but this gives us extra margin. I have tested this by inserting my collection of uSD cards (mostly UHS, though a few not) into a veyron_minnie and confirmed that they still seem to enumerate properly. For a subset of them I tried putting a filesystem on them and also tried running mmc_test. Fixes: 7a03fe6f48f3 ("clk: rockchip: reset init state before mmc card initialization") Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: dw_mmc: fix the wrong max_blk_sizeJaehoon Chung2016-05-23
| | | | | | | | | According to DesignWare TRM, BLKSIZ is 16bits. Then it's correct that max_blk_size should be 0xFFFF, not 0x10000. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-02 17:20:10 -0400