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path: root/drivers/media/platform/cadence/cdns-csi2tx.c
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* media: v4l: fwnode: Initialise the V4L2 fwnode endpoints to zeroSakari Ailus2018-10-04
| | | | | | | | | | | | Initialise the V4L2 fwnode endpoints to zero in all drivers using v4l2_fwnode_endpoint_parse(). This prepares for setting default endpoint flags as well as the bus type. Setting bus type to zero will continue to guess the bus among the guessable set (parallel, Bt.656 and CSI-2 D-PHY). Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Tested-by: Steve Longerbeam <steve_longerbeam@mentor.com> Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
* media: v4l: mediabus: Recognise CSI-2 D-PHY and C-PHYSakari Ailus2018-10-04
| | | | | | | | | | The CSI-2 bus may use either D-PHY or C-PHY. Make this visible in media bus enum. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Tested-by: Steve Longerbeam <steve_longerbeam@mentor.com> Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
* media: v4l: cadence: include linux/slab.hArnd Bergmann2018-06-27
| | | | | | | | | | | | | | | | | I ran into a randconfig build error with the new driver: drivers/media/platform/cadence/cdns-csi2tx.c: In function 'csi2tx_probe': drivers/media/platform/cadence/cdns-csi2tx.c:477:11: error: implicit declaration of function 'kzalloc'; did you mean 'd_alloc'? [-Werror=implicit-function-declaration] kzalloc() is declared in linux/slab.h, so let's include this to make it build in all configurations. Fixes: 84b477e6d4bc ("media: v4l: cadence: Add Cadence MIPI-CSI2 TX driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
* media: v4l: cadence: Add Cadence MIPI-CSI2 TX driverMaxime Ripard2018-05-17
The Cadence MIPI-CSI2 TX controller is an hardware block meant to be used as a bridge between pixel interfaces and a CSI-2 bus. It supports operating with an internal or external D-PHY, with up to 4 lanes, or without any D-PHY. The current code only supports the latter case. While the virtual channel input on the pixel interface can be directly mapped to CSI2, the datatype input is actually a selection signal (3-bits) mapping to a table of up to 8 preconfigured datatypes/formats (programmed at start-up) The block supports up to 8 input datatypes. Acked-by: Benoit Parrot <bparrot@ti.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>