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| * drm/tegra: dpaux: Disable interrupt when detachedThierry Reding2015-08-13
| | | | | | | | | | | | | | | | When the DPAUX isn't attached to an SOR the interrupts are not useful. This also prevents a race that could potentially cause a crash on driver removal. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dpaux: Configure pads as I2C by defaultThierry Reding2015-08-13
| | | | | | | | | | | | | | | | | | | | The DPAUX code paths already configure the pads in AUX mode, but there is no way to reconfigure them in I2C mode for HDMI (the DPAUX module is unused in that case). Enabling the pads in I2C mode by default is the quickest way to support HDMI. Eventually this may need an explicit call in the user drivers. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dpaux: Provide error message in probeThierry Reding2015-08-13
| | | | | | | | | | | | | | When probing the dpaux device fails, output proper error messages to help diagnose the cause of the failure. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dsi: Add Tegra210 supportThierry Reding2015-08-13
| | | | | | | | | | | | | | The DSI host controller hasn't changed from Tegra132 to Tegra210, but different characterization parameters may be required. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dsi: Add Tegra132 supportThierry Reding2015-08-13
| | | | | | | | | | | | | | The DSI host controller hasn't changed from Tegra124 to Tegra132, but different characterization parameters may be required. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dsi: Add Tegra124 supportThierry Reding2015-08-13
| | | | | | | | | | | | | | The DSI host controller hasn't changed from Tegra114 to Tegra124, but different characterization parameters may be required. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dsi: Use proper back-porch for non-sync video modeThierry Reding2015-08-13
| | | | | | | | | | | | | | In video modes without sync pulses, the horizontal back-porch needs to include the horizontal sync width. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dc: Rename BASE_COLOR_SIZE* fieldsThierry Reding2015-08-13
| | | | | | | | | | | | Use an underscore to separate the prefix from the color size suffix. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dc: Don't explicitly set owner moduleThierry Reding2015-08-13
| | | | | | | | | | | | | | The call to platform_driver_register() will already set up the .owner field, so there's no need to do it explicitly. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dc: Rename register for consistencyThierry Reding2015-08-13
| | | | | | | | | | | | | | The horizontal pulse enable bits are named H_PULSE{0,1,2}_ENABLE in the TRM. Modify the driver to use the same naming for consistency. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dc: Record statisticsThierry Reding2015-08-13
| | | | | | | | | | | | | | Record interrupt statistics, such as the number of frames and VBLANKs received and the number of FIFO underflow and overflows. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dc: Request syncpoint earlierThierry Reding2015-08-13
| | | | | | | | | | | | | | | | Request a syncpoint for display prior to registering the host1x client. This will ensure that the syncpoint will be acquired when the KMS driver initializes. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dc: Remove gratuituous blank lineThierry Reding2015-08-13
| | | | | | | | | | | | Blank lines at the end of functions are hideous, so get rid of it. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dc: Clarify comment about cursor treatmentThierry Reding2015-08-13
| | | | | | | | Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dc: Implement CRC debugfs interfaceThierry Reding2015-08-13
| | | | | | | | Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dc: Add Tegra210 supportThierry Reding2015-08-13
| | | | | | | | Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dc: Reset VBLANK to offThierry Reding2015-08-13
| | | | | | | | | | | | | | | | | | Upon driver load, reset the VBLANK machinery to off to reflect the hardware state. Since the ->reset() callback is called from the initial drm_mode_config_reset() call, move the latter after the VBLANK machinery initialization by drm_vblank_init(). Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: output: Support low-active hotplug detectThierry Reding2015-08-13
| | | | | | | | | | | | | | Support low-active hotplug detect signals by storing the GPIO flags parsed from device tree. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: Use SIMPLE_DEV_PM_OPSThierry Reding2015-08-13
| | | | | | | | | | | | Use this macro to reduce some of the boilerplate. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: Allow VBLANK to be disabledThierry Reding2015-08-13
| | | | | | | | Signed-off-by: Thierry Reding <treding@nvidia.com>
* | drm/tegra: Use new drm_fb_helper functionsArchit Taneja2015-08-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the newly created wrapper drm_fb_helper functions instead of calling core fbdev functions directly. They also simplify the fb_info creation. v2: - Fix up error handling path in tegra_fbdev_probe Cc: Thierry Reding <thierry.reding@gmail.com> Cc: "Terje Bergström" <tbergstrom@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm: Make the connector dpms callback return a value, v2.Maarten Lankhorst2015-07-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is required to properly handle failing dpms calls. When making a wait in i915 interruptible, I've noticed that the dpms sequence could fail with -ERESTARTSYS because it was waiting interruptibly for flips. So from now on allow drivers to fail in their connector dpms callback. Encoder and crtc dpms callbacks are unaffected. Changes since v1: - Update kerneldoc for the drm helper functions. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> [danvet: Resolve conflicts due to different merge order.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* | drm/atomic: pass old crtc state to atomic_begin/flush.Maarten Lankhorst2015-07-27
|/ | | | | | | | | | | | In intel it's useful to keep track of some state changes with old crtc state vs new state, for example to disable initial planes or when a modeset's prevented during fastboot. Cc: dri-devel@lists.freedesktop.org Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com> [danvet: squash in fixup for exynos provided by Maarten.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* Merge tag 'drm/tegra/for-4.2-rc1' of ↵Dave Airlie2015-06-17
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/tegra/linux into drm-next drm/tegra: Changes for v4.2-rc1 This contains a couple of mostly fixes for issues that have crept up in recent versions of linux-next. One issue is that DP AUX transactions of more than 4 bytes will access the wrong FIFO registers and hence become corrupt. Another fix is required to restore functionality of Tegra20 if using the GART. The current code expects the IOMMU aperture to be the complete 4 GiB address space, whereas the GART on Tegra20 only provides a 128 MiB aperture. One more issue with IOMMU support is that on 64-bit ARM, swiotlb is the default IOMMU implementation backing the DMA API. A side-effect of that is that when dma_map_sg() is called to flush caches (yes, this is a bit of a hack, but ARM does not provide a better API), swiotlb will immediately run out of memory because its bounce buffer is too small to make a framebuffer. Finally I've included a mostly cosmetic fix that stores register values in u32 rather than unsigned long to avoid sign-extension issues on 64- bit ARM. This is only a precaution since it hasn't caused any issues (yet). * tag 'drm/tegra/for-4.2-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/tegra: dpaux: Registers are 32-bit drm/tegra: gem: Flush pages after allocation drm/tegra: gem: Take into account IOMMU aperture drm/tegra: dpaux: Fix transfers larger than 4 bytes
| * drm/tegra: dpaux: Registers are 32-bitThierry Reding2015-06-12
| | | | | | | | | | | | | | | | Use a sized unsigned 32-bit data type (u32) to store register contents. The DPAUX registers are 32 bits wide irrespective of the architecture's data width. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: gem: Flush pages after allocationThierry Reding2015-06-12
| | | | | | | | | | | | | | | | Pages allocated from shmemfs don't end up being cleared and flushed on ARMv7, so they must be flushed explicitly. Use the DMA mapping API for that purpose, even though it's not used for anything else. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: gem: Take into account IOMMU apertureThierry Reding2015-06-12
| | | | | | | | | | | | | | | | | | The IOMMU may not always be able to address 2 GiB of memory. On Tegra20, the GART supports 32 MiB starting at 0x58000000. Also the aperture on Tegra30 and later is in fact the full 4 GiB, rather than just 2 GiB as currently assumed. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dpaux: Fix transfers larger than 4 bytesThierry Reding2015-06-12
| | | | | | | | | | | | | | | | | | The DPAUX read/write FIFO registers aren't sequential in the register space, causing transfers larger than 4 bytes to cause accesses to non- existing FIFO registers. Fixes: 6b6b604215c6 ("drm/tegra: Add eDP support") Signed-off-by: Thierry Reding <treding@nvidia.com>
* | drm/tegra: Don't use vblank_disable_immediate on incapable driver.Mario Kleiner2015-05-08
|/ | | | | | | | | | | | | | | | | Tegra would not only need a hardware vblank counter that increments at leading edge of vblank, but also support for instantaneous high precision vblank timestamp queries, ie. a proper implementation of dev->driver->get_vblank_timestamp(). Without these, there can be off-by-one errors during vblank disable/enable if the scanout is inside vblank at en/disable time, and additionally clients will never see any useable vblank timestamps when querying via drmWaitVblank ioctl. This would negatively affect swap scheduling under X11 and Wayland. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* dma-buf: cleanup dma_buf_export() to make it easily extensibleSumit Semwal2015-04-21
| | | | | | | | | | | | | | | | | At present, dma_buf_export() takes a series of parameters, which makes it difficult to add any new parameters for exporters, if required. Make it simpler by moving all these parameters into a struct, and pass the struct * as parameter to dma_buf_export(). While at it, unite dma_buf_export_named() with dma_buf_export(), and change all callers accordingly. Reviewed-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org> Acked-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Acked-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
* Merge tag 'drm/tegra/for-4.1-rc1' of ↵Dave Airlie2015-04-07
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/tegra/linux into drm-next drm/tegra: Changes for v4.1-rc1 Perhaps the most noteworthy change in this set is the implementation of a hardware VBLANK counter using host1x syncpoints. The SOR registers can now be dumped via debugfs, which can be useful while debugging. The IOVA address space maintained by the driver can also be dumped via debugfs. Other than than, these changes are mostly cleanup work, such as making register names more consistent or removing unused code (that was left over after the atomic mode-setting conversion). There's also a fix for eDP that makes the driver cope with firmware that already initialized the display (such as the firmware on the Tegra-based Chromebooks). * tag 'drm/tegra/for-4.1-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/tegra: sor: Reset during initialization drm/tegra: gem: Return 64-bit offset for mmap(2) drm/tegra: hdmi: Name register fields consistently drm/tegra: hdmi: Resets are synchronous drm/tegra: dc: Document tegra_dc_state_setup_clock() drm/tegra: dc: Remove unused callbacks drm/tegra: dc: Remove unused function drm/tegra: dc: Use base atomic state helpers drm/atomic: Add helpers for state-subclassing drivers drm/tegra: dc: Implement hardware VBLANK counter gpu: host1x: Export host1x_syncpt_read() drm/tegra: sor: Dump registers via debugfs drm/tegra: sor: Registers are 32-bit drm/tegra: Provide debugfs file for the IOVA space drm/tegra: dc: Check for valid parent clock
| * drm/tegra: sor: Reset during initializationTomeu Vizoso2015-04-02
| | | | | | | | | | | | | | | | | | | | | | | | As there isn't a way for the firmware on the Nyan Chromebooks to hand over the display to the kernel, and the kernel isn't redoing the whole configuration at present. With this patch, the SOR is brought to a known state and we get correct display on every boot. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: hdmi: Name register fields consistentlyThierry Reding2015-04-02
| | | | | | | | | | | | Name the fields of the SOR_SEQ_CTL register consistently. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: hdmi: Resets are synchronousThierry Reding2015-04-02
| | | | | | | | | | | | | | Resets on Tegra are synchronous, so keep the clock enabled while asserting the reset. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dc: Document tegra_dc_state_setup_clock()Thierry Reding2015-04-02
| | | | | | | | | | | | | | This function is called by output drivers so should be documented. While at it, move it to a more appropriate location. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dc: Remove unused callbacksThierry Reding2015-04-02
| | | | | | | | | | | | | | The ->mode_set() and ->mode_set_base() callbacks are no longer used with full atomic mode-setting drivers, so remove them. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dc: Remove unused functionThierry Reding2015-04-02
| | | | | | | | | | | | | | The tegra_dc_setup_clock() function is unused after the conversion to atomic mode-setting, so remove it. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dc: Use base atomic state helpersThierry Reding2015-04-02
| | | | | | | | | | | | | | | | | | Instead of duplicating the code, make use of the newly introduced atomic state duplicate and destroy helpers. This allows changes to the base atomic state handling to automatically propagate to the Tegra driver and thereby prevent breakage resulting from both copies going out of sync. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dc: Implement hardware VBLANK counterThierry Reding2015-04-02
| | | | | | | | | | | | | | | | The display controller on Tegra can use syncpoints to count VBLANK events. syncpoints are 32-bit unsigned integers, so well suited as VBLANK counters. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: sor: Dump registers via debugfsThierry Reding2015-04-02
| | | | | | | | Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: sor: Registers are 32-bitThierry Reding2015-04-02
| | | | | | | | | | | | | | | | Use a sized unsigned 32-bit data type (u32) to store register contents. The SOR registers are 32 bits wide irrespective of the architecture's data width. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: Provide debugfs file for the IOVA spaceThierry Reding2015-04-02
| | | | | | | | | | | | | | The Tegra DRM driver uses a single IO virtual address space for buffer mappings. Provide a table of the address space usage in debugfs. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dc: Check for valid parent clockThierry Reding2015-04-02
| | | | | | | | | | | | | | | | | | Check that the desired parent clock is indeed a valid parent for the display controller clock. This is purely cosmetic at this point since the parent clocks are specified in DT and all the currently defined parents are in fact valid parents of the display controller clock. Signed-off-by: Thierry Reding <treding@nvidia.com>
* | Merge tag 'v4.0-rc3' into drm-nextDave Airlie2015-03-09
|\| | | | | | | | | | | | | | | | | Linux 4.0-rc3 backmerge to fix two i915 conflicts, and get some mainline bug fixes needed for my testing box Conflicts: drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/intel_display.c
| * drm/tegra: dc: Move more code into ->init()Thierry Reding2015-02-19
| | | | | | | | | | | | | | | | | | | | The code in tegra_crtc_prepare() really belongs in tegra_dc_init(), or at least most of it. This fixes an issue with VBLANK handling because tegra_crtc_prepare() would overwrite the interrupt mask register that tegra_crtc_enable_vblank() had written to to enable VBLANK interrupts. Tested-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dc: Wire up CRTC parent of atomic stateThierry Reding2015-02-19
| | | | | | | | | | | | | | | | Store a pointer to the CRTC in its atomic state to make it easy for state handling code to get at the CRTC. Tested-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: dc: Reset state's active_changed fieldThierry Reding2015-02-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit eab3bbeffd15 ("drm/atomic: Add drm_crtc_state->active") added the field to track the DPMS state. However, the Tegra driver was in modified in parallel and subclasses the CRTC atomic state, so needed to duplicate the code in the atomic helpers. After the addition of the active_changed field it became out of sync and doesn't reset it when duplicating state. This causes a full modeset on things like page-flips, which will in turn cause warnings due to the VBLANK machinery being disabled when it really should remain on. Tested-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: hdmi: Explicitly set clock rateThierry Reding2015-02-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Recent changes in the clock framework have caused a behavioural change in that clocks that have not had their rate set explicitly will now be reset to their initial rate (or 0) when the clock is released. This is triggered in the deferred probing path, resulting in the clock running at a wrong frequency after the successful probe. This can be easily fixed by setting the rate explicitly rather than by relying on the implicit rate inherited by the parent. Tested-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | drm: Pass in new and old plane state to prepare_fb and cleanup_fbTvrtko Ursulin2015-03-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use cases like rotation require these hooks to have some context so they know how to prepare and cleanup the frame buffer correctly. For i915 specifically, object backing pages need to be mapped differently for different rotation modes and the driver needs to know which mapping to instantiate and which to tear down when transitioning between them. v2: Made passed in states const. (Daniel Vetter) [airlied: add mdp5 and atmel fixups] Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: dri-devel@lists.freedesktop.org Reviewed-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* | drm/atomic-helper: Rename commmit_post/pre_planesDaniel Vetter2015-02-23
|/ | | | | | | | | | | | | | | | | | These names only make sense because of backwards compatability with the order used by the crtc helper library. There's not really any real requirement in the ordering here. So rename them to something more descriptive and update the kerneldoc a bit. Motivated in a discussion with Laurent about how to restore plane state for dpms for drivers with runtime pm. v2: Squash in fixup from Stephen Rothwell to fix a conflict with tegra. Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Rob Clark <robdclark@gmail.com> Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
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