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path: root/drivers/gpu/drm/nouveau/nouveau_drv.h
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* drm/nv04-nv40: Fix up PCI(E) GART DMA object bus address calculation.Francisco Jerez2010-12-08
| | | | | Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: kick vram functions out into an "engine"Ben Skeggs2010-12-07
| | | | | | | | | NVC0 will be able to share some of nv50's paths this way. This also makes it the card-specific vram code responsible for deciding if a given set of tile_flags is valid, rather than duplicating the allowed types in nv50_vram.c and nouveau_gem.c Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: allow gpuobj vinst to be a virtual address when necessaryBen Skeggs2010-12-07
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: tidy up PCIEGART implementationBen Skeggs2010-12-07
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: implement global channel address space on new VM codeBen Skeggs2010-12-07
| | | | | | | As of this commit, it's guaranteed that if an object is in VRAM that its GPU virtual address will be constant. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: implement BAR1/BAR3 management on top of new VM codeBen Skeggs2010-12-07
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: import new vm codeBen Skeggs2010-12-07
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: implement custom vram mmBen Skeggs2010-12-07
| | | | | | | | | | | This is required on nv50 as we need to be able to have more precise control over physical VRAM allocations to avoid buffer corruption when using buffers of mixed memory types. This removes some nasty overallocation/alignment that we were previously using to "control" this problem. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: wrap calls to ttm_bo_validate()Ben Skeggs2010-12-07
| | | | | | | This will be used later to fixup bo.offset with a buffer's fixed GPU virtual address. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: introduce a util function to wait on reg != valBen Skeggs2010-12-07
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: implicitly insert non-DMA objects into RAMHTBen Skeggs2010-12-07
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: Synchronize with the user channel before GPU object destruction.Francisco Jerez2010-12-07
| | | | | | | | | | | | | | There have been reports of PFIFO cache errors during context take down (fdo bug 31637). They are caused by some GPU objects being taken out while the channel is still potentially processing commands. Make sure that all the previous rendering has landed before releasing a GPU object. Reported-by: Grzesiek Sójka <pld@pfu.pl> Reported-by: Patrice Mandin <patmandin@gmail.com> Signed-off-by: Francisco Jerez <currojerez@riseup.net> Acked-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: tidy up and extend dma object creation interfacesBen Skeggs2010-12-03
| | | | | Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: remove dummy page use from PCI(E)GART, use PTE present insteadBen Skeggs2010-12-03
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: allocate page for unknown PFB object in nv50_fb.cBen Skeggs2010-12-03
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: rework gpu-specific instmem interfacesBen Skeggs2010-12-03
| | | | | Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: simplify gpuobj suspend/resumeBen Skeggs2010-12-03
| | | | | Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: rework PGPIO IRQ handling and hotplug detectionBen Skeggs2010-12-03
| | | | | | | | | | | | Allows callers to install their own handlers for when a GPIO line changes state (such as for hotplug detect). This also fixes a bug where we weren't acknowledging the GPIO IRQ until after the bottom half had run, causing a severe IRQ storm in some cases. Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: tidy+move PGRAPH ISRs to their respective *_graph.c filesBen Skeggs2010-12-03
| | | | | Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: move PFIFO ISR into nv04_fifo.cBen Skeggs2010-12-03
| | | | | Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: move GPIO ISR to nv50_gpio.cBen Skeggs2010-12-03
| | | | | Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: allow irq handlers to be installed by engine-specific codeBen Skeggs2010-12-03
| | | | | | | Lets start to clean up this mess! Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv20: Add Z compression support.Francisco Jerez2010-12-03
| | | | | | Signed-off-by: Francisco Jerez <currojerez@riseup.net> Tested-by: Xavier Chantry <chantry.xavier@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: Rework tile region handling.Francisco Jerez2010-12-03
| | | | | | | | | The point is to share more code between the PFB/PGRAPH tile region hooks, and give the hardware specific functions a chance to allocate per-region resources. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: Add a separate class for the kernel channel mutex.Francisco Jerez2010-12-03
| | | | | | | | | | nouveau_bo_move_m2mf() needs to lock the kernel channel, and it may be called from the pushbuf IOCTL with an user channel already locked. Use a separate subclass for the kernel channel mutex because this is legitimate mutex nesting. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: Keep track of the head a channel is vsync'ing to.Francisco Jerez2010-12-03
| | | | | | | | | | | In a multihead setup vblank interrupts may end up enabled in both heads. In that case we want to ignore the vblank interrupts coming from the wrong CRTC to avoid tearing and unbalanced calls to drm_vblank_get/put (fdo bug 31074). Reported-by: Felix Leimbach <felix.leimbach@gmx.net> Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: Implement the pageflip ioctl.Francisco Jerez2010-12-03
| | | | | | | nv0x-nv4x should be mostly fine, nv50 doesn't work yet. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: Implement the vblank DRM hooks.Francisco Jerez2010-12-03
| | | | | Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: fix annoying nouveau_fence type issueMarcin Slusarz2010-12-03
| | | | | | | | | | | | | | nouveau_fence_* functions are not type safe, which could lead to bugs. Additionally every use of nouveau_fence_unref had to cast struct nouveau_fence to void **. Fix it by renaming old functions and creating static inline functions with new prototypes. We still need old functions, because we pass function pointers to ttm. As we are wrapping functions, drop unused "void *arg" parameter where possible. Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: add support for MSIBen Skeggs2010-12-03
| | | | | | | | | | | | | | | | Only supported on NV50+ so far, and disabled by default currently. The module parameter "msi=1" will enable it. There's a kernel bug which will cause this to fail if the module (or the NVIDIA binary driver) has ever been loaded before loading nouveau with MSI enabled. As such, this is only safe to enable if you have nouveau load on boot, and don't wish to ever reload it. The workaround is to "echo 0 > /sys/bus/pci/devices/<device>/enable" until the enable count reads 0. Then you should be able to load nouveau with MSI enabled. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: initial work to allow multiple evo channelsBen Skeggs2010-12-03
| | | | | | This doesn't work yet for unknown reasons. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv84: add support for the PCRYPT engineBen Skeggs2010-12-03
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: only expose the object classes that are supported by the chipsetBen Skeggs2010-12-03
| | | | | | | We previously added all the available classes for the entire generation, even though the objects wouldn't work on the hardware. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: use object class structs more extensivelyBen Skeggs2010-12-03
| | | | | | | The structs themselves, as well as the non-sw object creation function are probably very misnamed now. That's a problem for later :) Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: store engine type in gpuobj class structsBen Skeggs2010-12-03
| | | | | | We will eventually want to address hw engines other than PGRAPH. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: pass gpuobj alignment request down into backing allocatorBen Skeggs2010-12-03
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: Implement weak channel references.Francisco Jerez2010-12-03
| | | | | | | | | nouveau_channel_ref() takes a "weak" channel reference that doesn't prevent the hardware channel resources from being released, it just keeps the channel data structure alive. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: Add unlocked variants of nouveau_channel_get/put.Francisco Jerez2010-12-03
| | | | | Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: Refactor context destruction to avoid a lock ordering issue.Francisco Jerez2010-12-03
| | | | | | | | | | | | | | | | The destroy_context() engine hooks call gpuobj management functions to release the channel resources, these functions use HARDIRQ-unsafe locks whereas destroy_context() is called with the HARDIRQ-safe context_switch_lock held, that's a lock ordering violation. Push the engine-specific channel destruction logic into destroy_context() and let the hardware-specific code lock and unlock when it's actually needed. Change the engine destruction order to avoid a race in the small gap between pgraph and pfifo context uninitialization. Reported-by: Marcin Slusarz <marcin.slusarz@gmail.com> Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: hook up acpi power supply change trackingBen Skeggs2010-12-03
| | | | | | Not used at all yet, but lets hook it up now anyway. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: remove cpu_writers lockBen Skeggs2010-12-03
| | | | | | | No other driver uses this, and userspace should be responsible for handling locking between them if they share BOs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: add more fine-grained locking to channel list + structuresBen Skeggs2010-12-03
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: add per-channel mutex, use to lock access to drm's channelBen Skeggs2010-12-03
| | | | | | | | | | | | | | | This fixes a race condition between fbcon acceleration and TTM buffer moves. To reproduce: - start X - switch to vt and "while (true); do dmesg; done" - switch to another vt and "sleep 2 && cat /path/to/debugfs/dri/0/evict_vram" - switch back to vt running dmesg We don't make use of this on any other channel yet, they're currently protected by drm_global_mutex. This will change in the near future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* nouveau: Acknowledge HPD irq in handler, not bottom halfAndy Lutomirski2010-11-17
| | | | | | | | The old code generated an interrupt storm bad enough to completely take down my system. Signed-off-by: Andy Lutomirski <luto@mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: implement possible workaround for NV86 PGRAPH TLB flush hangBen Skeggs2010-11-17
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: Expose some BO usage flags to userspace.Francisco Jerez2010-11-17
| | | | | | | | | This will be needed for Z compression and to take smarter placement decisions. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Acked-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: Some random cleanups.Francisco Jerez2010-11-17
| | | | | | | Remove some unused/duplicated definitions and make sparse happy again. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: Fix large 3D performance regression caused by the interchannel ↵Francisco Jerez2010-10-04
| | | | | | | | | | | sync patches. Reported-by: Christoph Bumiller <e0425955@student.tuwien.ac.at> Signed-off-by: Francisco Jerez <currojerez@riseup.net> Tested-by: Maarten Maathuis <madman2003@gmail.com> Tested-by: Xavier Chantry <chantry.xavier@gmail.com> Tested-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: Use semaphores to handle inter-channel sync in hardware.Francisco Jerez2010-10-04
| | | | | Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: Provide a means to have arbitrary work run on fence completion.Francisco Jerez2010-10-04
| | | | | Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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