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path: root/drivers/gpu/drm/amd/amdgpu/soc15.c
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* drm/amdgpu/renoir: move gfxoff handling into gfx9 moduleAlex Deucher2019-11-06
| | | | | | | To properly handle the option parsing ordering. Reviewed-by: Yong Zhao <yong.zhao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: hide another #warningArnd Bergmann2019-10-02
| | | | | | | | | | | | | An earlier patch of mine disabled some #warning statements that get in the way of build testing, but then another instance was added around the same time. Remove that as well. Fixes: b5203d16aef4 ("drm/amd/amdgpu: hide #warning for missing DC config") Fixes: e1c14c43395c ("drm/amdgpu: Enable DC on Renoir") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: don't increment vram lost if we are in hibernationAlex Deucher2019-10-02
| | | | | | | | | | We reset the GPU as part of our hibernation sequence so we need to make sure we don't mark vram as lost in that case. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=111879 Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Enable DC on RenoirRoman Li2019-08-29
| | | | | | | | Enable DC support for renoir. Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: introduce vram lost for reset (v2)Monk Liu2019-08-29
| | | | | | | | | | | | | for SOC15/vega10 the BACO reset & mode1 would introduce vram lost in high end address range, current kmd's vram lost checking cannot catch it since it only check very ahead visible frame buffer v2: cover NV as well Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable VCN DPG for RenoirThong Thai2019-08-22
| | | | | | | | | This will enable indirect SRAM loading for VCN DPG mode initialization. Signed-off-by: Thong Thai <thong.thai@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable SDMA power gating for rnPrike Liang2019-08-22
| | | | | | | | Enable SDMA PG flag during device ip early init. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable DF clock gating for rnPrike Liang2019-08-22
| | | | | | | | Enable DF clock gating during DF IP early init. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable athub clock gating for rnPrike Liang2019-08-22
| | | | | | | | Enable athub MG and LS clock gating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable IH clock gating for rnPrike Liang2019-08-22
| | | | | | | | Enable IH clock gating during IH block initialized. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable vcn clock gating for rnPrike Liang2019-08-22
| | | | | | | | Enable VCN middle grain clock gating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable rom clock gating for rnPrike Liang2019-08-22
| | | | | | | | Enable rom light sleep clock gating. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable HDP clock gating for rnPrike Liang2019-08-22
| | | | | | | | Enable HDP light sleep clock gating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable BIF clock gating for rnPrike Liang2019-08-22
| | | | | | | | Enable BIF light sleep clock gating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable sdma clock gating for rnPrike Liang2019-08-22
| | | | | | | | Enable sdma middle grain and light sleep clock gating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable mmhub clock gating for rnPrike Liang2019-08-22
| | | | | | | | Enable mmhub midle grain and light sleep clock gating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable gfx clock gating for rnPrike Liang2019-08-22
| | | | | | | | Enable gfx cg/mg/cp etc clock gating. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add and enable gfxoff featureAaron Liu2019-08-22
| | | | | | | | | | This patch updates gfxoff feature. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: add power up/down SDMA interfaces for renoirAaron Liu2019-08-22
| | | | | | | | | 1.Implement PowerUpSDMA/PowerDownSDMA interfaces in the swSMU for renoir 2.adjust smu ip block ahead of gfx&sdma ip block Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/powerplay: add smu ip block for renoir (v2)Aaron Liu2019-08-22
| | | | | | | | | | add swSMU [smu_v12_0] for renoir v2: whitespace fixes (Alex) Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/gfx9: update pg_flags after determining if gfx off is possibleAlex Deucher2019-08-21
| | | | | | | | | | | | | | | We need to set certain power gating flags after we determine if the firmware version is sufficient to support gfxoff. Previously we set the pg flags in early init, but we later we might have disabled gfxoff if the firmware versions didn't support it. Move adding the additional pg flags after we determine whether or not to support gfxoff. Fixes: 005440066f92 ("drm/amdgpu: enable gfxoff again on raven series (v2)") Tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Tested-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
* drm/amdgpu: Use new mode2 reset interface for RV.Andrey Grodzovsky2019-08-15
| | | | | | | | | | | | Integrate the mode2 reset into rest sequence. v2: Check ppfuncs pointer for NULL Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable clock gating for renoirAaron Liu2019-08-12
| | | | | | | | | | enable gfx&common clock gating for renoir Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add VCN2.0 to Renoir IP blocksLeo Liu2019-08-12
| | | | | | | | | Thus enable VCN2.0 for Renoir Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add psp_v12_0 for renoir (v2)Aaron Liu2019-08-12
| | | | | | | | | | | | | | 1. Add psp ip block 2. Use direct loading type by default and it can also config psp loading type. 3. Bypass sos fw loading and xgmi&ras interface v2: drop TA loading Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add asic funcs for renoirAaron Liu2019-08-12
| | | | | | | | | | add asic funcs for renoir, init soc15_asic_funcs Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable dce virtual ip module for RenoirAaron Liu2019-08-12
| | | | | | | Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: set ip blocks for renoirHuang Rui2019-08-12
| | | | | | | | | Enable ip blocks for renoir. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add soc15 common ip block support for renoirHuang Rui2019-08-12
| | | | | | | | | This patch adds common ip support for renoir. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable mmhub clock gating for ArcturusLe Ma2019-08-12
| | | | | | | | Init MC_MGCG/LS flag. Also apply to athub CG. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add GFX_CP_LS flag to ArcturusLe Ma2019-08-12
| | | | | | | | | Missed AMD_CG_SUPPORT_GFX_CP_LS accidently when commit patch before drm/amdgpu: enable gfx clock gating for Arcturus Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable sdma clock gating for ArcturusLe Ma2019-08-12
| | | | | | | | | Init sdma MGCG/LS flag Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable hdp clock gating for ArcturusLe Ma2019-08-12
| | | | | | | | | Init hdp MGCG/LS flag as Vega20 Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add hdp clock gating for ArcturusLe Ma2019-08-12
| | | | | | | | | Add hdp CGLS for Arcturus in set common clockgating function Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable gfx clock gating for ArcturusLe Ma2019-08-12
| | | | | | | | | Init gfx MGCG/LS and CGCG/LS flag. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Fix pcie_bw on Vega20Kent Russell2019-08-02
| | | | | | | | | | The registers used for VG20 are different in that certain performance counters were split off to TXCLK3/4. Vega10/12 doesn't have this, so add a new vg20_get_pcie_usage to reflect this change. Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Add amdgpu_asic_funcs.reset_method for Vega20Andrey Grodzovsky2019-08-02
| | | | | | | | Fixes GPU reset crash. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: cleanup vega10 SRIOV code pathMonk Liu2019-08-02
| | | | | | | | | | | | | | | | | | we can simplify all those unnecessary function under SRIOV for vega10 since: 1) PSP L1 policy is by force enabled in SRIOV 2) original logic always set all flags which make itself a dummy step besides, 1) the ih_doorbell_range set should also be skipped for VEGA10 SRIOV. 2) the gfx_common registers should also be skipped for VEGA10 SRIOV. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add RREG64/WREG64(_PCIE) operationsTao Zhou2019-07-31
| | | | | | | | | | add 64 bits register access functions v2: implement 64 bit functions in low level Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Dennis Li <dennis.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: enable arcturus powerplayEvan Quan2019-07-31
| | | | | | | | Arcturus powerplay is ready to use. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: add reset_method asic callback for soc15Alex Deucher2019-07-31
| | | | | | | | APUs only support mode2 reset. dGPUs use either mode1 or baco depending on various conditions. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: init arct external rev idHawking Zhang2019-07-18
| | | | | | | | Properly set the external silicon revision id. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: correct ip for mmHDP_READ_CACHE_INVALIDATE register accessLe Ma2019-07-18
| | | | | | | | Use the proper IP index for HDP registers. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: enable VCN2.5 on ArcturusLeo Liu2019-07-18
| | | | | | | | VCN is the video decode and encode engine on Arcturus Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Enable xgmi support for ArcturusOak Zeng2019-07-18
| | | | | | | | xgmi is a high performance cross-GPU communication channel. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Initialize asic functions for ArcturusOak Zeng2019-07-18
| | | | | | | | | | After cherry-picking doorbell rework changes from drm-next branch, Arcturus asic functions pointer need to be initialized to init doorbell index for Arcturus. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/soc15: add Arcturus common ip blocksLe Ma2019-07-18
| | | | | | | | Add common IP blocks for Arcturus. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: dynamically initialize IP offset for ArcturusLe Ma2019-07-18
| | | | | | | | Add support for the IP offsets on Arcturus. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Snow Zhang < Snow.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/amdgpu: hide #warning for missing DC configArnd Bergmann2019-07-16
| | | | | | | | | | | | | It is annoying to have #warnings that trigger in randconfig builds like drivers/gpu/drm/amd/amdgpu/soc15.c:653:3: error: "Enable CONFIG_DRM_AMD_DC for display support on SOC15." drivers/gpu/drm/amd/amdgpu/nv.c:400:3: error: "Enable CONFIG_DRM_AMD_DC for display support on navi." Remove these and rely on the users to turn these on. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Fix Vega20 Perf counter for pcie_bwKent Russell2019-07-16
| | | | | | | | | The perf counter for Vega20 is 108, instead of 104 which it was on all previous GPUs, so add a check to use the appropriate value. Signed-off-by: Kent Russell <kent.russell@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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