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| * | MIPS: Loongson-3: Improve -march option and move it to PlatformHuacai Chen2016-01-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If GCC >= 4.9 and Binutils >=2.25, we use -march=loongson3a, otherwise we use -march=mips64r2, this can slightly improve performance. Besides, arch/mips/loongson64/Platform is a better location rather than arch/ mips/Makefile. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12161/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Cleanup the unused __arch_local_irq_restore() functionHuacai Chen2016-01-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In history, __arch_local_irq_restore() is only used by SMTC. However, SMTC support has been removed since 3.16, this patch remove the unused function. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12159/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Add IEEE Std 754 conformance mode selectionMaciej W. Rozycki2016-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an `ieee754=' kernel parameter to control IEEE Std 754 conformance mode. Use separate flags copied from the respective CPU feature flags, and adjusted according to the conformance mode selected, to make binaries requesting individual NaN encoding modes accepted or rejected as needed. Update the initial setting for FCSR and, in the full FPU emulation mode, its read-only mask accordingly. Accept the mode selection requested for legacy processors as well. As with the EF_MIPS_NAN2008 ELF file header flag adjust both ABS2008 and NAN2008 bits at the same time, to match the choice made for hardware currently implemented. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11481/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Determine the presence of IEEE Std 754-2008 featuresMaciej W. Rozycki2016-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Determine the presence of and the amount of control available over IEEE Std 754-2008 features. In the case of a hardware FPU being used examine the FIR register for the presence of the HAS2008 bit and then the FCSR register for the writability of the ABS2008 and NAN2008 bits and the hardwired state of each of these bits if read-only. Update the initial FCSR contents used for threads and the FCSR writability mask accordingly. For full FPU emulation and MIPS32 or MIPS64 processors make the FCSR ABS2008 and NAN2008 bits writable. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11480/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ELF: Interpret the NAN2008 file header flagMaciej W. Rozycki2016-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Handle the EF_MIPS_NAN2008 ELF file header flag and refuse execution where there is no support in the FPU for the NaN encoding mode requested by a binary invoked. Ensure that the setting of the bit in the binary matches one in any intepreter used. Set the thread's initial FCSR contents according to the value of the EF_MIPS_NAN2008. Set the values of the FCSR ABS2008 and NAN2008 bits both to the same value if possible, to take the approach taken with existing FPU hardware into account. As of now all implementations have both bits hardwired to the same value, that is both are fixed at 0 or both are fixed at 1, even though the architecture allows for implementations where the amount of control implemented with each of these two individual bits is independent of each other. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11479/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | ELF: Also pass any interpreter's file header to `arch_check_elf'Maciej W. Rozycki2016-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also pass any interpreter's file header to `arch_check_elf' so that any architecture handler can have a look at it if needed. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Acked-by: Andrew Morton <akpm@linux-foundation.org> Acked-by: Al Viro <viro@zeniv.linux.org.uk> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11478/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: math-emu: Add IEEE Std 754-2008 NaN encoding emulationMaciej W. Rozycki2016-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement IEEE Std 754-2008 NaN encoding wired to the state of the FCSR.NAN2008 bit. Make the interpretation of the quiet bit in NaN data as follows: * in the legacy mode originally defined by the MIPS architecture the value of 1 denotes an sNaN whereas the value of 0 denotes a qNaN, * in the 2008 mode introduced with revision 5 of the MIPS architecture the value of 0 denotes an sNaN whereas the value of 1 denotes a qNaN, following the definition of the preferred NaN encoding introduced with IEEE Std 754-2008. In the 2008 mode, following the requirement of the said standard, quiet an sNaN where needed by setting the quiet bit to 1 and leaving all the NaN payload bits unchanged. Update format conversion operations according to the rules set by IEEE Std 754-2008 and the MIPS architecture. Specifically: * propagate NaN payload bits through conversions between floating-point formats such that as much information as possible is preserved and specifically a conversion from a narrower format to a wider format and then back to the original format does not change a qNaN payload in any way, * conversions from a floating-point to an integer format where the source is a NaN, infinity or a value that would convert to an integer outside the range of the result format produce, under the default exception handling, the respective values defined by the MIPS architecture. In full FPU emulation set the FIR.HAS2008 bit to 1, however do not make any further FCSR bits writable. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11477/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: math-emu: Add IEEE Std 754-2008 ABS.fmt and NEG.fmt emulationMaciej W. Rozycki2016-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement IEEE Std 754-2008 non-arithmetic ABS.fmt and NEG.fmt emulation wired to the state of the FCSR.ABS2008 bit. In the non-arithmetic mode the sign bit is altered according to the operation requested regardless of the datum encoded in the input operand, no other bits are changed, the resulting bit pattern is written to the output operand and no exception is ever signalled. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11476/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Define the legacy-NaN and 2008-NaN featuresMaciej W. Rozycki2016-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allocate CPU option bits and define macros for the legacy-NaN and 2008-NaN IEEE Std 754 MIPS architecture features. Unconditionally mark the legacy-NaN feature as present across hardware and emulated floating-point configurations. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11475/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Use a union to access the ELF file headerMaciej W. Rozycki2016-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rewrite `arch_elf_pt_proc' and `arch_check_elf' using a union to access the ELF file header. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11474/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: pci: Add MT7620a PCIE driverJohn Crispin2016-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "a" version of the MT7620 has single port PCIE bus. The driver is straightforward without any special magic required. The driver works on MT7620 and MT7628. There are a few magic values that get written to the pcie phy and a register of which we only know the name. I marked these places as vodoo in the comments above the code. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11996/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ralink: Add a few missing clocksJohn Crispin2016-01-19
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11995/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ralink: Fix vendor string for mt7620John Crispin2016-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ralink was acquired by Mediatek. Represent this in the cpuinfo. It apparently confused people. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11994/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ralink: Fix invalid assignment of SoC typeJohn Crispin2016-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 418d29c87061 ("MIPS: ralink: Unify SoC id handling") introduced broken code. We obviously need to assign the value. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11993/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ralink: fix USB frequency scalingJohn Crispin2016-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 418d29c87061 ("MIPS: ralink: Unify SoC id handling") was not fully correct. The logic for the SoC check got inverted. We need to check if it is not a MT76x8. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11992/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ralink: MT7688 pinmux fixesJohn Crispin2016-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few fixes to the pinmux data, 2 new muxes and a minor whitespace cleanup. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11991/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ralink: add MT7621 supportJohn Crispin2016-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MT7621 is based on a 1004k core. This patch adds support for the SoC. The timer and IRQ is just boiler plate as GIC has recently been moved to generic places in the kernel and just works. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11990/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ralink: add a symbol for INTCJohn Crispin2016-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the newer SoCs use the GIC. This patch splits the INTC out into its own symbol, allowing us to add the gic code in the following patch. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11989/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: BCM47xx: Support SPROM prefixes on other platformsRafał Miłecki2016-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BCM47XX platform has specific PCI setup because all buses share the same domain. It's different e.g. on ARM ARCH_BCM_5301X where each PCI bus gets its own domain (they are handled by iProc PCIe controller driver). As we want to make SPROM driver more generic, let's add an exception for BCM47xx. It was tested on BCM4706 (MIPS) and BCM4708A0 (ARM). Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11969/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: dts: jz4780/ci20: Add NEMC, BCH and NAND device tree nodesAlex Smith2016-01-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device tree nodes for the NEMC and BCH to the JZ4780 device tree, and make use of them in the Ci20 device tree to add a node for the board's NAND. Note that since the pinctrl driver is not yet upstream, this includes neither pin configuration nor busy/write-protect GPIO pins for the NAND. Use of the NAND relies on the boot loader to have left the pins configured in a usable state, which should be the case when booted from the NAND. [ralf@linux-mips.org: fold in Geert Uytterhoeven's patch and acks from Harvey's latest version.] Signed-off-by: Alex Smith <alex.smith@imgtec.com> Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Alex Smith <alex.smith@imgtec.com> Cc: linux-mtd@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org Patchwork: https://patchwork.linux-mips.org/patch/11695/ Patchwork: https://patchwork.linux-mips.org/patch/11914/ Patchwork: https://patchwork.linux-mips.org/patch/11985/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: bmips: Support SMP on BCM63168Simon Arlott2016-01-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BCM63168 requires the same CPU1 fix as BCM6368. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Cc: Linux Kernel Mailing List <linux-kernel@vger.kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/11487/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: Remove some unused code from setup.cAlban Bedel2016-01-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the unused defines for the reference clocks rate and the useless machine init function. Signed-off-by: Alban Bedel <albeu@free.fr> Cc: Felix Fietkau <nbd@openwrt.org> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11505/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: Allow using ath79_ddr_wb_flush() from driversAlban Bedel2016-01-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the declaration of ath79_ddr_wb_flush() to asm/mach-ath79/ath79.h to allow using it from drivers. This is needed to move the CPU IRQ driver to drivers/irqchip. Signed-off-by: Alban Bedel <albeu@free.fr> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Alexander Couzens <lynxis@fe80.eu> Cc: Joel Porquet <joel@porquet.org> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11502/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: Prepare moving the MISC driver to drivers/irqchipAlban Bedel2016-01-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To prepare moving out of the arch directory rework the MISC implementation to use irq domains instead of hard coded IRQ numbers. Also remove the uses of the ath79_reset_base global pointer in the IRQ methods. Signed-off-by: Alban Bedel <albeu@free.fr> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Alexander Couzens <lynxis@fe80.eu> Cc: Joel Porquet <joel@porquet.org> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11506/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: Remove useless #ifdef CONFIG_IRQCHIPAlban Bedel2016-01-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IRQCHIP is always enabled, so the #ifdef can just be removed. Signed-off-by: Alban Bedel <albeu@free.fr> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Alexander Couzens <lynxis@fe80.eu> Cc: Joel Porquet <joel@porquet.org> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11504/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: Enable the USB port on the TL-WR1043NDAlban Bedel2016-01-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Alban Bedel <albeu@free.fr> Cc: linux-mips@linux-mips.org Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11499/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: ath79: Add the EHCI controller and USB phy to the AR9132 dtsiAlban Bedel2016-01-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Alban Bedel <albeu@free.fr> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11498/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | Merge branch 'for-linus' of ↵Linus Torvalds2016-01-23
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs Pull final vfs updates from Al Viro: - The ->i_mutex wrappers (with small prereq in lustre) - a fix for too early freeing of symlink bodies on shmem (they need to be RCU-delayed) (-stable fodder) - followup to dedupe stuff merged this cycle * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs: vfs: abort dedupe loop if fatal signals are pending make sure that freeing shmem fast symlinks is RCU-delayed wrappers for ->i_mutex access lustre: remove unused declaration
| * | | wrappers for ->i_mutex accessAl Viro2016-01-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | parallel to mutex_{lock,unlock,trylock,is_locked,lock_nested}, inode_foo(inode) being mutex_foo(&inode->i_mutex). Please, use those for access to ->i_mutex; over the coming cycle ->i_mutex will become rwsem, with ->lookup() done with it held only shared. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* | | | Merge branch 'akpm' (patches from Andrew)Linus Torvalds2016-01-23
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge small final update from Andrew Morton: - DAX feature work: add fsync/msync support - kfree cleanup, MAINTAINERS update * emailed patches from Andrew Morton <akpm@linux-foundation.org>: MAINTAINERS: return arch/sh to maintained state, with new maintainers tree wide: use kvfree() than conditional kfree()/vfree() dax: never rely on bh.b_dev being set by get_block() xfs: call dax_pfn_mkwrite() for DAX fsync/msync ext4: call dax_pfn_mkwrite() for DAX fsync/msync ext2: call dax_pfn_mkwrite() for DAX fsync/msync dax: add support for fsync/sync mm: add find_get_entries_tag() dax: support dirty DAX entries in radix tree pmem: add wb_cache_pmem() to the PMEM API dax: fix conversion of holes to PMDs dax: fix NULL pointer dereference in __dax_dbg()
| * | | | tree wide: use kvfree() than conditional kfree()/vfree()Tetsuo Handa2016-01-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are many locations that do if (memory_was_allocated_by_vmalloc) vfree(ptr); else kfree(ptr); but kvfree() can handle both kmalloc()ed memory and vmalloc()ed memory using is_vmalloc_addr(). Unless callers have special reasons, we can replace this branch with kvfree(). Please check and reply if you found problems. Signed-off-by: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp> Acked-by: Michal Hocko <mhocko@suse.com> Acked-by: Jan Kara <jack@suse.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Reviewed-by: Andreas Dilger <andreas.dilger@intel.com> Acked-by: "Rafael J. Wysocki" <rjw@rjwysocki.net> Acked-by: David Rientjes <rientjes@google.com> Cc: "Luck, Tony" <tony.luck@intel.com> Cc: Oleg Drokin <oleg.drokin@intel.com> Cc: Boris Petkov <bp@suse.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| * | | | pmem: add wb_cache_pmem() to the PMEM APIRoss Zwisler2016-01-22
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | __arch_wb_cache_pmem() was already an internal implementation detail of the x86 PMEM API, but this functionality needs to be exported as part of the general PMEM API to handle the fsync/msync case for DAX mmaps. One thing worth noting is that we really do want this to be part of the PMEM API as opposed to a stand-alone function like clflush_cache_range() because of ordering restrictions. By having wb_cache_pmem() as part of the PMEM API we can leave it unordered, call it multiple times to write back large amounts of memory, and then order the multiple calls with a single wmb_pmem(). Signed-off-by: Ross Zwisler <ross.zwisler@linux.intel.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: "J. Bruce Fields" <bfields@fieldses.org> Cc: "Theodore Ts'o" <tytso@mit.edu> Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: Andreas Dilger <adilger.kernel@dilger.ca> Cc: Dave Chinner <david@fromorbit.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jan Kara <jack@suse.com> Cc: Jeff Layton <jlayton@poochiereds.net> Cc: Matthew Wilcox <willy@linux.intel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Matthew Wilcox <matthew.r.wilcox@intel.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | | Merge tag 'please-pull-copy_file_range' of ↵Linus Torvalds2016-01-22
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux Pull ia64 copy_file_range syscall update from Tony Luck: "Another release, another new syscall to wire up" * tag 'please-pull-copy_file_range' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux: [IA64] Enable copy_file_range syscall for ia64
| * | | | [IA64] Enable copy_file_range syscall for ia64Tony Luck2016-01-22
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | New system call added in: 29732938a6289a15e907da234d6692a2ead71855 vfs: add copy_file_range syscall and vfs helper Signed-off-by: Tony Luck <tony.luck@intel.com>
* | | | Merge tag 'armsoc-tegra' of ↵Linus Torvalds2016-01-22
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC support for Tegra platforms from Olof Johansson: "Here's a single-SoC topic branch that we've staged separately. Mainly because it was hard to sort the branch contents in a way that fit our existing branches due to some refactorings. The code has been in -next for quite a while, but we staged it in arm-soc a bit late, which is why we've kept it separate from the other updates and are sending it separately here" * tag 'armsoc-tegra' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: arm64: tegra: Add NVIDIA Jetson TX1 Developer Kit support arm64: tegra: Add NVIDIA P2597 I/O board support arm64: tegra: Add NVIDIA Jetson TX1 support arm64: tegra: Add NVIDIA P2571 board support arm64: tegra: Add NVIDIA P2371 board support arm64: tegra: Add NVIDIA P2595 I/O board support arm64: tegra: Add NVIDIA P2530 main board support arm64: tegra: Add Tegra210 support arm64: tegra: Add NVIDIA Tegra132 Norrin support arm64: tegra: Add Tegra132 support ARM: tegra: select USB_ULPI from EHCI rather than platform ARM: tegra: Ensure entire dcache is flushed on entering LP0/1 amba: Hide TEGRA_AHB symbol soc/tegra: Add Tegra210 support soc/tegra: Provide per-SoC Kconfig symbols
| * \ \ \ Merge tag 'tegra-for-4.5-dt' of ↵Olof Johansson2016-01-12
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into late/tegra ARM: tegra: Devicetree changes for v4.5-rc1 This adds support for the Tegra132 Norrin and various Tegra210-based reference designs. There is also an initial device tree for the Jetson TX1 development kit. * tag 'tegra-for-4.5-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Add NVIDIA Jetson TX1 Developer Kit support arm64: tegra: Add NVIDIA P2597 I/O board support arm64: tegra: Add NVIDIA Jetson TX1 support arm64: tegra: Add NVIDIA P2571 board support arm64: tegra: Add NVIDIA P2371 board support arm64: tegra: Add NVIDIA P2595 I/O board support arm64: tegra: Add NVIDIA P2530 main board support arm64: tegra: Add Tegra210 support arm64: tegra: Add NVIDIA Tegra132 Norrin support arm64: tegra: Add Tegra132 support clk: tegra: Add Tegra210 device tree binding Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | arm64: tegra: Add NVIDIA Jetson TX1 Developer Kit supportThierry Reding2015-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Jetson TX1 Development Kit is the successor of the Jetson TK1. The Jetson TX1 is composed of the Jetson TX1 module (P2180) that connects to the P2597 I/O board. It comes with a 1200x1920 MIPI DSI panel connected via the P2597's display connector. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | arm64: tegra: Add NVIDIA P2597 I/O board supportThierry Reding2015-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NVIDIA P2597 I/O board is a carrier board for the Jetson TX1 module and together they are also known as the Jetson TX1 Developer Kit. The I/O board provides an RJ45 connector routed to the network adapter that is part of the Jetson TX1 module. It exposes many other connectors such as SATA, USB 3.0, HDMI, JTAG and PCIe, among others, as well. Dedicated connectors allow display and camera modules to be attached. A full-size SD slot is provided to extend storage beyond the 32 GiB of eMMC found on the Jetson TX1 module. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | arm64: tegra: Add NVIDIA Jetson TX1 supportThierry Reding2015-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NVIDIA Jetson TX1 is a processor module that features a Tegra210 SoC with 4 GiB of LPDDR4 RAM attached, a 32 GiB eMMC and other essentials. It is typically connected to some I/O board (such as the P2597) that has the connectors needed to hook it up to the outside world. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | arm64: tegra: Add NVIDIA P2571 board supportThierry Reding2015-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NVIDIA P2571 is an internal reference design that's very similar to the P2371, but targetting different use-cases. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | arm64: tegra: Add NVIDIA P2371 board supportThierry Reding2015-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NVIDIA P2371 is an internal reference design that uses a P2530 processor module hooked up to a P2595 I/O board and an optional display module for a 1200x1920 MIPI DSI panel. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | arm64: tegra: Add NVIDIA P2595 I/O board supportThierry Reding2015-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NVIDIA P2595 I/O board is used in several reference designs and has the connectors to connect the P2530 compute module to the outside world. It features a USB 3.0 network adapter, a USB 3.0 port, an HDMI port, a SATA port, an audio codec, a microSD card slot and a display connector, among others. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | arm64: tegra: Add NVIDIA P2530 main board supportThierry Reding2015-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NVIDIA P2530 is a processor module used in several reference designs that features a Tegra210 SoC, 4 GiB of LPDDR4 RAM, 16 GiB eMMC and other essentials. It is typically connected to some I/O board that provides the connectors needed to hook it up to the outside world. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | arm64: tegra: Add Tegra210 supportThierry Reding2015-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 cores in a switched configuration. It features a GPU using the Maxwell architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware accelerated en- and decoding of various video standards including H.265, H.264 and VP8 at 4K resolutions and up to 60 fps. Besides the multimedia features it also comes with a variety of I/O controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to name only a few. Add a SoC-level device tree file that describes most of the hardware available on the SoC. This includes only hardware for which a device tree binding already exists or which is trivial to describe. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | arm64: tegra: Add NVIDIA Tegra132 Norrin supportThierry Reding2015-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Norrin is a Tegra132-based FFD used as reference platform within NVIDIA. Based on work by Allen Martin <amartin@nvidia.com> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Allen Martin <amartin@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | arm64: tegra: Add Tegra132 supportThierry Reding2015-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NVIDIA Tegra132 (also known as Tegra K1 64-bit) is a variant of Tegra124 but with 2 Denver CPUs instead of the 4+1 Cortex-A15. This adds the DTSI file for the SoC, which is mostly similar to the one for Tegra124. Based on work by Allen Martin <amartin@nvidia.com> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Allen Martin <amartin@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | | | Merge tag 'tegra-for-4.5-soc' of ↵Olof Johansson2016-01-12
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into late/tegra ARM: tegra: Core SoC changes for v4.5-rc1 The big thing here is Tegra210 support, which is really only the Kconfig symbol. Other than that there's a few miscellaneous fixes. * tag 'tegra-for-4.5-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: select USB_ULPI from EHCI rather than platform ARM: tegra: Ensure entire dcache is flushed on entering LP0/1 amba: Hide TEGRA_AHB symbol soc/tegra: Add Tegra210 support soc/tegra: Provide per-SoC Kconfig symbols Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | | ARM: tegra: select USB_ULPI from EHCI rather than platformArnd Bergmann2015-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For historic reasons, the tegra platform selects USB_ULPI from architecture code, but that hasn't really made sense for a long time, as the only user of that code is the Tegra EHCI driver that has its own Kconfig symbol. This removes the 'select' statements from mach-tegra and drivers/soc/tegra and adds them with the device driver that actually needs them. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | ARM: tegra: Ensure entire dcache is flushed on entering LP0/1Jon Hunter2015-11-24
| | |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra support several low-power (LPx) states, which are: - LP0: CPU + Core voltage off and DRAM in self-refresh - LP1: CPU voltage off and DRAM in self-refresh - LP2: CPU voltage off When entering any of the above states the tegra_disable_clean_inv_dcache() function is called to flush the dcache. The function tegra_disable_clean_inv_dcache() will either flush the entire data cache or up to the Level of Unification Inner Shareable (LoUIS) depending on the value in r0. When tegra_disable_clean_inv_dcache() is called by tegra20_sleep_core_finish() or tegra30_sleep_core_finish(), to enter LP0 and LP1 power state, the r0 register contains a physical memory address which will not be equal to TEGRA_FLUSH_CACHE_ALL (1) and so the data cache will be only flushed to the LoUIS. However, when tegra_disable_clean_inv_dcache() called by tegra_sleep_cpu_finish() to enter to LP2 power state, r0 is set to TEGRA_FLUSH_CACHE_ALL to flush the entire dcache. Please note that tegra20_sleep_core_finish(), tegra30_sleep_core_finish() and tegra_sleep_cpu_finish() are called by the boot CPU once all other CPUs have been disabled and so it seems appropriate to flush the entire cache at this stage. Therefore, ensure that r0 is set to TEGRA_FLUSH_CACHE_ALL when calling tegra_disable_clean_inv_dcache() from tegra20_sleep_core_finish() and tegra30_sleep_core_finish(). Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | soc/tegra: Provide per-SoC Kconfig symbolsThierry Reding2015-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move per-SoC generation Kconfig symbols to drivers/soc/tegra/Kconfig to gather them all in a single place. This directory is a natural location for these options since it already contains the drivers that are shared across 32-bit and 64-bit ARM architectures. Signed-off-by: Thierry Reding <treding@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-05 14:52:00 -0400