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* powerpc/85xx: Add ucc uart support for p1025rdbZhicheng Fan2012-07-10
| | | | | | | Add device tree nodes to enable ucc uart support on P1025RDB. Signed-off-by: Zhicheng Fan <B32736@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add BSC9131 RDB SupportPrabhakar Kushwaha2012-07-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BSC9131RDB is a Freescale reference design board for BSC9131 SoC. The BSC9131 is integrated SoC that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. The BSC9131 SoC includes the following function and features: . Power Architecture subsystem including a e500 processor with 256-Kbyte shared L2 cache . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband Processing (MAPLE-B2F) . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms . Consists of accelerators for Convolution, Filtering, Turbo Encoding, Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with ECC, up to 400-MHz clock/800 MHz data rate . Dedicated security engine featuring trusted boot . DMA controller . OCNDMA with four bidirectional channels . Interfaces . Two triple-speed Gigabit Ethernet controllers featuring network acceleration including IEEE 1588. v2 hardware support and virtualization (eTSEC) . eTSEC 1 supports RGMII/RMII . eTSEC 2 supports RGMII . High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC) . Antenna interface controller (AIC), supporting three industry standard JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces . ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards . TDM with one TDM port . Two DUART, four eSPI, and two I2C controllers . Integrated Flash memory controller (IFC) . TDM with 256 channels . GPIO . Sixteen 32-bit timers The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations. BSC9131RDB Overview ---------------------- BSC9131 SoC 1Gbyte DDR3 (on board DDR) 128Mbyte 2K page size NAND Flash 256 Kbit M24256 I2C EEPROM 128 Mbit SPI Flash memory USB-ULPI eTSEC1: Connected to RGMII PHY eTSEC2: Connected to RGMII PHY DUART interface: supports one UARTs up to 115200 bps for console display Linux runs on e500v2 core and access some DSP peripherals like AIC Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Revert "powerpc/p3060qds: Add support for P3060QDS board"Timur Tabi2012-07-10
| | | | | | | | | | This reverts commit 96cc017c5b7ec095ef047d3c1952b6b6bbf98943. The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc85xx: add MPIC message dts nodeMingkai Hu2012-04-19
| | | | | Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/fsl: Added aliased MSIIR register address to MSI node in dtsDiana CRACIUN2012-03-16
| | | | | | | | | | | | | | | The MSIIR register for each MSI bank is aliased to a different address. The MSI node reg property was updated to contain this address: e.g. reg = <0x41600 0x200 0x44140 4>; The first region contains the address and length of the MSI register set and the second region contains the address of the aliased MSIIR register at 0x44140. Signed-off-by: Diana CRACIUN <Diana.Craciun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: mpc8548cds - fix alias in mpc8548si-pre.dtsiZhao Chenhui2012-03-16
| | | | | | | | Correct ethernet1 and add ethernet2 and ethernet3. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: mpc8548cds - Add RapidIO node to dtschenhui zhao2012-03-16
| | | | | | | | Enable RapidIO and add rapidio and rmu nodes to dts. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/dts: fix the compatible string of sec 4.0Liu Shuo2012-03-16
| | | | | | | | | Fix the compatible string of sec 4.0 to match with CAAM driver according to Documentation/devicetree/bindings/crypto/fsl-sec4.txt Signed-off-by: Liu Shuo <shuo.liu@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: p1022ds: disable the NOR flash node if video is enabledTimur Tabi2012-03-16
| | | | | | | | | | | | | | | | The Freescale P1022 has a unique pin muxing "feature" where the DIU video controller's video signals are muxed with 24 of the local bus address signals. When the DIU is enabled, the bulk of the local bus is disabled, preventing access to memory-mapped devices like NOR flash and the pixis FPGA. Therefore, if the DIU is going to be enabled, then memory-mapped devices on the localbus, like NOR flash, need to be disabled. This also means that the localbus is not a 'simple-bus' any more, so remove that string from the compatible node. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add magic-packet properties for etsecXie Xiaobo2012-03-16
| | | | | | | | The properties indicates that the hardware supports waking up via magic packet. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add usb controller version infoRamneek Mehresh2012-03-16
| | | | | | | | | Add usb controller version info for the following: MPC8536, P1010, P1020, P1021, P1022, P1023, P2020, P2041, P3041, P3060, P5020 Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Added dts for P1021RDB-PC boardXu Jiucheng2012-03-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | P1021RDB-PC Overview ----------------- 1Gbyte DDR3 (on board DDR) 16Mbyte NOR flash 32Mbyte eSLC NAND Flash 256 Kbit M24256 I2C EEPROM 128 Mbit SPI Flash memory Real-time clock on I2C bus SD/MMC connector to interface with the SD memory card PCIex - x1 PCIe slot or x1 PCIe to dual SATA controller - x1 mini-PCIe slot USB 2.0 - ULPI PHY interface: SMSC USB3300 USB PHY and Genesys Logic’s GL850A - Two USB2.0 Type A receptacles - One USB2.0 signal to Mini PCIe slot eTSEC1: Connected to RGMII PHY VSC7385 eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY AR8021 DUART interface: supports two UARTs up to 115200 bps for console display Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Xu Jiucheng <B37781@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpic: Add "last-interrupt-source" property to override hardwareKyle Moffett2012-02-22
| | | | | | | | | | | | The FreeScale PowerQUICC-III-compatible (mpc85xx/mpc86xx) MPICs do not correctly report the number of hardware interrupt sources, so software needs to override the detected value with "256". To avoid needing to write custom board-specific code to detect that scenario, allow it to be easily overridden in the device-tree. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* fsl/mpic: Create and document the "single-cpu-affinity" device-tree flagKyle Moffett2012-02-22
| | | | | | | | | | | | | | | | The Freescale MPIC (and perhaps others in the future) is incapable of routing non-IPI interrupts to more than once CPU at a time. Currently all of the Freescale boards msut pass the MPIC_SINGLE_DEST_CPU flag to mpic_alloc(), but that information should really be present in the device-tree. Older board code can't rely on the device-tree having the property set, but newer platforms won't need it manually specified in the code. [BenH: Remove unrelated changes, folded in a different patch] Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* fsl/mpic: Document and use the "big-endian" device-tree flagKyle Moffett2012-02-22
| | | | | | | | | | | | | | | | | The MPIC code checks for a "big-endian" property and sets the flag MPIC_BIG_ENDIAN if one is present, although prior to the "mpic->flags" fixup that would never have worked anways. Unfortunately, even now that it works properly, the Freescale mpic device-node (the "PowerQUICC-III"-compatible one) does not specify it, so all of the board ports need to manually pass it to mpic_alloc(). Document the flag and add it to the pq3 device tree. Existing code will still need to pass the MPIC_BIG_ENDIAN flag because their dtb may not have this property, but new platforms shouldn't need to do so. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/85xx: Fix cmd12 bug and add the chip compatible for eSDHCJerry Huang2012-01-18
| | | | | | | | | | | According to latest kernel, the auto-cmd12 property should be "sdhci,auto-cmd12", and according to the SDHC binding and the workaround for the special chip, add the chip compatible for eSDHC: "fsl,p1022-esdhc", "fsl,mpc8536-esdhc", "fsl,p1020-esdhc", "fsl,p2020-esdhc" and "fsl,p1010-esdhc". Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/fsl: update compatiable on fsl 16550 uart nodesKumar Gala2012-01-04
| | | | | | | | The Freescale serial port's are pretty much a 16550, however there are some FSL specific bugs and features. Add a "fsl,ns16550" compatiable string to allow code to handle those FSL specific issues. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Update SRIO device tree nodesKumar Gala2011-11-24
| | | | | | | Update all dts files that support SRIO controllers to match the new fsl,srio device tree binding. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P5020DS device treeKumar Gala2011-11-24
| | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Adding of MPIC timer blocks * Dropping "fsl,p5020-IP..." from compatibles for standard blocks * Removed mpic interrupt-parent from dcsr-epu node, just use top level * Removed mpic interrupt-parent from sec nodes, just use top level Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P4080DS device treesKumar Gala2011-11-24
| | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Adding of MPIC timer blocks * Dropping "fsl,p4080-IP..." from compatibles for standard blocks * Removed mpic interrupt-parent from dcsr-epu node, just use top level * Removed mpic interrupt-parent from sec nodes, just use top level Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P3060QDS device treeKumar Gala2011-11-24
| | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Adding of MPIC timer blocks * Dropping "fsl,p3060-IP..." from compatibles for standard blocks * Removed mpic interrupt-parent from dcsr-epu node, just use top level * Removed mpic interrupt-parent from sec nodes, just use top level * Fixed l3-cache IRQs, we have 2 CPCs, so we should have IRQs for both Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P3041DS device treeKumar Gala2011-11-24
| | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Adding of MPIC timer blocks * Dropping "fsl,p3041-IP..." from compatibles for standard blocks * Removed mpic interrupt-parent from dcsr-epu node, just use top level * Fixed some dcsr compatiable typo's from 'p43041' to 'p3041' Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P2041RDB device treeKumar Gala2011-11-24
| | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Adding of MPIC timer blocks * Dropping "fsl,p2041-IP..." from compatibles for standard blocks * Removed mpic interrupt-parent from dcsr-epu node, just use top level Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P2020DS device treeKumar Gala2011-11-24
| | | | | | | | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Updated spi node to new espi binding specification * Renamed 'sdhci' node to 'sdhc' * Changed GPIO compatiable from 'fsl,mpc8572-gpio' to 'fsl,pq3-gpio' as the 'mpc8572' compatiable is to deal with a 'mpc8572' specific to an erratum * Fixed wrong reg offsets for mdio nodes associated with etsec2 & etsec3 * Dropping "fsl,p2020-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P1023RDS device treeKumar Gala2011-11-24
| | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Dropping "fsl,p1023-IP..." from compatibles for standard blocks * Removed incorrect power/pmc node, there are no etsec on P1023 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P1022DS device treeKumar Gala2011-11-24
| | | | | | | | | | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Changed GPIO compatiable from 'fsl,mpc8572-gpio' to 'fsl,pq3-gpio' as the 'mpc8572' compatiable is to deal with a 'mpc8572' specific to an erratum * Updated spi node to new espi binding specification * Renamed SDHC node from 'sdhci' to 'sdhc' * Added usb node for 2nd usb controller * Dropping "fsl,p1022-IP..." from compatibles for standard blocks * Fixed bug in local bus range node for CS2, was maping to 0x0 0x0xffa00000 instead of 0xf 0xffa00000 * Fixed localbus reg property should have been 0xf 0xffe05000 Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Tested-by: Timur Tabi <timur@freescale.com>
* powerpc/85xx: Rework P1021MDS device treeKumar Gala2011-11-24
| | | | | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Renamed SDHC node from 'sdhci' to 'sdhc' * Added usb node for 2nd usb controller * Dropping "fsl,p1021-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P1020RDB device treeKumar Gala2011-11-24
| | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Dropping "fsl,p1020-IP..." from compatibles for standard blocks * Fixed PCIe interrupt-maps to have proper number of cells * Added mdio node for etsec@26000 * Added usb node for 2nd usb controller Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add crypto engine to P1010 SoC device treeKumar Gala2011-11-24
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P1010RDB and P1010 device treeKumar Gala2011-11-24
| | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Dropping "fsl,p1010-IP..." from compatibles for standard blocks * PCI interrupt map - wrong IRQs for PCI-0 controller * SDHC interrupt sense was wrong Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8572DS device treeKumar Gala2011-11-24
| | | | | | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Added GPIO controller node to MPC8572 SoC template * Dropping "fsl,mpc8572-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8569MDS device treeKumar Gala2011-11-24
| | | | | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Renamed SDHC node from 'sdhci' to 'sdhc' * Dropping "fsl,mpc8569-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8568MDS device treeKumar Gala2011-11-24
| | | | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Dropping "fsl,mpc8568-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8548CDS device treesKumar Gala2011-11-24
| | | | | | | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Moved mdio nodes up one level instead of under tsec nodes * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Added MPIC / PCIe msi node * Dropping "fsl,mpc8548-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8544DS device treeKumar Gala2011-11-24
| | | | | | | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Updated ethernet 'model' to 'eTSEC' as that's what on MPC8544 * Dropping "fsl,mpc8544-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8536DS device treesKumar Gala2011-11-24
| | | | | | | | | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) * and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Added GPIO controller node to MPC8536 SoC template [ marked as MPC8572 compatiable to get errata handling that applies ] * Added missing cache-line-size & cache-size properties missing from L2-cache node * Added IP level IEEE 1588 / ptp timer node Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: create dts components to build up an SoCKumar Gala2011-11-24
Introduce some common components that we can utilize to build up the various PQ3/85xx device trees. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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