| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | nds32: To fix a cache inconsistency issue by setting correct cacheability of NTC | Greentime Hu | 2018-05-23 |
| | | | | | | | | | | | | | | | | The nds32 architecture will use physical memory when interrupt or exception comes and it will use the setting of NTC0-4. The original implementation didn't consider the DRAM start address may start from 1GB, 2GB or 3GB to cause this issue. It will write the data to DRAM if it is running in physical address however kernel will read the data with virtaul address through data cache. In this case, the data of DRAM is latest. This fix will set the correct cacheability to let kernel write/read the latest data in cache instead of DRAM. Signed-off-by: Greentime Hu <greentime@andestech.com> | ||
| * | nds32: To refine readability of INT_MASK_INITAIAL_VAL | Greentime Hu | 2018-05-23 |
| | | | | | | | | Refine readability of INT_MASK_INITAIAL_VAL with meaningful macro instead of magic number. Signed-off-by: Greentime Hu <greentime@andestech.com> | ||
| * | nds32: Assembly macros and definitions | Greentime Hu | 2018-02-21 |
| This patch includes assembly macros, bit field definitions used in .S files across arch/nds32/. Signed-off-by: Vincent Chen <vincentc@andestech.com> Signed-off-by: Greentime Hu <greentime@andestech.com> Acked-by: Arnd Bergmann <arnd@arndb.de> | |||
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index : litmus-rt-ext-res.git | |
| LITMUS^RT with extended reservations for Forbidden Zones paper @ RTAS'20 | Zelin Tong |
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