aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/mm
Commit message (Collapse)AuthorAge
...
* MIPS: uasm: Add s3s1s2 instruction builderMarkos Chandras2014-06-26
| | | | | | | | | It will be used later on by the SLT instruction. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7119/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2014-06-09
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: - three fixes for 3.15 that didn't make it in time - limited Octeon 3 support. - paravirtualization support - improvment to platform support for Netlogix SOCs. - add support for powering down the Malta eval board in software - add many instructions to the in-kernel microassembler. - add support for the BPF JIT. - minor cleanups of the BCM47xx code. - large cleanup of math emu code resulting in significant code size reduction, better readability of the code and more accurate emulation. - improvments to the MIPS CPS code. - support C3 power status for the R4k count/compare clock device. - improvments to the GIO support for older SGI workstations. - increase number of supported CPUs to 256; this can be reached on certain embedded multithreaded ccNUMA configurations. - various small cleanups, updates and fixes * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (173 commits) MIPS: IP22/IP28: Improve GIO support MIPS: Octeon: Add twsi interrupt initialization for OCTEON 3XXX, 5XXX, 63XX DEC: Document the R4k MB ASIC mini interrupt controller DEC: Add self as the maintainer MIPS: Add microMIPS MSA support. MIPS: Replace calls to obsolete strict_strto call with kstrto* equivalents. MIPS: Replace obsolete strict_strto call with kstrto MIPS: BFP: Simplify code slightly. MIPS: Call find_vma with the mmap_sem held MIPS: Fix 'write_msa_##' inline macro. MIPS: Fix MSA toolchain support detection. mips: Update the email address of Geert Uytterhoeven MIPS: Add minimal defconfig for mips_paravirt MIPS: Enable build for new system 'paravirt' MIPS: paravirt: Add pci controller for virtio MIPS: Add code for new system 'paravirt' MIPS: Add functions for hypervisor call MIPS: OCTEON: Add OCTEON3 to __get_cpu_type MIPS: Add function get_ebase_cpunum MIPS: Add minimal support for OCTEON3 to c-r4k.c ...
| * Merge branch '3.15-fixes' into mips-for-linux-nextRalf Baechle2014-06-04
| |\
| | * MIPS: Call find_vma with the mmap_sem heldDavidlohr Bueso2014-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Performing vma lookups without taking the mm->mmap_sem is asking for trouble. While doing the search, the vma in question can be modified or even removed before returning to the caller. Take the lock (exclusively) in order to avoid races while iterating through the vmacache and/or rbtree. Updates two functions: - process_fpemu_return() - cteon_flush_cache_sigtramp() Signed-off-by: Davidlohr Bueso <davidlohr@hp.com> Tested-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: akpm@linux-foundation.org Cc: zeus@gnu.org Cc: aswin@hp.com Cc: davidlohr@hp.com Cc: linux-mm@kvack.org Cc: linux-kernel@vger.kernel.org Patchwork: http://patchwork.linux-mips.org/patch/6811/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Add code for new system 'paravirt'David Daney2014-06-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For para-virtualized guests running under KVM or other equivalent hypervisor. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7004/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Add minimal support for OCTEON3 to c-r4k.cDavid Daney2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are needed to boot a generic mips64r2 kernel on OCTEONIII. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7003/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Don't build fast TLB refill handler with 32-bit kernelsDavid Daney2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fast handler only supports 64-bit kernels. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7010/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: uasm: Add lb uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | MIPS: uasm: Add mflo uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
| * | MIPS: uasm: Add mul uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6736/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: uasm: Add lh uam instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6733/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: uasm: Add wsbh uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6732/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: uasm: Add sltu uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6731/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: uasm: Add sltiu uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6730/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: uasm: Add jalr uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6729/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: uasm: Add mfhi uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: http://patchwork.linux-mips.org/patch/6728/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: uasm: Add divu uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6727/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: uasm: Add srlv uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Fixed conflict due to other preceeding conflicts.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6726/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: uasm: Add sllv uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Fixed conflict with 49e9529b9d43773307b8c73bd251b71784830c3d [MIPS: uasm: add jalr instruction]. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6725/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: uasm: Add u3u2u1 instruction buildersMarkos Chandras2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | It will be used later on by the sllv and srlv instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6723/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | Merge branch 'wip-mips-pm' of https://github.com/paulburton/linux into ↵Ralf Baechle2014-05-29
| |\ \ | | | | | | | | | | | | mips-for-linux-next
| | * | MIPS: uasm: add MT ASE yield instructionPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows use of the MT ASE yield instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | MIPS: uasm: add wait instructionPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows use of the wait instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | MIPS: uasm: add sync instructionPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows use of the sync instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | MIPS: uasm: add jalr instructionPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows use of the jalr instruction from uasm. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | MIPS: uasm: add a label variant of beqPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows for use of the beq instruction with labels from uasm, much as bne & others already do. It will be used by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | MIPS: add kmap_noncoherent to wire a cached non-coherent TLB entryPaul Burton2014-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is identical to kmap_coherent apart from the cache coherency attribute used for the TLB entry, so kmap_coherent is abstracted to kmap_prot which is then called for both kmap_coherent & kmap_noncoherent. This will be used by a subsequent patch. Suggested-by: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | MIPS: tlb-r4k: Add CPU PM callback to reconfigure TLBJames Hogan2014-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a CPU power management callback for the r4k TLB which reconfigures it after the CPU leaves a powered down state. Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| | * | MIPS: c-r4k: Add CPU PM callback for coherencyJames Hogan2014-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement a CPU power management callback for the r4k cache, to set up coherency again after leaving a powered down state. Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | | MIPS: MT: Remove SMTC supportRalf Baechle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nobody is maintaining SMTC anymore and there also seems to be no userbase. Which is a pity - the SMTC technology primarily developed by Kevin D. Kissell <kevink@paralogos.com> is an ingenious demonstration for the MT ASE's power and elegance. Based on Markos Chandras <Markos.Chandras@imgtec.com> patch https://patchwork.linux-mips.org/patch/6719/ which while very similar did no longer apply cleanly when I tried to merge it plus some additional post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to merge once upon a time. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: c-r4k: Call R4600_HIT_CACHEOP_WAR_IMPL only for 32 byte cache lines.Ralf Baechle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R4600_HIT_CACHEOP_WAR_IMPL is only needed on R4600 v1.6 and the R4600 has data cache lines that are always 32 bytes so the call is pointless in r4k_blast_dcache_page_dc64. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | hugetlb: restrict hugepage_migration_support() to x86_64Naoya Horiguchi2014-06-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently hugepage migration is available for all archs which support pmd-level hugepage, but testing is done only for x86_64 and there're bugs for other archs. So to avoid breaking such archs, this patch limits the availability strictly to x86_64 until developers of other archs get interested in enabling this feature. Simply disabling hugepage migration on non-x86_64 archs is not enough to fix the reported problem where sys_move_pages() hits the BUG_ON() in follow_page(FOLL_GET), so let's fix this by checking if hugepage migration is supported in vma_migratable(). Signed-off-by: Naoya Horiguchi <n-horiguchi@ah.jp.nec.com> Reported-by: Michael Ellerman <mpe@ellerman.id.au> Tested-by: Michael Ellerman <mpe@ellerman.id.au> Acked-by: Hugh Dickins <hughd@google.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Tony Luck <tony.luck@intel.com> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: David Miller <davem@davemloft.net> Cc: <stable@vger.kernel.org> [3.12+] Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | | Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm into nextLinus Torvalds2014-06-04
|\ \ \ \ | |_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull KVM updates from Paolo Bonzini: "At over 200 commits, covering almost all supported architectures, this was a pretty active cycle for KVM. Changes include: - a lot of s390 changes: optimizations, support for migration, GDB support and more - ARM changes are pretty small: support for the PSCI 0.2 hypercall interface on both the guest and the host (the latter acked by Catalin) - initial POWER8 and little-endian host support - support for running u-boot on embedded POWER targets - pretty large changes to MIPS too, completing the userspace interface and improving the handling of virtualized timer hardware - for x86, a larger set of changes is scheduled for 3.17. Still, we have a few emulator bugfixes and support for running nested fully-virtualized Xen guests (para-virtualized Xen guests have always worked). And some optimizations too. The only missing architecture here is ia64. It's not a coincidence that support for KVM on ia64 is scheduled for removal in 3.17" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (203 commits) KVM: add missing cleanup_srcu_struct KVM: PPC: Book3S PR: Rework SLB switching code KVM: PPC: Book3S PR: Use SLB entry 0 KVM: PPC: Book3S HV: Fix machine check delivery to guest KVM: PPC: Book3S HV: Work around POWER8 performance monitor bugs KVM: PPC: Book3S HV: Make sure we don't miss dirty pages KVM: PPC: Book3S HV: Fix dirty map for hugepages KVM: PPC: Book3S HV: Put huge-page HPTEs in rmap chain for base address KVM: PPC: Book3S HV: Fix check for running inside guest in global_invalidates() KVM: PPC: Book3S: Move KVM_REG_PPC_WORT to an unused register number KVM: PPC: Book3S: Add ONE_REG register names that were missed KVM: PPC: Add CAP to indicate hcall fixes KVM: PPC: MPIC: Reset IRQ source private members KVM: PPC: Graciously fail broken LE hypercalls PPC: ePAPR: Fix hypercall on LE guest KVM: PPC: BOOK3S: Remove open coded make_dsisr in alignment handler KVM: PPC: BOOK3S: Always use the saved DAR value PPC: KVM: Make NX bit available with magic page KVM: PPC: Disable NX for old magic page using guests KVM: PPC: BOOK3S: HV: Add mixed page-size support for guest ...
| * | | MIPS: Export local_flush_icache_range for KVMJames Hogan2014-05-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Export the local_flush_icache_range function pointer for GPL modules so that it can be used by KVM for syncing the icache after binary translation of trapping instructions. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: kvm@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Sanjay Lal <sanjayl@kymasys.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | | | MIPS: R46000: Fix Micro-assembler field overflow for R4600 V2Thomas Bogendoerfer2014-05-28
| |/ / |/| | | | | | | | | | | | | | | | | | | | | | | Fix uasm warning, which triggered because of workaround for R4600 V2 CPUs. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6716/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: mm: Fix broken microMIPS kernel regression.Steven J. Hill2014-05-14
| |/ |/| | | | | | | | | | | | | | | | | | | | | Commit f4ae17aa0f2122b52f642985b46210a1f2eceb0a [MIPS: mm: Use scratch for PGD when !CONFIG_MIPS_PGD_C0_CONTEXT] broke microMIPS kernel builds. This patch refactors that code similar to what was done for the 'clear_page' and 'copy_page' functions. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6744/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | mips: export flush_icache_rangeKees Cook2014-04-18
|/ | | | | | | | | | | | | | | | The lkdtm module performs tests against executable memory ranges, so it needs to flush the icache for proper behaviors. Other architectures already export this, so do the same for MIPS. [akpm@linux-foundation.org: relocate export sites] Signed-off-by: Kees Cook <keescook@chromium.org> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Sanjay Lal <sanjayl@kymasys.com> Cc: John Crispin <blogic@openwrt.org> Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* MIPS: Loongson: Add basic Loongson-3 CPU supportHuacai Chen2014-03-31
| | | | | | | | | | | | | | | | | | | Basic Loongson-3 CPU support include CPU probing and TLB/cache initializing. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6630 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Use current_cpu_type() instead of c->cputypeWu Zhangjin2014-03-31
| | | | | | | | | | If current_cpu_type() is pre-defined in cpu-feature-overrides.h, This may save about 10k for the compressed kernel image(vmlinuz). Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1901/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add support for the M5150 processorLeonid Yegoshin2014-03-26
| | | | | | | | | | | | | | The M5150 core is a 32-bit MIPS RISC which implements the MIPS Architecture Release-5 in a 5-stage pipeline. In addition, it includes the MIPS Architecture Virtualization Module that enables virtualization of operating systems, which provides a scalable, trusted, and secure execution environment. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6596/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Extend DMA_MAYBE_COHERENT logic to DMA_NONCOHERENT useManuel Lauss2014-03-26
| | | | | | | | | | Setting DMA_MAYBE_COHERENT gives a platform the opportunity to select use of cache ops at boot. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/6575/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: mm: c-r4k: Flush scache to avoid cache aliasesLeonid Yegoshin2014-03-26
| | | | | | | | | | | | There is a chance for the secondary cache to have memory aliases. This can happen if the bootloader is in a non-EVA mode (or even in EVA mode but with different mapping from the kernel) and the kernel switching to EVA afterwards. It's best to flush the icache to avoid having the secondary CPUs fetching stale data from it. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: mm: c-r4k: Add support for flushing user pages from cacheMarkos Chandras2014-03-26
| | | | | | | Use the userspace cache flushing functions if the interrupted process is a userspace one. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: mm: c-r4k: Build EVA {d,i}cache flushing functionsLeonid Yegoshin2014-03-26
| | | | | | | | Build EVA specific cache flushing functions (ie cachee). They will be used by a subsequent patch. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: mm: init: Add free_init_pages() callback for EVAMarkos Chandras2014-03-26
| | | | | | | | A core in EVA mode can have any possible segment mapping, so the default free_initmem_default() function may not always work as expected. Therefore, add a callback that platforms can use to free up the init section. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Add cases for CPU_P5600James Hogan2014-03-26
| | | | | | | | | | | Add a CPU_P5600 case to various switch statements, doing the same thing as for CPU_PROAPTIV. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6408/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Coherent Processing System SMP implementationPaul Burton2014-03-26
| | | | | | | | | | | | | | | | | | This patch introduces a new SMP implementation for systems implementing the MIPS Coherent Processing System architecture. The kernel will make use of the Coherence Manager, Cluster Power Controller & Global Interrupt Controller in order to detect, bring up & make use of other cores in the system. SMTC is not supported, so only a single TC per VPE in the system is used. That is, this option enables an SMVP style setup but across multiple cores. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6362/ Patchwork: https://patchwork.linux-mips.org/patch/6611/ Patchwork: https://patchwork.linux-mips.org/patch/6651/ Patchwork: https://patchwork.linux-mips.org/patch/6652/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add 1074K CPU support explicitly.Steven J. Hill2014-03-06
| | | | | | | | | | | | The 1074K is a multiprocessing coherent processing system (CPS) based on modified 74K cores. This patch makes the 1074K an actual unique CPU type, instead of a 74K derivative, which it is not. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6389/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: mm: c-r4k: Detect instruction cache aliasesMarkos Chandras2014-03-06
| | | | | | | | | | | | | The *Aptiv cores can use the CONF7/IAR bit to detect if the core has hardware support to remove instruction cache aliasing. This also defines the CONF7/AR bit in order to avoid using the '16' magic number. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6499/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2014-01-30
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: "The most notable new addition inside this pull request is the support for MIPS's latest and greatest core called "inter/proAptiv". The patch series describes this core as follows. "The interAptiv is a power-efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The interAptiv combines a multi-threading pipeline with a coherence manager to deliver improved computational throughput and power efficiency. The interAptiv can contain one to four MIPS32R3 interAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit." The platform specific patches touch all 3 Broadcom families. It adds support for the new Broadcom/Netlogix XLP9xx Soc, building a common BCM63XX SMP kernel for all BCM63XX SoCs regardless of core type/count and full gpio button/led descriptions for BCM47xx. The rest of the series are cleanups and bug fixes that are MIPS generic and consist largely of changes that Imgtec/MIPS had published in their linux-mti-3.10.git stable tree. Random other cleanups and patches preparing code to be merged in 3.15" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits) mips: select ARCH_MIGHT_HAVE_PC_SERIO mips: delete non-required instances of include <linux/init.h> MIPS: KVM: remove shadow_tlb code MIPS: KVM: use common EHINV aware UNIQUE_ENTRYHI mips/ide: flush dcache also if icache does not snoop dcache MIPS: BCM47XX: fix position of cpu_wait disabling MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_<N> MIPS: introduce MIPS_L1_CACHE_SHIFT_<N> MIPS: ZBOOT: gather string functions into string.c arch/mips/pci: don't check resource with devm_ioremap_resource arch/mips/lantiq/xway: don't check resource with devm_ioremap_resource bcma: gpio: don't cast u32 to unsigned long ssb: gpio: add own IRQ domain MIPS: BCM47XX: fix sparse warnings in board.c MIPS: BCM47XX: add board detection for Linksys WRT54GS V1 MIPS: BCM47XX: fix detection for some boards MIPS: BCM47XX: Enable buttons support on SSB MIPS: BCM47XX: Convert WNDR4500 to new syntax MIPS: BCM47XX: Use "timer" trigger for status LEDs ...
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-25 00:53:32 -0400