| Commit message (Collapse) | Author | Age |
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The Libretech ALL-H3-CC has a high density connector for attaching
an eMMC module. The module form factor and connection is specific
to Libretech, and has provisions for split vmmc/vqmmc (core and I/O)
voltage supplies, but this board does not wire the vqmmc side. The
H2+/H3/H5 SoCs do not support alternate I/O voltages for eMMC either.
Only 3.3V is supported. A specific module that ties vqmmc to vmmc,
with both at 3.3V, must be used.
Given that a) eMMC is not designed to be hotplugged, b) power is
always provided on the pins, and c) MMC controllers can deal with
missing cards, we can enable this by default. If a module is attached
it will be picked up by the system.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Banana Pi M2 Zero board has a SY8113B regulator, which is controlled via
GPIO and capable of outputing 1.1V when the PL1 GPIO is set to output 0
or 1.1V when the PL6 GPIO is set to input or output 1, and the output is
the power supply of the ARM cores in H3 SoC.
Add the device tree node of this regulator and set the cpu's cpu-supply
property to it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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The enabling of the EMAC was reverted as there was an issue on how
to handle the integrated PHY and it was getting close to the release
window (fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes")).
When a solution was found, then the changes were restored in
4b236a0fe512 ("arm: dts: sunxi: h3/h5: Restore EMAC changes") and
4904337fe34f ("ARM: dts: sunxi: Restore EMAC changes (boards)").
Unfortunately enabling for the Beelink X2 was missed.
This reverts partially commit 6b0e06df5cad (Revert "ARM: dts:
sun8i: h3: Enable dwmac-sun8i on the Beelink X2")
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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The cooling device properties, like "#cooling-cells" and
"dynamic-power-coefficient", should either be present for all the CPUs
of a cluster or none. If these are present only for a subset of CPUs of
a cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.
Add such missing properties.
Fix other missing properties (clocks, clock-names) as well to make it all
work.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt
Samsung DTS ARM changes for v4.19, part 2
1. Add missing interrupts to PWM nodes on Exynos5.
2. Add missing interrupt pin pull up/down configuration on Exynos4412
Midas boards. The interrupts were mostly working thanks to initial
configuration by bootloader.
* tag 'samsung-dt-4.19-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: Configure Midas SD card CD pin
ARM: dts: exynos: Configure max77686 IRQ pin on Midas
ARM: dts: exynos: Add pinctrl for Midas fuelgauge IRQ pin
ARM: dts: exynos: Add pinctrl config for Midas keys
ARM: dts: exynos: Add max77693 pinctrl config for Midas
ARM: dts: exynos: Add missing interrupts for pwm node on Exynos5
Signed-off-by: Olof Johansson <olof@lixom.net>
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This pin is externally pulled up, so we need to disable the SoC's
internal pull down resistor to allow it to function properly.
Signed-off-by: Simon Shields <simon@lineageos.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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This pin is externally pulled up, so we need to disable the
SoC's internal pull-down.
Signed-off-by: Simon Shields <simon@lineageos.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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This pin is externally pulled up, so we should disable the SoC's
pull down resistor in order for the interrupt to function properly.
Signed-off-by: Simon Shields <simon@lineageos.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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This pins are externally pulled up, and so we should explicitly
configure them to disable the SoC-internal pull-downs. Previously
we relied on the bootloader doing this in order to allow the buttons
to function properly.
Signed-off-by: Simon Shields <simon@lineageos.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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Currently, we assume that the bootloader has correctly configured
the interrupt pin for max77693. This might not actually be the case -
so it's better to configure it explicitly.
Signed-off-by: Simon Shields <simon@lineageos.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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Add missing GIC interrupts property for pwm nodes.
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt
Allwinner DT changes for 4.19
There's a number of additions for the ARMv7 SoCs for this merge window, and
especially:
- Addition of the system controller for a number of SoCs, as part of the
VPU effort
- Addition of the R40 HDMI support
- Addition of the Mali GPU node for the A10
* tag 'sunxi-dt-for-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (21 commits)
ARM: dts: sun4i: Add GPU node
ARM: dts: sun5i: Fix the SRAM A3-A4 declaration
ARM: dts: sun8i: r40: Remove unused address-cells/size-cells of dwmac-sun8i
ARM: dts: sun8i: a83t: Remove unused address-cells/size-cells of dwmac-sun8i
dt-bindings: net: dwmac-sun8i: Remove unused address-cells/size-cells
ARM: dts: sun8i: h3: Add SRAM controller node and C1 SRAM region
ARM: dts: sun8i: a23-a33: Add SRAM controller node and C1 SRAM region
ARM: dts: sun7i: Add support for the C1 SRAM region with the SRAM controller
ARM: dts: sun5i: Add support for the C1 SRAM region with the SRAM controller
ARM: dts: sun7i: Use most-qualified system control compatibles
ARM: dts: sun5i: Use most-qualified system control compatibles
ARM: dts: sun4i: Switch to new system control compatible string
ARM: dts: sun8i: r40: Disable TCONs by default.
ARM: dts: sun8i: r40: Add missing TCON-TOP - TCON connections
ARM: dts: sun8i: r40: Remove fallback compatible for TCON TV
ARM: dts: sun8i: r40: Add mixer ids to TCON TOP
ARM: dts: sun8i: r40: Remove fallback display engine compatible
ARM: dts: sun8i: a83t: Add CPU regulator supplies for A83T boards
ARM: dts: sun8i: r40: Enable HDMI output on BananaPi M2 Ultra
ARM: dts: sun8i: r40: Add HDMI pipeline
...
Signed-off-by: Olof Johansson <olof@lixom.net>
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Add mali gpu node to sun4i a10 platforms.
Tested with offscreen rendering with lima mesa (freedesktop gitlab)
Signed-off-by: Steven Vanden Branden <stevenvandenbrandenstift@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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According to the system control bindings, the A3-A4 SRAM node should be
a child node of the SRAM it belongs to. However, it was introduced at the
same level, therefore breaking the binding. Fix this.
Fixes: 85870196258f ("ARM: sun5i: a13: Merge common controllers into the common DTSI")
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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address-cells/size-cells is unnecessary for dwmac-sun8i node.
It was in early days, but since a mdio node is used, it could be
removed.
This patch fix the following DT warning:
Warning (avoid_unnecessary_addr_size): /soc/ethernet@1c50000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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ddress-cells/size-cells is unnecessary for dwmac-sun8i node.
It was in early days, but since a mdio node is used, it could be
removed.
This patch fix the following DT warning:
Warning (avoid_unnecessary_addr_size): /soc/ethernet@1c50000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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This adds a SRAM controller node for the H3, with support for the C1
SRAM region that is shared between the Video Engine and the CPU.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
[Maxime: Fixed the compatible and commit prefix]
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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This adds a SRAM controller node for the A23 and A33, with support for
the C1 SRAM region that is shared between the Video Engine and the CPU.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
[Maxime: Fixed the prefix and the compatibles]
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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This adds support for the C1 SRAM region (to be used with the SRAM
controller driver) for the A20 platform. The region is shared
between the Video Engine and the CPU.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
[Maxime: Fixed the SRAM C size]
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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This adds support for the C1 SRAM region (to be used with the SRAM
controller driver) for sun5i-based platforms. The region is shared
between the Video Engine and the CPU.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
[Maxime: Fixed the SRAM C size to take the C2 and C3 SRAM into account]
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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This switches the sun7i-a20 dtsi to use the most qualified compatibles
for the system-control block (previously named SRAM controller) as well
as the SRAM blocks. The sun4i-a10 compatibles are kept since these
hardware blocks are backward-compatible.
The node name for system control is also updated to reflect the fact that
the controller described is really about system control rather than SRAM
control.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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This switches the sun5i dtsi to use the most qualified compatibles for
the system-control block (previously named SRAM controller) as well as
the SRAM blocks.
The node name for system control is also updated to reflect the fact that
the controller described is really about system control rather than SRAM
control.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
[Maxime: Removed the A10 compatible for the driver]
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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This switches the sun4i-a10 dtsi to use the new compatible for the
system-control block (previously named SRAM controller) instead of
the deprecated one.
The node name is also updated to reflect the fact that the controller
described is really about system control rather than SRAM control.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
[Maxime: Amended the commit message]
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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R40 has 4 TCONs, but only 2 of them can receive some kind of output at
the same time. Let's disable them by default, so only those which are
really connected on board can be enabled in board dts file.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Current R40 is missing some graph connections between TCON TOP and
TCONs.
Add them.
Fixes: 05a43a262d03 ("ARM: dts: sun8i: r40: Add HDMI pipeline")
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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A83T and R40 TCON TV are very similar. However, R40 TCON TV is wired
differently, which makes it incompatible with A83T TCON TV.
Because of that, remove fallback A83T TCON TV compatible.
Fixes: 05a43a262d03 ("ARM: dts: sun8i: r40: Add HDMI pipeline")
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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sun4i-drm DT binding, second paragraph of the first section says:
For all connections between components up to the TCONs in the display
pipeline, when there are multiple components of the same type at the
same depth, the local endpoint ID must be the same as the remote
component's index.
Add mixer ids in R40 DT as mandated by DT binding.
Fixes: 05a43a262d03 ("ARM: dts: sun8i: r40: Add HDMI pipeline")
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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R40 has pretty unique display pipeline. Because of that, H3 display
engine compatible fallback should be removed.
Fixes: 05a43a262d03 ("ARM: dts: sun8i: r40: Add HDMI pipeline")
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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The OPPs for the A83T CPU cores were added in v4.17 in commit 2db639d8c166
("ARM: dts: sun8i: a83t: add stable OPP tables and CPUfreq"), but board
level regulator supplies for the CPU clusters were only added for the
TBS-A711 tablet. This means the other A83T boards do not benefit from
voltage scaling, or worse, if the implementation does not scale the
frequency when the voltage is fixed, no benefit at all.
Add board level CPU cluster power supplies to all the A83T development
boards, so they can have proper dynamic CPU voltage and frequency scaling.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Since HDMI can be considered as main output, most capable mixer is
connected to it (mixer0).
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Add all entries needed for HDMI to function properly.
Since R40 has highly configurable pipeline, both mixers and both TCON
TVs are added. Board specific DT should then connect them together
trough TCON TOP muxers to best fit the purpose of the board.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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The cooling device properties, like "#cooling-cells" and
"dynamic-power-coefficient", should either be present for all the CPUs
of a cluster or none. If these are present only for a subset of CPUs of
a cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.
Add such missing properties.
Fix other missing properties (clocks, OPP, clock latency) as well to
make it all work.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Start using ti-sysc with device tree data for omap4 l4 devices
With ti-sysc driver working for most use cases, we can start converting
the omap variant SoCs to use device tree data for the interconnect target
modules instead of the legacy hwmod platform data.
We start with omap4 l4 devices excluding the ones that still depend on
a reset controller driver like DSP MMU. And we don't yet convert the l4
ABE instance as that needs a bit more work.
We also add a proper interconnect hierarchy for the devices while at it
to make further work on genpd easier and to avoid most deferred probe
issues.
At this point we are not dropping any platform data, and we initially
still use it to validate the dts data. Then in later merge cycles we
can start dropping the related platform data.
* tag 'omap-for-v4.19/dt-pt3-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: omap4: Add l4 ranges for 4460
ARM: dts: omap4: Move l4 child devices to probe them with ti-sysc
ARM: dts: omap4: Probe watchdog 3 with ti-sysc
ARM: dts: omap4: Add l4 interconnect hierarchy and ti-sysc data
dt-bindings: Update omap l4 binding for optional registers
Signed-off-by: Olof Johansson <olof@lixom.net>
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Compared to 4430, 4460 and 4470 just have slightly different
l4 cfg ranges.
Signed-off-by: Tony Lindgren <tony@atomide.com>
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With l4 interconnect hierarchy and ti-sysc interconnect target module
data in place, we can simply move all the related child devices to
their proper location and enable probing using ti-sysc.
In general the first child device address range starts at range 0
from the ti-sysc interconnect target so the move involves adjusting
the child device reg properties for that.
And we cannot yet move mmu_dsp until we have a proper reset controller
driver for rstctrl registers.
In case of any regressions, problem devices can be reverted to probe
with legacy platform data as needed by moving them back and removing
the related interconnect target module node.
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Before updating wdt2 to probe with ti-sysc we want to have wdt3
probed with ti-sysc to avoid having them unnecessarily swap order.
With ti-sysc, we probe child devices at module_init time while
and until l4 abe interconnect is converted to use ti-sysc, wdt3
will probe earlier with legacy platform data.
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Let's add proper interconnect hierarchy for l4 interconnect
instances with the related ti-sysc interconnect module data as
documented in Documentation/devicetree/bindings/bus/ti-sysc.txt.
Using ti-sysc driver binding allows us to start dropping
legacy platform data in arch/arm/mach-omap2/omap*hwmod*data.c
files later on in favor of ti-sysc dts data.
For setting up a proper hierarchy for the interconnect and
ti-sysc data, there are multiple reasons:
1. We can use dts ranges to protect registers from being
ioremapped from other devices and prevent hard to track
issues with failed flush of posted write between modules
2. Some of the ranges may not be accessible to operating systems
at all if configured so on high-security devices
3. The interconnect hierarchy provides proper clockdomain
hierarchy that can be used for genpd later on
4. We can avoid almost all deferred probe related issues simply
by probing the resource providing interconnect instance first
for l4 wkup instance
5. With deferred probe issues gone, we can probe everything
later at module_init time except for system timer and interrupt
controller and their clocks.
This data is generated based on platform data from a booted system
and the interconnect acces protection registers for ranges. To avoid
regressions, we initially validate the device tree provided data
against the existing platform data on boot.
Each interconnect instance is typically divided into segments
to avoid powering up the whole interconnect. And each segment
has one or more ranges TI specific interconnect target modules
connected to it. Some devices can also have a separate data
access port directly to the parent L3 interconnect for DMA that
can be set up as a separate range.
Note that we cannot yet include this file from omap4.dtsi
until child devices are moved to their proper locations in
the interconnect hierarchy in the following patch. Otherwise
we would have the each module probed twice.
Also note that this does not yet add l4 abe instance, that will
be added separately later on.
Signed-off-by: Tony Lindgren <tony@atomide.com>
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https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Renesas ARM Based SoC DT Updates for v4.19
* RZ/G1C (r8a77470) SoC: Use r8a77470-cpg-mssr binding definitions
* Add GR-Peach audio camera shield support with MT9V111 image sensor
* Add initial support for RZ/N1D (r9a06g032) SoC and its RZN1D-DB board
* Use SPDX identifiers in DT for all SoCs and boards
* Add missing OPP properties for all CPUs on various SoCs
* Add missing PMIC nodes to R-Car Gen2 M2-W (r8a7791) based porter board
* tag 'renesas-arm-dt-for-v4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: dts: r8a77470: Use r8a77470-cpg-mssr binding definitions
ARM: dts: gr-peach: Add GR-Peach audiocamerashield support
ARM: dts: Renesas R9A06G032 SMP enable method
ARM: dts: Renesas RZN1D-DB Board base file
ARM: dts: Renesas R9A06G032 base device tree file
ARM: dts: convert to SPDX identifier for Renesas boards
ARM: dts: r8a77(43|9[013]): Add missing OPP properties for CPUs
ARM: dts: porter: Add missing PMIC nodes
Signed-off-by: Olof Johansson <olof@lixom.net>
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Replace the hardcoded clock indices by R8A77470_CLK_* symbols.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add device tree header for GR-Peach's audiocamerashield with MT9V111
image sensor.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add a special enable method for the second CA7 of the R9A06G032
as well as the default value for the "cpu-release-addr" property.
Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.
Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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This adds the Renesas R9A06G032 bare bone support.
This currently only handles the SYSCTRL block note,
generic parts (gic, architected timer) and a UART.
Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
[simon: updated MAINTAINERS file
[simon: do not use r9a06g032-sysctrl.h as it is not in the renesas tree yet]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The OPP properties, like "operating-points", should either be present
for all the CPUs of a cluster or none. If these are present only for a
subset of CPUs of a cluster then things will start falling apart as soon
as the CPUs are brought online in a different order. For example, this
will happen because the operating system looks for such properties in
the CPU node it is trying to bring up, so that it can create an OPP
table.
Add such missing properties.
Fix other missing properties (like, clock latency, voltage tolerance,
etc) as well to make it all work.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add PMIC nodes to Porter and connect CPU DVFS supply. There is
one DA9063L and one DA9210 on Porter, the only difference from
the other boards is that DA9063L is at I2C address 0x5a rather
than 0x58 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt
Qualcomm Device Tree Changes for v4.19
* Add missing OPPs on IPQ4019
* Fix sdhci l20 load on Hammerhead
* Use proper IRQ macros for IPQ8064 interrupts
* tag 'qcom-dts-for-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
ARM: dts: qcom: Add missing OPP properties for CPUs
ARM: dts: qcom: msm8974-hammerhead: increase load on l20 for sdhci
ARM: dts: qcom: Fix 'interrupts = <>' property to use proper macros
Signed-off-by: Olof Johansson <olof@lixom.net>
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The OPP properties, like "operating-points", should either be present
for all the CPUs of a cluster or none. If these are present only for a
subset of CPUs of a cluster then things will start falling apart as soon
as the CPUs are brought online in a different order. For example, this
will happen because the operating system looks for such properties in
the CPU node it is trying to bring up, so that it can create an OPP
table.
Add such missing properties.
Fix other missing property (clock latency) as well to make it all
work.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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The kernel would not boot on the hammerhead hardware due to the
following error:
mmc0: Timeout waiting for hardware interrupt.
mmc0: sdhci: ============ SDHCI REGISTER DUMP ===========
mmc0: sdhci: Sys addr: 0x00000200 | Version: 0x00003802
mmc0: sdhci: Blk size: 0x00000200 | Blk cnt: 0x00000200
mmc0: sdhci: Argument: 0x00000000 | Trn mode: 0x00000023
mmc0: sdhci: Present: 0x03e80000 | Host ctl: 0x00000034
mmc0: sdhci: Power: 0x00000001 | Blk gap: 0x00000000
mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x00000007
mmc0: sdhci: Timeout: 0x0000000e | Int stat: 0x00000000
mmc0: sdhci: Int enab: 0x02ff900b | Sig enab: 0x02ff100b
mmc0: sdhci: AC12 err: 0x00000000 | Slot int: 0x00000000
mmc0: sdhci: Caps: 0x642dc8b2 | Caps_1: 0x00008007
mmc0: sdhci: Cmd: 0x00000c1b | Max curr: 0x00000000
mmc0: sdhci: Resp[0]: 0x00000c00 | Resp[1]: 0x00000000
mmc0: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000
mmc0: sdhci: Host ctl2: 0x00000008
mmc0: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x70040220
mmc0: sdhci: ============================================
mmc0: Card stuck in wrong state! mmcblk0 card_busy_detect status: 0xe00
mmc0: cache flush error -110
mmc0: Reset 0x1 never completed.
This patch increases the load on l20 to 0.2 amps for the sdhci
and allows the device to boot normally.
Signed-off-by: Bhushan Shah <bshah@kde.org>
Signed-off-by: Brian Masney <masneyb@onstation.org>
Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Brian Masney <masneyb@onstation.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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