| Commit message (Collapse) | Author | Age |
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This machine is based on I2SE's Duckbill 2 board and features a
RS-485 daugther board. This device is intended to be used for
e.g. home automation purposes.
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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This machine is an USB pen drive sized development board,
based on NXP's i.MX28 CPU. In contrast to the previous
model "Duckbill", the "Duckbill 2" series has internal
eMMC storage.
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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This patch updates the Duckbill device tree and synchronize it with
the vendor distributed file. The changes in mostly pin-muxing stuff,
but also some minor fixes. In detail:
- enable SPI pins
- enable I2C pins
- enable UART pins
- enable LRADC pin
- adjust USB DR mode
- add default triggers for LEDs
- get rid of regulators simple-bus container
- adjust phy reset duration
According to phy datasheet, 25ms are sufficient. This also reduces
the time to boot the system.
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Signed-off-by: Michael Heimpold <michael.heimpold@i2se.com>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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This patch renames mmc2_sck_cfg in order to prepare for an alternative
muxing setup.
Signed-off-by: Michael Heimpold <michael.heimpold@i2se.com>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Signed-off-by: Michael Heimpold <michael.heimpold@i2se.com>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Quoting Philipp Zabel:
"Since this regulator is used as the TVDAC analog power supply, this
range should at least be limited to the analog power supply range of the
TVDAC, listed in Table 74-9. of the i.MX53 reference manual (2.5-2.75V).
But since the nominal voltage is 2.75V, which was used to determine the
analog gain that is supposed to result in the necessary 0.7V
peak-to-peak amplitude on the VGA output, I'd say we should just fix the
voltage to 2750000 here."
, so limit the TVDAC analog power supply as suggested.
Suggested-by: Lucas Stach <l.stach@pengutronix.de>
Suggested-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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imx6ul.dtsi already contains:
cpu0: cpu@0 {
....
arm-supply = <®_arm>;
soc-supply = <®_soc>;
};
, so remove the duplication.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The cm-fx6 module has an onboard Wolfson wm8731 codec which is muxed
to the ssi2 controller. Unlike most (all?) supported i.MX6 board/codec
combinations the wm8731 is operated in slave mode and the clock setup
is static.
Add support for it.
Signed-off-by: Valentin Raevsky <valentin@compulab.co.il>
[christopher.spinrath@rwth-aachen.de: enhanced commit message, ported
to upstream and some cleanup]
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Leave pca953x P06,P07 pins on b850v3 platform and P06 pin on
b450v3/b650v3 unconfigured in the kernel space since they could be
configured as DP1_RST and DP2_RST by the applications for the DP FW
update support.
Signed-off-by: Ken Lin <ken.lin@advantech.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Support for the usb-sata controller on the rock2 and another new rk3288
board, the phyCORE som and its PCM-947 carrier board from Phytec.
* tag 'v4.12-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: Add support for PCM-947 carrier board
dt-bindings: Document Phytec phyCORE-RK3288 RDK
ARM: dts: rockchip: Add support for phyCORE-RK3288 SoM
ARM: dts: rockchip: Enable sata support on rock2 square
Signed-off-by: Olof Johansson <olof@lixom.net>
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Add basic support for the PCM-947 carrier board, a RK3288 based development
board made by PHYTEC. This board works in a combination with
the phyCORE-RK3288 System on Module.
Following interfaces and devices are available on the PCM-947 carrier board:
- 2x UART
- micro SDMMC
- USB host and USB otg
- USB 3503 HSIC hub
- Ethernet
- 2nd alternative KSZ9031 ethernet phy
- Display connectors: PHYTEC LVDS, DDG LVDS, parallel signals, HDMI
- Parallel Camera CIF
- SGTL5000-32QFN audio codec
- 4x LEDs connected via PCA9533
- 2 user buttons
- Expansion connectors for WiFi and other modules
- RTC RV-4162-C7
- Resistive touch STMPE811
- EEPROM M24C32
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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The phyCORE-RK3288 is a SoM (System on Module) containing a RK3288 SoC.
The module can be connected to different carrier boards.
It can be also equipped with different RAM, SPI flash and eMMC variants.
The Rapid Development Kit option is using the following setup:
- 1 GB DDR3 RAM (2 Banks)
- 1x 4 KB EEPROM
- DP83867 Gigabit Ethernet PHY
- 16 MB SPI Flash
- 4 GB eMMC Flash
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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The Rock 2 square board has a USB -> SATA converter hooked up to its usb
host1 connection. Enable the usb controller and always turn on the power
on the 5V sata power connector (controlled by gpio).
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt
Samsung DeviceTree ARM update for v4.12:
1. Enhancements to PCIe nodes on Exynos5440.
2. Fix thermal values on some of Exynos5420 boards like Odroid XU3.
3. Add proper clock frequency properties to DSI nodes.
4. Fix watchdog reset on Exynos4412.
5. Fix watchdog infinite interrupt in soft mode on Exynos4210,
Exynos5440, S3C64xx and S5Pv210.
6. Enable watchdog on Exynos4 and S3C SoCs.
* tag 'samsung-dt-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: add HDMI controller phandle to exynos4.dtsi
ARM: dts: s5pv210: Fix infinite interrupt in soft mode
ARM: dts: s3c64xx: Fix infinite interrupt in soft mode
ARM: dts: exynos: Fix infinite interrupt in soft mode on Exynos4210 and Exynos5440
ARM: dts: exynos: Enable watchdog on all Exynos4 boards
ARM: dts: s3c64xx: Enable watchdog on all S3C64xx boards
ARM: dts: exynos: Fix watchdog reset on Exynos4412
ARM: dts: exynos: Add the burst and esc clock frequency properties to DSI node
ARM: dts: exynos: Do not ignore real-world fuse values for thermal zone 0 on Exynos5420
ARM: dts: exynos: Add phy-pcie node for pcie to Exynos5440
Signed-off-by: Olof Johansson <olof@lixom.net>
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Add to hdmi-cec node a phandle to hdmi node for new hdmi-cec notifier.
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Add the new hdmi phandle to exynos4.dtsi. This phandle is needed by the
s5p-cec driver to initialize the CEC notifier framework.
Tested with my Odroid U3.
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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In soft (no-reboot) mode, the driver self-pings watchdog upon expiration
of an interrupt. The interrupt has to be cleared, because otherwise
system enters infinite interrupt handling loop.
Use a samsung,s3c6410-wdt compatible to select appropriate quirk for
clearing the watchdog interrupt.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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In soft (no-reboot) mode, the driver self-pings watchdog upon expiration
of an interrupt. The interrupt has to be cleared, because otherwise
system enters infinite interrupt handling loop.
Use a samsung,s3c6410-wdt compatible to select appropriate quirk for
clearing the watchdog interrupt.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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Exynos5440
In soft (no-reboot) mode, the driver self-pings watchdog upon expiration
of an interrupt. The interrupt has to be cleared, because otherwise
system enters infinite interrupt handling loop.
Use a samsung,s3c6410-wdt compatible to select appropriate quirk for
clearing the watchdog interrupt.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
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Watchdog module does not have external dependencies so it can be safely
enabled in exynos4.dtsi thus making it available for all Exynos4-based
boards.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
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Watchdog module does not have external dependencies so it can be safely
enabled in s3c64xx.dtsi thus making it available for all S3C64xx-based
boards.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
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The Exynos4412 has the same watchdog as newer SoCs (e.g. Exynos5250).
Just like the others, for working it requires additional steps in Power
Management Unit: unmasking the reset request and enabling the system
reset. Without these additional steps in PMU, the watchdog will not be
able to reset the system on expiration event.
Change the compatible of Exynos4412 watchdog device node to
samsung,exynos5250-wdt which includes the additional PMU steps.
This will also fix infinite watchdog interrupt in soft mode (lack of
interrupt clear) because it is also included in samsung,exynos5250-wdt.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
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Add the burst and esc clock frequency properties to the parent (DSI node).
Currently the clock is parsed from the port node, while it should be
taken from the dsi node.
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Andi Shyti <andi.shyti@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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Exynos5420
In Odroid XU3 Lite board, the temperature levels reported for thermal
zone 0 were weird. In warm room:
/sys/class/thermal/thermal_zone0/temp:32000
/sys/class/thermal/thermal_zone1/temp:51000
/sys/class/thermal/thermal_zone2/temp:55000
/sys/class/thermal/thermal_zone3/temp:54000
/sys/class/thermal/thermal_zone4/temp:51000
Sometimes after booting the value was even equal to ambient temperature
which is highly unlikely to be a real temperature of sensor in SoC.
The thermal sensor's calibration (trimming) is based on fused values.
In case of the board above, the fused values are: 35, 52, 43, 58 and 43
(corresponding to each TMU device). However driver defined a minimum value
for fused data as 40 and for smaller values it was using a hard-coded 55
instead. This lead to mapping data from sensor to wrong temperatures
for thermal zone 0.
Various vendor 3.10 trees (Hardkernel's based on Samsung LSI, Artik 10)
do not impose any limits on fused values. Since we do not have any
knowledge about these limits, use 0 as a minimum accepted fused value.
This should essentially allow accepting any reasonable fused value thus
behaving like vendor driver.
The exynos5420-tmu-sensor-conf.dtsi is copied directly from existing
exynos4412 with one change - the samsung,tmu_min_efuse_value.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
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Add pcie-phy node to phy-exynos-pcie along with some changes to other
nodes:
1. Remove the configuration space from "ranges" property because this
was the old way of getting it. Preferred is to use "config" reg.
2. Use the reg-names as "elbi" and "config" so the purpose of addresses
will be easily known.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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mvebu dt for 4.12 (part 2)
Use disk-activity trigger for armada-385-linksys
Keep dts alphabetically ordered for clearfog (Armada 388)
* tag 'mvebu-dt-4.12-2' of git://git.infradead.org/linux-mvebu:
ARM: dts: armada-385-linksys: disk-activity trigger for all
ARM: dts: clearfog: keep dts alphabetically ordered
Signed-off-by: Olof Johansson <olof@lixom.net>
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Commit a4ee7e18d808 ("ARM: dts: armada: Add default trigger for sata
led") adds the default trigger to individual boards, move it to
armada-385-linksys.dtsi which effectively enables the definition for
the WRT1900ACS (Shelby) as well as for future boards.
Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Keep the clearfog DTS file ordered alphabetically - Florian placed the
MDIO entry after pinctrl, which mis-orders the file.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Second Round of Renesas ARM Based SoC DT Updates for v4.12
Corrections:
* Correct clock frequency of X2 DU clock input for r8a7791/koelsch board
* Correct Z clock for r8a7792 SoC
* Correct parent of SSI[0-9] clocks for r8a779[013] SoCs
* Correct ethernet clock parent on r7s72100 SoC
* Correct DU clock for r8a7794/silk board
Cleanups:
* Drop _clk suffix from external CAN clock node name on r8a779[01] SoCs
Enhancements:
* Enable rtc r7s72100/genmai board
* Add Z2 clock for r8a7794 SoC
* Add DU clock for r8a7794 SoC
* Add power-domains to SDHI for r8a7794 and r7s72100 SoCs
* Add reset control properties for r8a774[35] SoCs
* tag 'renesas-dt2-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (22 commits)
ARM: dts: r8a7791: Drop _clk suffix from external CAN clock node name
ARM: dts: r8a7790: Drop _clk suffix from external CAN clock node name
ARM: dts: genmai: Enable rtc and rtc_x1 clock
ARM: dts: rskrza1: add rtc DT support
ARM: dts: rskrza1: set rtc_x1 clock value
ARM: dts: r7s72100: add rtc to device tree
ARM: dts: r7s72100: add RTC_X clock inputs to device tree
ARM: dts: r7s72100: add rtc clock to device tree
ARM: dts: koelsch: Correct clock frequency of X2 DU clock input
ARM: dts: r8a7794: Add Z2 clock
ARM: dts: r8a7792: Correct Z clock
ARM: dts: r8a7793: Correct parent of SSI[0-9] clocks
ARM: dts: r8a7791: Correct parent of SSI[0-9] clocks
ARM: dts: r8a7790: Correct parent of SSI[0-9] clocks
ARM: dts: r7s72100: fix ethernet clock parent
ARM: dts: silk: Correct clock of DU1
ARM: dts: alt: Correct clock of DU1
ARM: dts: r8a7794: Correct clock of DU1
ARM: dts: r8a7794: Add DU1 clock to device tree
ARM: dts: r7s72100: add power-domains to sdhi
...
Signed-off-by: Olof Johansson <olof@lixom.net>
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The current practice is to not add _clk suffixes to clock node names in
DT, as these names are used as the actual clock names.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The current practice is to not add _clk suffixes to clock node names in
DT, as these names are used as the actual clock names.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Enable the 32.768 kHz RTC_X1 clock by setting the frequency value to
non-zero and enable the realtime clock.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Enable the realtime clock.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Enable the 32.768 kHz RTC_X1 clock by setting the frequency value to
non-zero.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add the realtime clock device node.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add the RTC clocks to device tree. The frequencies must be fixed values
according to the hardware manual.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add the realtime clock functional clock source.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The X2 crystal oscillator on the Koelsch development board provides a
74.25 MHz clock, not a 148.5 MHz clock.
Fixes: cd21cb46e14aae3a ("ARM: shmobile: koelsch: Add DU external pixel clocks to DT")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add the Z2 clock (Cortex-A7 CPU core clock), which uses a fixed divider,
and link the first CPU node to it.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Unlike other R-Car Gen2 SoCs with Cortex-A15 CPU cores, R-Car V2H does
not have a programmable Z clock (Cortex-A15 CPU core clock), but uses a
fixed divider.
This is similar to the Z2 clock (Cortex-A7 CPU core clock) on R-Car E2.
Hence:
- Remove the Z clock output from the cpg_clocks node, as this implied
a programmable clock,
- Add the Z clock as a fixed factor clock,
- Let the first CPU node point to the new Z clock,
- Remove the Z clock index from the bindings (this definition was used
by r8a7792.dtsi only, and was not a contract between DT and driver).
Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The SSI-ALL gate clock is located in between the P clock and the
individual SSI[0-9] clocks, hence the former should be listed as their
parent.
Fixes: 072d326542e49187 ("ARM: dts: r8a7793: add MSTP10 clocks to device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The SSI-ALL gate clock is located in between the P clock and the
individual SSI[0-9] clocks, hence the former should be listed as their
parent.
Fixes: ee9141522dcf13f8 ("ARM: shmobile: r8a7791: add MSTP10 support on DTSI")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The SSI-ALL gate clock is located in between the P clock and the
individual SSI[0-9] clocks, hence the former should be listed as their
parent.
Fixes: bcde372254386872 ("ARM: shmobile: r8a7790: add MSTP10 support on DTSI")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Technically, the Ethernet block is run off the 133MHz Bus (B) clock, not
the 33MHz Peripheral 0 (P0) clock.
Fixes: 969244f9c720 ("ARM: dts: r7s72100: add ethernet clock to device tree")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The second channel of the display unit uses a different module clock
than the first channel.
Fixes: 84e734f497cd48f6 ("ARM: dts: silk: add DU DT support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The second channel of the display unit uses a different module clock
than the first channel.
Fixes: 876e7fb9f418fd86 ("ARM: shmobile: r8a7794: alt: Enable VGA port")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The second channel of the display unit uses a different module clock
than the first channel.
Fixes: 46c4f13d04d729fa ("ARM: shmobile: r8a7794: Add DU node to device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add the missing module clock for the second channel of the display unit.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Fixes: 66474697923c ("ARM: dts: r7s72100: add sdhi to device tree")
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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