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| | * | | | | | | | | ARM: dts: rskrza1: add rtc DT supportChris Brandt2017-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the realtime clock. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | | | | | | | ARM: dts: rskrza1: set rtc_x1 clock valueChris Brandt2017-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the 32.768 kHz RTC_X1 clock by setting the frequency value to non-zero. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | | | | | | | ARM: dts: r7s72100: add rtc to device treeChris Brandt2017-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the realtime clock device node. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | | | | | | | ARM: dts: r7s72100: add RTC_X clock inputs to device treeChris Brandt2017-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the RTC clocks to device tree. The frequencies must be fixed values according to the hardware manual. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | | | | | | | ARM: dts: r7s72100: add rtc clock to device treeChris Brandt2017-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the realtime clock functional clock source. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | | | | | | | ARM: dts: koelsch: Correct clock frequency of X2 DU clock inputGeert Uytterhoeven2017-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The X2 crystal oscillator on the Koelsch development board provides a 74.25 MHz clock, not a 148.5 MHz clock. Fixes: cd21cb46e14aae3a ("ARM: shmobile: koelsch: Add DU external pixel clocks to DT") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | | | | | | | ARM: dts: r8a7794: Add Z2 clockGeert Uytterhoeven2017-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the Z2 clock (Cortex-A7 CPU core clock), which uses a fixed divider, and link the first CPU node to it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | | | | | | | ARM: dts: r8a7792: Correct Z clockGeert Uytterhoeven2017-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike other R-Car Gen2 SoCs with Cortex-A15 CPU cores, R-Car V2H does not have a programmable Z clock (Cortex-A15 CPU core clock), but uses a fixed divider. This is similar to the Z2 clock (Cortex-A7 CPU core clock) on R-Car E2. Hence: - Remove the Z clock output from the cpg_clocks node, as this implied a programmable clock, - Add the Z clock as a fixed factor clock, - Let the first CPU node point to the new Z clock, - Remove the Z clock index from the bindings (this definition was used by r8a7792.dtsi only, and was not a contract between DT and driver). Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | | | | | | | ARM: dts: r8a7793: Correct parent of SSI[0-9] clocksGeert Uytterhoeven2017-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SSI-ALL gate clock is located in between the P clock and the individual SSI[0-9] clocks, hence the former should be listed as their parent. Fixes: 072d326542e49187 ("ARM: dts: r8a7793: add MSTP10 clocks to device tree") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | | | | | | | ARM: dts: r8a7791: Correct parent of SSI[0-9] clocksGeert Uytterhoeven2017-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SSI-ALL gate clock is located in between the P clock and the individual SSI[0-9] clocks, hence the former should be listed as their parent. Fixes: ee9141522dcf13f8 ("ARM: shmobile: r8a7791: add MSTP10 support on DTSI") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | | | | | | | ARM: dts: r8a7790: Correct parent of SSI[0-9] clocksGeert Uytterhoeven2017-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SSI-ALL gate clock is located in between the P clock and the individual SSI[0-9] clocks, hence the former should be listed as their parent. Fixes: bcde372254386872 ("ARM: shmobile: r8a7790: add MSTP10 support on DTSI") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | | | | | | | ARM: dts: r7s72100: fix ethernet clock parentChris Brandt2017-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Technically, the Ethernet block is run off the 133MHz Bus (B) clock, not the 33MHz Peripheral 0 (P0) clock. Fixes: 969244f9c720 ("ARM: dts: r7s72100: add ethernet clock to device tree") Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | | | | | | | ARM: dts: silk: Correct clock of DU1Geert Uytterhoeven2017-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The second channel of the display unit uses a different module clock than the first channel. Fixes: 84e734f497cd48f6 ("ARM: dts: silk: add DU DT support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | | | | | | | ARM: dts: alt: Correct clock of DU1Geert Uytterhoeven2017-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The second channel of the display unit uses a different module clock than the first channel. Fixes: 876e7fb9f418fd86 ("ARM: shmobile: r8a7794: alt: Enable VGA port") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | | | | | | | ARM: dts: r8a7794: Correct clock of DU1Geert Uytterhoeven2017-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The second channel of the display unit uses a different module clock than the first channel. Fixes: 46c4f13d04d729fa ("ARM: shmobile: r8a7794: Add DU node to device tree") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | | | | | | | ARM: dts: r8a7794: Add DU1 clock to device treeGeert Uytterhoeven2017-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the missing module clock for the second channel of the display unit. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | | | | | | | ARM: dts: r7s72100: add power-domains to sdhiChris Brandt2017-03-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Fixes: 66474697923c ("ARM: dts: r7s72100: add sdhi to device tree") Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | | | | | | | ARM: dts: r8a7745: Add reset control propertiesGeert Uytterhoeven2017-03-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that all resets added match the corresponding module clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * | | | | | | | | ARM: dts: r8a7743: Add reset control propertiesGeert Uytterhoeven2017-03-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that all resets added match the corresponding module clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | | | | | | | | Merge tag 'qcom-dts-for-4.12' of ↵Olof Johansson2017-04-19
| |\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt Qualcomm Device Tree Changes for v4.12 * Add Coresight components for MSM8974 * Fixup MSM8974 ADSP XO clk and add RPMCC node * Fix typo in APQ8060 * Add SDCs on MSM8660 * Revert MSM8974 USB gadget change due to issues * tag 'qcom-dts-for-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: Revert "ARM: dts: qcom: msm8974: Add USB gadget nodes" ARM: dts: qcom: msm8974: Add RPMCC DT node ARM: dts: fix typo on APQ8060 Dragonboard ARM: dts: add SDC2 and SDC4 to the MSM8660 family ARM: dts: msm8974: Hook up adsp-pil's xo clock ARM: dts: qcom: Add msm8974 CoreSight components Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | | | | | | | Revert "ARM: dts: qcom: msm8974: Add USB gadget nodes"Andy Gross2017-04-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 769907ae6e6c2871c2ba4f578814d86fbfbe8d91. This change caused issues with people using USB gadget for serial consoles. In addition, with the other USB changes coming in, it makes sense to revert this patch and apply the new set as it becomes ready. Signed-off-by: Andy Gross <andy.gross@linaro.org>
| | * | | | | | | | | | ARM: dts: qcom: msm8974: Add RPMCC DT nodeGeorgi Djakov2017-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the RPM Clock Controller DT node for msm8974-based platforms, so that drivers can use the clocks provided by the RPM processor. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
| | * | | | | | | | | | ARM: dts: fix typo on APQ8060 DragonboardLinus Walleij2017-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DTS referred to SDC5 when it meant SDC1. Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
| | * | | | | | | | | | ARM: dts: add SDC2 and SDC4 to the MSM8660 familyLinus Walleij2017-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To make the picture complete, add DTS entries also for the second and fourth MMC/SD blocks on the MSM8660. SDC2 is an 8-bit interface and SDC4 is a 4-bit interface. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
| | * | | | | | | | | | ARM: dts: msm8974: Hook up adsp-pil's xo clockJonathan Neuschäfer2017-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this patch (and with CONFIG_QCOM_ADSP_PIL), I get this error: [ 0.711529] qcom_adsp_pil adsp-pil: failed to get xo clock [ 0.711540] remoteproc remoteproc0: releasing adsp-pil With this patch, adsp-pil can initialize correctly. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
| | * | | | | | | | | | ARM: dts: qcom: Add msm8974 CoreSight componentsIvan T. Ivanov2017-03-28
| | | |_|/ / / / / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial set of CoreSight components found on Qualcomm msm8974 and apq8074 based platforms, including the APQ8074 Dragonboard board. Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
| * | | | | | | | | | Merge tag 'sunxi-dt-h3-for-4.12' of ↵Olof Johansson2017-04-19
| |\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt Allwinner H3 DT changes for 4.12 H3 patches for 4.12, which are mostly related to reworking the H3 DTSI to be usable on the arm64 H5 DTSI, that shares almost everything with the H3 but the CPU cores. We also have some new device addition (USB, mostly) that would conflict otherwise. * tag 'sunxi-dt-h3-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: ARM: sun8i: h2+: enable USB OTG for Orange Pi Zero board ARM: sun8i: h3: enable USB OTG on Orange Pi One ARM: sunxi: h3/h5: add usb_otg and OHCI/EHCI for usbc0 on H3/H5 arm: sun8i: h3: split Allwinner H3 .dtsi arm: sun8i: h3: correct the GIC compatible in H3 to gic-400 arm: sun8i: h3: drop pinctrl-a10.h inclusion for H3 DTSI arm: sun8i: h3: drop skeleton.dtsi inclusion in H3 DTSI Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | | | | | | | ARM: sun8i: h2+: enable USB OTG for Orange Pi Zero boardIcenowy Zheng2017-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Orange Pi Zero board features a USB OTG port, which has a ID pin, and can be used to power up the board. However, even if the board is powered via +5V pin in GPIO/expansion headers, the VBUS in the OTG port cannot be powered up, thus it's impossible to use it in host mode with simple OTG cables. Add support for it in peripheral mode. If someone really want to use it in host mode, the mode of PHY can be switch via sysfs, then use a powered USB OTG cable or powered USB HUB to power up external USB devices. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | | | | | | | ARM: sun8i: h3: enable USB OTG on Orange Pi OneIcenowy Zheng2017-03-27
| | | |_|_|_|_|_|_|/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Orange Pi One features a MicroUSB port that can work in both host mode and peripheral mode. When in host mode, its VBUS is controlled via a GPIO; when in peripheral mode, its VBUS cannot be used to power up the board. Add support for this port. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | | | | | | ARM: sunxi: h3/h5: add usb_otg and OHCI/EHCI for usbc0 on H3/H5Icenowy Zheng2017-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner H3/H5 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI or MUSB controller. Add device nodes for these controllers. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | | | | | | arm: sun8i: h3: split Allwinner H3 .dtsiAndre Przywara2017-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new Allwinner H5 SoC is pin-compatible to the H3 SoC, but with the Cortex-A7 cores replaced by Cortex-A53 cores and the MMC controller updated. So we should really share almost the whole .dtsi. In preparation for that move the peripheral parts of the existing sun8i-h3.dtsi into a new sunxi-h3-h5.dtsi. The actual sun8i-h3.dtsi then includes that and defines the H3 specific parts on top of it. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [Icenowy: also split out mmc and gic, as well as pio and ccu's compatible, and make drop of skeleton into a seperated patch] Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | | | | | | arm: sun8i: h3: correct the GIC compatible in H3 to gic-400Icenowy Zheng2017-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the datasheets provided by Allwinner, both Allwinner H3 and H5 use GIC-400 as their interrupt controller. For better device tree reusing, correct the GIC compatible in H3 DTSI to "arm,gic-400", thus this node can be reused in H5. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | | | | | | arm: sun8i: h3: drop pinctrl-a10.h inclusion for H3 DTSIIcenowy Zheng2017-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After converting to generic pinconf binding, pinctrl-a10.h is now not used at all. Drop its inclusion for H3 DTSI. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | | | | | | arm: sun8i: h3: drop skeleton.dtsi inclusion in H3 DTSIIcenowy Zheng2017-03-27
| | |/ / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The skeleton.dtsi file is now deprecated, and do not exist in ARM64 environment. Since we will soon reuse most part of H3 DTSI for H5, which is an ARM64 chip, drop skeleton.dtsi inclusion now. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | | | | | | | Merge tag 'sunxi-dt-for-4.12' of ↵Olof Johansson2017-04-19
| |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt Allwinner DT changes for 4.12 As usual a number of changes, among which: - All the sun5i DTSI has been reworked based on the new documentation and the IPs that are actually found in all those SoCs. Part of that rework also brought the GR8 DTSI to include sun5i.dtsi - Mali devfreq and thermal throttling support on the A33 - AC power supplies for the AXP209 and AXP22X PMIC - CAN support for the A20 - CPUFreq-based thermal throttling for the A33 - New board: NanoPi NEO Air * tag 'sunxi-dt-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (38 commits) ARM: sun8i: sina33: add highest OPP of CPUs ARM: sun8i: a33: Add devfreq-based GPU cooling ARM: sun8i: a33: add CPU thermal throttling ARM: sun8i: a33: add thermal sensor ARM: dts: sun7i: fix device node ordering ARM: dts: sun4i: fix device node ordering ARM: dts: sun7i: Add can0_pins_a pinctrl settings ARM: dts: sun7i: Add CAN node ARM: dts: sun4i: Add can0_pins_a pinctrl settings ARM: dts: sun4i: Add CAN node ARM: sun7i: cubietruck: enable ACIN und USB power supply subnode ARM: dts: sun5i: Add interrupt for display backend dt-bindings: display: sun4i: Add display backend interrupt to device tree binding ARM: dts: sun7i: Use axp209.dtsi on A20-OLinuXino-Micro ARM: dts: sun6i: sina31s: Enable SPDIF out ARM: sun8i: sina33: add cpu-supply ARM: sun8i: a33: add all operating points ARM: sun5i: chip: enable ACIN power supply subnode ARM: dts: sun8i: sina33: enable ACIN power supply subnode ARM: dtsi: axp22x: add AC power supply subnode ... Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | | | | | | ARM: sun8i: sina33: add highest OPP of CPUsQuentin Schulz2017-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A33 supports 1.1GHz and 1.2GHz frequencies at 1.32V and the Sinlinx SinA33 has its cpu-supply property set in the cpu DT node. Therefore, CPUfreq knows how to handle the regulator in charge of the CPU and can adjust its voltage to match the OPP. Add these two CPU frequencies to the CPU OPP table of the Sinlinx SinA33. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | | | | | | ARM: sun8i: a33: Add devfreq-based GPU coolingMaxime Ripard2017-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds GPU thermal throttling for the Allwinner A33. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
| | * | | | | | | | | ARM: sun8i: a33: add CPU thermal throttlingQuentin Schulz2017-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds CPU thermal throttling for the Allwinner A33. It uses the thermal sensor present in the SoC's GPADC. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | | | | | | ARM: sun8i: a33: add thermal sensorQuentin Schulz2017-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the DT node for the thermal sensor present in the Allwinner A33 GPADC. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | | | | | | ARM: dts: sun7i: fix device node orderingPatrick Menschel2017-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the device node position of ps20 and ps21 to fix ordering by rising physical address. From uart7: serial@01c29c00 i2c0: i2c@01c2ac00 i2c1: i2c@01c2b000 i2c2: i2c@01c2b400 i2c3: i2c@01c2b800 i2c4: i2c@01c2c000 gmac: ethernet@01c50000 hstimer@01c60000 gic: interrupt-controller@01c81000 ps20: ps2@01c2a000 ps21: ps2@01c2a400 to uart7: serial@01c29c00 ps20: ps2@01c2a000 ps21: ps2@01c2a400 i2c0: i2c@01c2ac00 i2c1: i2c@01c2b000 i2c2: i2c@01c2b400 i2c3: i2c@01c2b800 i2c4: i2c@01c2c000 gmac: ethernet@01c50000 hstimer@01c60000 gic: interrupt-controller@01c81000 Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | | | | | | ARM: dts: sun4i: fix device node orderingPatrick Menschel2017-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the device node position of ps20 and ps21 to fix ordering by rising physical address. From uart7: serial@01c29c00 i2c0: i2c@01c2ac00 i2c1: i2c@01c2b000 i2c2: i2c@01c2b400 ps20: ps2@01c2a000 ps21: ps2@01c2a400 to uart7: serial@01c29c00 ps20: ps2@01c2a000 ps21: ps2@01c2a400 i2c0: i2c@01c2ac00 i2c1: i2c@01c2b000 i2c2: i2c@01c2b400 Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | | | | | | ARM: dts: sun7i: Add can0_pins_a pinctrl settingsPatrick Menschel2017-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A20 SoC has an on-board CAN controller. This patch adds the pinctrl settings for pins PH20 and PH21. This patch is adapted from the description in Documentation/devicetree/bindings/net/can/sun4i_can.txt Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | | | | | | ARM: dts: sun7i: Add CAN nodePatrick Menschel2017-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A20 SoC has an on-board CAN controller. This patch adds the device node. The CAN controller is inherited from the A10 SoC and uses the same driver. This patch is adapted from the description in Documentation/devicetree/bindings/net/can/sun4i_can.txt Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | | | | | | ARM: dts: sun4i: Add can0_pins_a pinctrl settingsPatrick Menschel2017-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A10 SoC has an on-board CAN controller. This patch adds the pinctrl settings for pins PH20 and PH21. This patch is adapted from the description in Documentation/devicetree/bindings/net/can/sun4i_can.txt Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | | | | | | ARM: dts: sun4i: Add CAN nodePatrick Menschel2017-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A10 SoC has an on-board CAN controller. This patch adds the device node. This patch is adapted from the description in Documentation/devicetree/bindings/net/can/sun4i_can.txt Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | | | | | | ARM: sun7i: cubietruck: enable ACIN und USB power supply subnodeAlexander Syring2017-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cubietruck has an AXP209 PMIC and can be power-supplied by ACIN via the CHG-IN pin or by USB. This enables the ACIN and the USB power supply subnode in the DT. Signed-off-by: Alexander Syring <alex@asyring.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | | | | | | ARM: dts: sun5i: Add interrupt for display backendChen-Yu Tsai2017-03-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The display backend on sun5i shares the same interrupt line as the display frontend. Add it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | | | | | | ARM: dts: sun7i: Use axp209.dtsi on A20-OLinuXino-MicroEzequiel Garcia2017-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit makes use of the axp209.dtsi file to define the AXP209 PMIC. While here, define the rails that are enabled on this board. Tested checking the regulator voltage varies according to the CPU frequency. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | | | | | | ARM: dts: sun6i: sina31s: Enable SPDIF outChen-Yu Tsai2017-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SinA31s has a coaxial SPDIF output. Enable it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | | | | | | ARM: sun8i: sina33: add cpu-supplyQuentin Schulz2017-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the cpu-supply DT property to the cpu0 DT node needed by the board to adapt the regulator voltage depending on the currently used OPP. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-06 01:48:20 -0400