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* ARM: mvebu: Add the core-divider clock to Armada 370/XPEzequiel Garcia2013-10-23
| | | | | | | | | The Armada 370/XP SoC has a clock provider called "Core Divider", that is derived from a fixed 2 GHz PLL clock. Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: Add a 2 GHz fixed-clock Armada 370/XPEzequiel Garcia2013-10-23
| | | | | | | | | | Armada 370/XP SoCs have a 2 GHz fixed PLL that is used to feed other clocks. This commit adds a DT representation of this clock through a fixed-clock compatible node. Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: Add Core Divider clock device-tree bindingEzequiel Garcia2013-10-23
| | | | | | | | | The Armada 370/XP SoCs have a Core Divider clock providing several clocks. For now, only the NAND clock is supported. Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: Dove: fix bad properties of the si5351 clkout2 used by Cubox audioJean-Francois Moine2013-10-09
| | | | | | | | | | | | | | | As defined in the DT, clkout2 is not allowed to change the pll inside si5351. This patch extends the properties of clkout2 so that it works as the external clock of the audio device in the Cubox. Also, as the second si5351 clock is not used in the Cubox, its definition is removed. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: Dove: Add the audio device to the Cubox DTJean-Francois Moine2013-10-09
| | | | | | | | | | | | This patch activates the audio device of the Cubox. The audio flow (pin mpp_audio1) is output on both I2S and S/PDIF. The third si5351 clock (#2, pin mpp13) is used as the external clock. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: Dove: Add the audio devices in DTJean-Francois Moine2013-10-09
| | | | | | | | | This patch adds the nodes to instantiate the audio devices of the Dove boards. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* arm: mvebu: add support for the Armada XP Matrix boardThomas Petazzoni2013-10-03
| | | | | | | | | | The Armada XP Matrix board is the mother board of a more complex system. The mother board uses an Armada XP MV78460, 4 serial ports, 2 SATA ports, one Ethernet connection, a PCIe port and a USB port. All those devices are enabled in the Device Tree added by this patch. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: kirkwood: ib62x0: add u-boot environment partitionLuka Perkov2013-10-03
| | | | | | | Also, add some trivial whitespace cleanup. Signed-off-by: Luka Perkov <luka@openwrt.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: kirkwood: Move the nand node under the mbus nodeJason Gunthorpe2013-10-01
| | | | | | | | | | | There should be no nodes that are not children of the mbus. Move the nand node under the mbus, and rework the board .dts files to use an & reference to the nand node. Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: kirkwood: Move the crypto node under the mbus nodeJason Gunthorpe2013-10-01
| | | | | | | | There should be no nodes that are not children of the mbus. Move the crypto node under the mbus. Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: kirkwood: Remove kirkwood_setup_wins and rely on the DT bindingJason Gunthorpe2013-10-01
| | | | | | | | | | | | | | | | | | | kirkwood_setup_wins is the last manual caller of mbus in kirkwood, don't call it for DT boards and rely on the DT having a mbus node with a proper ranges property to setup these windows. Move all the mbus ranges properties for all boards into kirkwood.dtsi, since they are currently all the same. This makes the DT self consistent, since the physical address of the NAND and CRYPTO are both referenced internally. The arbitary Linux constants KIRKWOOD_NAND_MEM_PHYS_BASE and KIRKWOOD_SRAM_PHYS_BASE no longer have to match the DT values. Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: dove: add initial DT file for Globalscale D3PlugSebastian Hesselbarth2013-09-30
| | | | | | | This adds an initial DT file for the Globalscale D3Plug with Dove SoC. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: dove: add PCIe controllers to SoC DTSebastian Hesselbarth2013-09-30
| | | | | | | | This adds a node for the pcie controllers found on Dove SoCs to the SoC DT include. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: dove: relocate internal registers device nodesSebastian Hesselbarth2013-09-30
| | | | | | | | With mbus node in place, now relocate all internal device nodes to internal-regs node with proper address ranges. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: dove: add MBus DT nodeSebastian Hesselbarth2013-09-30
| | | | | | | This adds a MBus node including ranges and pcie apertures required later. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: dove: add MBUS_ID macro to Dove DTSebastian Hesselbarth2013-09-30
| | | | | | | | This adds a macro used for defining address window's target ID and attribute cells for the MBus ranges entry. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: dove: use preprocessor on device tree filesSebastian Hesselbarth2013-09-30
| | | | | | | | This coverts Dove DT board files to preprocessor includes instead of dtc includes. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: link PCIe controllers to the MSI controllerThomas Petazzoni2013-09-30
| | | | | | | | | | | This commit adjusts the Armada 370 and Armada XP PCIe controllers Device Tree informations to reference their MSI controller. In the case of this platform, the MSI controller is implemented by the MPIC. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Daniel Price <daniel.price@gmail.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: the MPIC now provides MSI controller featuresThomas Petazzoni2013-09-30
| | | | | | | | | | | | Adds the 'msi-controller' property to the main interrupt controller Device Tree node, to indicate that it can now behave as a MSI controller. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Thierry Reding <thierry.reding@gmail.com> Tested-by: Daniel Price <daniel.price@gmail.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: dts: mvebu: Update with the new compatible string for mv64xxx-i2cGregory CLEMENT2013-09-17
| | | | | | | | | | | | | | | | The mv64xxx-i2c embedded in the Armada XP have a new feature to offload i2c transaction. This new version of the IP come also with some errata. This lead to the introduction to a another compatible string. This commit split the i2c information into armada-370.dtsi and armada-xp.dtsi. Most of the data remains the same and stay in the common file Armada-370-xp.dtsi. With this new feature the size of the registers are bigger for Armada XP and the new compatible string is used. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* Linux 3.12-rc1Linus Torvalds2013-09-16
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* Merge branch 'timers/core' of ↵Linus Torvalds2013-09-16
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull timer code update from Thomas Gleixner: - armada SoC clocksource overhaul with a trivial merge conflict - Minor improvements to various SoC clocksource drivers * 'timers/core' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: clocksource: armada-370-xp: Add detailed clock requirements in devicetree binding clocksource: armada-370-xp: Get reference fixed-clock by name clocksource: armada-370-xp: Replace WARN_ON with BUG_ON clocksource: armada-370-xp: Fix device-tree binding clocksource: armada-370-xp: Introduce new compatibles clocksource: armada-370-xp: Use CLOCKSOURCE_OF_DECLARE clocksource: armada-370-xp: Simplify TIMER_CTRL register access clocksource: armada-370-xp: Use BIT() ARM: timer-sp: Set dynamic irq affinity ARM: nomadik: add dynamic irq flag to the timer clocksource: sh_cmt: 32-bit control register support clocksource: em_sti: Convert to devm_* managed helpers
| * clocksource: armada-370-xp: Add detailed clock requirements in devicetree ↵Ezequiel Garcia2013-09-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | binding Specifies the required clock inputs for each supported compatible. Armada 370 requires a single clock phandle, and Armada XP requires two clock phandles with clock-names "nbclk" and "fixed". Cc: devicetree@vger.kernel.org Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * clocksource: armada-370-xp: Get reference fixed-clock by nameEzequiel Garcia2013-09-02
| | | | | | | | | | | | | | | | | | | | | | | | | | The Armada XP timer has two mandatory clock inputs: nbclk and refclk, as specified by the device-tree binding. This commit fixes the clock selection. Instead of hard-coding the clock rate for the 25 MHz reference fixed-clock, obtain the clock by its name. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * clocksource: armada-370-xp: Replace WARN_ON with BUG_ONEzequiel Garcia2013-09-02
| | | | | | | | | | | | | | | | | | | | | | If the clock fails to be obtained and the timer fails to be properly registered, the kernel will freeze real soon. Instead, let's BUG() where the actual problem is located. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * clocksource: armada-370-xp: Fix device-tree bindingEzequiel Garcia2013-09-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes the DT binding for the Armada 370/XP SoC timer. The previous "marvell,armada-370-xp-timer" compatible is removed and two new compatible strings are introduced: "marvell,armada-xp-timer" and "marvell,armada-370-timer". The rationale behind this change is that the Armada 370 SoC and the Armada XP SoC timers are not really compatible: * Armada 370 has no 25 MHz fixed timer. * Armada XP cannot work properly without such 25 MHz fixed timer as doing otherwise leads to using a clocksource whose frequency varies when doing cpufreq frequency changes. This commit also removes the "marvell,timer-25Mhz" property, given it's now meaningless. Cc: devicetree@vger.kernel.org Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * clocksource: armada-370-xp: Introduce new compatiblesEzequiel Garcia2013-09-02
| | | | | | | | | | | | | | | | | | | | | | | | The Armada XP SoC clocksource driver cannot work without the 25 MHz fixed timer. Therefore it's appropriate to introduce a new compatible string and use it to set the 25 MHz fixed timer. The 'marvell,timer-25MHz' property will be marked as deprecated. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
| * clocksource: armada-370-xp: Use CLOCKSOURCE_OF_DECLAREEzequiel Garcia2013-09-02
| | | | | | | | | | | | | | | | | | | | This is almost cosmetic: we achieve a bit of consistency with other clocksource drivers by using the CLOCKSOURCE_OF_DECLARE macro for the boilerplate code. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
| * clocksource: armada-370-xp: Simplify TIMER_CTRL register accessEzequiel Garcia2013-09-02
| | | | | | | | | | | | | | | | | | | | | | | | This commit creates two functions to access the TIMER_CTRL register: one for global one for the per-cpu. This makes the code much more readable. In addition, since the TIMER_CTRL register is also used for watchdog, this is preparation work for future thread-safe improvements. Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * clocksource: armada-370-xp: Use BIT()Ezequiel Garcia2013-09-02
| | | | | | | | | | | | | | | | | | This is a purely cosmetic commit: we replace hardcoded values that representing bits by BIT(), which is slightly more readable. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
| * ARM: timer-sp: Set dynamic irq affinityViresh Kumar2013-08-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a cpu goes to a deep idle state where its local timer is shutdown, it notifies the time frame work to use the broadcast timer instead. Unfortunately, the broadcast device could wake up any CPU, including an idle one which is not concerned by the wake up at all. This implies, in the worst case, an idle CPU will wake up to send an IPI to another idle cpu. This patch fixes this for ARM platforms using timer-sp, by setting CLOCK_EVT_FEAT_DYNIRQ feature. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * ARM: nomadik: add dynamic irq flag to the timerDaniel Lezcano2013-08-21
| | | | | | | | | | | | | | | | Add the dynamic irq affinity feature to the timer clock device. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Vincent Guittot <vincent.guittot@linaro.org> Acked-by: Rickard Andersson <rickard.andersson@stericsson.com>
| * clocksource: sh_cmt: 32-bit control register supportMagnus Damm2013-08-21
| | | | | | | | | | | | | | | | | | | | | | Add support for CMT hardware with 32-bit control and counter registers, as found on r8a73a4 and r8a7790. To use the CMT with 32-bit hardware a second I/O memory resource needs to point out the CMSTR register and it needs to be 32 bit wide. Signed-off-by: Magnus Damm <damm@opensource.se> Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * clocksource: em_sti: Convert to devm_* managed helpersLaurent Pinchart2013-08-21
| | | | | | | | | | | | | | | | Replace kzalloc, clk_get, ioremap and request_irq by their managed counterparts to simplify error paths. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* | Merge branch 'for-next' of git://git.samba.org/sfrench/cifs-2.6Linus Torvalds2013-09-16
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull CIFS fixes from Steve French: "Two minor cifs fixes and a minor documentation cleanup for cifs.txt" * 'for-next' of git://git.samba.org/sfrench/cifs-2.6: cifs: update cifs.txt and remove some outdated infos cifs: Avoid calling unlock_page() twice in cifs_readpage() when using fscache cifs: Do not take a reference to the page in cifs_readpage_worker()
| * | cifs: update cifs.txt and remove some outdated infosBjörn Jacke2013-09-13
| | | | | | | | | | | | | | | | | | Acked-by: Jeff Layton <jlayton@redhat.com> Signed-off-by: Björn JACKE <bj@sernet.de> Signed-off-by: Steve French <smfrench@gmail.com>
| * | cifs: Avoid calling unlock_page() twice in cifs_readpage() when using fscacheSachin Prabhu2013-09-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When reading a single page with cifs_readpage(), we make a call to fscache_read_or_alloc_page() which once done, asynchronously calls the completion function cifs_readpage_from_fscache_complete(). This completion function unlocks the page once it has been populated from cache. The module then attempts to unlock the page a second time in cifs_readpage() which leads to warning messages. In case of a successful call to fscache_read_or_alloc_page() we should skip the second unlock_page() since this will be called by the cifs_readpage_from_fscache_complete() once the page has been populated by fscache. With the modifications to cifs_readpage_worker(), we will need to re-grab the page lock in cifs_write_begin(). The problem was first noticed when testing new fscache patches for cifs. https://bugzilla.redhat.com/show_bug.cgi?id=1005737 Signed-off-by: Sachin Prabhu <sprabhu@redhat.com> Reviewed-by: Jeff Layton <jlayton@redhat.com> Signed-off-by: Steve French <smfrench@gmail.com>
| * | cifs: Do not take a reference to the page in cifs_readpage_worker()Sachin Prabhu2013-09-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We do not need to take a reference to the pagecache in cifs_readpage_worker() since the calling function will have already taken one before passing the pointer to the page as an argument to the function. Signed-off-by: Sachin Prabhu <sprabhu@redhat.com> Reviewed-by: Jeff Layton <jlayton@redhat.com> Signed-off-by: Steve French <smfrench@gmail.com>
* | | Merge tag 'upstream-3.12-rc1' of git://git.infradead.org/linux-ubiLinus Torvalds2013-09-16
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull UBI fixes from Artem Bityutskiy: "Just a single fastmap fix plus a regression fix" * tag 'upstream-3.12-rc1' of git://git.infradead.org/linux-ubi: UBI: Fix invalidate_fastmap() UBI: Fix PEB leak in wear_leveling_worker()
| * | | UBI: Fix invalidate_fastmap()Richard Weinberger2013-08-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Onging tests uncovered that invalidate_fastmap() is broken. It must not call ubi_wl_put_fm_peb() because all PEBs used by the old fastmap have already been put back. Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
| * | | UBI: Fix PEB leak in wear_leveling_worker()Richard Weinberger2013-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | get_peb_for_wl() removes the PEB from the free list. If the WL subsystem detects that no wear leveling is needed it cancels the operation and drops the gained PEB. In this case we have to put the PEB back into the free list. This issue was introduced with commit ed4b7021c (UBI: remove PEB from free tree in get_peb_for_wl()). Cc: <stable@vger.kernel.org> # 3.7.x Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
* | | | Merge tag 'upstream-3.12-rc1' of git://git.infradead.org/linux-ubifsLinus Torvalds2013-09-16
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ubifs fix from Artem Bityutskiy: "Just one patch which fixes the power-cut recovery testing mode. I'll start using a single UBI/UBIFS tree instead of 2 trees from now on. So in the future you'll get 1 small pull request instead of 2 tiny ones" * tag 'upstream-3.12-rc1' of git://git.infradead.org/linux-ubifs: UBIFS: remove invalid warn msg with tst_recovery enabled
| * | | | UBIFS: remove invalid warn msg with tst_recovery enabledMats Kärrman2013-08-16
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Mats Karrman <mats.karrman@tritech.se> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
* | | | | Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2013-09-15
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS fixes from Ralf Baechle: "These are four patches for three construction sites: - Fix register decoding for the combination of multi-core processors and multi-threading. - Two more fixes that are part of the ongoing DECstation resurrection work. One of these touches a DECstation-only network driver. - Finally Markos' trivial build fix for the AP/SP support. (With this applied now all MIPS defconfigs are building again)" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: kernel: vpe: Make vpe_attrs an array of pointers. MIPS: Fix SMP core calculations when using MT support. MIPS: DECstation I/O ASIC DMA interrupt handling fix MIPS: DECstation HRT initialization rearrangement
| * | | | | MIPS: kernel: vpe: Make vpe_attrs an array of pointers.Markos Chandras2013-09-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 567b21e973ccf5b0d13776e408d7c67099749eb8 "mips: convert vpe_class to use dev_groups" broke the build on MIPS since vpe_attrs should be an array of 'struct device_attribute' pointers. Fixes the following build problem: arch/mips/kernel/vpe.c:1372:2: error: missing braces around initializer [-Werror=missing-braces] arch/mips/kernel/vpe.c:1372:2: error: (near initialization for 'vpe_attrs[0]') [-Werror=missing-braces] Cc: Ralf Baechle <ralf@linux-mips.org> Cc: John Crispin <blogic@openwrt.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5819/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: Fix SMP core calculations when using MT support.Leonid Yegoshin2013-09-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TCBIND register is only available if the core has MT support. It should not be read otherwise. Secondly, the number of TCs (siblings) are calculated differently depending on if the kernel is configured as SMVP or SMTC. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5822/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: DECstation I/O ASIC DMA interrupt handling fixMaciej W. Rozycki2013-09-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change complements commit d0da7c002f7b2a93582187a9e3f73891a01d8ee4 and brings clear_ioasic_irq back, renaming it to clear_ioasic_dma_irq at the same time, to make I/O ASIC DMA interrupts functional. Unlike ordinary I/O ASIC interrupts DMA interrupts need to be deasserted by software by writing 0 to the respective bit in I/O ASIC's System Interrupt Register (SIR), similarly to how CP0.Cause.IP0 and CP0.Cause.IP1 bits are handled in the CPU (the difference is SIR DMA interrupt bits are R/W0C so there's no need for an RMW cycle). Otherwise the handler is reentered over and over again. The only current user is the DEC LANCE Ethernet driver and its extremely uncommon DMA memory error handler that does not care when exactly the interrupt is cleared. Anticipating the use of DMA interrupts by the Zilog SCC driver this change however exports clear_ioasic_dma_irq for device drivers to choose the right application-specific sequence to clear the request explicitly rather than calling it implicitly in the .irq_eoi handler of `struct irq_chip'. Previously these interrupts were cleared in the .end handler of the said structure, before it was removed. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5826/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | | | MIPS: DECstation HRT initialization rearrangementMaciej W. Rozycki2013-09-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all I/O ASIC versions have the free-running counter implemented, an early revision used in the 5000/1xx models aka 3MIN and 4MIN did not have it. Therefore we cannot unconditionally use it as a clock source. Fortunately if not implemented its register slot has a fixed value so it is enough if we check for the value at the end of the calibration period being the same as at the beginning. This also means we need to look for another high-precision clock source on the systems affected. The 5000/1xx can have an R4000SC processor installed where the CP0 Count register can be used as a clock source. Unfortunately all the R4k DECstations suffer from the missed timer interrupt on CP0 Count reads erratum, so we cannot use the CP0 timer as a clock source and a clock event both at a time. However we never need an R4k clock event device because all DECstations have a DS1287A RTC chip whose periodic interrupt can be used as a clock source. This gives us the following four configuration possibilities for I/O ASIC DECstations: 1. No I/O ASIC counter and no CP0 timer, e.g. R3k 5000/1xx (3MIN). 2. No I/O ASIC counter but the CP0 timer, i.e. R4k 5000/150 (4MIN). 3. The I/O ASIC counter but no CP0 timer, e.g. R3k 5000/240 (3MAX+). 4. The I/O ASIC counter and the CP0 timer, e.g. R4k 5000/260 (4MAX+). For #1 and #2 this change stops the I/O ASIC free-running counter from being installed as a clock source of a 0Hz frequency. For #2 it also arranges for the CP0 timer to be used as a clock source rather than a clock event device, because having an accurate wall clock is more important than a high-precision interval timer. For #3 there is no change. For #4 the change makes the I/O ASIC free-running counter installed as a clock source so that the CP0 timer can be used as a clock event device. Unfortunately the use of the CP0 timer as a clock event device relies on a succesful completion of c0_compare_interrupt. That never happens, because while waiting for a CP0 Compare interrupt to happen the function spins in a loop reading the CP0 Count register. This makes the CP0 Count erratum trigger reliably causing the interrupt waited for to be lost in all cases. As a result #4 resorts to using the CP0 timer as a clock source as well, just as #2. However we want to keep this separate arrangement in case (hope) c0_compare_interrupt is eventually rewritten such that it avoids the erratum. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5825/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | | | Merge branch 'for_linus' of git://cavan.codon.org.uk/platform-drivers-x86Linus Torvalds2013-09-15
|\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull x86 platform updates from Matthew Garrett: "Nothing amazing here, almost entirely cleanups and minor bugfixes and one bit of hardware enablement in the amilo-rfkill driver" * 'for_linus' of git://cavan.codon.org.uk/platform-drivers-x86: platform/x86: panasonic-laptop: reuse module_acpi_driver samsung-laptop: fix config build error platform: x86: remove unnecessary platform_set_drvdata() amilo-rfkill: Enable using amilo-rfkill with the FSC Amilo L1310. wmi: parse_wdg() should return kernel error codes hp_wmi: Fix unregister order in hp_wmi_rfkill_setup() platform: replace strict_strto*() with kstrto*() x86: irst: use module_acpi_driver to simplify the code x86: smartconnect: use module_acpi_driver to simplify the code platform samsung-q10: use ACPI instead of direct EC calls thinkpad_acpi: add the ability setting TPACPI_LED_NONE by quirk thinkpad_acpi: return -NODEV while operating uninitialized LEDs
| * | | | | | platform/x86: panasonic-laptop: reuse module_acpi_driverAndy Shevchenko2013-09-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a macro to register and unregister modules in simple cases, Let's use it and clean up the driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-24 15:54:14 -0400