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* Merge branch 'pci/host-vmd' into nextBjorn Helgaas2017-09-07
|\ | | | | | | | | | | | | | | | | | | | | | | * pci/host-vmd: iommu/vt-d: Prevent VMD child devices from being remapping targets x86/PCI: Use is_vmd() rather than relying on the domain number x86/PCI: Move VMD quirk to x86 fixups MAINTAINERS: Add Jonathan Derrick as VMD maintainer PCI: vmd: Remove IRQ affinity so we can allocate more IRQs PCI: vmd: Free up IRQs on suspend path PCI: vmd: Assign vector zero to all bridges PCI: vmd: Reserve IRQ pre-vector for better affinity
| * iommu/vt-d: Prevent VMD child devices from being remapping targetsJon Derrick2017-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | VMD child devices must use the VMD endpoint's ID as the requester. Because of this, there needs to be a way to link the parent VMD endpoint's IOMMU group and associated mappings to the VMD child devices such that attaching and detaching child devices modify the endpoint's mappings, while preventing early detaching on a singular device removal or unbinding. The reassignment of individual VMD child devices devices to VMs is outside the scope of VMD, but may be implemented in the future. For now it is best to prevent any such attempts. Prevent VMD child devices from returning an IOMMU, which prevents it from exposing an iommu_group sysfs directory and allowing subsequent binding by userspace-access drivers such as VFIO. Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * x86/PCI: Use is_vmd() rather than relying on the domain numberJon Derrick2017-08-30
| | | | | | | | | | | | | | Use the is_vmd() predicate to identify devices below a VMD host rather than relying on the domain number. Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * x86/PCI: Move VMD quirk to x86 fixupsJon Derrick2017-08-30
| | | | | | | | | | | | | | VMD currently only exists for Intel x86 products, so move the VMD quirk to arch/x86. Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * MAINTAINERS: Add Jonathan Derrick as VMD maintainerJon Derrick2017-08-30
| | | | | | | | | | | | | | Add Jonathan Derrick as VMD maintainer. Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Keith Busch <keith.busch@intel.com>
| * PCI: vmd: Remove IRQ affinity so we can allocate more IRQsKeith Busch2017-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | VMD hardware has to share its vectors among child devices in its PCI domain so we should allocate as many as possible rather than just ones that can be affinitized. pci_alloc_irq_vectors_affinity() limits the number of affinitized IRQs to the number of present CPUs (see irq_calc_affinity_vectors()). But we'd prefer to have more vectors, even if they aren't distributed across the CPUs, so use pci_alloc_irq_vectors() instead. Reported-by: Brad Goodman <Bradley.Goodman@dell.com> Signed-off-by: Keith Busch <keith.busch@intel.com> [bhelgaas: add irq_calc_affinity_vectors() reference to changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * PCI: vmd: Free up IRQs on suspend pathScott Bauer2017-08-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Free up the IRQs we request on the suspend path and reallocate them on the resume path. Fixes this error: CPU 111 disable failed: CPU has 9 vectors assigned and there are only 0 available. Error taking CPU111 down: -34 Non-boot CPUs are not disabled Enabling non-boot CPUs ... Signed-off-by: Scott Bauer <scott.bauer@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Keith Busch <keith.busch@intel.com>
| * PCI: vmd: Assign vector zero to all bridgesKeith Busch2017-08-03
| | | | | | | | | | | | | | | | | | | | | | We don't want slower IRQ handlers impacting faster devices that happen to be assigned the same VMD interrupt vector. The driver was trying to separate such devices by checking if MSI-X wasn't used, but really we just don't want endpoint devices to share with bridges. Most bridges may use MSI currently, so that criteria happened to work, but newer ones may use MSI-X, so this patch explicitly checks the device type when choosing a vector. Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * PCI: vmd: Reserve IRQ pre-vector for better affinityKeith Busch2017-08-03
| | | | | | | | | | | | | | The driver has a special purpose for the VMD device's first IRQ, so this one shouldn't be considered for IRQ affinity. Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'pci/host-tegra' into nextBjorn Helgaas2017-09-07
|\ \ | | | | | | | | | | | | * pci/host-tegra: PCI: tegra: Explicitly request exclusive reset control
| * | PCI: tegra: Explicitly request exclusive reset controlPhilipp Zabel2017-08-03
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting reset lines") started to transition the reset control request API calls to explicitly state whether the driver needs exclusive or shared reset control behavior. Convert all drivers requesting exclusive resets to the explicit API call so the temporary transition helpers can be removed. No functional changes. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com>
* | Merge branch 'pci/host-spear13xx' into nextBjorn Helgaas2017-09-07
|\ \ | | | | | | | | | | | | * pci/host-spear13xx: PCI: spear13xx: Fix platform_get_irq() error handling
| * | PCI: spear13xx: Fix platform_get_irq() error handlingFabio Estevam2017-09-05
| |/ | | | | | | | | | | | | | | | | platform_get_irq() returns a negative number on failure, so adjust the logic to detect such condition and propagate the real error value on failure. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Pratyush Anand <pratyush.anand@gmail.com>
* | Merge branch 'pci/host-rockchip' into nextBjorn Helgaas2017-09-07
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/host-rockchip: PCI: rockchip: Fix platform_get_irq() error handling PCI: rockchip: Umap IO space if probe fails PCI: rockchip: Remove IRQ domain if probe fails PCI: rockchip: Disable vpcie0v9 if resume_noirq fails PCI: rockchip: Clean up PHY if driver probe or resume fails PCI: rockchip: Factor out rockchip_pcie_deinit_phys() PCI: rockchip: Factor out rockchip_pcie_disable_clocks() PCI: rockchip: Factor out rockchip_pcie_enable_clocks() PCI: rockchip: Factor out rockchip_pcie_setup_irq() PCI: rockchip: Use gpiod_set_value_cansleep() to allow reset via expanders PCI: rockchip: Use PCI_NUM_INTX PCI: rockchip: Explicitly request exclusive reset control dt-bindings: phy-rockchip-pcie: Convert to per-lane PHY model dt-bindings: PCI: rockchip: Convert to per-lane PHY model arm64: dts: rockchip: convert PCIe to use per-lane PHYs for rk3339 PCI: rockchip: Idle inactive PHY(s) phy: rockchip-pcie: Reconstruct driver to support per-lane PHYs PCI: rockchip: Add per-lane PHY support PCI: rockchip: Factor out rockchip_pcie_get_phys() PCI: rockchip: Control optional 12v power supply dt-bindings: PCI: rockchip: Add vpcie12v-supply for Rockchip PCIe controller
| * | PCI: rockchip: Fix platform_get_irq() error handlingFabio Estevam2017-09-05
| | | | | | | | | | | | | | | | | | | | | | | | When platform_get_irq() fails we should propagate the real error value instead of always returning -EINVAL. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Shawn Lin <shawn.lin@rock-chips.com>
| * | PCI: rockchip: Umap IO space if probe failsJeffy Chen2017-08-29
| | | | | | | | | | | | | | | | | | | | | Call pci_unmap_iospace() to clean up if probe fails. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: rockchip: Remove IRQ domain if probe failsJeffy Chen2017-08-29
| | | | | | | | | | | | | | | | | | | | | Call irq_domain_remove() to clean up if probe fails. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: rockchip: Disable vpcie0v9 if resume_noirq failsJeffy Chen2017-08-29
| | | | | | | | | | | | | | | | | | | | | Disable vpcie0v9 regulator if resume_noirq fails. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: rockchip: Clean up PHY if driver probe or resume failsShawn Lin2017-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We observed that the clk_pciephy_ref is still enabled when we fail to probe the driver. root@linaro-alip:~# grep pcie /sys/kernel/debug/clk/clk_summary clk_pciephy_ref 1 1 24000000 0 0 clk_pcie_pm 0 0 24000000 0 0 clk_pcie_core_cru 0 0 125000000 0 0 clk_pciephy_ref100m 0 0 100000000 0 0 aclk_pcie 0 0 148500000 0 0 aclk_perf_pcie 0 0 148500000 0 0 pclk_pcie 0 0 37125000 0 0 clk_pcie_core 0 0 0 0 0 clk_pciephy_ref is used by the PHY driver and we need to properly disable it for this case. Add error handling in rockchip_pcie_init_port() and rockchip_pcie_resume_noirq() to fix this issue. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: rockchip: Factor out rockchip_pcie_deinit_phys()Shawn Lin2017-08-29
| | | | | | | | | | | | | | | | | | | | | | | | Factor out rockchip_pcie_deinit_phys() so it can be reused by rockchip_pcie_suspend_noirq() and rockchip_pcie_remove(). No functional change intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: rockchip: Factor out rockchip_pcie_disable_clocks()Shawn Lin2017-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Factor out rockchip_pcie_disable_clocks() so it can be reused by other functions. No functional change intended, but it does change the order of unpreparing clocks in the rockchip_pcie_resume_noirq() error path so it matches the other paths. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: rockchip: Factor out rockchip_pcie_enable_clocks()Shawn Lin2017-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Factor out rockchip_pcie_enable_clocks() so it can be reused by rockchip_pcie_resume_noirq() and rockchip_pcie_probe(). No functional change intended, but it does change the order of unpreparing clocks in the rockchip_pcie_resume_noirq() error path. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: rockchip: Factor out rockchip_pcie_setup_irq()Shawn Lin2017-08-29
| | | | | | | | | | | | | | | | | | | | | Factor out rockchip_pcie_setup_irq() to prepare for future bug fixes. No functional change intended. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: rockchip: Use gpiod_set_value_cansleep() to allow reset via expandersFabio Estevam2017-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | The reset GPIO can be connected to a I2C or SPI IO expander, which may sleep, so it is safer to use the gpiod_set_value_cansleep() variant instead. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
| * | PCI: rockchip: Use PCI_NUM_INTXPaul Burton2017-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the PCI_NUM_INTX macro to indicate the number of PCI INTx interrupts rather than the magic number 4. This makes it clearer where the number comes from & what it relates to. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Shawn Lin <shawn.lin@rock-chips.com>
| * | PCI: rockchip: Explicitly request exclusive reset controlPhilipp Zabel2017-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting reset lines") started to transition the reset control request API calls to explicitly state whether the driver needs exclusive or shared reset control behavior. Convert all drivers requesting exclusive resets to the explicit API call so the temporary transition helpers can be removed. No functional changes. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
| * | dt-bindings: phy-rockchip-pcie: Convert to per-lane PHY modelShawn Lin2017-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | Deprecate the legacy Rockchip PCIe PHY and encourage users to use per-lane PHY mode by setting #phy-cells to 1. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Rob Herring <robh@kernel.org>
| * | dt-bindings: PCI: rockchip: Convert to per-lane PHY modelShawn Lin2017-08-29
| | | | | | | | | | | | | | | | | | | | | | | | Deprecate legacy PHY model and encourage per-lane PHY model. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Rob Herring <robh@kernel.org>
| * | arm64: dts: rockchip: convert PCIe to use per-lane PHYs for rk3339Shawn Lin2017-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | Convert all RK3399 platforms to use per-lane PHY model in order to save more power by idling unused lane(s). Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org>
| * | PCI: rockchip: Idle inactive PHY(s)Shawn Lin2017-08-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check the status of all lanes and idle the inactive one(s). Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: always set lanes_map, even for legacy_phy case] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | phy: rockchip-pcie: Reconstruct driver to support per-lane PHYsShawn Lin2017-08-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reconstruct the whole driver to support per-lane PHYs. Note that we could also support the legacy PHY if you don't provide argument to rockchip_pcie_phy_of_xlate(). Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: use postincrement/decrement when order doesn't matter, uninline to_pcie_phy() so decl fits on one line] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | PCI: rockchip: Add per-lane PHY supportShawn Lin2017-08-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We distinguish the legacy PHY from newer per-lane PHYs by adding legacy_phy flag. Note that the legacy PHY is still the first option to be searched in order not to break the backward compatibility of DTB. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: tidy rockchip_pcie_get_phys()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | PCI: rockchip: Factor out rockchip_pcie_get_phys()Shawn Lin2017-08-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We plan to introduce per-lane PHYs, so factor out rockchip_pcie_get_phys() to make it easier in the future. No functional change intended. Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | PCI: rockchip: Control optional 12v power supplyShawn Lin2017-08-16
| | | | | | | | | | | | | | | | | | Get vpcie12v from DT and control it if available. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | dt-bindings: PCI: rockchip: Add vpcie12v-supply for Rockchip PCIe controllerShawn Lin2017-08-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | The PCIe connector provide a optional 12V power supply for high power downstream components, so we add this as an optional one if we need to control it. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org>
* | | Merge branch 'pci/host-rcar' into nextBjorn Helgaas2017-09-07
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | * pci/host-rcar: PCI: rcar: Add device tree support for r8a7743/5 PCI: rcar: Fix memory leak when no PCIe card is inserted PCI: rcar: Fix error exit path
| * | | PCI: rcar: Add device tree support for r8a7743/5Biju Das2017-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add internal PCI bridge support for r8a7743/5 SoC. The Renesas RZ/G1[ME] (R8A7743/5) internal PCI bridge is identical to the R-Car Gen2 family. This doesn't change the driver, so it does nothing by itself. But it does mean that checkpatch won't complain about a future patch that adds "renesas,pci-r8a7743" to a DT, which helps ensure that shipped DTs use documented compatibility strings. Signed-off-by: Biju Das <biju.das@bp.renesas.com> [bhelgaas: add explanatory note] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au>
| * | | PCI: rcar: Fix memory leak when no PCIe card is insertedHarunobu Kurokawa2017-08-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When no PCIe card is inserted, there is a memory leak as pci_free_resource_list() is not called before returning. Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au>
| * | | PCI: rcar: Fix error exit pathLorenzo Pieralisi2017-08-15
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 90634e854079 ("PCI: rcar: Convert PCI scan API to pci_scan_root_bus_bridge()") converted PCI root bus scan API to the new pci_scan_root_bus_bridge() API; in the process some error paths were not updated correctly which may cause memory leaks. Fix the driver error exit path reinstating the previous correct error exit behaviour. Fixes: 90634e854079 ("PCI: rcar: Convert PCI scan API to pci_scan_root_bus_bridge()") Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au>
* | | Merge branch 'pci/host-qcom' into nextBjorn Helgaas2017-09-07
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/host-qcom: PCI: qcom: Add support for IPQ8074 PCIe controller dt-bindings: PCI: qcom: Add support for IPQ8074 PCI: qcom: Use block IP version for operations PCI: qcom: Explicitly request exclusive reset control PCI: qcom: Use gpiod_set_value_cansleep() to allow reset via expanders
| * | | PCI: qcom: Add support for IPQ8074 PCIe controllerVaradarajan Narayanan2017-08-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one lane, two PCIe root complex with support for MSI and legacy interrupts, and it conforms to PCI Express Base 2.1 specification. The core init is the similar to the existing SoC, however the clocks and reset lines differ. Signed-off-by: smuthayy <smuthayy@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> [bhelgaas: fix capitalization and "dev" usage to match existing style] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
| * | | dt-bindings: PCI: qcom: Add support for IPQ8074Varadarajan Narayanan2017-08-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one lane, two PCIe root complex with support for MSI and legacy interrupts, and it conforms to PCI Express Base 2.1 specification. Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org>
| * | | PCI: qcom: Use block IP version for operationsVaradarajan Narayanan2017-08-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Presently, when support for a new SoC is added, the driver ops structures and functions are versioned with plain 1, 2, 3 etc. Instead use the block IP version number. Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
| * | | PCI: qcom: Explicitly request exclusive reset controlPhilipp Zabel2017-08-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting reset lines") started to transition the reset control request API calls to explicitly state whether the driver needs exclusive or shared reset control behavior. Convert all drivers requesting exclusive resets to the explicit API call so the temporary transition helpers can be removed. No functional changes. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
| * | | PCI: qcom: Use gpiod_set_value_cansleep() to allow reset via expandersFabio Estevam2017-08-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The reset GPIO can be connected to a I2C or SPI IO expander, which may sleep, so it is safer to use the gpiod_set_value_cansleep() variant instead. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
* | | | Merge branch 'pci/host-mvebu' into nextBjorn Helgaas2017-09-07
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | * pci/host-mvebu: PCI: mvebu: Remove unneeded gpiod NULL check
| * | | | PCI: mvebu: Remove unneeded gpiod NULL checkFabio Estevam2017-08-02
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | The gpiod API checks for NULL descriptors, so there is no need to duplicate the check in the driver. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com
* | | | Merge branch 'pci/host-mediatek' into nextBjorn Helgaas2017-09-07
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/host-mediatek: PCI: mediatek: Use PCI_NUM_INTX PCI: mediatek: Add MSI support for MT2712 and MT7622 PCI: mediatek: Use bus->sysdata to get host private data dt-bindings: PCI: Add support for MT2712 and MT7622 PCI: mediatek: Add controller support for MT2712 and MT7622 dt-bindings: PCI: Cleanup MediaTek binding text dt-bindings: PCI: Rename MediaTek binding PCI: mediatek: Switch to use platform_get_resource_byname() PCI: mediatek: Add a structure to abstract the controller generations PCI: mediatek: Rename port->index and mtk_pcie_parse_ports() PCI: mediatek: Use readl_poll_timeout() to wait for Gen2 training PCI: mediatek: Explicitly request exclusive reset control
| * | | | PCI: mediatek: Use PCI_NUM_INTXHonghui Zhang2017-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch from using custom INTX_NUM macro to the generic PCI_NUM_INTX definition for the number of INTx interrupts. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> [bhelgaas: use subject/changelog from similar patches] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | | | PCI: mediatek: Add MSI support for MT2712 and MT7622Honghui Zhang2017-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MT2712 and MT7622's PCIe host controller support MSI, but only 32-bit MSI addresses are supported. It connects to GIC with the same IRQ number as the INTx IRQ, so it shares the same IRQ with INTx IRQ. Add MSI support for MT2712 and MT7622. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> [bhelgaas: changes to follow rcar & tegra: rename to mtk_pcie_msi_alloc(), add mtk_pcie_msi_free(), free hwirq if irq_create_mapping() fails, call irq_dispose_mapping() from mtk_msi_teardown_irq()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Ryder Lee <ryder.lee@mediatek.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 16:13:00 -0400