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* ARM: tegra: dalmore: add cpu regulator nodeLaxman Dewangan2013-04-04
| | | | | | | | | | Dalmore uses the TPS51632 as CPU regulator. The device is connected on I2C5. Add DT node for TPS51632. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Add sbs-battery node to DalmoreRhyland Klein2013-04-04
| | | | | | | | | This patch adds the node for the bq20z45 I2C gas gauge which is compatible with the sbs-battery power supply driver. Signed-off-by: Rhyland Klein <rklein@nvidia.com> [swarren: remove unit-address from node name since it's unique already] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add DT binding for i2c-tegraLaxman Dewangan2013-04-04
| | | | | | | | | | | | Add documentation for device tree binding of NVIDIA's Tegra I2C controller driver. Describing all compatible values used for different Tegra SoCs in details in this documentation. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: fixed a couple typos, trimmed examples] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add SPI nodes to Tegra114 DTLaxman Dewangan2013-04-04
| | | | | | | | | | | | NVIDIA's Tegra114 has 6 SPI controllers. These controllers are redesign on T114 with different register interface. Add DT entry for spi controllers and make it compatible with "nvidia,tegra114-spi", since they are a new incompatible design. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: fixed reg property for 3rd SPI controller] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add KBC nodes to Tegra114 DTLaxman Dewangan2013-04-04
| | | | | | | | | | | NVIDIA's Tegra114 SoCs have the matrix keyboard controller which supports 11x8 type of matrix. The number of rows and columns are configurable. Add DT entry for KBC controller with compatibility as "nvidia,tegra114-kbc". Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add aliases and DMA requestor for serial nodes of Tegra114Laxman Dewangan2013-04-04
| | | | | | | | | | | | | | Add APB DMA requestor and serial aliases for serial controller. There are two serial drivers i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver is selected by compatible value "nvidia,tegra114-uart", "nvidia,tegra20-uart", and the APB DMA based driver is selected by compatible value "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add I2C nodes to Tegra114 DTLaxman Dewangan2013-04-04
| | | | | | | | | | | | | | NVIDIA's Tegra114 has 5 I2C controllers. These controllers have the following changes which makes incompatible with previous hardware: - Single clock source to I2C controller. - Interrupt support for per packet transfer. Add DT entry for I2C controllers and make it compatible with "nvidia,tegra114-i2c". Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: fixed location of status property for consistency] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add APB DMA nodes to Tegra114 DTLaxman Dewangan2013-04-04
| | | | | | | | | | | | | | NVIDIA's Tegra114 has 32 channels APB DMA controller. Add DT entry for APB DMA controllers and make it compatible with "nvidia,tegra114-apbdma". Tegra114 DMA controller is not compatible with Tegra30/Tegra20 DMA controller driver as in Tegra114, the global pause also clock gate the DMA register and hence it iw not possible to write the DMA register with global pause. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: fixed DT node order] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add PWM nodes to Tegra114 DTAndrew Chew2013-04-04
| | | | | | | | This patch adds a device tree node for the four PWM controllers present on Tegra114. Signed-off-by: Andrew Chew <achew@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: fix the status of PWM DT nodesAndrew Chew2013-04-04
| | | | | | | | | | | | | | | We should be defining the PWM nodes with status as "disabled" in the chip-specific dtsi file, since we don't know whether specific boards will use the PWM or not. This patch fixes the PWM node status for Tegra20 and Tegra30. Also fixed the one user of PWM, which is the Tegra20 medcom-wide board, so that PWM is set to "okay" in the board-specific dts file. Signed-off-by: Andrew Chew <achew@nvidia.com> [swarren: in medcom-wide: fixed node sort order, removed duplicate pwm: label, fixed syntax error] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add SDHCI support for DalmoreRhyland Klein2013-04-04
| | | | | | | | | | Dalmore has a built-in eMMC device and a user-accessible SD card slot. Add device tree nodes to enable these. Based on changes by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> [swarren: added commit description, fixed DT node sort order] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add SDHCI nodes with common propertiesPritesh Raithatha2013-04-04
| | | | | | | | | | | This patch adds in the SDHCI nodes for the busses supported on Tegra114 boards. Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> [Rhyland added clk refs to & reordered sdhci nodes and removed spaces] Signed-off-by: Rhyland Klein <rklein@nvidia.com> [swarren: fixed DT node sort order] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add default pinctrl nodes for DalmorePritesh Raithatha2013-04-04
| | | | | | | | | | | | This change adds the default pinctrl nodes for the Dalmore Tegra114 platform. Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> [Rhyland added patch description] Signed-off-by: Rhyland Klein <rklein@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> [swarren: fixed DT node sort order] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: fix sort order of USB PHY nodesStephen Warren2013-04-04
| | | | | | | | | | The USB PHY nodes are all grouped together rather than being sorted based on reg address like all other nodes fix this. I apologize for the churn; I should have noticed this during review of the patches that caused this. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: device tree whitespace cleanupStephen Warren2013-04-04
| | | | | | Remove white-space from empty line; triggers checkpatch. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: fix enum tegra114_clk to match bindingStephen Warren2013-04-04
| | | | | | | | | | A gap exists in the binding's clock ID definitions. Fix the clock driver to be consistent. This allows pclk to be looked up through device tree and prevents: ERROR: could not get clock /pmc:pclk(0) Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Remove forced clk_enable of uartdPeter De Schrijver2013-04-04
| | | | | | | | | The UART driver enables the console uart clock, so we don't need to do that anymore in this file. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: dt: Add references to tegra_car clocksPeter De Schrijver2013-04-04
| | | | | | | | | | Add references to tegra_car clocks for the basic device nodes. Also remove the clock-frequency property of the serial node as the UART driver can now use the clock framework to obtain the frequency. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: devicetree match for nvidia,tegra114-carPeter De Schrijver2013-04-04
| | | | | | Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Implement clocks for Tegra114Peter De Schrijver2013-04-04
| | | | | | | | Implement clocks for Tegra114. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Define Tegra114 CAR bindingPeter De Schrijver2013-04-04
| | | | | | | | | The device tree binding models Tegra114 CAR (Clock And Reset) as a single monolithic clock provider. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Workaround for Tegra114 MSENC problemPeter De Schrijver2013-04-04
| | | | | | | | Workaround a hardware bug in MSENC during clock enable. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Add flags to tegra_clk_periph()Peter De Schrijver2013-04-04
| | | | | | | | | We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag, most notably mselect, which is a bridge between AXI and most peripherals. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Add new fields and PLL types for Tegra114Peter De Schrijver2013-04-04
| | | | | | | | | Tegra114 introduces new PLL types. This requires new clocktypes as well as some new fields in the pll structure. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: move from a lock bit idx to a lock maskPeter De Schrijver2013-04-04
| | | | | | | | | PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits. So switch to a lock mask to be able to test both at the same time. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Add PLL post divider tablePeter De Schrijver2013-04-04
| | | | | | | | | Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider. Introduce a table based approach and switch PLLU to it. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLEPeter De Schrijver2013-04-04
| | | | | | | | | Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are always functional. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Add TEGRA_PLL_BYPASS flagPeter De Schrijver2013-04-04
| | | | | | | | | Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use this bit when available. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Refactor PLL programming codePeter De Schrijver2013-04-04
| | | | | | | | | | | | | | | | | | | | Refactor the PLL programming code to make it useable by the new PLL types introduced by Tegra114. The following changes were done: * Split programming the PLL into updating m,n,p and updating cpcon * Move locking from _update_pll_cpcon() to clk_pll_set_rate() * Introduce _get_pll_mnp() helper * Move check for identical m,n,p values to clk_pll_set_rate() * struct tegra_clk_pll_freq_table will always contain the values as defined by the hardware. * Simplify the arguments to clk_pll_wait_for_lock() * Split _tegra_clk_register_pll() Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: provide dummy cpu car opsPeter De Schrijver2013-04-04
| | | | | | | | | | | tegra_boot_secondary() relies on some of the car ops. This means having an uninitialized tegra_cpu_car_ops will lead to an early boot panic. Providing a dummy struct avoids this and makes adding Tegra114 clock support in a bisectable way a lot easier. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: defer application of init tableStephen Warren2013-04-04
| | | | | | | | | | | | | | | | | The Tegra clock driver is initialized during the ARM machine descriptor's .init_irq() hook. It can't be initialized earlier, since dynamic memory usage is required. It can't be initialized later, since the .init_timer() hook needs the clocks initialized. However, at this time, udelay() doesn't work. The Tegra clock initialization table may enable some PLLs. Enabling a PLL may require usage of udelay(). Hence, this can't happen right when the clock driver is initialized. To solve this, separate the clock driver initialization from the clock table processing, so they can execute at separate times. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Fix cdev1 and cdev2 IDsPrashant Gaikwad2013-04-04
| | | | | | | | Correct IDs for cdev1 and cdev2 are 94 and 93 respectively. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: split into separate driver and device-tree patches] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Make gr2d and gr3d clocks children of pll_cThierry Reding2013-04-04
| | | | | | | | | | | | | | By default these clocks are children of pll_m, but in downstream kernels they are reparented to pll_c. While at it, decrease their frequencies to 300 MHz because the defaults aren't in the specified range. gr2d can reportedly run at much higher frequencies, but 300 MHz works and is a more conservative default. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Export peripheral reset functionsThierry Reding2013-04-04
| | | | | | | | | | | | | The tegra_periph_reset_assert() and tegra_periph_reset_deassert() functions can be used by drivers to reset peripherals. In order to allow such drivers to be built as modules, export the functions. Note that this restores the status quo as the functions were exported before the move to the drivers/clk tree. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* clk: tegra: Fix periph_clk_to_bit macroYen Lin2013-04-04
| | | | | | | | | | | | | | The parameter name should be "gate", not "periph". This worked, however, because it happens that everywhere periph_clk_to_bit is called, "gate" was in the local scope. Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Andrew Chew <achew@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Merge remote-tracking branch 'linaro_mturquette_linux/clk-for-3.10' into ↵Stephen Warren2013-04-04
|\ | | | | | | for-3.10/clk
| * clk: allow reentrant calls into the clk frameworkMike Turquette2013-04-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reentrancy into the clock framework is necessary for clock operations that result in nested calls to the clk api. A common example is a clock that is prepared via an i2c transaction, such as a clock inside of a discrete audio chip or a power management IC. The i2c subsystem itself will use the clk api resulting in a deadlock: clk_prepare(audio_clk) i2c_transfer(..) clk_prepare(i2c_controller_clk) The ability to reenter the clock framework prevents this deadlock. Other use cases exist such as allowing .set_rate callbacks to call clk_set_parent to achieve the best rate, or to save power in certain configurations. Yet another example is performing pinctrl operations from a clk_ops callback. Calls into the pinctrl subsystem may call clk_{un}prepare on an unrelated clock. Allowing for nested calls to reenter the clock framework enables both of these use cases. Reentrancy is implemented by two global pointers that track the owner currently holding a global lock. One pointer tracks the owner during sleepable, mutex-protected operations and the other one tracks the owner during non-interruptible, spinlock-protected operations. When the clk framework is entered we try to hold the global lock. If it is held we compare the current task against the current owner; a match implies a nested call and we reenter. If the values do not match then we block on the lock until it is released. Signed-off-by: Mike Turquette <mturquette@linaro.org> Cc: Rajagopal Venkat <rajagopal.venkat@linaro.org> Cc: David Brown <davidb@codeaurora.org> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
| * clk: abstract locking out into helper functionsMike Turquette2013-04-02
| | | | | | | | | | | | | | | | | | | | | | | | | | Create locking helpers for the global mutex and global spinlock. The definitions of these helpers will be expanded upon in the next patch which introduces reentrancy into the locking scheme. Signed-off-by: Mike Turquette <mturquette@linaro.org> Cc: Rajagopal Venkat <rajagopal.venkat@linaro.org> Cc: David Brown <davidb@codeaurora.org> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
| * clk: zynq: Add missing zynq clk headerMichal Simek2013-03-27
| | | | | | | | | | | | | | | | | | | | | | Include zynq clk header where init function is declared. It removes this sparse warning: drivers/clk/clk-zynq.c:373:13: warning: symbol 'xilinx_zynq_clocks_init' was not declared. Should it be static? Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: sunxi: rename compatible stringsEmilio López2013-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During the introduction of the Allwinner SoC platforms, sunxi was initially meant as a generic name for all the variants of the Allwinner SoC. It was ok at the time of the support of only the A10 and A13 that look pretty much the same; but it's beginning to be troublesome with the future addition of the Allwinner A31 (sun6i) that is quite different, and would introduce some weird logic, where sunxi would actually mean in some case sun4i and sun5i but without sun6i... Moreover, it makes the compatible strings naming scheme not consistent with other architectures, where usually for this kind of compability, we just use the oldest SoC name that has this IP, so let's do just this. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * arm: sunxi: Add useful information about sunxi clocksEmilio López2013-03-27
| | | | | | | | | | | | | | | | | | This patch contains useful bits of information about the sunxi clocks that may help and/or be interesting for current and future developers. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: arm: sunxi: Add a new clock driver for sunxi SOCsEmilio López2013-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit implements the base CPU clocks for sunxi devices. It has been tested using a slightly modified cpufreq driver from the linux-sunxi 3.0 tree. Additionally, document the new bindings introduced by this patch. Idling: / # cat /sys/kernel/debug/clk/clk_summary clock enable_cnt prepare_cnt rate --------------------------------------------------------------------- osc32k 0 0 32768 osc24M_fixed 0 0 24000000 osc24M 0 0 24000000 apb1_mux 0 0 24000000 apb1 0 0 24000000 pll1 0 0 60000000 cpu 0 0 60000000 axi 0 0 60000000 ahb 0 0 60000000 apb0 0 0 30000000 dummy 0 0 0 After "yes >/dev/null &": / # cat /sys/kernel/debug/clk/clk_summary clock enable_cnt prepare_cnt rate --------------------------------------------------------------------- osc32k 0 0 32768 osc24M_fixed 0 0 24000000 osc24M 0 0 24000000 apb1_mux 0 0 24000000 apb1 0 0 24000000 pll1 0 0 1008000000 cpu 0 0 1008000000 axi 0 0 336000000 ahb 0 0 168000000 apb0 0 0 84000000 dummy 0 0 0 Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: ux500: Fix prcmu clocks registrationMaxime Coquelin2013-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In clk_reg_prcmu(), clk->hw.init field is assigned with a reference local to clk_reg_prcmu() function. This patch replaces references to clk->hw.init with calls to __clk_get_name when called after clock registration. This patch applies on top of v3.9-rc4. Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: resolved trivial merge issues]
| * ARM: imx: adapt clk_busy_mux to new clk_mux structFabio Estevam2013-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ce4f3313b05 (clk: add table lookup to mux) caused the following build error on imx_v4_v5_defconfig/imx_v6_v7_defconfig: arch/arm/mach-imx/clk-busy.c:172:11: error: 'struct clk_mux' has no member named 'width' Fix it by passing the 'mask' field. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: shortened $SUBJECT line]
| * clk: Add composite clock typePrashant Gaikwad2013-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all clocks are required to be decomposed into basic clock types but at the same time want to use the functionality provided by these basic clock types instead of duplicating. For example, Tegra SoC has ~100 clocks which can be decomposed into Mux -> Div -> Gate clock types making the clock count to ~300. Also, parent change operation can not be performed on gate clock which forces to use mux clock in driver if want to change the parent. Instead aggregate the basic clock types functionality into one clock and just use this clock for all operations. This clock type re-uses the functionality of basic clock types and not limited to basic clock types but any hardware-specific implementation. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: add table lookup to muxPeter De Schrijver2013-03-22
| | | | | | | | | | | | | | | | | | | | Add a table lookup feature to the mux clock. Also allow arbitrary masks instead of the width. This will be used by some clocks on Tegra114. Also adapt the tegra periph clk because it uses struct clk_mux directly. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: Fix incorrect return type in clk.cSachin Kamat2013-03-22
| | | | | | | | | | | | | | | | | | | | | | Return type of function clk_propagate_rate_change is a pointer. But 0 was being returned. Change it to NULL. Silences the following warning: drivers/clk/clk.c:977:24: warning: Using plain integer as NULL pointer Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Reviewed-by: Pankaj Jangra <jangra.pankaj9@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: prima2: fix return value check in sirfsoc_of_clk_init()Wei Yongjun2013-03-22
| | | | | | | | | | | | | | | | | | | | | | In case of error, the function clk_get() returns ERR_PTR() not NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by: Barry Song <21cnbao@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: added missing parenthesis to fix compile break]
| * clk:SPEAr1340: Correct parent clock configurationVipul Kumar Samar2013-03-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch corrects wrongly configured parent clock for following devices: * Video enc/decoder * Video ip * Pin control * ACP * camx Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Reviewed-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * documentation: clk: fix couple of misspellingEduardo Valentin2013-03-21
| | | | | | | | | | | | | | Correcting misspelling inside the clk.txt. Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-16 00:16:06 -0400