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* Merge tag 'mvebu-soc-3.15-2' of git://git.infradead.org/linux-mvebu into ↵Arnd Bergmann2014-03-17
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/soc Merge "mvebu soc changes for v3.15 (incremental pull #2)" from Jason Cooper: - mvebu - Add Armada 375, 380 and 385 SoCs - kirkwood - move kirkwood DT support to mach-mvebu - add mostly DT support for HP T5325 thin client * tag 'mvebu-soc-3.15-2' of git://git.infradead.org/linux-mvebu: ARM: kirkwood: Add HP T5325 thin client ARM: kirkwood: select dtbs based on SoC ARM: kirkwood: Remove redundant kexec code ARM: mvebu: Armada 375/38x depend on MULTI_V7 ARM: mvebu: Simplify headers and make local ARM: mvebu: Enable mvebu-soc-id on Kirkwood ARM: mvebu: Let kirkwood use the system controller for restart ARM: mvebu: Move kirkwood DT boards into mach-mvebu ARM: MM Enable building Feroceon L2 cache controller with ARCH_MVEBU ARM: Fix default CPU selection for ARCH_MULTI_V5 ARM: MM: Add DT binding for Feroceon L2 cache ARM: orion: Move cache-feroceon-l2.h out of plat-orion ARM: mvebu: Add ARCH_MULTI_V7 to SoCs ARM: kirkwood: ioremap memory control register ARM: kirkwood: ioremap the cpu_config register before using it. ARM: kirkwood: Separate board-dt from common and pcie code. ARM: kirkwood: Drop printing the SoC type and revision ARM: kirkwood: Convert mv88f6281gtw_ge switch setup to DT ARM: kirkwood: Give pm.c its own header file. ARM: mvebu: Rename the ARCH_MVEBU menu option Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * Merge branch 'mvebu/soc-kw' into mvebu/socJason Cooper2014-02-28
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| | * ARM: kirkwood: Add HP T5325 thin clientAndrew Lunn2014-02-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert the kirkwood t5325-setup.c to mostly device tree for mach-mvebu. Part of the audio setup needs to remain in C for the moment until suitable bindings are designed and implemented. So add board code, triggered by the compatibility string. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * ARM: kirkwood: select dtbs based on SoCJason Cooper2014-02-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To prevent problems later with mvebu_v5_defconfig builds, we restrict the scope of the changes this series makes. Selecting ARCH_KIRKWOOD and MACH_KIRKWOOD is necessary during the migration from mach-kirkwood to mach-mvebu. Until the last four legacy kirkwood board files have a DT equivalent, we need to support building DT from both mach-kirkwood and mach-mvebu. Reported-by: Kevin Hilman <khilman@linaro.org> Acked-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * ARM: kirkwood: Remove redundant kexec codeAndrew Lunn2014-02-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCIe driver has been fully clock aware for quite a while. Remove the kexec code to enable the PCIe clock, since the PCIe driver will do the right thing. jac adds: [arnd]: fixes a build error when KEXEC is enabled and KIRKWOOD_LEGACY is not Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * ARM: mvebu: Simplify headers and make localAndrew Lunn2014-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | kirkwood is very nearly fully DT. Remove most of the address definitions from the header files and make it a local header file. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * ARM: mvebu: Enable mvebu-soc-id on KirkwoodAndrew Lunn2014-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the Kirkwood PCIe compatibility string to mvebu-soc-id, so that it can get the SoC ID and revision from the PCIe endpoints. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * ARM: mvebu: Let kirkwood use the system controller for restartAndrew Lunn2014-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mvebu system controller already supports restarting orion systems. Remove all the C code which will be replaced by the system controller. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * ARM: mvebu: Move kirkwood DT boards into mach-mvebuAndrew Lunn2014-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the kirkwood DT support into mach-mvebu, and make them part of ARCH_MULTI_V5. Minimal changes have been made in order to make it boot. Cleanup of the header files and integration with mvebu will take place in following patches. In order to help Debian transition between mach-kirkwood and mach-mvebu, the DTS files are compiled for both, allowing Debian to continue using mach-kirkwood until all remaining boards are supported by mach-mvebu. Debian is then expected to simply swap from mach-kirkwood to mach-mvebu and mach-kirkwood will be removed. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * ARM: MM Enable building Feroceon L2 cache controller with ARCH_MVEBUAndrew Lunn2014-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kirkwood, which uses the Feroceon L2 cache controller will soon be moving into mach-mvebu. Allow the cache controller to be built in this situation. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * ARM: Fix default CPU selection for ARCH_MULTI_V5Andrew Lunn2014-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPU_ARM926T should be selected if no other CPU is. Put the ! in the right place so this works. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Fixes: 24e860fbfdb1c ("ARM: multiplatform: always pick one CPU type") Cc: stable@vger.kernel.org # v3.11+ Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * ARM: MM: Add DT binding for Feroceon L2 cacheAndrew Lunn2014-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instantiate the L2 cache from DT. Indicate in DT where the cache control register is so that it is possible to enable/disable write through on the CPU. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * ARM: orion: Move cache-feroceon-l2.h out of plat-orionAndrew Lunn2014-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the gradual move to DT, kirkwood has become a lot less dependent on plat-orion. cache-feroceon-l2.h is the last dependency. Move it out so we can drop plat-orion when building DT only kirkwood boards. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * ARM: mvebu: Add ARCH_MULTI_V7 to SoCsAndrew Lunn2014-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prepare mach-mvebu to house both ARCH_MULTI_V7 and ARCH_MULTI_V5 systems by adding ARCH_MULTI_V7 to the existing SOCs. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * ARM: kirkwood: ioremap memory control registerAndrew Lunn2014-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To allow removal of the global map of registers, make the pm code ioremap the registers it needs. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * ARM: kirkwood: ioremap the cpu_config register before using it.Andrew Lunn2014-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the move to mach-mvebu and MULTI_V5, the global iomap for all registers will be going away. So explicitly map the CPU configuration register before using it. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * ARM: kirkwood: Separate board-dt from common and pcie code.Andrew Lunn2014-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to be able to move DT support into mach-mvebu, the DT code needs to be cleanly separated from common and pcie code. Import the needed bits of these files into board-dt.c. The "common" code then becomes purely legacy, supporting non-DT boards, so reflect this in the Makefile targets. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * ARM: kirkwood: Drop printing the SoC type and revisionAndrew Lunn2014-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will be added back using the mach-mvebu equivalent once the move has been made. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * ARM: kirkwood: Convert mv88f6281gtw_ge switch setup to DTAndrew Lunn2014-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mv88f6281gtw_ge has a ethernet switch connected to the ethernet port of the SoC. Convert the platform device instantiation to a DT instantiation. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Cc: florian@openwrt.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * ARM: kirkwood: Give pm.c its own header file.Andrew Lunn2014-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pm code needs to be separated from common.h in order to split DT and non-DT systems apart. Move the declarations into a header file of its own and include it where needed. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> (on kirkwood) Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | Merge branch 'mvebu/soc-3xx' into mvebu/socJason Cooper2014-02-28
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| | * ARM: mvebu: Armada 375/38x depend on MULTI_V7Jason Cooper2014-02-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During this release cycle, we're adding the new Armada 375, 380, and 385 SoCs. We're also migrating DT kirkwood boards into mach-mvebu. The kirkwood changes make the different SoCs in mach-mvebu/ depend on MULTI_V7 or MULTI_V5 as appropriate. We add this dependency to the new SoCs so that when the branches are merged, everything is as it should be. Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | ARM: mvebu: Rename the ARCH_MVEBU menu optionEzequiel Garcia2014-02-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | The previous name "Marvell SOCs with Device Tree support" is a bit ambiguous and not too informative for users. Instead, use a more appropriate name. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | | Merge tag 'renesas-soc3-for-v3.15' of ↵Olof Johansson2014-03-17
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Merge "Third Round of Renesas ARM Based SoC Updates for v3.15" from Simon Horman: Fix warnings due to improper printk formats in shared APMU code. * tag 'renesas-soc3-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: APMU: Fix warnings due to improper printk formats Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | ARM: shmobile: APMU: Fix warnings due to improper printk formatsLaurent Pinchart2014-03-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the %pr printk specifier to print resource variables. This fixes warnings on platforms where resource_size_t has a different size than int. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | Merge tag 'renesas-soc2-for-v3.15' of ↵Olof Johansson2014-03-17
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Merge "Second Round of Renesas ARM Based SoC Updates for v3.15" from Simon Horman: * R-Car Gen2 SoCs: r8a7791 (R-Car M2) and r8a7790 (R-Car H2) - Remove __init from rcar_gen2_read_mode_pins() * r8a7791 (R-Car M2) - Use 64-bit dma_addr_t * r8a7790 (R-Car H2) - Add CA15-SCU, CA7-SCU - Add SYSC setup code - Use 64-bit dma_addr_t * tag 'renesas-soc2-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: Move SYSC base variable to inside ifdefs ARM: shmobile: Remove __init from rcar_gen2_read_mode_pins() ARM: shmobile: r8a7790 CA15-SCU enablement ARM: shmobile: r8a7790 CA7-SCU enablement ARM: shmobile: r8a7790 SYSC setup code ARM: shmobile: Break out R-Car SYSC PM code ARM: shmobile: Use 64-bit dma_addr_t on r8a7790/r8a7791 Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | ARM: shmobile: Move SYSC base variable to inside ifdefsMagnus Damm2014-02-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the rcar_sysc_base variable to inside #ifdefs to avoid triggering build warnings in case PM or SMP is not selected. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | ARM: shmobile: Remove __init from rcar_gen2_read_mode_pins()Magnus Damm2014-02-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove __init from rcar_gen2_read_mode_pins() to allow it to be used after boot. For instance the R-Car Gen2 MD21 check is needed even in the case of CPU Hotplug. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | ARM: shmobile: r8a7790 CA15-SCU enablementKeita Kobayashi2014-02-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Power on CA15 SCU in case of booting from a CA7 core. Signed-off-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> [damm@opensource.se: Converted to use broken out SYSC code] Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | ARM: shmobile: r8a7790 CA7-SCU enablementGaku Inami2014-02-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Power on CA7 SCU in case of booting from a CA15 core. Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> [damm@opensource.se: Converted to use broken out SYSC code] Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | ARM: shmobile: r8a7790 SYSC setup codeHisashi Nakamura2014-02-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add r8a7790 SYSC power management support. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com> [damm@opensource.se: Converted to use broken out SYSC code] Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | ARM: shmobile: Break out R-Car SYSC PM codeMagnus Damm2014-02-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Break out the R-Car SYSC power management code from the r8a7779 SoC code. With this new shared R-Car SYSC code base it is possible to hook in Generation 2 SoCs as well. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | ARM: shmobile: Use 64-bit dma_addr_t on r8a7790/r8a7791Magnus Damm2014-02-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some on-chip devices on r8a7790 and r8a7791 can do bus mastering and access more than 32-bits of address space. Select ARCH_DMA_ADDR_T_64BIT when LPAE is set in case of multiplatform and legacy SoC support. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | Merge tag 'armsoc/for-3.15/soc-2' of git://github.com/broadcom/mach-bcm into ↵Olof Johansson2014-03-11
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/soc Merge "ARM: mach-bcm soc updates" from Matt Porter: - add BCM5301x support - remove GENERIC_TIME * tag 'armsoc/for-3.15/soc-2' of git://github.com/broadcom/mach-bcm: ARM: BCM5301X: workaround suppress fault ARM: BCM5301X: add early debugging support ARM: BCM5301X: initial support for the BCM5301X/BCM470X SoCs with ARM CPU ARM: mach-bcm: Remove GENERIC_TIME Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | | ARM: BCM5301X: workaround suppress faultHauke Mehrtens2014-03-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this patch I am getting a unhandled fault exception like this one after "Freeing unused kernel memory": Freeing unused kernel memory: 1260K (c02c1000 - c03fc000) Unhandled fault: imprecise external abort (0x1c06) at 0xb6f89005 Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007 The address which is here 0xb6f89005 changes from boot to boot, with a new build the changes are bigger. With kernel 3.10 I have also seen this fault at different places in the boot process, but starting with 3.11 they are always occurring after the "Freeing unused kernel memory" message. I never was able to completely boot to userspace without this handler. The abort code is constant 0x1c06. This fault just happens once in the boot process I have never seen it happing twice or more. I also tried changing the CPSR.A bit to 0 in init_early, with this code like Afzal suggested, but that did not change anything: asm volatile("mrs r12, cpsr\n" "bic r12, r12, #0x00000100\n" "msr cpsr_c, r12" ::: "r12", "cc", "memory"); Disabling the L2 cache by building with CONFIG_CACHE_L2X0 unset did not help. This workaround was copied from the vendor code including most of the comments. It says it they think this is caused by the CFE boot loader used on this device. I do not have any access to any datasheet or errata document to check this. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Christian Daudt <bcm@fixthebug.org> Signed-off-by: Matt Porter <mporter@linaro.org>
| * | | | ARM: BCM5301X: add early debugging supportHauke Mehrtens2014-03-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for early debugging of BCM5301X SoC. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Christian Daudt <bcm@fixthebug.org> Signed-off-by: Matt Porter <mporter@linaro.org>
| * | | | ARM: BCM5301X: initial support for the BCM5301X/BCM470X SoCs with ARM CPUHauke Mehrtens2014-03-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the BCM5301X/BCM470X SoCs with an ARM CPUs. Currently just booting to a shell is working and nothing else, no Ethernet, wifi, flash, ... I have some pending patches to make Ethernet work for this device. Mostly device tree support for bcma is missing. This SoC is used in small office and home router with Broadcom SoCs it's internal name is Northstar. This code should support the BCM4707, BCM4708, BCM4709, BCM53010, BCM53011 and BCM53012 SoC. It uses one or two ARM Cortex A9 Cores, some highlights are 2 PCIe 2.0 controllers, 4 Gigabit Ethernet MACs and a USB 3.0 host controller. This SoC uses a dual core CPU, but this is currently not implemented. More information about this SoC can be found here: http://www.anandtech.com/show/5925/broadcom-announces-bcm4708x-and-bcm5301x-socs-for-80211ac-routers Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Christian Daudt <bcm@fixthebug.org> Signed-off-by: Matt Porter <mporter@linaro.org>
| * | | | ARM: mach-bcm: Remove GENERIC_TIMERichard Weinberger2014-03-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The symbol is an orphan, get rid of it. Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Christian Daudt <bcm@fixthebug.org> Signed-off-by: Matt Porter <mporter@linaro.org>
* | | | | ARM: enable ARM_HAS_SG_CHAIN for multiplatformOlof Johansson2014-03-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable ARM_HAS_SG_CHAIN for all multiplatform targets, it makes sense to enable on all "modern" platforms; downsides are limited for platforms that don't need it. Requested-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Olof Johansson <olof@lixom.net>
* | | | | Merge tag 'imx-soc-3.15' of git://git.linaro.org/people/shawnguo/linux-2.6 ↵Olof Johansson2014-03-09
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/soc i.MX SoC changes for 3.15 from Shawn Guo: - Support suspend from ocram (DDR IO floating) for imx6 platforms - Add cpuidle support for imx6sl - Sparse warning fixes for imx6sl and vf610 clock code - Remove PWM platform code - Support ptp and rmii clock from pad - Support WEIM CS GPR configuration - Random cleanups and defconfig updates * tag 'imx-soc-3.15' of git://git.linaro.org/people/shawnguo/linux-2.6: (373 commits) ARM: imx6: drop .text.head section annotation from headsmp.S ARM: imx6: build suspend-imx6.o with CONFIG_SOC_IMX6 ARM: imx6: rename pm-imx6q.c to pm-imx6.c ARM: imx6: introduce CONFIG_SOC_IMX6 for i.MX6 common stuff ARM: imx6: do not call imx6q_suspend_init() with !CONFIG_SUSPEND ARM: imx6: call suspend_set_ops() from suspend routine ARM: imx6: build headsmp.o only on CONFIG_SMP ARM: imx6: move v7_cpu_resume() into suspend-imx6.S ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority ARM: imx6q: Add GPR6 and GPR7 register definitions for iomuxc gpr bus: imx-weim: support CS GPR configuration ARM: mach-imx: Kconfig: Remove IMX_HAVE_PLATFORM_IMX2_WDT from SOC_IMX53 ARM: imx_v6_v7_defconfig: Select CONFIG_DEBUG_FS ARM: mach-imx: Select CONFIG_SRAM at ARCH_MXC level ARM: imx: add speed grading check for i.mx6 soc ARM: imx: avoid calling clk APIs in idle thread which may cause schedule ARM: imx6q: support ptp and rmii clock from pad ARM: imx6q: remove unneeded clk lookups ARM: imx_v6_v7_defconfig: Select CONFIG_MMC_UNSAFE_RESUME ARM: imx_v4_v5_defconfig: Select CONFIG_MMC_UNSAFE_RESUME ...
| * | | | | ARM: imx6: drop .text.head section annotation from headsmp.SShawn Guo2014-03-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function v7_secondary_startup() works just fine in .text section, so there is no need to have .text.head section annotation at all. Drop it. Suggested-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | | | ARM: imx6: build suspend-imx6.o with CONFIG_SOC_IMX6Shawn Guo2014-03-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even when CONFIG_SUSPEND is enabled, it makes no sense to build suspend-imx6.o if none of i.MX6 support is built in. Let's build suspend-imx6.o only when both CONFIG_SUSPEND and CONFIG_SOC_IMX6 are enabled. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | | | ARM: imx6: rename pm-imx6q.c to pm-imx6.cShawn Guo2014-03-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pm-imx6q.c works for all i.MX6 SoCs, so let's rename it to pm-imx6.c and have the build controlled by option CONFIG_SOC_IMX6. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | | | ARM: imx6: introduce CONFIG_SOC_IMX6 for i.MX6 common stuffShawn Guo2014-03-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX6 SoCs have something in common, so let's introduce CONFIG_SOC_IMX6 for those stuff. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | | | ARM: imx6: do not call imx6q_suspend_init() with !CONFIG_SUSPENDShawn Guo2014-03-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_SUSPEND is not enabled, we should reasonably skip the call to imx6q_suspend_init(). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | | | ARM: imx6: call suspend_set_ops() from suspend routineShawn Guo2014-03-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename function imx6q_ocram_suspend_init() to imx6q_suspend_init() and call suspend_set_ops() from there. Now we get a centralized function for suspend initialization. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | | | ARM: imx6: build headsmp.o only on CONFIG_SMPShawn Guo2014-03-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With v7_cpu_resume() being moved out of headsmp.S, all the remaining code in the file is only needed by CONFIG_SMP build. So we can control the build of headsmp.o with only obj-$(CONFIG_SMP) now. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | | | ARM: imx6: move v7_cpu_resume() into suspend-imx6.SShawn Guo2014-03-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The suspend-imx6.S is introduced recently for suspend low-level assembly code. Since function v7_cpu_resume() is only used by suspend support, it makes sense to move the function into suspend-imx6.S, and control the build of the file with CONFIG_SUSPEND option. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | | | ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priorityPhilipp Zabel2014-03-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is needed so that the IPU framebuffer scanout cannot be starved by VPU or GPU activity. Some boards like the SabreLite and SabreSD seem to set this in the DCD already, but the documented register reset values do not contain the necessary settings. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | | | ARM: imx6q: Add GPR6 and GPR7 register definitions for iomuxc gprPhilipp Zabel2014-03-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Masks for IPU AXI transaction QoS settings Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-06 21:28:26 -0400