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* Merge branch 'pci/virtualization' into nextBjorn Helgaas2017-09-07
|\ | | | | | | | | | | | | | | | | | | * pci/virtualization: PCI: Disable VF decoding before pcibios_sriov_disable() updates resources PCI: Add ACS quirk for APM X-Gene devices PCI: Mark AMD Stoney GPU ATS as broken Conflicts: drivers/pci/quirks.c
| * PCI: Disable VF decoding before pcibios_sriov_disable() updates resourcesGavin Shan2017-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A struct resource represents the address space consumed by a device. We should not modify that resource while the device is actively using the address space. For VFs, pci_iov_update_resource() enforces this by printing a warning and doing nothing if the VFE (VF Enable) and MSE (VF Memory Space Enable) bits are set. Previously, both sriov_enable() and sriov_disable() called the pcibios_sriov_disable() arch hook, which may update the struct resource, while VFE and MSE were enabled. This effectively dropped the resource update pcibios_sriov_disable() intended to do. Disable VF memory decoding before calling pcibios_sriov_disable(). Reported-by: Carol L Soto <clsoto@us.ibm.com> Tested-by: Carol L Soto <clsoto@us.ibm.com> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: shan.gavin@gmail.com Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org>
| * PCI: Add ACS quirk for APM X-Gene devicesFeng Kan2017-08-10
| | | | | | | | | | | | | | | | | | | | | | | | The APM X-Gene PCIe root port does not support ACS at this point. However, the hardware provides isolation and source validation through the SMMU. The stream ID generated by the PCIe ports contain both the bus/device/ function number as well as the port ID in its 3 most significant bits. Turn on ACS but disable all the peer-to-peer features. Signed-off-by: Feng Kan <fkan@apm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com> Acked-by: Tanmay Inamdar <tinamdar@apm.com>
| * PCI: Mark AMD Stoney GPU ATS as brokenJoerg Roedel2017-07-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ATS is broken on this hardware and causes IOMMU stalls and system failure. Disable ATS on these devices to make them usable again with IOMMU enabled. Note that the commit in the Fixes tag is not buggy; it just uncovers the problem in the hardware by increasing the ATS flush rate. Link: https://lists.linuxfoundation.org/pipermail/iommu/2017-March/020836.html Link: https://bugzilla.redhat.com/show_bug.cgi?id=1409201 Fixes: b1516a14657a ("iommu/amd: Implement flush queue") Signed-off-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
* | Merge branch 'pci/trivial' into nextBjorn Helgaas2017-09-07
|\ \ | | | | | | | | | | | | | | | | | | * pci/trivial: PCI: Fix typos and whitespace errors PCI: Remove unused "res" variable from pci_resource_io() PCI: Correct kernel-doc of pci_vpd_srdt_size(), pci_vpd_srdt_tag()
| * | PCI: Fix typos and whitespace errorsBjorn Helgaas2017-09-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix various typos and whitespace errors: s/Synopsis/Synopsys/ s/Designware/DesignWare/ s/Keystine/Keystone/ s/gpio/GPIO/ s/pcie/PCIe/ s/phy/PHY/ s/confgiruation/configuration/ No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Remove unused "res" variable from pci_resource_io()Shawn Lin2017-09-01
| | | | | | | | | | | | | | | | | | | | | The "res" variable in pci_resource_io() is never used. Remove it. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Correct kernel-doc of pci_vpd_srdt_size(), pci_vpd_srdt_tag()Shawn Lin2017-09-01
| |/ | | | | | | | | | | | | The kernel-doc comments don't match the arguments, so fix the comments. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'pci/resource' into nextBjorn Helgaas2017-09-07
|\ \ | | | | | | | | | | | | | | | | | | | | | * pci/resource: microblaze/PCI: Remove pcibios_setup_bus_{self/devices} dead code ARC: Remove empty kernel/pcibios.c PCI: Add a generic weak pcibios_align_resource() PCI: Add a generic weak pcibios_fixup_bus()
| * | microblaze/PCI: Remove pcibios_setup_bus_{self/devices} dead codeLorenzo Pieralisi2017-08-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 01cf9d524ff0 ("microblaze/PCI: Support generic Xilinx AXI PCIe Host Bridge IP driver") removed pcibios calls to: pcibios_setup_bus_self() pcibios_setup_bus_devices() Given that pcibios_fixup_bus() was the only caller of those functions they have now become dead code (along with the functions they were calling in turn), so they can be removed. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> [bhelgaas: remove "Fixup resources of a PCI<->PCI bridge" comment] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Ravi Kiran Gummaluri <rgummal@xilinx.com>
| * | ARC: Remove empty kernel/pcibios.cPalmer Dabbelt2017-08-02
| | | | | | | | | | | | | | | | | | ARC requires no arch-specific pcibios hooks, so delete this empty file. Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Add a generic weak pcibios_align_resource()Palmer Dabbelt2017-08-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Multiple architectures define this as a trivial function, and I'm adding another one as part of the RISC-V port. Add a __weak version of pcibios_align_resource() and delete the now-obselete ones in a handful of ports. The only functional change should be that a handful of ports used to export pcibios_fixup_bus(). Only some architectures export this, so I just dropped it. Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Add a generic weak pcibios_fixup_bus()Palmer Dabbelt2017-08-02
| |/ | | | | | | | | | | | | | | | | | | | | | | | | Multiple architectures define this as an empty function, and I'm adding another one as part of the RISC-V port. Add a __weak version of pcibios_fixup_bus() and delete the now-obselete ones in a handful of ports. The only functional change should be that microblaze used to export pcibios_fixup_bus(). None of the other architectures exports this, so I just dropped it. Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'pci/pm' into nextBjorn Helgaas2017-09-07
|\ \ | | | | | | | | | | | | * pci/pm: PCI/PM: Expand description of pci_set_power_state()
| * | PCI/PM: Expand description of pci_set_power_state()Piotr Gregor2017-08-03
| |/ | | | | | | | | | | | | | | | | | | Add two reasons for returning 0 value to the description of pci_set_power_state() to include the cases when: - the transition is to D1 or D2 but D1 and D2 are not supported - the transition is to D3 but D3 is not supported Signed-off-by: Piotr Gregor <piotrgregor@rsyncme.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'pci/msi' into nextBjorn Helgaas2017-09-07
|\ \ | | | | | | | | | | | | * pci/msi: PCI/MSI: Assume MSIs use real Requester ID, not an alias
| * | PCI/MSI: Assume MSIs use real Requester ID, not an aliasRobin Murphy2017-08-14
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, we handle all DMA aliases equally when calculating MSI requester IDs for the generic infrastructure. This turns out to be the wrong thing to do in the face of pure DMA quirks like those of Marvell SATA cards, where in the usual case the last thing seen in the alias walk is the DMA phantom function: we end up configuring the MSI doorbell to expect that alias, then find we have no interrupts since the MSI writes still come from the 'real' RID, thus get filtered out and ignored. Improve the alias walk to only account for the topological aliases that matter, based on the logic from the Intel IRQ remapping code. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
* | Merge branch 'pci/misc' into nextBjorn Helgaas2017-09-07
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/misc: PCI: Fix PCIe capability sizes PCI: Convert to using %pOF instead of full_name() PCI: Constify endpoint pci_epf_type device_type PCI: Constify bin_attribute structures PCI: Constify hotplug pci_device_id structures PCI: Constify hotplug attribute_group structures PCI: Constify label attribute_group structures PCI: Constify sysfs attribute_group structures
| * | PCI: Fix PCIe capability sizesAlex Williamson2017-08-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 defines the size of the PCIe capability structure for v1 devices with link, but we also have a need in the vfio code for sizing the capability for devices without link, such as Root Complex Integrated Endpoints. Create a separate define for this ending the structure before the link fields. Additionally, this reveals that PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 is currently incorrect, ending the capability length before the v2 link fields. Rename this to specify an RC Integrated Endpoint (no link) capability length and move PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 to include the link fields as we have for the v1 version. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> [bhelgaas: add "_" in "PCI_CAP_EXP_RC ENDPOINT_SIZEOF_V2 44"] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Eric Auger <eric.auger@redhat.com>
| * | PCI: Convert to using %pOF instead of full_name()Rob Herring2017-08-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have a custom printf format specifier, convert users of full_name() to use %pOF instead. This is preparation for removing storing of the full path string for each node. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Tyrel Datwyler <tyreld@linux.vnet.ibm.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Michael Ellerman <mpe@ellerman.id.au>
| * | PCI: Constify endpoint pci_epf_type device_typeBhumika Goyal2017-08-24
| | | | | | | | | | | | | | | | | | | | | Make this const as it is only stored in the type field of a device structure, which is const. Done using Coccinelle. Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Constify bin_attribute structuresBhumika Goyal2017-08-10
| | | | | | | | | | | | | | | | | | | | | | | | Add const to bin_attribute structures as they are only passed to the functions sysfs_{remove/create}_bin_file. The corresponding arguments are of type const, so declare the structures to be const. Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Constify hotplug pci_device_id structuresArvind Yadav2017-08-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | pci_device_id are not supposed to change at runtime. All functions working with pci_device_id provided by <linux/pci.h> work with const pci_device_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> [bhelgaas: squash shpchp, ibmphp, bmphp_ebda, cpcihp_zt5550, cpqphp] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Constify hotplug attribute_group structuresArvind Yadav2017-08-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | attribute_groups are not supposed to change at runtime. All functions working with attribute_groups provided by <linux/sysfs.h> work with const attribute_group. So mark the non-const structs as const. File size before: text data bss dec hex filename 418 160 8 586 24a drivers/pci/hotplug/rpadlpar_sysfs.o File size After adding 'const': text data bss dec hex filename 482 96 8 586 232 drivers/pci/hotplug/rpadlpar_sysfs.o Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Tyrel Datwyler <tyreld@linux.vnet.ibm.com>
| * | PCI: Constify label attribute_group structuresArvind Yadav2017-08-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | attribute_groups are not supposed to change at runtime. All functions working with attribute_groups provided by <linux/sysfs.h> work with const attribute_group. So mark the non-const structs as const. File size before: text data bss dec hex filename 930 320 0 1250 4e2 drivers/pci/pci-label.o File size After adding 'const': text data bss dec hex filename 1058 192 0 1250 4ca drivers/pci/pci-label.o Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Constify sysfs attribute_group structuresArvind Yadav2017-08-10
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | attribute_groups are not supposed to change at runtime. All functions working with attribute_groups provided by <linux/sysfs.h> work with const attribute_group. So mark the non-const structs as const. File size before: text data bss dec hex filename 8480 2024 4 10508 290c drivers/pci/pci-sysfs.o File size After adding 'const': text data bss dec hex filename 8736 1768 4 10508 290c drivers/pci/pci-sysfs.o Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'pci/irq-fixups' into nextBjorn Helgaas2017-09-07
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/irq-fixups: PCI: Inline and remove pcibios_update_irq() PCI: Remove unused pci_fixup_irqs() function sparc/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooks unicore32/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooks tile/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooks MIPS: PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooks m68k/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooks alpha/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooks sh/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooks sh/PCI: Remove __init optimisations from IRQ mapping functions/data MIPS: PCI: Fix pcibios_scan_bus() NULL check code path
| * | PCI: Inline and remove pcibios_update_irq()Bjorn Helgaas2017-08-10
| | | | | | | | | | | | | | | | | | | | | pcibios_update_irq() was a weak function with only one trivial implementation. Inline it and remove the weak function. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Remove unused pci_fixup_irqs() functionMatthew Minter2017-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now we have removed all callers of pci_fixup_irqs() and migrated everything to pci_assign_irq(), delete the pci_fixup_irqs() function completely. Signed-off-by: Matthew Minter <matt@masarand.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | sparc/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooksLorenzo Pieralisi2017-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pci_fixup_irqs() function allocates IRQs for all PCI devices present in a system; those PCI devices possibly belong to different PCI bus trees (and possibly rooted at different host bridges) and may well be enabled (ie probed and bound to a driver) by the time pci_fixup_irqs() is called when probing a given host bridge driver. Furthermore, current kernel code relying on pci_fixup_irqs() to assign legacy PCI IRQs to devices does not work at all for hotplugged devices in that the code carrying out the IRQ fixup is called at host bridge driver probe time, which just cannot take into account devices hotplugged after the system has booted. The introduction of map/swizzle function hooks in struct pci_host_bridge allows us to define per-bridge map/swizzle functions that can be used at device probe time in PCI core code to allocate IRQs for a given device (through pci_assign_irq()). Convert PCI host bridge initialization code to the pci_scan_root_bus_bridge() API (that allows to pass a struct pci_host_bridge with initialized map/swizzle pointers) and remove the pci_fixup_irqs() call from arch code. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: "David S. Miller" <davem@davemloft.net>
| * | unicore32/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooksLorenzo Pieralisi2017-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pci_fixup_irqs() function allocates IRQs for all PCI devices present in a system; those PCI devices possibly belong to different PCI bus trees (and possibly rooted at different host bridges) and may well be enabled (ie probed and bound to a driver) by the time pci_fixup_irqs() is called when probing a given host bridge driver. Furthermore, current kernel code relying on pci_fixup_irqs() to assign legacy PCI IRQs to devices does not work at all for hotplugged devices in that the code carrying out the IRQ fixup is called at host bridge driver probe time, which just cannot take into account devices hotplugged after the system has booted. The introduction of map/swizzle function hooks in struct pci_host_bridge allows us to define per-bridge map/swizzle functions that can be used at device probe time in PCI core code to allocate IRQs for a given device (through pci_assign_irq()). Convert PCI host bridge initialization code to the pci_scan_root_bus_bridge() API (that allows to pass a struct pci_host_bridge with initialized map/swizzle pointers) and remove the pci_fixup_irqs() call from arch code. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
| * | tile/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooksLorenzo Pieralisi2017-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pci_fixup_irqs() function allocates IRQs for all PCI devices present in a system; those PCI devices possibly belong to different PCI bus trees (and possibly rooted at different host bridges) and may well be enabled (ie probed and bound to a driver) by the time pci_fixup_irqs() is called when probing a given host bridge driver. Furthermore, current kernel code relying on pci_fixup_irqs() to assign legacy PCI IRQs to devices does not work at all for hotplugged devices in that the code carrying out the IRQ fixup is called at host bridge driver probe time, which just cannot take into account devices hotplugged after the system has booted. The introduction of map/swizzle function hooks in struct pci_host_bridge allows us to define per-bridge map/swizzle functions that can be used at device probe time in PCI core code to allocate IRQs for a given device (through pci_assign_irq()). Convert PCI host bridge initialization code to the pci_scan_root_bus_bridge() API (that allows to pass a struct pci_host_bridge with initializedmap/swizzle pointers) and remove the pci_fixup_irqs() call from arch code. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Metcalf <cmetcalf@mellanox.com>
| * | MIPS: PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooksLorenzo Pieralisi2017-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pci_fixup_irqs() function allocates IRQs for all PCI devices present in a system; those PCI devices possibly belong to different PCI bus trees (and possibly rooted at different host bridges) and may well be enabled (ie probed and bound to a driver) by the time pci_fixup_irqs() is called when probing a given host bridge driver. Furthermore, current kernel code relying on pci_fixup_irqs() to assign legacy PCI IRQs to devices does not work at all for hotplugged devices in that the code carrying out the IRQ fixup is called at host bridge driver probe time, which just cannot take into account devices hotplugged after the system has booted. The introduction of map/swizzle function hooks in struct pci_host_bridge allows us to define per-bridge map/swizzle functions, that can be used at device probe time in PCI core code to allocate IRQs for a given device (through pci_assign_irq()). Convert PCI host bridge initialization code to the pci_scan_root_bus_bridge() API (that allows to pass a struct pci_host_bridge with initialized map/swizzle pointers) and remove the pci_fixup_irqs() call from arch code. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com>
| * | m68k/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooksLorenzo Pieralisi2017-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pci_fixup_irqs() function allocates IRQs for all PCI devices present in a system; those PCI devices possibly belong to different PCI bus trees (and possibly rooted at different host bridges) and may well be enabled (ie probed and bound to a driver) by the time pci_fixup_irqs() is called when probing a given host bridge driver. Furthermore, current kernel code relying on pci_fixup_irqs() to assign legacy PCI IRQs to devices does not work at all for hotplugged devices in that the code carrying out the IRQ fixup is called at host bridge driver probe time, which just cannot take into account devices hotplugged after the system has booted. The introduction of map/swizzle function hooks in struct pci_host_bridge allows us to define per-bridge map/swizzle functions that can be used at device probe time in PCI core code to allocate IRQs for a given device (through pci_assign_irq()). Convert PCI host bridge initialization code to the pci_scan_root_bus_bridge() API (that allows to pass a struct pci_host_bridge with initialized map/swizzle pointers) and remove the pci_fixup_irqs() call from arch code. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Geert Uytterhoeven <geert@linux-m68k.org>
| * | alpha/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooksLorenzo Pieralisi2017-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pci_fixup_irqs() function allocates IRQs for all PCI devices present in a system; those PCI devices possibly belong to different PCI bus trees (and possibly rooted at different host bridges) and may well be enabled (ie probed and bound to a driver) by the time pci_fixup_irqs() is called when probing a given host bridge driver. Furthermore, current kernel code relying on pci_fixup_irqs() to assign legacy PCI IRQs to devices does not work at all for hotplugged devices in that the code carrying out the IRQ fixup is called at host bridge driver probe time, which just cannot take into account devices hotplugged after the system has booted. The introduction of map/swizzle function hooks in struct pci_host_bridge allows us to define per-bridge map/swizzle functions that can be used at device probe time in PCI core code to allocate IRQs for a given device (through pci_assign_irq()). Convert PCI host bridge initialization code to the pci_scan_root_bus_bridge() API (that allows to pass a struct pci_host_bridge with initialized map/swizzle pointers) and remove the pci_fixup_irqs() call from arch code. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
| * | sh/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooksLorenzo Pieralisi2017-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pci_fixup_irqs() function allocates IRQs for all PCI devices present in a system; those PCI devices possibly belong to different PCI bus trees (and possibly rooted at different host bridges) and may well be enabled (ie probed and bound to a driver) by the time pci_fixup_irqs() is called when probing a given host bridge driver. Furthermore, current kernel code relying on pci_fixup_irqs() to assign legacy PCI IRQs to devices does not work at all for hotplugged devices in that the code carrying out the IRQ fixup is called at host bridge driver probe time, which just cannot take into account devices hotplugged after the system has booted. The introduction of map/swizzle function hooks in struct pci_host_bridge allows us to define per-bridge map/swizzle functions that can be used at device probe time in PCI core code to allocate IRQs for a given device (through pci_assign_irq()). Convert PCI host bridge initialization code to the pci_scan_root_bus_bridge() API (that allows to pass a struct pci_host_bridge with initialized map/swizzle pointers) and remove the pci_fixup_irqs() call from arch code. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Rich Felker <dalias@libc.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
| * | sh/PCI: Remove __init optimisations from IRQ mapping functions/dataMatthew Minter2017-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently many IRQ mapping functions and data structures use the __init and __initdata optimisations. These result in the relevant functions being innaccessible after boot time. However for deferred IRQ assignment it is important to have access to these functions at PCI device enable time. Therefore, remove the optimisation from the relevant data structures and functions to prepare for deferred IRQ assignment. Signed-off-by: Matthew Minter <matt@masarand.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Rich Felker <dalias@libc.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
| * | MIPS: PCI: Fix pcibios_scan_bus() NULL check code pathLorenzo Pieralisi2017-07-31
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | If pci_scan_root_bus() fails (ie returns NULL) pcibios_scan_bus() must return immediately since the struct pci_bus pointer it returns is not valid and cannot be used. Move code checking the pci_scan_root_bus() return value to reinstate proper pcibios_scanbus() error path behaviour. Fixes: 88555b481958 ("MIPS: PCI: Support for CONFIG_PCI_DOMAINS_GENERIC") Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com>
* | Merge branch 'pci/hotplug' into nextBjorn Helgaas2017-09-07
|\ \ | | | | | | | | | | | | | | | * pci/hotplug: PCI: pciehp: Report power fault only once until we clear it PCI: shpchp: Enable bridge bus mastering if MSI is enabled
| * | PCI: pciehp: Report power fault only once until we clear itKeith Busch2017-08-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a power fault occurs, the power controller sets Power Fault Detected in the Slot Status register, and pciehp_isr() queues an INT_POWER_FAULT event to handle it. It also clears Power Fault Detected, but since nothing has yet changed to correct the power fault, the power controller will likely set it again immediately, which may cause an infinite loop when pcie_isr() rechecks Slot Status. Fix that by masking off Power Fault Detected from new events if the driver hasn't seen the power fault clear from the previous handling attempt. Fixes: fad214b0aa72 ("PCI: pciehp: Process all hotplug events before looking for new ones") Signed-off-by: Keith Busch <keith.busch@intel.com> [bhelgaas: changelog, pull test out and add comment] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Mayurkumar Patel <mayurkumar.patel@intel.com> Cc: stable@vger.kernel.org # 4.9+
| * | PCI: shpchp: Enable bridge bus mastering if MSI is enabledAleksandr Bezzubikov2017-08-02
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | An SHPC may generate MSIs to notify software about slot or controller events (SHPC spec r1.0, sec 4.7). A PCI device can only generate an MSI if it has bus mastering enabled. Enable bus mastering if the bridge contains an SHPC that uses MSI for event notifications. Signed-off-by: Aleksandr Bezzubikov <zuban32s@gmail.com> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Cc: stable@vger.kernel.org
* | Merge branch 'pci/enumeration' into nextBjorn Helgaas2017-09-07
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/enumeration: PCI: Warn periodically while waiting for non-CRS ("device ready") status PCI: Wait up to 60 seconds for device to become ready after FLR PCI: Factor out pci_bus_wait_crs() PCI: Add pci_bus_crs_vendor_id() to detect CRS response data PCI: Always check for non-CRS response before timeout PCI: Avoid race while enabling upstream bridges PCI: Mark Broadcom HT2100 Root Port Extended Tags as broken
| * | PCI: Warn periodically while waiting for non-CRS ("device ready") statusSinan Kaya2017-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a print statement in pci_bus_wait_crs() so that user observes the progress of device polling instead of silently waiting for timeout to be reached. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> [bhelgaas: check for timeout first so we don't print "waiting, giving up", always print time we've slept (not the actual timeout, print a "ready" message if we've printed a "waiting" message] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Wait up to 60 seconds for device to become ready after FLRSinan Kaya2017-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sporadic reset issues have been observed with an Intel 750 NVMe drive while assigning the physical function to the guest machine. The sequence of events observed is as follows: - perform a Function Level Reset (FLR) - sleep up to 1000ms total - read ~0 from PCI_COMMAND (CRS completion for config read) - warn that the device didn't return from FLR - touch the device before it's ready - device drops config writes when we restore register settings (there's no mechanism for software to learn about CRS completions for writes) - incomplete register restore leaves device in inconsistent state - device probe fails because device is in inconsistent state After reset, an endpoint may respond to config requests with Configuration Request Retry Status (CRS) to indicate that it is not ready to accept new requests. See PCIe r3.1, sec 2.3.1 and 6.6.2. Increase the timeout value from 1 second to 60 seconds to cover the period where device responds with CRS and also report polling progress. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> [bhelgaas: include the mandatory 100ms in the delays we print] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Factor out pci_bus_wait_crs()Sinan Kaya2017-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Configuration Request Retry Status (CRS) was previously hidden inside pci_bus_read_dev_vendor_id(). We want to add support for CRS in other situations, such as waiting for a device to become ready after a Function Level Reset. Move CRS handling into pci_bus_wait_crs() so it can be called from other places. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> [bhelgaas: pass pointer, not value, to pci_bus_wait_crs() so caller gets correct Vendor ID] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Add pci_bus_crs_vendor_id() to detect CRS response dataSinan Kaya2017-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pci_bus_crs_vendor_id() to determine whether data returned for a config read of the Vendor ID indicates a Configuration Request Retry Status (CRS) response. Per PCIe r3.1, sec 2.3.2, this data is only returned if: - CRS Software Visibility is enabled, - a config read includes both bytes of the Vendor ID, and - the read receives a CRS completion Signed-off-by: Sinan Kaya <okaya@codeaurora.org> [bhelgaas: changelog, change name to pci_bus_crs_vendor_id(), make static in probe.c, use it in pci_bus_read_dev_vendor_id()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Always check for non-CRS response before timeoutBjorn Helgaas2017-08-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While waiting for a device to become ready (i.e., to return a non-CRS completion to a read of its Vendor ID), if we got a valid response to the very last read before timing out, we printed a warning and gave up on the device even though it was actually ready. For a typical 60s timeout, we wait about 65s (it's not exact because of the exponential backoff), but we treated devices that became ready between 33s and 65s as though they failed. Move the Device ID read later so we check whether the device is ready before checking for a timeout. Thanks to Sinan Kaya <okaya@codeaurora.org>, reorder reads so we always check device presence after sleep, since it's pointless to sleep unless we recheck afterwards. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Avoid race while enabling upstream bridgesSrinath Mannam2017-08-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we enable a device, we first enable any upstream bridges. If a bridge has multiple downstream devices and we enable them simultaneously, the race to enable the upstream bridge may cause problems. Consider this hierarchy: bridge A --+-- device B +-- device C If drivers for B and C call pci_enable_device() simultaneously, both will attempt to enable A, which involves setting PCI_COMMAND_MASTER via pci_set_master() and PCI_COMMAND_MEMORY via pci_enable_resources(). In the following sequence, B's update to set A's PCI_COMMAND_MEMORY is lost, and neither B nor C will work correctly: B C pci_set_master(A) cmd = read(A, PCI_COMMAND) cmd |= PCI_COMMAND_MASTER pci_set_master(A) cmd = read(A, PCI_COMMAND) cmd |= PCI_COMMAND_MASTER write(A, PCI_COMMAND, cmd) pci_enable_device(A) pci_enable_resources(A) cmd = read(A, PCI_COMMAND) cmd |= PCI_COMMAND_MEMORY write(A, PCI_COMMAND, cmd) write(A, PCI_COMMAND, cmd) Avoid this race by holding a new pci_bridge_mutex while enabling a bridge. This ensures that both PCI_COMMAND_MASTER and PCI_COMMAND_MEMORY will be updated before another thread can start enabling the bridge. Note that although pci_enable_bridge() is recursive, it enables any upstream bridges *before* acquiring the mutex. When it acquires the mutex and calls pci_set_master() and pci_enable_device(), any upstream bridges have already been enabled so pci_enable_device() will not deadlock by calling pci_enable_bridge() again. Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> [bhelgaas: changelog, comment] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Mark Broadcom HT2100 Root Port Extended Tags as brokenSinan Kaya2017-07-31
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per PCIe r3.1, sec 2.2.6.2 and 7.8.4, a Requester may not use 8-bit Tags unless its Extended Tag Field Enable is set, but all Receivers/Completers must handle 8-bit Tags correctly regardless of their Extended Tag Field Enable. Some devices do not handle 8-bit Tags as Completers, so add a quirk for them. If we find such a device, we disable Extended Tags for the entire hierarchy to make peer-to-peer DMA possible. The Broadcom HT2100 seems to have issues with handling 8-bit tags. Mark it as broken. The pci_walk_bus() in the quirk handles devices we've enumerated in the past, and pci_configure_device() handles devices we enumerate in the future. Fixes: 60db3a4d8cc9 ("PCI: Enable PCIe Extended Tags if supported") Link: https://bugzilla.redhat.com/show_bug.cgi?id=1467674 Reported-and-tested-by: Wim ten Have <wim.ten.have@oracle.com> Signed-off-by: Sinan Kaya <okaya@codeaurora.org> [bhelgaas: changelog, tweak messages, rename bit and quirk] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'pci/dpc' into nextBjorn Helgaas2017-09-07
|\ \ | | | | | | | | | | | | | | | * pci/dpc: PCI/DPC: Add local struct device pointers PCI/DPC: Add eDPC support
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