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* Merge tag 'pinctrl-v3.20-1' of ↵Linus Torvalds2015-02-11
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pincontrol updates from Linus Walleij: :This is the bulk of pin control changes for the v3.20 cycle: Framework changes and enhancements: - Passing -DDEBUG recursively to subdir drivers so we get debug messages properly turned on. - Infer map type from DT property in the groups parsing code in the generic pinconfig code. - Support for custom parameter passing in generic pin config. This is used when you are using the generic pin config, but want to add a few custom properties that no other driver will use. New drivers: - Driver for the Xilinx Zynq - Driver for the AmLogic Meson SoCs New features in drivers: - Sleep support (suspend/resume) for the Cherryview driver - mvebeu a38x can now mux a UART on pins MPP19 and MPP20 - Migrated the qualcomm driver to generic pin config handling of extended config options in the core code. - Support BUS1 and AUDIO in the Exynos pin controller. - Add some missing functions in the sun6i driver. - Add support for the A31S variant in the sun6i driver. - EMEv2 support in the Renesas PFC driver. - Add support for Qualcomm MSM8916 in the qcom driver. Deleted features - Drop support for the SiRF Marco that was never released to the market. - Drop SH7372 support as the support for this platform is removed from the kernel" * tag 'pinctrl-v3.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (40 commits) sh-pfc: emev2 - Fix mangled author name pinctrl: cherryview: Configure HiZ pins to be input when requested as GPIOs pinctrl: imx25: fix numbering for pins pinctrl: pinctrl-imx: don't use invalid value of conf_reg pinctrl: qcom: delete pin_config_get/set pinconf operations pinctrl: qcom: Add msm8916 pinctrl driver DT: pinctrl: Document Qualcomm MSM8916 pinctrl binding pinctrl: qcom: increase variable size for register offsets pinctrl: hide PCONFDUMP in #ifdef pinctrl: rockchip: Only mask interrupts; never disable pinctrl: zynq: Fix usb0 pins pinctrl: sh-pfc: sh7372: Remove DT binding documentation pinctrl: sh-pfc: sh7372: Remove PFC support sh-pfc: Add emev2 pinmux support sh-pfc: add macro to define pinmux without function pinctrl: add driver for Amlogic Meson SoCs staging: drivers: pinctrl: Fixed checkpatch.pl warnings pinctrl: exynos: Add AUDIO pin controller for exynos7 sh-pfc: r8a7790: add MLB+ pin group sh-pfc: r8a7791: add MLB+ pin group ...
| * sh-pfc: emev2 - Fix mangled author nameGeert Uytterhoeven2015-02-05
| | | | | | | | | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Fixes: 1e7d5d849cf4f0c5 ("sh-pfc: Add emev2 pinmux support") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: cherryview: Configure HiZ pins to be input when requested as GPIOsMika Westerberg2015-02-04
| | | | | | | | | | | | | | | | | | | | If the pin is in HiZ mode when it is requested as GPIO its value cannot be read (it always returns 0). In order to cope with the Linux GPIO subsystem where we do not have such state at all, turn the pin to be input instead. Reported-by: Jerome Blin <jerome.blin@intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: imx25: fix numbering for pinsUwe Kleine-König2015-02-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pin id for a given tuple listed in a fsl,pins property is calculated by dividing the first entry (which is also a register offset) by 4. As the first available register is at offset 0x8 and configures the pad MX25_PAD_A10 the right id for this pin is 2. All other pins are off by one, too. This patch drops the definition MX25_PAD_RESERVE1 (together with its only use) and decrements all following values by 1. Fixes: b4a87c9b966f ("pinctrl: pinctrl-imx: add imx25 pinctrl driver") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: pinctrl-imx: don't use invalid value of conf_regUwe Kleine-König2015-02-03
| | | | | | | | | | | | | | | | | | | | | | | | | | The right check for conf_reg to be invalid it testing against -1 not 0 as is done in the rest of the driver. This fixes an oops that can be triggered by: cat /sys/kernel/debug/pinctrl/43fac000.iomuxc/* Fixes: ae75ff814538 ("pinctrl: pinctrl-imx: add imx pinctrl core driver") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: delete pin_config_get/set pinconf operationsStanimir Varbanov2015-01-30
| | | | | | | | | | | | | | | | | | The .pin_config_get/set operation are not supported in qcom pinctrl driver. As the pinconf core is smart enough it doesn't complain about that. Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: Add msm8916 pinctrl driverJoonwoo Park2015-01-30
| | | | | | | | | | | | | | | | | | | | Add initial pinctrl driver to support pin configuration with pinctrl framework for msm8916. Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org> Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * DT: pinctrl: Document Qualcomm MSM8916 pinctrl bindingStanimir Varbanov2015-01-30
| | | | | | | | | | | | | | | | Adds devicetree binding documentation. Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: qcom: increase variable size for register offsetsJoonwoo Park2015-01-30
| | | | | | | | | | | | | | | | | | | | | | On newer TLMM hardware blocks the registers are spread and we need an offsets upper than 16 bits to address them. Increase the register offset variables to 32 bits size. Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org> Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: hide PCONFDUMP in #ifdefArnd Bergmann2015-01-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The zynq and qcom-spmi pinctrl drivers both use pin_config_item arrays to provide extra interfaces in debugfs. This structure and the PCONFDUMP macro are not defined if CONFIG_DEBUG_FS is turned off, so we get build errors like: pinctrl/qcom/pinctrl-spmi-gpio.c:139:37: error: array type has incomplete element type static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = { ^ pinctrl/qcom/pinctrl-spmi-gpio.c:140:2: error: implicit declaration of function 'PCONFDUMP' [-Werror=implicit-function-declaration] PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true), ^ pinctrl/qcom/pinctrl-spmi-gpio.c:139:37: warning: 'pmic_conf_items' defined but not used [-Wunused-variable] static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = { Lacking any better idea to solve this nicely, this patch uses #ifdef to hide the structures, just like the pinctrl core does. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * pinctrl: rockchip: Only mask interrupts; never disableDoug Anderson2015-01-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Rockchip GPIO interrupt controller totally throws away all status about an interrupt when you "disable" the interrupt. That has unfortunate consequences in the following situation: 1. An edge-triggered interrupt is enabled and should wake the system. 2. System suspend happens: interrupt is disabled and marked for wake. 3. rockchip_irq_suspend() reenables the interrupt so we can wake. 4. Interrupt happens when asleep. 5. rockchip_irq_resume() redisables the interrupt. 6. Disabling the interrupt throws away all status about it. 7. Normal system resume happens and we enable the interrupt again, since we threw away status about the interrupt we don't know it fired while suspended. Even worse: if we need both edges of the interrupt the logic to swap edges never runs. Note: even if we somehow can post the status about wakeup interrupts in rockchip_irq_resume() we would still have a window of losing any edges that came in while interrupts were disabled. If we use mask only then we don't need to worry. The GPIO Interrupt controller keeps track of pending interrupts that are enabled and just masked. There was no real strong reason to support the enable/disable functionality (other than that it seemed right), so let's go back to just supporting mask/unmask but actually map it to the real mask/unmask. This ends up with slightly different (and more correct) behavior than before (f2dd028 pinctrl: rockchip: Fix enable/disable/mask/unmask). Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * Merge tag 'v3.19-rc6' into develLinus Walleij2015-01-30
| |\ | | | | | | | | | Linux 3.19-rc6
| * | pinctrl: zynq: Fix usb0 pinsAndreas Färber2015-01-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix usb0 pin 19 -> 29 (matching ethernet1 pins and manual). Pin 19 is used for ethernet0 on the Parallella board. Fixes: add958cee967 ("pinctrl: Add driver for Zynq") Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sh-pfc: sh7372: Remove DT binding documentationMagnus Damm2015-01-29
| | | | | | | | | | | | | | | | | | | | | | | | Remove the DT compatible string entry for the now unsupported sh7372 SoC. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sh-pfc: sh7372: Remove PFC supportMagnus Damm2015-01-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove sh7372 PFC support as part of the sh7372 and Mackerel legacy code removal. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | sh-pfc: Add emev2 pinmux supportNiklas Söderlund2015-01-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add PFC support for the EMMA Mobile EV2 SoC including pin groups for on-chip devices. Signed-off-by: Niklas Söderlund <niso@kth.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | sh-pfc: add macro to define pinmux without functionNiklas Söderlund2015-01-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Used to define pinmux configurations where the pinmux function have no representation in the configuration registers but instead solely depends on a group selection. Signed-off-by: Niklas Söderlund <niso@kth.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: add driver for Amlogic Meson SoCsBeniamino Galvani2015-01-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a driver for the pinmux and GPIO controller available in Amlogic Meson SoCs. It currently supports only Meson8, however the common code should be generic enough to work also for other SoCs after having defined the proper set of functions and groups. GPIO interrupts are not supported at the moment due to lack of documentation. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | staging: drivers: pinctrl: Fixed checkpatch.pl warningsAnjana Sasindran2015-01-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes two checkpatch.pl warnings WARNING: Error trailing white space WARNING: MIssing blank line after declaration Signed-off-by: Anjana Sasindran <anjanasasindran123@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: exynos: Add AUDIO pin controller for exynos7Padmavathi Venna2015-01-19
| | | | | | | | | | | | | | | | | | | | | | | | Audio IPs on Exynos7 require gpios available in AUDIO pin controller block. So adding the AUDIO pinctrl support. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | sh-pfc: r8a7790: add MLB+ pin groupSergei Shtylyov2015-01-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MLB+ 3-pin mode pin group to R8A7790 PFC driver. Based on original patch by Andrey Gusakov <andrey.gusakov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | sh-pfc: r8a7791: add MLB+ pin groupSergei Shtylyov2015-01-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MLB+ 3-pin mode pin group to R8A7791 PFC driver. Based on original patch by Andrey Gusakov <andrey.gusakov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | sh-pfc: r8a7791: fix typo in MLB_CLKSergei Shtylyov2015-01-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The R8A7791 manual sometimes calls the signal MLB_CLK and sometimes MLB_CK; the latter can only be encountered in the PFC section and is probably just a typo (this signal is always called MLB_CLK in the R8A7790 manual). Fix occurences of MLB_CK throughout the R8A7791 PFC driver. Based on original patch by Andrey Gusakov <andrey.gusakov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sirf: drop marco supportBarry Song2015-01-14
| | | | | | | | | | | | | | | | | | | | | marco chip has been dropped, clear its support. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: bcm281xx: Constify struct regmap_configKrzysztof Kozlowski2015-01-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | The regmap_config struct may be const because it is not modified by the driver and regmap_init() accepts pointer to const. Make also of_device_id array const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: dove: Constify struct regmap_config and of_device_idKrzysztof Kozlowski2015-01-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | The regmap_config struct may be const because it is not modified by the driver and regmap_init() accepts pointer to const. Make also of_device_id array const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sun6i: Add A31s pinctrl supportHans de Goede2015-01-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A31s is a stripped down version of the A31, as such it is missing some pins and some functions on some pins. The new pinctrl-sun6i-a31s.c this commit adds is a copy of pinctrl-sun6i-a31s.c with the missing pins and functions removed. Note there is no a31s specific version of pinctrl-sun6i-a31-r.c, as the prcm pins are identical between the A31 and the A31s. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: sun6i: Add some missing functionsHans de Goede2015-01-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | While working on pinctrl for the A31s, I noticed that function 4 of PA15 - PA18 was missing, add these. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: consumer: use correct retval for placeholder functionsWolfram Sang2015-01-14
| | | | | | | | | | | | | | | | | | | | | These functions are supposed to return an error pointer, not NULL. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: exynos: Add BUS1 pin controller for exynos7Vivek Gautam2015-01-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB and Power regulator on Exynos7 require gpios available in BUS1 pin controller block. So adding the BUS1 pinctrl support. Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | Documentation: dt-bindings: Add aliases information for Exynos7 pin controllersVivek Gautam2015-01-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | Adding list of aliases for supported Exynos7 pin controller blocks. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: pinconf-generic: loose DT dependenceLinus Walleij2015-01-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New pin controllers such as ACPI-based may also have custom properties to parse, and should be able to use generic pin config. Let's make the code compile on !OF systems and rename members a bit to underscore it is custom parameters and not necessarily DT parameters. This fixes a build regression for x86_64 on the zeroday kernel builds. Reported-by: kbuild test robot <fengguang.wu@intel.com> Reviewed-and-tested-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: qcom-spmi-gpio: Migrate to pinconf-genericSoren Brinkmann2015-01-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of the driver caring about implementation details like device tree, just provide information about driver specific pinconf parameters to pinconf-generic which takes care of parsing the DT. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Tested-by: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: Add driver for ZynqSoren Brinkmann2015-01-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a pin-control driver for Zynq. Changes since v2: - driver-specific DT properties are passed to the core in two arrays, one for the actual DT parsing one for the debugfs representation. Issue a compiler warning when the number of entries is not the same for both arrays. Changes since v1: - fix EMIO_SD1_CD pin name - add USB to pinmux options changes since RFCv2: - let Zynq select PINCTRL_ZYNQ. Boot hangs when pinctrl information is present in DT but no driver available. - add #defines to get rid of magical constants - add commas at end of initializers - separate changes in mach-zynq in separate patch - add driver specific io-standard DT property - refactored pinconf set function to not require arguments for argument-less properties - squash other patches in - support for IO-standard property - support for low-power mode property - migration to pinconf_generic_dt_node_to_map_all() - use newly created infrastructure to add pass driver-specific DT params to pinconf-generic changes since RFC: - use syscon/regmap to access registers in SLCR space - rebase to 3.18: rename enable -> set_mux - add kernel-doc - support pinconf - supported attributes - pin-bias: pull up, tristate, disable - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display argument Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Tested-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: zynq: Document DT bindingSoren Brinkmann2015-01-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add documentation for the devicetree binding for the Zynq pincontroller. Changes since v1: - fix typo - add USB related documentation - remove 'pinctrl-' prefix for pinctrl sub-nodes - update documentation to enforce strict separation of pinmux and pinconf nodes - update example accordingly Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Tested-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: pinconf-generic: Allow driver to specify DT paramsSoren Brinkmann2015-01-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Additionally to the generic DT parameters, allow drivers to provide driver-specific DT parameters to be used with the generic parser infrastructure. To achieve this 'struct pinctrl_desc' is extended to pass custom pinconf option to the core. In order to pass this kind of information, the related data structures - 'struct pinconf_generic_dt_params', 'pin_config_item' - are moved from pinconf internals to the pinconf-generic header. Additionally pinconfg-generic is refactored to not only iterate over the generic pinconf parameters but also take the parameters into account that are provided through the driver's 'struct pinctrl_desc'. In particular 'pinconf_generic_parse_dt_config()' and 'pinconf_generic_dump' helpers are split into two parts each. In order to have a more generic helper that can be used to process the generic parameters as well as the driver-specific ones. v2: - fix typo - add missing documentation for @conf_items member in struct - rebase to pinctrl/devel: conflict in abx500 - rename _pinconf_generic_dump() to pinconf_generic_dump_one() - removed '_' from _parse_dt_cfg() - removed BUG_ONs, error condition is handled in if statements - removed pinconf_generic_dump_group() & pinconf_generic_dump_pin helpers - fixed up corresponding call sites - renamed pinconf_generic_dump() to pinconf_generic_dump_pins() - added kernel-doc to pinconf_generic_dump_pins() - add kernel-doc - more verbose commit message Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Tested-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: pinconf-generic: Infer map type from DT propertySoren Brinkmann2015-01-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the new 'groups' property, the DT parser can infer the map type from the fact whether 'pins' or 'groups' is used to specify the pin group to work on. To maintain backwards compatibitliy with current usage of the DT binding, this is only done when PIN_MAP_TYPE_INVALID is passed to the parsing function as type. Also, a new helper 'pinconf_generic_dt_node_to_map_all()' is introduced, which can be used by drivers as generic callback for dt_node_to_map() to leverage the new feature. Changes since v2: - rename dt_pin_specifier to subnode_target_type - add additional comment in header file explaining passing an invalid map type - mention map_all() helper in commit message Changes since RFC v2: - none Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Tested-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: pass -DDEBUG in subdirsLinus Walleij2015-01-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When drivers are compiled in subdirectories the -DDEBUG flag need to be passed in the individual Makefiles. Reported-by: Mika Westerberg <mika.westerberg@linux.intel.com> Suggested-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: nomadik:fix up device tree bindingsLinus Walleij2015-01-10
| | | | | | | | | | | | | | | | | | | | | | | | After the Nomadik pin controller was force migrated to generic pin control bindings, some leftovers in the documentation need to be cleaned up. The code and device trees are already migrated. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: mvebu: a38x: Add UART1 muxing optionsMaxime Ripard2015-01-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPP19 and MMP20 pins also have the ability to be muxed to the uart1 function. Add this case to the pinctrl driver. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: intel: drop owner assignment from platform_driversWolfram Sang2015-01-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | This platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | pinctrl: cherryview: Save and restore pin configs over system sleepMika Westerberg2015-01-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before resuming from system sleep BIOS restores its view of pin configuration. If we have configured some pins differently from that, for instance some driver requested a pin as a GPIO but it was not in GPIO mode originally, our view of the pin configuration will not match the hardware state anymore. This patch saves the pin configuration and interrupt mask registers on suspend and restores them on exit. This should make sure that the previously configured state is still in effect. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | Merge tag 'gpio-v3.20-1' of ↵Linus Torvalds2015-02-11
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull GPIO changes from Linus Walleij: "This is the GPIO bulk changes for the v3.20 series: GPIOLIB core changes: - Create and use of_mm_gpiochip_remove() for removing memory-mapped OF GPIO chips - GPIO MMIO library suppports bgpio_set_multiple for switching several lines at once, a feature merged in the last cycle. New drivers: - New driver for the APM X-gene standby GPIO controller - New driver for the Fujitsu MB86S7x GPIO controller Cleanups: - Moved rcar driver to use gpiolib irqchip - Moxart converted to the GPIO MMIO library - GE driver converted to GPIO MMIO library - Move sx150x to irqdomain - Move max732x to irqdomain - Move vx855 to use managed resources - Move dwapb to use managed resources - Clean tc3589x from platform data - Clean stmpe driver to use device tree only probe New subtypes: - sx1506 support in the sx150x driver - Quark 1000 SoC support in the SCH driver - Support X86 in the Xilinx driver - Support PXA1928 in the PXA driver Extended drivers: - max732x supports device tree probe - sx150x supports device tree probe Various minor cleanups and bug fixes" * tag 'gpio-v3.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (61 commits) gpio: kconfig: replace PPC_OF with PPC gpio: pxa: add PXA1928 gpio type support dt/bindings: gpio: add compatible string for marvell,pxa1928-gpio gpio: pxa: remove mach IRQ includes gpio: max732x: use an inline function for container cast gpio: use sizeof() instead of hardcoded values gpio: max732x: add set_multiple function gpio: sch: Consolidate similar algorithms gpio: tz1090-pdc: Use resource_size to fix off-by-one resource size calculation gpio: ge: Convert to use devm_kstrdup gpio: correctly use const char * const gpio: sx150x: fixup OF support gpio: mpc8xxx: Use of_mm_gpiochip_remove gpio: Add Fujitsu MB86S7x GPIO driver gpio: mpc8xxx: Convert to platform device interface. gpio: zevio: Use of_mm_gpiochip_remove gpio: gpio-mm-lantiq: Use of_mm_gpiochip_remove gpio: gpio-mm-lantiq: Use of_property_read_u32 gpio: gpio-mm-lantiq: Do not replicate code gpio :gpio-mm-lantiq: Use devm_kzalloc ...
| * | | gpio: kconfig: replace PPC_OF with PPCKevin Hao2015-02-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PPC_OF is a ppc specific option which is used to mean that the firmware device tree access functions are available. Since all the ppc platforms have a device tree, it is aways set to 'y' for ppc. So it makes no sense to keep a such option in the current kernel. Replace it with PPC. Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | gpio: pxa: add PXA1928 gpio type supportRob Herring2015-02-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for PXA1928 GPIOs. The PXA1928 adds a 6th bank from previous generations. Signed-off-by: Jing Xiang <jxiang@marvell.com> Signed-off-by: Xiangzhan Meng <mengxzh@marvell.com> [robh: ported to 3.19 from vendor kernel] Signed-off-by: Rob Herring <robh@kernel.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Alexandre Courbot <gnurou@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | dt/bindings: gpio: add compatible string for marvell,pxa1928-gpioRob Herring2015-02-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new compatible string for PXA1928 GPIO controller. The IP block is same as prior chips with a 6th bank added. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | gpio: pxa: remove mach IRQ includesRob Herring2015-02-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation to enable ARCH_MMP on ARM64, the include of mach/irqs.h must be eliminated. mach/irqs.h was being included for IRQ_GPIO{0,1}, but these IRQs are always passed in as resources now. We can use irq0 and irq1 and get rid of IRQ_GPIOx. Get rid of the ifdef in the process as it is no longer needed. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Alexandre Courbot <gnurou@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | gpio: max732x: use an inline function for container castLinus Walleij2015-02-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cast the struct gpio_chip into a max732x_chip using an inline macro and move the assignment to the variable declaration to save lines and simplify things. Cc: Semen Protsenko <semen.protsenko@globallogic.com> Acked-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | gpio: use sizeof() instead of hardcoded valuesOlliver Schinagl2015-01-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gpiolib uses a fixed string for the suffixes and defines it at 32 bytes. Later in the code snprintf is used with this fixed value of 32. Using sizeof() is safer in case the size for the suffixes is ever changed. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | gpio: max732x: add set_multiple functionMans Rullgard2015-01-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a set_multiple function to the MAX732x GPIO driver, allowing for performance gains when using gpiod_set_array(). Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-16 01:14:49 -0400