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* Merge branch 'next' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds2012-10-09
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull slave-dmaengine updates from Vinod Koul: "This time we have Andy updates on dw_dmac which is attempting to make this IP block available as PCI and platform device though not fully complete this time. We also have TI EDMA moving the dma driver to use dmaengine APIs, also have a new driver for mmp-tdma, along with bunch of small updates. Now for your excitement the merge is little unusual here, while merging the auto merge on linux-next picks wrong choice for pl330 (drivers/dma/pl330.c) and this causes build failure. The correct resolution is in linux-next. (DMA: PL330: Fix build error) I didn't back merge your tree this time as you are better than me so no point in doing that for me :)" Fixed the pl330 conflict as in linux-next, along with trivial header file conflicts due to changed includes. * 'next' of git://git.infradead.org/users/vkoul/slave-dma: (29 commits) dma: tegra: fix interrupt name issue with apb dma. dw_dmac: fix a regression in dwc_prep_dma_memcpy dw_dmac: introduce software emulation of LLP transfers dw_dmac: autoconfigure data_width or get it via platform data dw_dmac: autoconfigure block_size or use platform data dw_dmac: get number of channels from hardware if possible dw_dmac: fill optional encoded parameters in register structure dw_dmac: mark dwc_dump_chan_regs as inline DMA: PL330: return ENOMEM instead of 0 from pl330_alloc_chan_resources DMA: PL330: Remove redundant runtime_suspend/resume functions DMA: PL330: Remove controller clock enable/disable dmaengine: use kmem_cache_zalloc instead of kmem_cache_alloc/memset DMA: PL330: Set the capability of pdm0 and pdm1 as DMA_PRIVATE ARM: EXYNOS: Set the capability of pdm0 and pdm1 as DMA_PRIVATE dma: tegra: use list_move_tail instead of list_del/list_add_tail mxs/dma: Enlarge the CCW descriptor area to 4 pages dw_dmac: utilize slave_id to pass request line dmaengine: mmp_tdma: add dt support dmaengine: mmp-pdma support spi: davici - make davinci select edma ...
| * dma: tegra: fix interrupt name issue with apb dma.Laxman Dewangan2012-10-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When watching the interrupts through /proc/interrupts, the name of the interrupts are blank or garbage. The reason is the pointer passed for devname during irq registration is stack and so it get changed after dma registration completes. Allocate the pointer as part of dma channel and pass this pointer as the devname for irq registration to avoid change of name. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reported-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * dw_dmac: fix a regression in dwc_prep_dma_memcpyAndy Shevchenko2012-10-02
| | | | | | | | | | | | | | | | Sometimes memory-to-memory test is failed, that's why we need to choose minimum data portion between source and destination limits together. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * dw_dmac: introduce software emulation of LLP transfersAndy Shevchenko2012-09-27
| | | | | | | | | | | | | | | | | | | | | | Some controllers have the reduced functionality where the LLP multi block transfers are not supported. This patch introduces a support of such controllers. In case of memory copy or scatter-gather lists it emulates LLP transfers via bunch of the regular single block ones. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * dw_dmac: autoconfigure data_width or get it via platform dataAndy Shevchenko2012-09-27
| | | | | | | | | | | | | | | | | | | | Not all of the controllers support the 64 bit data width. Make it configurable via platform data. The driver will try to get a value from the component parameters, otherwise it will use the platform data. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * dw_dmac: autoconfigure block_size or use platform dataAndy Shevchenko2012-09-27
| | | | | | | | | | | | | | | | | | | | The maximum block size is a configurable parameter for the chip. So, driver will try to get it from the encoded component parameters. Otherwise it will come from the platform data. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * dw_dmac: get number of channels from hardware if possibleAndy Shevchenko2012-09-27
| | | | | | | | | | | | | | | | | | | | In case the controller has the encoded parameters feature enabled the driver will use it to get the number of channels. In the future it will be used for the other important parameters as well. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * dw_dmac: fill optional encoded parameters in register structureAndy Shevchenko2012-09-27
| | | | | | | | | | | | | | | | | | | | There is a block of the registers that are optional. However, if enabled they contain useful information about the controller hardware configuration. We will use this piece of data to autoconfigure the driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * dw_dmac: mark dwc_dump_chan_regs as inlineAndy Shevchenko2012-09-27
| | | | | | | | | | | | Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * DMA: PL330: return ENOMEM instead of 0 from pl330_alloc_chan_resourcesInderpal Singh2012-09-17
| | | | | | | | | | | | | | | | | | | | Since 0 is not considered as error at dmaengine level, return ENOMEM from pl330_alloc_chan_resources in case of failure. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * DMA: PL330: Remove redundant runtime_suspend/resume functionsInderpal Singh2012-09-17
| | | | | | | | | | | | | | | | | | | | | | | | The driver's runtime_suspend/resume functions just disable/enable the clock which is already being managed at AMBA bus level runtime_suspend/resume functions. Hence, remove the driver's runtime_suspend/resume functions. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> Tested-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * DMA: PL330: Remove controller clock enable/disableInderpal Singh2012-09-17
| | | | | | | | | | | | | | | | | | | | The controller clock is being enabled/disabled in AMBA bus infrastructre in probe/remove functions. Hence, its not required at driver level probe/remove. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> Tested-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * dmaengine: use kmem_cache_zalloc instead of kmem_cache_alloc/memsetWei Yongjun2012-09-17
| | | | | | | | | | | | | | | | | | | | Using kmem_cache_zalloc() instead of kmem_cache_alloc() and memset(). spatch with a semantic match is used to found this problem. (http://coccinelle.lip6.fr/) Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * DMA: PL330: Set the capability of pdm0 and pdm1 as DMA_PRIVATETushar Behera2012-09-13
| | | | | | | | | | | | | | | | | | | | | | DMA clients pdma0 and pdma1 are internal to the SoC and are used only by dedicated peripherals. Since they cannot be used for generic purpose, their capability should be set as DMA_PRIVATE. CC: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * ARM: EXYNOS: Set the capability of pdm0 and pdm1 as DMA_PRIVATETushar Behera2012-09-13
| | | | | | | | | | | | | | | | | | | | | | DMA clients pdma0 and pdma1 are internal to the SoC and are used only by dedicated peripherals. Since they cannot be used for generic purpose, their capability should be set as DMA_PRIVATE. CC: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * dma: tegra: use list_move_tail instead of list_del/list_add_tailWei Yongjun2012-09-13
| | | | | | | | | | | | | | | | | | | | | | Using list_move_tail() instead of list_del() + list_add_tail(). spatch with a semantic match is used to found this problem. (http://coccinelle.lip6.fr/) Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * mxs/dma: Enlarge the CCW descriptor area to 4 pagesMarek Vasut2012-09-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of a large SPI flash, the amount of DMA descriptors available to the DMA driver is not large enough anymore. For example 8MB SPI flash now needs 129 descriptors to be transfered in one long read. There are currently 53 descriptors available in one PAGE_SIZE-big block. Enlarge the allocated descriptor area to four PAGE_SIZE blocks to fulfill such requirements. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dan Williams <djbw@fb.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Shawn Guo <shawn.guo@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * dw_dmac: utilize slave_id to pass request lineAndy Shevchenko2012-09-13
| | | | | | | | | | | | | | | | | | | | | | | | There is slave_id field in the generic slave config structure that is dedicated for the uniq slave number. In our case we have the request lines wired to the certain hardware. Therefore the number of the request line is uniq and could be used as slave_id. It allows us in some cases to drop out the usage of the custom slave config structure. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * dmaengine: mmp_tdma: add dt supportZhangfei Gao2012-09-13
| | | | | | | | | | | | Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * dmaengine: mmp-pdma supportZhangfei Gao2012-09-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. virtual channel vs. physical channel Virtual channel is managed by dmaengine Physical channel handling resource, such as irq Physical channel is alloced dynamically as descending priority, freed immediately when irq done. The availble highest priority physically channel will alwayes be alloced Issue pending list -> alloc highest dma physically channel available -> dma done -> free physically channel 2. list: running list & pending list submit: desc list -> pending list issue_pending_list: if (IDLE) pending list -> running list; free pending list (RUN) irq: free running list (IDLE) check pendlist -> pending list -> running list; free pending list (RUN) 3. irq: Each list generate one irq, calling callback One list may contain several desc chain, in such case, make sure only the last desc list generate irq. 4. async Submit will add desc chain to pending list, which can be multi-called If multi desc chain is submitted, only the last desc would generate irq -> call back If IDLE, issue_pending_list start pending_list, transforming pendlist to running list If RUN, irq will start pending list 5. test 5.1 pxa3xx_nand on pxa910 5.2 insmod dmatest.ko (threads_per_chan=y) By default drivers/dma/dmatest.c test every channel and test memcpy with 1 threads per channel Signed-off-by: Zhangfei Gao <zhangfei.gao@marvell.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * spi: davici - make davinci select edmaVinod Koul2012-08-31
| | | | | | | | | | Reported-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * spi: spi-davinci: convert to DMA engine APIMatt Porter2012-08-31
| | | | | | | | | | | | | | | | | | | | Removes use of the DaVinci EDMA private DMA API and replaces it with use of the DMA engine API. Signed-off-by: Matt Porter <mporter@ti.com> Tested-by: Tom Rini <trini@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * mmc: davinci_mmc: convert to DMA engine APIMatt Porter2012-08-31
| | | | | | | | | | | | | | | | | | | | Removes use of the DaVinci EDMA private DMA API and replaces it with use of the DMA engine API. Signed-off-by: Matt Porter <mporter@ti.com> Tested-by: Tom Rini <trini@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * dmaengine: add TI EDMA DMA engine driverMatt Porter2012-08-31
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a DMA engine driver for the TI EDMA controller. This driver is implemented as a wrapper around the existing DaVinci private DMA implementation. This approach allows for incremental conversion of each peripheral driver to the DMA engine API. The EDMA driver supports slave transfers but does not yet support cyclic transfers. Signed-off-by: Matt Porter <mporter@ti.com> Tested-by: Tom Rini <trini@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * ioat: Adding Ivy Bridge IOATDMA PCI device IDsDave Jiang2012-08-31
| | | | | | | | | | | | Signed-off-by: Dave Jiang <dave.jiang@intel.com> Acked-by: Dan Williams <djbw@db.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * dma/ste_dma40: Fixup clock usage during probeUlf Hansson2012-08-30
| | | | | | | | | | | | | | | | | | Fixup some errorhandling for clocks during probe and make sure to use clk_prepare as well as clk_enable. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * drivers/dma/amba-pl08x.c: fix error return codeJulia Lawall2012-08-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert a 0 error return code to a negative one, as returned elsewhere in the function. A simplified version of the semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ identifier ret; expression e,e1,e2,e3,e4,x; @@ ( if (\(ret != 0\|ret < 0\) || ...) { ... return ...; } | ret = 0 ) ... when != ret = e1 *x = \(kmalloc\|kzalloc\|kcalloc\|devm_kzalloc\|ioremap\|ioremap_nocache\|devm_ioremap\|devm_ioremap_nocache\)(...); ... when != x = e2 when != ret = e3 *if (x == NULL || ...) { ... when != ret = e4 * return ret; } // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * drivers/dma/sirf-dma.c: fix usage of devm functionsJulia Lawall2012-08-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix some problems with the use of devm_ functions. devm_kzalloc: devm_kfree is not needed devm_ioremap: iounmap should not be used, no free is needed devm_request_irq: the devm_free_irq is followed by irq_dispose_mapping. I don't know if it is safe to move the freeing of the irq in this case, so I have just un-devm'd this function, since the implicit freeing is never taken advantage of. In the original code failure of of_address_to_resource jumped to free_mem, but should have jumped to irq_dispose, since irq_of_parse_and_map has completed at this point. In the original code unmap_mem was after irq_dispose, but it should have been before, again since irq_of_parse_and_map has completed at this point. One of these problems was found using the following semantic match: (http://coccinelle.lip6.fr/) // <smpl> @@ expression x; @@ *x = devm_ioremap(...) ... iounmap(x); // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Acked-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| * Merge branch 'fixes_for-3.6' into nextVinod Koul2012-08-05
| |\
| * \ Merge branch 'for-3.7' into nextVinod Koul2012-08-05
| |\ \
| | * | dma: tegra: enable/disable dma clockLaxman Dewangan2012-07-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the DMA clock when allocating channel and disable clock when freeing channels. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
| | * | dw_dmac: use devm_* functions to simplify codeAndy Shevchenko2012-07-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use devm_kzalloc, devm_clk_get, devm_request_irq, and devm_request_and_ioremap to reduce the code and to simplify the error path. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Viresh Kumar <viresh.linux@gmail.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
* | | | Merge tag 'mmc-merge-for-3.7-rc1' of ↵Linus Torvalds2012-10-09
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc Pull MMC updates from Chris Ball: "Core: - Add DT properties for card detection (broken-cd, cd-gpios, non-removable) - Don't poll non-removable devices - Fixup/rework eMMC sleep mode/"power off notify" feature - Support eMMC background operations (BKOPS). To set the one-time programmable fuse that enables bkops on an eMMC that doesn't already have it set, you can use the "mmc bkops enable" command in: git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc-utils.git Drivers: - atmel-mci, dw_mmc, pxa-mci, dove, s3c, spear: Add device tree support - bfin_sdh: Add support for the controller in bf60x - dw_mmc: Support Samsung Exynos SoCs - eSDHC: Add ADMA support - sdhci: Support testing a cd-gpio (from slot-gpio) instead of presence bit - sdhci-pltfm: Support broken-cd DT property - tegra: Convert to only supporting DT (mach-tegra has gone DT-only)" * tag 'mmc-merge-for-3.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc: (67 commits) mmc: core: Fixup broken suspend and eMMC4.5 power off notify mmc: sdhci-spear: Add clk_{un}prepare() support mmc: sdhci-spear: add device tree bindings mmc: sdhci-s3c: Add clk_(enable/disable) in runtime suspend/resume mmc: core: Replace MMC_CAP2_BROKEN_VOLTAGE with test for fixed regulator mmc: sdhci-pxav3: Use sdhci_get_of_property for parsing DT quirks mmc: dt: Support "broken-cd" property in sdhci-pltfm mmc: sdhci-s3c: fix the wrong number of max bus clocks mmc: sh-mmcif: avoid oops on spurious interrupts mmc: sh-mmcif: properly handle MMC_WRITE_MULTIPLE_BLOCK completion IRQ mmc: sdhci-s3c: Fix crash on module insertion for second time mmc: sdhci-s3c: Enable only required bus clock mmc: Revert "mmc: dw_mmc: Add check for IDMAC configuration" mmc: mxcmmc: fix bug that may block a data transfer forever mmc: omap_hsmmc: Pass on the suspend failure to the PM core mmc: atmel-mci: AP700x PDC is not connected to MCI mmc: atmel-mci: DMA can be used with other controllers mmc: mmci: use clk_prepare_enable and clk_disable_unprepare mmc: sdhci-s3c: Add device tree support mmc: dw_mmc: add support for exynos specific implementation of dw-mshc ...
| * | | | mmc: core: Fixup broken suspend and eMMC4.5 power off notifyUlf Hansson2012-10-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes up the broken suspend sequence for eMMC with sleep support. Additionally it reworks the eMMC4.5 Power Off Notification feature so it fits together with the existing sleep feature. The CMD0 based re-initialization of the eMMC at resume is re-introduced to maintain compatiblity for devices using sleep. A host shall use MMC_CAP2_POWEROFF_NOTIFY to enable the Power Off Notification feature. We might be able to remove this cap later on, if we think that Power Off Notification always is preferred over sleep, even if the host is not able to cut the eMMC VCCQ power. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Saugata Das <saugata.das@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | | | mmc: sdhci-spear: Add clk_{un}prepare() supportViresh Kumar2012-10-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk_{un}prepare is mandatory for platforms using common clock framework. Since this driver is used by SPEAr platform, which supports common clock framework, add clk_{un}prepare() support for it. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | | | mmc: sdhci-spear: add device tree bindingsViresh Kumar2012-10-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds simple DT bindings for SDHCI SPEAr controller. It uses cd-gpios from common mmc bindings. This also fixes spear300-evb.dts with correct name for card detect binding. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | | | mmc: sdhci-s3c: Add clk_(enable/disable) in runtime suspend/resumeChander Kashyap2012-10-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Perform clock disable/enable in runtime suspend/resume. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | | | mmc: core: Replace MMC_CAP2_BROKEN_VOLTAGE with test for fixed regulatorChris Ball2012-10-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this patch, we were using MMC_CAP2_BROKEN_VOLTAGE as a way to avoid calling regulator_set_voltage() on a fixed regulator, but that's just duplicating information that already exists -- we should test whether the regulator is fixed directly, instead of via a capability. This patch implements that test. We can't reclaim the capability bit just yet, since there are still boards in arch/arm/ that reference it; those references can be removed now. Reported-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | | | mmc: sdhci-pxav3: Use sdhci_get_of_property for parsing DT quirksChris Ball2012-10-07
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Chris Ball <cjb@laptop.org>
| * | | | mmc: dt: Support "broken-cd" property in sdhci-pltfmChris Ball2012-10-07
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Chris Ball <cjb@laptop.org>
| * | | | mmc: sdhci-s3c: fix the wrong number of max bus clocksJaehoon Chung2012-10-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can use up to four bus-clocks; but on module remove, we didn't disable the fourth bus clock. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: stable <stable@vger.kernel.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | | | mmc: sh-mmcif: avoid oops on spurious interruptsGuennadi Liakhovetski2012-10-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some systems, e.g., kzm9g, MMCIF interfaces can produce spurious interrupts without any active request. To prevent the Oops, that results in such cases, don't dereference the mmc request pointer until we make sure, that we are indeed processing such a request. Reported-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Cc: stable <stable@vger.kernel.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | | | mmc: sh-mmcif: properly handle MMC_WRITE_MULTIPLE_BLOCK completion IRQGuennadi Liakhovetski2012-10-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upon completion of a MMC_WRITE_MULTIPLE_BLOCK command MMCIF issues an IRQ with the DTRANE bit set and often with one or several of CMD12 bits set. If those interrupts are not acknowledged, an additional interrupt can be produced and will be delivered later, possibly, when the transaction has already been completed. To prevent this from happening, CMD12 completion interrupt sources have to be cleared too upon reception of an DTRANE IRQ. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Tested-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | | | mmc: sdhci-s3c: Fix crash on module insertion for second timeChander Kashyap2012-10-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If sdhci-s3c driver is built as module, it gives following error if inserted again after removing. This was happening as pm_runtime_use_autosuspend() is called in sdhci_s3c_probe() function but in sdhci_s3c_remove() its complementary pm_runtime_dont_use_autosuspend() is not called. BUG: spinlock bad magic on CPU#1, insmod/955 lock: 0xee771368, .magic: 00000000, .owner: insmod/955, .owner_cpu: 1 [<c00147e0>] (unwind_backtrace+0x0/0xf8) from [<c0136b40>] (do_raw_spin_unlock+0xa4/0xe4) [<c0136b40>] (do_raw_spin_unlock+0xa4/0xe4) from [<c01be508>] (_raw_spin_unlock_irqrestore+0xc/0x38) [<c01be508>] (_raw_spin_unlock_irqrestore+0xc/0x38) from [<c01a9334>] (sdhci_runtime_suspend_host+0x54/0x80) [<c01a9334>] (sdhci_runtime_suspend_host+0x54/0x80) from [<bf0060a8>] (sdhci_s3c_runtime_suspend+0x14/0x38 [sdhci_s3c]) [<bf0060a8>] (sdhci_s3c_runtime_suspend+0x14/0x38 [sdhci_s3c]) from [<c016cb00>] (pm_generic_runtime_suspend+0x2c/0x40) [<c016cb00>] (pm_generic_runtime_suspend+0x2c/0x40) from [<c0170090>] (__rpm_callback+0x70/0x98) [<c0170090>] (__rpm_callback+0x70/0x98) from [<c01703f0>] (rpm_suspend+0xf0/0x534) [<c01703f0>] (rpm_suspend+0xf0/0x534) from [<c0171670>] (__pm_runtime_suspend+0x5c/0x74) [<c0171670>] (__pm_runtime_suspend+0x5c/0x74) from [<c016d018>] (pm_generic_runtime_idle+0x44/0x4c) [<c016d018>] (pm_generic_runtime_idle+0x44/0x4c) from [<c0170090>] (__rpm_callback+0x70/0x98) [<c0170090>] (__rpm_callback+0x70/0x98) from [<c0170984>] (rpm_idle+0xdc/0x18c) [<c0170984>] (rpm_idle+0xdc/0x18c) from [<c0171608>] (pm_runtime_set_autosuspend_delay+0x30/0x3c) [<c0171608>] (pm_runtime_set_autosuspend_delay+0x30/0x3c) from [<bf0069c4>] (sdhci_s3c_probe+0x35c/0x52c [sdhci_s3c]) [<bf0069c4>] (sdhci_s3c_probe+0x35c/0x52c [sdhci_s3c]) from [<c016a014>] (platform_drv_probe+0x18/0x1c) Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | | | mmc: sdhci-s3c: Enable only required bus clockChander Kashyap2012-10-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of multiple bus clock sources, all the clock sources were getting enabled. As only one clock source is needed at the time hence enable only the required bus clock. This patch does as follows: 1. In sdhci_s3c_probe enable only required bus clock source. 2. Handle the disabling of old bus clock and enables the best clock selected in sdhci_s3c_set_clock(). Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | | | mmc: Revert "mmc: dw_mmc: Add check for IDMAC configuration"Seungwon Jeon2012-10-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 94c6cee91 (Add check for IDMAC configuration). Synopsys says that only if internal dmac is not present, optional external dma interface is present. When internal dmac is present, '0' value in DMA_INTERFACE of HCON is reasonable. DMA_INTERFACE indicates external dma interface. And idmac initialization is prohibited now. The commit should be reverted since: the check for IDMAC is not reliable; falling back to PIO would provide awful performance; we wouldn't expect to see instances of this block without DMA support. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Acked-by: Will Newton <will.newton@imgtec.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | | | mmc: mxcmmc: fix bug that may block a data transfer foreverJavier Martin2012-10-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The problem can be easily reproduced using a script that loops copying a file in an SD card to another place in the same SD card and its related to read transfers. This only happens with DMA enabled. This is related to the fact that, when reading, an MMC irq signals the fact that all data from the SD card has been copied to the internal buffers. However, it doesn't signal whether the DMA transfer that is in charge of moving data from these internal buffers to RAM has finished or not. Thus, calling dmaengine_terminate_all() in the MMC irq routine can cancel an ongoing DMA transfer leaving some data in the internal buffers that produces an accumulative effect which, in the end, blocks a read data transfer forever. The following patch watches DMA irq for reading and MMC irqs for writing transfers. The 'dangerous' usage of dmaengine_terminate_all() is removed and a timeout of 10 seconds is added so that the MMC won't block forever anymore. Signed-off-by: Javier Martin <javier.martin@vista-silicon.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | | | mmc: omap_hsmmc: Pass on the suspend failure to the PM coreVaibhav Bedia2012-10-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases mmc_suspend_host() is not able to claim the host and proceed with the suspend process. The core returns -EBUSY to the host controller driver. Unfortunately, the host controller driver does not pass on this information to the PM core and hence the system suspend process continues. ret = mmc_suspend_host(host->mmc); if (ret) { host->suspended = 0; if (host->pdata->resume) { ret = host->pdata->resume(dev, host->slot_id); The return status from mmc_suspend_host() is overwritten by return status from host->pdata->resume. So the original return status is lost. In these cases the MMC core gets to an unexpected state during resume and multiple issues related to MMC crop up. 1. Host controller driver starts accessing the device registers before the clocks are enabled which leads to a prefetch abort. 2. A file copy thread which was launched before suspend gets stuck due to the host not being reclaimed during resume. To avoid such problems pass on the -EBUSY status to the PM core from the host controller driver. With this change, MMC core suspend might still fail but it does not end up making the system unusable. Suspend gets aborted and the user can try suspending the system again. Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com> Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com> Acked-by: Venkatraman S <svenkatr@ti.com> Cc: stable <stable@vger.kernel.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | | | mmc: atmel-mci: AP700x PDC is not connected to MCIHein_Tibosch2012-10-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Earlier, atmel-mci was adapted to make use of the peripheral DMA controller (PDC), in case normal DMA wouldn't work. ( http://comments.gmane.org/gmane.linux.kernel.mmc/9403 ) This works OK on ARM platforms (AT91), but it broke the driver for AVR32, the AP700x. Although the MCI has PDC support, the connection is not done for AVR chips. This patch makes the use of PDC depend on !CONFIG_AVR32. Signed-off-by: Hein Tibosch <hein_tibosch@yahoo.es> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | | | mmc: atmel-mci: DMA can be used with other controllersHein_Tibosch2012-10-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After the latest changes to atmel-mci, it could not be used with DMA on the AVR32 platform. This patch will allow to use DMA again and it will avoid access to MCI register ATMCI_DMA. Even if the IP version is lower than v3xx and doesn't have the DMA configuration register, DMA transfers can be used with a different controller than the Atmel AHB DMA one. For instance, some AVR chips use the Synopsys DesignWare AHB DMA controller. Signed-off-by: Hein Tibosch <hein_tibosch@yahoo.es> Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Chris Ball <cjb@laptop.org>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 21:31:36 -0400