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* crypto: omap-aes - Add fallback supportLokesh Vutla2016-09-13
| | | | | | | | | | | As setting up the DMA operations is quite costly, add software fallback support for requests smaller than 200 bytes. This change gives some 10% extra performance in ipsec use case. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [t-kristo@ti.com: udpated against latest upstream, to use skcipher mainly] Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: omap-aes - Add support for multiple coresLokesh Vutla2016-09-13
| | | | | | | | | | | Some SoCs like omap4/omap5/dra7 contain multiple AES crypto accelerator cores. Adapt the driver to support this. The driver picks the last used device from a list of AES devices. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [t-kristo@ti.com: forward ported to 4.7 kernel] Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: omap-aes - use runtime_pm autosuspend for clock handlingTero Kristo2016-09-13
| | | | | | | | | | | | Calling runtime PM API at the cra_init/exit is bad for power management purposes, as the lifetime for a CRA can be very long. Instead, use pm_runtime autosuspend approach for handling the device clocks. Clocks are enabled when they are actually required, and autosuspend disables these if they have not been used for a sufficiently long time period. By default, the timeout value is 1 second. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: omap-sham - fix SW fallback HMAC handling for omap2/omap3Tero Kristo2016-09-13
| | | | | | | | | | | If software fallback is used on older hardware accelerator setup (OMAP2/ OMAP3), the first block of data must be purged from the buffer. The first block contains the pre-generated ipad value required by the HW, but the software fallback algorithm generates its own, causing wrong results. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: omap-sham - fix software fallback handlingTero Kristo2016-09-13
| | | | | | | | | | If we have processed any data with the hardware accelerator (digcnt > 0), we must complete the entire hash by using it. This is because the current hash value can't be imported to the software fallback algorithm. Otherwise we end up with wrong hash results. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: omap-sham - avoid executing tasklet where not neededTero Kristo2016-09-13
| | | | | | | | | | Some of the call paths of OMAP SHA driver can avoid executing the next step of the crypto queue under tasklet; instead, execute the next step directly via function call. This avoids a costly round-trip via the scheduler giving a slight performance boost. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: arm/ghash - change internal cra_name to "__ghash"Ard Biesheuvel2016-09-07
| | | | | | | | | | The fact that the internal synchrous hash implementation is called "ghash" like the publicly visible one is causing the testmgr code to misidentify it as an algorithm that requires testing at boottime. So rename it to "__ghash" to prevent this. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* PCI: Fix cavium quirk compile failure with PCI_ATS offHerbert Xu2016-09-07
| | | | | | | | | The newly added quirk_cavium_sriov_rnm_link doesn't compile if PCI_ATS is off. This patch adds a check for PCI_ATS. Fixes: 21b5b8eebbae ("PCI: quirk fixup for cavium invalid sriov...") Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* hwrng: pasemi - Migrate to managed APIPrasannaKumar Muralidharan2016-09-07
| | | | | | | | | | | | | | | | | Use devm_ioremap and devm_hwrng_register instead of ioremap and hwrng_register. This removes unregistering and error handling code. Changes in v2: Remove hardcoded resource size in ioremap, use resource struct obtained by calling platform_get_resource. Removing hardcoded resource size was suggested by LABBE Corentin. CC: Darren Stevens <darren@stevens-zone.net> Suggested-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: mv_cesa - remove NO_IRQ referenceArnd Bergmann2016-09-07
| | | | | | | | | | | | | | Drivers should not use NO_IRQ, as we are trying to get rid of that. In this case, the call to irq_of_parse_and_map() is both wrong (as it returns '0' on failure, not NO_IRQ) and unnecessary (as platform_get_irq() does the same thing) This removes the call to irq_of_parse_and_map() and checks for the error code correctly. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: ccp - add missing release in ccp_dmaengine_registerQuentin Lambert2016-09-07
| | | | | | | | | | | ccp_dmaengine_register used to return with an error code before releasing all resource. This patch adds a jump to the appropriate label ensuring that the resources are properly released before returning. This issue was found with Hector. Signed-off-by: Quentin Lambert <lambert.quentin@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: arm/ghash-ce - add missing async import/exportArd Biesheuvel2016-09-07
| | | | | | | | | | | Since commit 8996eafdcbad ("crypto: ahash - ensure statesize is non-zero"), all ahash drivers are required to implement import()/export(), and must have a non-zero statesize. Fix this for the ARM Crypto Extensions GHASH implementation. Fixes: 8996eafdcbad ("crypto: ahash - ensure statesize is non-zero") Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: arm/sha1-neon - add support for building in Thumb2 modeArd Biesheuvel2016-09-07
| | | | | | | | | | The ARMv7 NEON module is explicitly built in ARM mode, which is not supported by the Thumb2 kernel. So remove the explicit override, and leave it up to the build environment to decide whether the core SHA1 routines are assembled as ARM or as Thumb2 code. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: algif_hash - Handle NULL hashes correctlyHerbert Xu2016-09-07
| | | | | | | | | Right now attempting to read an empty hash simply returns zeroed bytes, this patch corrects this by calling the digest function using an empty input. Reported-by: Russell King - ARM Linux <linux@armlinux.org.uk> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: caam - fix rfc3686(ctr(aes)) IV loadCatalin Vasile2016-09-07
| | | | | | | | | | | | -nonce is being loaded using append_load_imm_u32() instead of append_load_as_imm() (nonce is a byte array / stream, not a 4-byte variable) -counter is not being added in big endian format, as mandatated by RFC3686 and expected by the crypto engine Signed-off-by: Catalin Vasile <cata.vasile@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: engine - permit to enqueue ashash_requestCorentin LABBE2016-09-07
| | | | | | | | | | | | | The current crypto engine allow only ablkcipher_request to be enqueued. Thus denying any use of it for hardware that also handle hash algo. This patch modify the API for allowing to enqueue ciphers and hash. Since omap-aes/omap-des are the only users, this patch also convert them to the new cryptoengine API. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: engine - move crypto engine to its own headerCorentin LABBE2016-09-07
| | | | | | | | This patch move the whole crypto engine API to its own header crypto/engine.h. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - fix incorrect accelerator mask for C3X devicesMaksim Lukoshkov2016-09-07
| | | | | | | | Fix incorrect value of ADF_C3XXX_ACCELERATORS_MASK. Signed-off-by: Maksim Lukoshkov <maksim.lukoshkov@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* hwrng: bcm2835 - handle of_iomap failuresArvind Yadav2016-09-07
| | | | | | | | Check return value of of_iomap and handle errors correctly. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: FIPS - allow tests to be disabled in FIPS modeStephan Mueller2016-08-31
| | | | | | | | | | | | | | In FIPS mode, additional restrictions may apply. If these restrictions are violated, the kernel will panic(). This patch allows test vectors for symmetric ciphers to be marked as to be skipped in FIPS mode. Together with the patch, the XTS test vectors where the AES key is identical to the tweak key is disabled in FIPS mode. This test vector violates the FIPS requirement that both keys must be different. Reported-by: Tapas Sarangi <TSarangi@trustwave.com> Signed-off-by: Stephan Mueller <smueller@chronox.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: qat - fix constants table DMAMaksim Lukoshkov2016-08-31
| | | | | | | | Copy const_tab array into DMA-able memory (accesible by qat hw). Signed-off-by: Maksim Lukoshkov <maksim.lukoshkov@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* hwrng: tx4939 - Use devm_hwrng_register instead of hwrng_registerPrasannaKumar Muralidharan2016-08-31
| | | | | | | | | By using devm_hwrng_register instead of hwrng_register the .remove callback in platform_driver can be removed. This reduces a few lines in code. Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* hwrng: Remove check for max less than 4 bytesPrasannaKumar Muralidharan2016-08-31
| | | | | | | | HW RNG core never asks for data less than 4 bytes. The check whether max is less than 4 bytes is unnecessary. Remove the check. Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: xor - Fix warning when XOR_SELECT_TEMPLATE is unsetHerbert Xu2016-08-31
| | | | | | | | | | This patch fixes an unused label warning triggered when the macro XOR_SELECT_TEMPLATE is not set. Fixes: 39457acda913 ("crypto: xor - skip speed test if the xor...") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Suggested-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* hwrng: amd - Convert to new hwrng read() APICorentin LABBE2016-08-31
| | | | | | | | This patch convert the hwrng interface used by amd768-rng to its new API by replacing data_read()/data_present() by read(). Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* hwrng: amd - Access hardware via ioread32/iowrite32Corentin LABBE2016-08-31
| | | | | | | | Instead of accessing hw directly via pmbase, it's better to access after ioport_map() via ioread32/iowrite32. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* hwrng: amd - Replace global variable with private structCorentin LABBE2016-08-31
| | | | | | | | Instead of having two global variable, it's better to use a private struct. This will permit to remove amd_pdev variable Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* hwrng: amd - release_region must be called after hwrng_unregisterCorentin LABBE2016-08-31
| | | | | | | | | | The driver release the memory region before being sure that nobody use it. This patch made hwrng_unregister ran before any release was done. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* hwrng: amd - Remove asm/io.hCorentin LABBE2016-08-31
| | | | | | | | | checkpatch complains about <asm/io.h> used instead of linux/io.h. In fact it is not needed. This patch remove it, and in the process, alphabetize the other headers. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* hwrng: amd - Be consitent with the driver nameCorentin LABBE2016-08-31
| | | | | | | | The driver name is displayed each time differently. This patch make use of the same name everywhere. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* hwrng: amd - use the BIT macroCorentin LABBE2016-08-31
| | | | | | | This patch add usage of the BIT() macro Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* hwrng: amd - Fix style problem with blank lineCorentin LABBE2016-08-31
| | | | | | | | Some blank line are unncessary, and one is missing after declaration. This patch fix thoses style problems. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: caam - add missing header dependenciesBaoyou Xie2016-08-31
| | | | | | | | | | | We get 1 warning when biuld kernel with W=1: drivers/crypto/caam/ctrl.c:398:5: warning: no previous prototype for 'caam_get_era' [-Wmissing-prototypes] In fact, this function is declared in drivers/crypto/caam/ctrl.h, so this patch add missing header dependencies. Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* hwrng: cavium - Add Cavium HWRNG driver for ThunderX SoC.Omer Khaliq2016-08-31
| | | | | | | | | | The Cavium ThunderX SoC has a hardware random number generator. This driver provides support using the HWRNG framework. Signed-off-by: Omer Khaliq <okhaliq@caviumnetworks.com> Signed-off-by: Ananth Jasty <Ananth.Jasty@cavium.com> Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* PCI: quirk fixup for cavium invalid sriov link value.Ananth Jasty2016-08-31
| | | | | | | | | | | Cavium cn88xx hardware presents an incorrect SR-IOV Function Dependency Link, add a fixup quirk for the affected devices. Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: Ananth Jasty <Ananth.Jasty@cavium.com> Signed-off-by: Omer Khaliq <okhaliq@caviumnetworks.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: rockchip - use devm_add_action_or_reset()Sudip Mukherjee2016-08-24
| | | | | | | | | | | If devm_add_action() fails we are explicitly calling the cleanup to free the resources allocated. Lets use the helper devm_add_action_or_reset() and return directly in case of error, as we know that the cleanup function has been already called by the helper if there was any error. Signed-off-by: Sudip Mukherjee <sudip.mukherjee@codethink.co.uk> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: rsa - allow keys >= 2048 bits in FIPS modeStephan Mueller2016-08-24
| | | | | | | | | | | | | | | With a public notification, NIST now allows the use of RSA keys with a modulus >= 2048 bits. The new rule allows any modulus size >= 2048 bits provided that either 2048 or 3072 bits are supported at least so that the entire RSA implementation can be CAVS tested. This patch fixes the inability to boot the kernel in FIPS mode, because certs/x509.genkey defines a 4096 bit RSA key per default. This key causes the RSA signature verification to fail in FIPS mode without the patch below. Signed-off-by: Stephan Mueller <smueller@chronox.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: mxc-scc - check clk_prepare_enable() errorFabio Estevam2016-08-24
| | | | | | | | clk_prepare_enable() may fail, so we should better check its return value and propagate it in the case of failure. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* hwrng: omap3-rom - Remove obsoleted functionsPrasannaKumar Muralidharan2016-08-24
| | | | | | | | | | | Remove omap3_rom_rng_data_present method as it was returning 1 always. Use .read callback instead of .data_read callback. This avoids use of obsolete callbacks. This patch is not tested with hardware as I don't have access to it. Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: drbg - fix error return codeWei Yongjun2016-08-24
| | | | | | | | | Fix to return a negative error code from the error handling case instead of 0. Signed-off-by: Wei Yongjun <weiyj.lk@gmail.com> Acked-by: Stephan Mueller <smueller@chronox.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: sun4i-ss - fix missing unlock on error in sun4i_hash()Wei Yongjun2016-08-24
| | | | | | | | | | Add the missing unlock before return from function sun4i_hash() in the error handling case. Fixes: 477d9b2e591b ("crypto: sun4i-ss - unify update/final function") Signed-off-by: Wei Yongjun <weiyj.lk@gmail.com> Acked-by: Corentin LABBE <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: xor - skip speed test if the xor function is selected automaticallyMartin Schwidefsky2016-08-24
| | | | | | | | | | If the architecture selected the xor function with XOR_SELECT_TEMPLATE the speed result of the do_xor_speed benchmark is of limited value. The speed measurement increases the bootup time a little, which can makes a difference for kernels used in container like virtual machines. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* hwrng: core - Improve description of the ->read() interfaceDaniel Thompson2016-08-24
| | | | | | | | | | | | | | | | | | | Currently, very few RNG drivers support single byte reads using the ->read() interface. Of the 14 drivers in drivers/char/hw_random that support this interface only three of these actually support max == 1. The other behaviours vary between return 0, return 2, return 4 and return -EIO). This is not a problem in practice because the core hw_random code never performs a read shorter than 16 bytes. The documentation for this function already contrains the alignment of the buffer pointer, so let's also guarantee that the buffer is at least as large as its alignment. This constraint is intended to be the weakest guarantee neccessary to allow driver writers to safely simplify their code. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: doc - fix documentation for bulk registration functionsEric Biggers2016-08-24
| | | | | | | | Update the documentation for crypto_register_algs() and crypto_unregister_algs() to match the actual behavior. Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: drbg - do not call drbg_instantiate in healt testStephan Mueller2016-08-16
| | | | | | | | | | | | | | | When calling the DRBG health test in FIPS mode, the Jitter RNG is not yet present in the kernel crypto API which will cause the instantiation to fail and thus the health test to fail. As the health tests cover the enforcement of various thresholds, invoke the functions that are supposed to enforce the thresholds directly. This patch also saves precious seed. Reported-by: Tapas Sarangi <TSarangi@trustwave.com> Signed-off-by: Stephan Mueller <smueller@chronox.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* hwrng: pic32 - Delete unnecessary assignment for the field "owner"Markus Elfring2016-08-16
| | | | | | | | | The field "owner" is set by the core. Thus delete an unneeded initialisation. Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: ccp - Fix non static symbol warningWei Yongjun2016-08-16
| | | | | | | | | | Fixes the following sparse warning: drivers/crypto/ccp/ccp-dev.c:62:14: warning: symbol 'ccp_increment_unit_ordinal' was not declared. Should it be static? Signed-off-by: Wei Yongjun <weiyj.lk@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: sun4i-ss - fix indentation of two crypto algCorentin LABBE2016-08-16
| | | | | | | Two crypto alg are badly indented, this patch fix this style issue. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: sun4i-ss - Always use sun4i_tfm_ctx for storing pointer to dev ssCorentin LABBE2016-08-16
| | | | | | | | | The dev *ss is stored both in sun4i_tfm_ctx and sun4i_req_ctx. Since this pointer will never be changed during tfm life, it is better to remove it from sun4i_req_ctx. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: sun4i-ss - fix spellingCorentin LABBE2016-08-16
| | | | | | | Two words are badly spelled, this patch respell them. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-14 08:58:22 -0400