| Commit message (Collapse) | Author | Age |
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http://github.com/Broadcom/stblinux into next/soc
Merge "Broadcom maintainers changes for 4.6" from Florian Fainelli:
This pull request contains MAINTAINERS file updates for Broadcom ARM-based SoCs:
- Florian updates the Broadcom BCM63xx ARM-based DSL SoCs to use the same mailing-list
and development tree as all the other Broadcom SoCS
* tag 'arm-soc/for-4.6/maintainers' of http://github.com/Broadcom/stblinux:
MAINTAINERS: ARM: BCM63xx: Update git and mailing-lists
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arm-bcm63xx.git has not been used for development, instead, all patches
have been added to stblinux.git, so reflect that. While at it, add
bcm-kernel-feedback-list@broadcom.com as a secondary list to include
submissions, and finally update LAKML to reflect that it is moderated.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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next/soc
Merge "Broadcom soc changes for 4.6" from Florian Fainelli:
This pull request contains Broadcom ARM-based SoC/platform changes:
- Masahiro updates the Broadcom Northstar Plus SMP operations to be annotated
with const and __initconst
- Florian removes an unused variable in the Broadcom BCM63XX SMP code
* tag 'arm-soc/for-4.6/soc' of http://github.com/Broadcom/stblinux:
ARM: BCM63xx: Remove unused pmb_dn variable
ARM: bcm: use const and __initconst for smp_operations
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Introduced in commit 3f2a43c98d72b ("ARM: BCM63xx: Add secondary CPU PMB
initialization sequence"), but not used by the code.
Reported-by: David Binderman <dcb314@hotmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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This newly added code missed the global fixup by commit 75305275a721
("ARM: use const and __initconst for smp_operations"). So fix it now.
Also, add missing "static" qualifier.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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Select the Alpine MSI controller driver when using an Alpine platform.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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next/soc
Merge "ARM: Xilinx Zynq patches for v4.6" from Michal Simek:
- SLCR early init
- Fix L2 cache data corruption
- Fix early printk uart setting
* tag 'zynq-soc-for-4.6' of https://github.com/Xilinx/linux-xlnx:
ARM: zynq: Move early printk virtual address to vmalloc area
ARM: zynq: address L2 cache data corruption
ARM: zynq: initialize slcr mapping earlier
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The patch
"ARM: 8432/1: move VMALLOC_END from 0xff000000 to 0xff800000"
(sha1: 6ff0966052c46efb53980b8a1add2e7b49c9f560)
has moved also start of VMALLOC area because size didn't change.
That's why origin location of vmalloc was
vmalloc : 0xf0000000 - 0xff000000 ( 240 MB)
and now is
vmalloc : 0xf0800000 - 0xff800000 ( 240 MB)
That's why uart virtual addresses need to be changed to reflect this new
memory setup. Starting address should be vmalloc start address.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
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The Zynq has a bug where the L2 cache will return invalid data in some
circumstances unless the L2C_RAM register is set to 0x00020202 before the first
enabling of the L2 cache.
The Xilinx-recommended solution to this problem is to ensure that early one of
the earlier bootstages correctly initialize L2C_RAM, however, this issue wasn't
discovered and fixed until after their EDK/SDK 14.4 release. For systems built
prior to that, and which lack field-upgradable bootloaders, this issue still
exists and silent data corruption can be seen in the wild.
Fix these systems by ensuring L2C_RAM is properly initialized at the
earliest convenient moment prior to the L2 being brought up, which is
when the SLCR is first mapped.
The Zynq bug is described in more detail by Xilinx AR# 54190 as quoted
below.
Xilinx AR# 54190
http://www.xilinx.com/support/answers/54190.htm
Captured on 2014-09-24 14:43 -0500
= Description =
For proper L2 cache operation, the user code must program the
slcr.L2C_RAM register (address 0xF800_0A1C) to the value of
0x0002_0202 before enabling the L2 cache. The reset value
(0x0001_0101) might cause, very infrequently, the L2 cache to return
invalid data.
= Solution =
It is up to the user code (FSBL or other user code) to set the
slcr.L2C_RAM register to the value 0x0002_0202 before enabling the L2
cache.
Note: The L2 cache is disabled after reset and is not enabled by the
BootROM.
Note: The slcr.l2C_RAM register was previously reserved. It is added
in the Zynq-7000 AP SoC Technical Reference Manual (TRM) v1.5 as
"Reserved".
Thanks to Jaeden Amero for initial debugging and triage efforts.
Signed-off-by: Josh Cartwright <joshc@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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In preparation for performing additional configuration prior to bringing
up L2, move the slcr initialization earlier in the boot process.
Signed-off-by: Josh Cartwright <joshc@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc
Merge "DaVinci EDMA enhancements for v4.6" from Sekhar Nori:
Pass dma_slave_map data to EDMA driver. This will help
migration to new DMA engine API for requesting
slave channels dma_request_chan().
* tag 'davinci-for-v4.6/edma' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: davinci: dm646x: Add dma_slave_map to edma
ARM: davinci: dm644x: Add dma_slave_map to edma
ARM: davinci: dm365: Add dma_slave_map to edma
ARM: davinci: dm355: Add dma_slave_map to edma
ARM: davinci: devices-da8xx: Add dma_slave_map to edma
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Provide the dma_slave_map to edma which will allow us to move the drivers
to the new, simpler dmaengine API and we can remove the DMA resources also
for the devices.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[nsekhar@ti.com: fix typos in code]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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Provide the dma_slave_map to edma which will allow us to move the drivers
to the new, simpler dmaengine API and we can remove the DMA resources also
for the devices.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[nsekhar@ti.com: typo fixes in code]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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Provide the dma_slave_map to edma which will allow us to move the drivers
to the new, simpler dmaengine API and we can remove the DMA resources also
for the devices.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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Provide the dma_slave_map to edma which will allow us to move the drivers
to the new, simpler dmaengine API and we can remove the DMA resources also
for the devices.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[nsekhar@ti.com: typo fixes in code]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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Provide the dma_slave_map to edma which will allow us to move the drivers
to the new, simpler dmaengine API and we can remove the DMA resources also
for the devices.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[nsekhar@ti.com: fix map for edma1]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Merge "Renesas ARM Based SoC Updates for v4.6" from Simon Horman:
* Enable PM and PM_GENERIC_DOMAINS for SoCs with PM Domains
* Move emev2_smp_ops to emev2
* Remove legacy map_io callbacks on r8a7740 and emev2 SoCs
* Migrate to generic l2c OF initialization on r8a7740
* tag 'renesas-soc-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Enable PM and PM_GENERIC_DOMAINS for SoCs with PM Domains
ARM: shmobile: emev2: Move declaration of emev2_smp_ops to emev2.h
ARM: shmobile: emev2: Remove legacy machine_desc.map_io() callback
ARM: shmobile: r8a7740: Remove legacy machine_desc.map_io() callback
ARM: shmobile: r8a7740: Remove mapping of L2 cache controller registers
ARM: shmobile: r8a7740: Migrate to generic l2c OF initialization
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All supported Renesas ARM SoCs (except for Emma Mobile EV2) have clock
domains. Some SoCs also have power domains. To ensure proper operation
of on-SoC modules, module clocks must be ungated, and power domains must
be powered up when needed.
Currently the user can choose to build a kernel with power management
enabled or disabled:
- If CONFIG_PM=y, power domains and/or module clocks are handled
dynamically by Runtime PM and the generic power domain.
- If CONFIG_PM=n, power domains are assumed to be powered up by reset
state or by the boot loader, and module clocks are handled by the
legacy clock domain on driver (un)bind.
The latter is implemented using a platform bus notifier, which
applies not only to all on-SoC devices, but to all platform devices
present in the system.
To remove the dependency on implicit assumptions, and to get rid of the
peculiarities of the legacy clock domain, enable CONFIG_PM and
CONFIG_PM_GENERIC_DOMAINS unconditionally, for all Renesas ARM SoCs with
clock and/or power domains.
This does cause an increase in kernel size. Given bloat-o-meter reports
a modest increase of 26 KiB for an RZ/A1H kernel, this should not be a
problem, even when used on RZ/A1H with XIP and internal RAM only.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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make C=1:
arch/arm/mach-shmobile/smp-emev2.c:51:29: warning: symbol 'emev2_smp_ops' was not declared. Should it be static?
To fix this, move the forward declaration of emev2_smp_ops to a header
file, and include it where appropriate.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Commit FIXME ("ARM: shmobile: Consolidate SCU mapping code") removed the
last user of the static mapping on emev2-based systems. Remove the
mapping and the legacy machine_desc.map_io() callback.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Commit 37201ba5c99d0be8 ("ARM: shmobile: r8a7740: Migrate to generic l2c
OF initialization") removed the last user of the legacy "IOMEM()" macro
on r8a7740-based systems. Hence there's no longer a need to set up a
transparent mapping of system I/O registers. Remove the mapping and the
legacy machine_desc.map_io() callback.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Now all r8a7740-based platforms have been migrated to the generic l2c OF
initialization, it's no longer needed to map the L2 cache controller
registers from .map_io().
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Migrate the generic r8a7740 platform from calling l2x0_of_init() to the
generic l2c OF initialization.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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next/soc
Merge "ARM: mediatek: soc updates for v4.6" from Matthias Brugger:
Fix state machine implemenation of PMIC wrapper.
Add SMP support for mt7623.
Disable watchdog of STAUPD in PMIC wrapper for mt8173.
Add SMP support for mt2701.
Use builtin_platform_driver for scpsys. Driver can't be build as module.
Fix regulator enablement in scpsys.
* tag 'v4.5-next-soc' of https://github.com/mbgg/linux-mediatek:
soc: mediatek: SCPSYS: Fix double enabling of regulators
soc: mediatek: SCPSYS: use builtin_platform_driver
ARM: mediatek: add mt2701 smp bringup code
soc: mediatek: PMIC wrap: clear the STAUPD_TRIG bit of WDT_SRC_EN
ARM: mediatek: add MT7623 smp bringup code
soc: mediatek: PMIC wrap: Clear the vldclr if state machine stay on FSM_VLDCLR state.
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With CONFIG_PM enabled do not call genpd->power_on manually as this
will cause the regulators being turned on once in SCPSYS probe and
then again when the genpd core turns on the domains. Instead, call
genpd->power_on only with CONFIG_PM disabled and tell the genpd core
that the domains are disabled when registered.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Tested-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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SCPSYS can't be built as module. Use builtin_platform_driver instead.
For this probe must not be __init and the data accessed can't be
__initconst. Remove this macros. To make the impact as small as possible,
fold scp_domain_data into scp_domain via a pointer.
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Reported-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Daniel Kurtz <djkurtz@chromium.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
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Add support for booting secondary CPUs on mt2701.
Signed-off-by: Louis Yu <louis.yu@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Since STAUPD interrupts aren't handled on mt8173, disable watchdog timeout
monitor of STAUPD to avoid WDT_INT triggered by STAUPD.
Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Add support for booting secondary CPUs on MT7623.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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FSM_VLDCLR state.
Sometimes PMIC is too busy to send data in time to cause pmic wrap timeout,
because pmic wrap is waiting for FSM_VLDCLR after finishing WACS2_CMD. It
just return error when issue happened, so the state machine will stay on
FSM_VLDCLR state when data send back later by PMIC and timeout again in next
time because pmic wrap waiting for FSM_IDLE state at the beginning of the
read/write function.
Clear the vldclr when timeout if state machine stay on FSM_VLDCLR.
Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Tested-by: Ricky Liang <jcliang@chromium.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Signed-off-by: Lars Persson <larper@axis.com>
Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Basic machine port for the Artpec-6 SoC from Axis
Communications.
Signed-off-by: Lars Persson <larper@axis.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32 into next/soc
Highlights:
-----------
- Make STM32 to select PINCTRL
- Introduce MACH_STM32F429 flag
* tag 'stm32-soc-for-v4.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32:
ARM: mach-stm32: Select pinctrl
ARM: Kconfig: Introduce MACH_STM32F429 flag
Signed-off-by: Olof Johansson <olof@lixom.net>
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Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
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This patch introduces the MACH_STM32F429 to make possible to only select
STM32F429 pinctrl driver.
By default, all the MACH_STM32Fxxx flags will be set with STM32 defconfig.
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Linus Walleij <linux.walleij@linaro.org>
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
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next/soc
mvebu driver for 4.6 (part 1)
implement ARM delay timer for orion
* tag 'mvebu-drivers-4.6-1' of git://git.infradead.org/linux-mvebu:
ARM: orion: implement ARM delay timer
Signed-off-by: Olof Johansson <olof@lixom.net>
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Implement an ARM delay timer to be used for udelay() on orion legacy
platforms. This allows us to skip the delay loop calibration at boot.
It also means that udelay() will be unaffected by CPU frequency changes
when cpufreq is enabled on these platforms.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Tested-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Some SoCs use a Palmchip BK-310x UART which is mostly 16550 compatible
but with a different register layout. While this UART has previously
only been supported in MIPS based chips (Alchemy, Ralink), the ARM based
SMP87xx series from Sigma Designs also uses it.
This patch allows the debug console to work with this type of UART.
Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"The first real batch of fixes for this release cycle, so there are a
few more than usual.
Most of these are fixes and tweaks to board support (DT bugfixes,
etc). I've also picked up a couple of small cleanups that seemed
innocent enough that there was little reason to wait (const/
__initconst and Kconfig deps).
Quite a bit of the changes on OMAP were due to fixes to no longer
write to rodata from assembly when ARM_KERNMEM_PERMS was enabled, but
there were also other fixes.
Kirkwood had a bunch of gpio fixes for some boards. OMAP had RTC
fixes on OMAP5, and Nomadik had changes to MMC parameters in DT.
All in all, mostly the usual mix of various fixes"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (46 commits)
ARM: multi_v7_defconfig: enable DW_WATCHDOG
ARM: nomadik: fix up SD/MMC DT settings
ARM64: tegra: Add chosen node for tegra132 norrin
ARM: realview: use "depends on" instead of "if" after prompt
ARM: tango: use "depends on" instead of "if" after prompt
ARM: tango: use const and __initconst for smp_operations
ARM: realview: use const and __initconst for smp_operations
bus: uniphier-system-bus: revive tristate prompt
arm64: dts: Add missing DMA Abort interrupt to Juno
bus: vexpress-config: Add missing of_node_put
ARM: dts: am57xx: sbc-am57x: correct Eth PHY settings
ARM: dts: am57xx: cl-som-am57x: fix CPSW EMAC pinmux
ARM: dts: am57xx: sbc-am57x: fix UART3 pinmux
ARM: dts: am57xx: cl-som-am57x: update SPI Flash frequency
ARM: dts: am57xx: cl-som-am57x: set HOST mode for USB2
ARM: dts: am57xx: sbc-am57x: fix SB-SOM EEPROM I2C address
ARM: dts: LogicPD Torpedo: Revert Duplicative Entries
ARM: dts: am437x: pixcir_tangoc: use correct flags for irq types
ARM: dts: am4372: fix irq type for arm twd and global timer
ARM: dts: at91: sama5d4 xplained: fix phy0 IRQ type
...
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The watchdog timer on the SoCFPGA platform is the Synopsys Designware watchdog.
Enable CONFIG_DW_WATCHDOG for the driver to get built.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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The DTSI file for the Nomadik does not properly specify how the
PL180 levelshifter is connected: the Nomadik actually needs all
the five st,sig-dir-* flags set to properly control all lines out.
Further this board supports full power cycling of the card, and
since this variant has no hardware clock gating, it needs a
ridiculously low frequency setting to keep up with the ever
overflowing FIFO.
The pin configuration set-up is a bit of a mystery, because of
course these pins are a mix of inputs and outputs. However the
reference implementation sets all pins to "output" with
unspecified initial value, so let's do that here as well.
Cc: stable@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into fixes
vexpress fixes for v4.5
Couple of minor fixes for vexpress platforms:
1. Add missing of_node_put in vexpress config bus
2. Add missing DMA-330 abort interrupt on Juno platforms
* tag 'vexpress-for-v4.5/fixes-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: Add missing DMA Abort interrupt to Juno
bus: vexpress-config: Add missing of_node_put
Signed-off-by: Olof Johansson <olof@lixom.net>
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The DMA-330 has an "irq_abort" interrupt line on which it signals faults
separately from the "irq[n:0]" channel interrupts. On Juno, this is
wired up to SPI 92; add it to the DT so that DMAC faults are correctly
reported for the driver to reset the thing, rather than leaving it
locked up and waiting to time out.
CC: Liviu Dudau <liviu.dudau@arm.com>
CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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for_each_compatible_node performs an of_node_get on each iteration, so
to break out of the loop an of_node_put is required.
Found using Coccinelle. The semantic patch used for this is as follows:
// <smpl>
@@
expression e;
local idexpression n;
@@
for_each_compatible_node(n, ...) {
... when != of_node_put(n)
when != e = n
(
return n;
+ of_node_put(n);
? return ...;
)
...
}
// </smpl>
Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Amitoj Kaur Chawla <amitoj1606@gmail.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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mvebu fixes for 4.5 (part 1)
- Fix dts on buffalo linksations machines (gpios and leds)
- Fix dts partition node according to new binding introduced in v4.5
* tag 'mvebu-fixes-4.5-1' of git://git.infradead.org/linux-mvebu:
ARM: dts: orion5x: gpio pin fixes for linkstation lswtgl
ARM: dts: kirkwood: gpio-leds fixes for linkstation ls-wvl/vl
ARM: dts: kirkwood: gpio-leds fixes for linkstation ls-wxl/wsxl
ARM: dts: kirkwood: gpio pin fixes for linkstation ls-wvl/vl
ARM: dts: kirkwood: gpio pin fixes for linkstation ls-wxl/wsxl
ARM: mvebu: ix4-300d: Add compatible property to "partitions" node
ARM: mvebu: kirkwood: Add compatible property to "partitions" node
Signed-off-by: Olof Johansson <olof@lixom.net>
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Here're a few gpio pin related fixes:
- remove pinctrl-0 definition from pinctrl, since those pins are used
in other places such as gpio-fan and regulators.
- keep initial state of power led
- fix for alarm pin of gpio-fan.
Fixes: dc57844a736f ("ARM: dts: orion5x: add buffalo linkstation ls-wtgl")
Signed-off-by: Roger Shimizu <rogershimizu@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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The GPIOs controlling the LEDs, listed below, are active high, not low:
- gpio-leds: "lswvl:red:alarm" pin
- gpio-leds: "lswvl:red:func" pin
- gpio-leds: "lswvl:amber:info" pin
- gpio-leds: "lswvl:blue:func" pin
- gpio-leds: "lswvl:red:hdderr{0,1}" pin
Fixes: c43379e150aa ("ARM: dts: add buffalo linkstation ls-wvl/vl")
Signed-off-by: Roger Shimizu <rogershimizu@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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The GPIOs controlling the LEDs, listed below, are active high, not low:
- gpio-leds: "lswxl:blue:power" pin
- gpio-leds: "lswxl:red:func" pin
- gpio-leds: "lswxl:red:hdderr{0,1}" pin
Fixes: e54e4b1b622e ("ARM: dts: add buffalo linkstation ls-wxl/wsxl")
Signed-off-by: Roger Shimizu <rogershimizu@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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For kirkwood, gpio pins starts from 32 are in the 2nd bank, so it should be
converted to "gpio1 <pin minus 32>" in dts file.
e.g. gpio 40 should be "gpio1 8"
The pin/bank issue was found when discussing Debian Bug #810894
[https://bugs.debian.org/810894#47]
Fixes: c43379e150aa ("ARM: dts: add buffalo linkstation ls-wvl/vl")
Reported-by: Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
Signed-off-by: Roger Shimizu <rogershimizu@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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