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* Merge tag 'omap-for-v4.13/dt-part2-signed' of ↵Olof Johansson2017-06-18
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt Second set of device tree changes for omaps for v4.13 merge window: - Updates for droid 4 proximity sensor, WLAN and battery - Configure clocks for remoteproc devices for omap5 and dra7 - Configure omap4 crypto accelerators * tag 'omap-for-v4.13/dt-part2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: omap4: add SHAM node ARM: dts: omap4: add aes2 instance ARM: dts: omap4.dtsi: remove aes[12]_fck ARM: dts: omap4: Fix aes entry ARM: dts: omap4-droid4: Configure CPCAP battery driver ARM: dts: dra7xx-clocks: Use DPLL_GPU for GPU clocks ARM: dts: dra7xx-clocks: Set IVA DPLL and its output clock rates ARM: dts: dra7xx-clocks: Set DSP DPLL and its output clock rates ARM: dts: dra7xx-clocks: Source IPU1 functional clock from CORE DPLL ARM: dts: omap54xx-clocks: Set IVA DPLL and its output clock rates ARM: dts: omap44xx-clocks: Set IVA DPLL and its output clock rates ARM: dts: omap4-droid4: Fix WLAN compatible ARM: dts: omap4-droid4: Add isl29030 ALS/proximity sensor Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: dts: omap4: add SHAM nodeTero Kristo2017-06-14
| | | | | | | | | | | | | | Add SHAM crypto accelerator. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * ARM: dts: omap4: add aes2 instanceTero Kristo2017-06-14
| | | | | | | | | | | | | | OMAP4 has AES2 instance, so add its integration data under DT. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * ARM: dts: omap4.dtsi: remove aes[12]_fckSebastian Reichel2017-06-14
| | | | | | | | | | | | | | | | | | "aes1_fck" and "aes2_fck" are controlled by hwmod. Drop clock entries to avoid conflicts. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * ARM: dts: omap4: Fix aes entrySebastian Reichel2017-06-14
| | | | | | | | | | | | | | | | | | OMAP4 has a second aes module, so let's use proper name for the first instance. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * ARM: dts: omap4-droid4: Configure CPCAP battery driverTony Lindgren2017-06-12
| | | | | | | | | | | | | | | | | | | | Configure CPCAP battery driver. Cc: devicetree@vger.kernel.org Cc: Marcel Partap <mpartap@gmx.net> Cc: Michael Scott <michael.scott@linaro.org> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * ARM: dts: dra7xx-clocks: Use DPLL_GPU for GPU clocksSubhajit Paul2017-06-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPU has two functional clocks - GPU_CORE_GCLK and GPU_HYD_GCLK. Both of these are mux clocks and are derived from the DPLL_CORE H14 output clock CORE_GPU_CLK by default. These clocks can also be be derived from DPLL_PER or DPLL_GPU. The GPU DPLL provides the output clocks primarily for the GPU. Configuring the GPU for different OPP clock frequencies is easier to achieve when using the DPLL_GPU rather than the other two DPLLs due to: 1. minimal affect on any other output clocks from these DPLLs 2. may require an impossible post-divider values on existing DPLLs without affecting other clocks. So, switch the GPU functional clocks to be sourced from GPU DPLL by default. This is done using the DT standard properties "assigned-clocks" and "assigned-clock-parents". Newer u-boots (from 2017.01 onwards) reuse and can update these properties to choose an appropriate one-time fixed OPP configuration as all the required ABB/AVS setup is performed within the bootloader. Note that there is no DVFS supported for any of the non-MPU domains. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. This patch also sets the initial values for the DPLL_GPU outputs. These values are chosen based on the OPP_NOM values defined as per recommendation from design team. The DPLL locked frequency is kept at 1277 MHz, so that the value for the divider clock, dpll_gpu_m2_ck, can be set to 425.67 MHz for OPP_NOM. Signed-off-by: Subhajit Paul <subhajit_paul@ti.com> [s-anna@ti.com: revise patch description] Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * ARM: dts: dra7xx-clocks: Set IVA DPLL and its output clock ratesSuman Anna2017-06-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IVA DPLL in DRA7xx provides the output clocks for only the IVAHD subsystem in DRA7xx as compared to previous OMAP generations when it provided the clocks for both DSP and IVAHD subsystems. This DPLL is currently not configured by older bootloaders. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL and be independent of the bootloader version. Newer u-boots (from 2017.01 onwards) reuse and can update these properties to choose an appropriate one-time fixed OPP configuration. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The reset value of the divider M2 (that supplies the IVA_GFLCK, the functional clock for the IVAHD subsystem) does not match a specific OPP. So, the derived output clock from this IVA DPLL has to be initialized as well to avoid initializing these divider outputs to an incorrect frequencies. The OPP_NOM clock frequencies are defined in the AM572x SR2.0 Data Sheet vB, section 5.5.2 "Voltage And Core Clock Specifications". The clock rates are chosen based on these OPP_NOM values and defined as per a DRA7xx PLL spec document. The DPLL locked frequency is 2300 MHz, so the dpll_iva_ck clock rate used is half of this value. The value for the divider clock, dpll_iva_m2_ck, has to be set to 388.333334 MHz or more for the divider clk logic to compute the appropriate divider value for OPP_NOM. Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * ARM: dts: dra7xx-clocks: Set DSP DPLL and its output clock ratesSuman Anna2017-06-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DSP DPLL is a new DPLL compared to previous OMAP generations and supplies the root clocks for the DSP processors, as well as a mux input source for EVE sub-system (on applicable SoCs). This DPLL is currently not configured by older bootloaders. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the DSP DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL and be independent of the bootloader version. Newer u-boots (from 2017.01 onwards) reuse and can update these properties to choose an appropriate one-time fixed OPP configuration. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The DSP DPLL provides two output clocks, DSP_GFCLK and EVE_GCLK. The desired rate for DSP_GFCLK is 600 MHz (same as DSP DPLL CLKOUT frequency), and is currently auto set due to the desired M2 divider value being the same as reset value for the locked frequency of 600 MHz. The EVE_GCLK however is required to be 400 MHz, so set the dpll_dsp_m3x2_ck's rate explicitly so that the divider is set properly. The dpll_dsp_m2_ck rate is also set explicitly to not rely on any implicit matching divider reset values to the locked DPLL frequency. The OPP_NOM clock frequencies are defined in the AM572x SR2.0 Data Sheet vB, section 5.5.2 "Voltage And Core Clock Specifications". The clock rates are chosen based on these OPP_NOM values and defined as per a DRA7xx PLL spec document. The DPLL locked frequency is 1200 MHz, so the dpll_dsp_ck clock rate used is half of this value. Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * ARM: dts: dra7xx-clocks: Source IPU1 functional clock from CORE DPLLSuman Anna2017-06-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IPU1 functional clock is actually the output of a mux clock, ipu1_gfclk_mux. The mux clock is sourced by default from the DPLL_ABE_X2_CLK, and this results in a rather odd clock frequency (361 MHz) for the IPU1 functional clock on platforms where ABE_DPLL is configured properly. Reconfigure the mux clock to be sourced from CORE_IPU_ISS_BOOST_CLK (dpll_core_h22x2_ck), so that both the IPU1 and IPU2 are running from the same clock and clocked at the same nominal frequency of 425 MHz. This also ensures that IPU1 functional clock is always configured properly and becomes independent of the state of the ABE DPLL on all boards. Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * ARM: dts: omap54xx-clocks: Set IVA DPLL and its output clock ratesSuman Anna2017-06-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IVA DPLL is not an essential DPLL for the functionality of a bootloader and is usually not configured (e.g. older u-boots configure it only if CONFIG_SYS_CLOCKS_ENABLE_ALL is enabled and u-boots newer than 2014.01 do not even have an option), and this results in incorrect operating frequencies when trying to use a DSP or IVAHD, whose root clocks are derived from this DPLL. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The reset values of the dividers H11 & H12 (functional clocks for DSP and IVAHD respectively) are identical to each other, but are different at each OPP. The reset values also do not match a specific OPP. So, the derived output clocks from the IVA DPLL have to be initialized as well to avoid initializing these divider outputs to incorrect frequencies. The clock rates are chosen based on the OPP_NOM values as defined in the OMAP5432 SR2.0 Data Manual Book vK, section 5.2.3.5 "DPLL_IVA Preferred Settings". The recommended maximum DPLL locked frequency is 2330 MHz for OPP_NOM (value for DPLL_IVA_X2_CLK), so the dpll_iva_ck clock rate used is half of this value. The value 465.92 MHz is used instead of 465.9 MHz for dpll_iva_h11x2_ck so that proper divider value can be calculated. Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * ARM: dts: omap44xx-clocks: Set IVA DPLL and its output clock ratesSuman Anna2017-06-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IVA DPLL is not an essential DPLL for the functionality of a bootloader and is usually not configured (e.g. older u-boots configure it only if CONFIG_SYS_CLOCKS_ENABLE_ALL is enabled and u-boots newer than 2014.01 do not even have an option), and this results in incorrect operating frequencies when trying to use a DSP or IVAHD, whose root clocks are derived from this DPLL. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The reset values of the dividers M4 & M5 (functional clocks for DSP and IVAHD respectively) are identical to each other, but are different at each OPP. The reset values also do not match a specific OPP. So, the derived output clocks from the IVA DPLL have to be initialized as well to avoid initializing these divider outputs to incorrect frequencies. The clock rates are chosen based on the OPP100 values as defined in the OMAP4430 ES2.x Public TRM vAP, section "3.6.3.8.7 DPLL_IVA Preferred Settings". The DPLL locked frequency is 1862.4 MHz (value for DPLL_IVA_X2_CLK), so the dpll_iva_ck clock rate used is half of this value. Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * ARM: dts: omap4-droid4: Fix WLAN compatibleSebastian Reichel2017-06-12
| | | | | | | | | | | | | | | | | | | | Motorola Droid 4 uses a WL1285C, so use proper compatible value. To avoid regressions while support for the new compatible value is added to the Linux kernel, the old compatible value is preserved as fallback. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * ARM: dts: omap4-droid4: Add isl29030 ALS/proximity sensorSebastian Reichel2017-06-12
| | | | | | | | | | | | | | | | The Droid 4 has a isl29030 to measure ambient light (e.g. for automatically adapting display brightness) and proximity. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | Merge tag 'sunxi-dt-h3-for-4.13' of ↵Olof Johansson2017-06-18
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt Allwinner H3 changes for 4.13 This tag is about bringing the EMAC support to the H3 boards. * tag 'sunxi-dt-h3-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: ARM: sun8i: h3: Enable EMAC with external PHY on Orange Pi Plus 2E arm: sun8i: orangepi-zero: Enable dwmac-sun8i ARM: sun8i: bananapi-m2-plus: Enable dwmac-sun8i ARM: sun8i: orangepi-plus: Enable dwmac-sun8i arm: sun8i: nanopi-neo: Enable dwmac-sun8i arm: sun8i: orangepi-pc-plus: Set EMAC activity LEDs to active high arm: sun8i: orangepi-2: Enable dwmac-sun8i arm: sun8i: orangepi-one: Enable dwmac-sun8i arm: sun8i: orangepi-pc: Enable dwmac-sun8i arm: sun8i: sunxi-h3-h5: add dwmac-sun8i ethernet driver arm: sun8i: sunxi-h3-h5: Add dt node for the syscon control module ARM: sunxi: h3-h5: Convert R_CCU raw numbers to macros Signed-off-by: Olof Johansson <olof@lixom.net>
| * | ARM: sun8i: h3: Enable EMAC with external PHY on Orange Pi Plus 2EChen-Yu Tsai2017-06-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Orange Pi Plus 2E, unlike the Orange Pi PC and PC Plus which its schematics are based on, uses an external Realtek RTL8211E PHY in RGMII mode, with a GPIO enabling the regulator for I/O signalling power supplies. The PHY's main power supply is enabled by the main 5V power supply. Add the regulator and PHY nodes, and override the PHY phandle under the EMAC node, so that the EMAC works properly on this board. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | arm: sun8i: orangepi-zero: Enable dwmac-sun8iCorentin Labbe2017-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dwmac-sun8i hardware is present on the Orange PI Zero. It uses the internal PHY. This patch create the needed emac node. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: sun8i: bananapi-m2-plus: Enable dwmac-sun8iCorentin Labbe2017-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dwmac-sun8i hardware is present on the Banana Pi M2+ It uses an external PHY rtl8211e via RGMII. This patch create the needed regulator, emac and phy nodes. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: sun8i: orangepi-plus: Enable dwmac-sun8iCorentin Labbe2017-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dwmac-sun8i hardware is present on the Orange PI plus. It uses an external PHY rtl8211e via RGMII. This patch create the needed regulator, emac and phy nodes. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | arm: sun8i: nanopi-neo: Enable dwmac-sun8iCorentin Labbe2017-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | The dwmac-sun8i hardware is present on the NanoPi Neo. It uses the internal PHY. This patch create the needed emac node. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | arm: sun8i: orangepi-pc-plus: Set EMAC activity LEDs to active highCorentin Labbe2017-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | On the Orange Pi PC Plus, the polarity of the LEDs on the RJ45 Ethernet port were changed from active low to active high. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | arm: sun8i: orangepi-2: Enable dwmac-sun8iCorentin Labbe2017-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dwmac-sun8i hardware is present on the Orange PI 2. It uses the internal PHY. This patch create the needed emac node. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | arm: sun8i: orangepi-one: Enable dwmac-sun8iCorentin Labbe2017-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dwmac-sun8i hardware is present on the Orange PI One. It uses the internal PHY. This patch create the needed emac node. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | arm: sun8i: orangepi-pc: Enable dwmac-sun8iCorentin Labbe2017-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dwmac-sun8i hardware is present on the Orange PI PC. It uses the internal PHY. This patch create the needed emac node. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | arm: sun8i: sunxi-h3-h5: add dwmac-sun8i ethernet driverCorentin Labbe2017-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000 speed. This patch enable the dwmac-sun8i on Allwinner H3/H5 SoC Device-tree. SoC H3/H5 have an internal PHY, so optionals syscon and ephy are set. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | arm: sun8i: sunxi-h3-h5: Add dt node for the syscon control moduleCorentin Labbe2017-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add the dt node for the syscon register present on the Allwinner H3/H5 Only two register are present in this syscon and the only one useful is the one dedicated to EMAC clock.. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: sunxi: h3-h5: Convert R_CCU raw numbers to macrosChen-Yu Tsai2017-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the R_CCU device tree binding headers have been merged, we can convert the raw number references in the device trees to use the defined macros. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | | Merge tag 'sunxi-dt-for-4.13' of ↵Olof Johansson2017-06-18
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt Allwinner DT changes for 4.13 The usual chunk of patches. The most notable improvements are the power supplies improvements (battery and AC-IN), crypto support for the sun5i family, HDMI support for the A10s, plus a lot of new things for the V3S and the A83T. * tag 'sunxi-dt-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (47 commits) ARM: sun6i: a31s: primo81: Enable battery power supply ARM: sun6i: a31s: primo81: Change USB OTG to OTG mode ARM: sun8i: a83t: Add dt node for the syscon control module ARM: sun8i: a83t: Add device node for R_PIO ARM: sun8i: v3s: add device nodes for DE2 display pipeline ARM: dts: sunxi: add SoC specific compatibles for the crypto nodes ARM: sun5i: add a cryptographic engine node ARM: sun8i: a83t: Add device node for PRCM ARM: dts: sun8i: h3: Add initial NanoPi M1 Plus support ARM: dts: orange-pi-zero: add node for SPI NOR ARM: sun7i: a20: cubietruck: Tie AXP209's USB power supply to USB PHY ARM: sun6i: a31: hummingbird: Enable AXP221's ACIN power supply ARM: sun4i: a10: cubieboard: Enable AXP209's ACIN power supply ARM: sun7i: a20: bananapi-m1-plus: Enable AXP209's ACIN power supply ARM: sun7i: a20: cubieboard2: Enable AXP209's ACIN power supply ARM: sun7i: a20: cubieboard2: Move usb_otg node for alphabetical ordering ARM: sun8i: a83t: cubietruck-plus: Enable SPDIF output ARM: sun8i: a83t: cubietruck-plus: Add LED device nodes ARM: sun8i: a83t: Add device node for SPDIF transmitter ARM: sun8i: a83t: Add device node for DMA controller ... Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | ARM: sun6i: a31s: primo81: Enable battery power supplyChen-Yu Tsai2017-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MSI Primo81 tablet has a 3500 mAh 3.7V LiPo battery. Enable the PMIC's battery power supply so the battery can be monitored. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | ARM: sun6i: a31s: primo81: Change USB OTG to OTG modeChen-Yu Tsai2017-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have support for the AXP221 PMIC's USB VBUS detection and DRIVEVBUS vbus control, we can use the USB OTG port in proper OTG mode. This patch enables the aforementioned PMIC functions, adds the OTG ID detection pin to the USB PHY node, and changes the mode of USB OTG to "otg". Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | ARM: sun8i: a83t: Add dt node for the syscon control moduleCorentin Labbe2017-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add the dt node for the syscon register present on the Allwinner A83T Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | ARM: sun8i: a83t: Add device node for R_PIOChen-Yu Tsai2017-06-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A83T has 1 pingroup with 13 pins belonging to the R_PIO or special pin controller. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
| * | | ARM: sun8i: v3s: add device nodes for DE2 display pipelineIcenowy Zheng2017-06-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner V3s SoC features a "Display Engine 2.0" with only one mixer and only one TCON connected to this mixer, which have RGB LCD output. Add device nodes for this display pipeline. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | ARM: dts: sunxi: add SoC specific compatibles for the crypto nodesAntoine Tenart2017-06-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SoC specific compatibles for all sunXi crypto nodes, in addition to the one already used (allwinner,sun4i-a10-crypto). Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | ARM: sun5i: add a cryptographic engine nodeAntoine Tenart2017-06-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a node for the cryptographic engine that can be found on sun5i SoCs. This cryptographic engine is compatible with the Allwinner cryptographic accelerator driver. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | ARM: sun8i: a83t: Add device node for PRCMChen-Yu Tsai2017-06-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A83T's PRCM has the same set of clocks and resets as the A64. However, a few dividers are different. And due to the lack of a low speed 32.768 kHz oscillator, a few of the clock parents are different. The PRCM also has controls for various power domains. These are not supported yet, neither in software nor in the device tree binding. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | ARM: dts: sun8i: h3: Add initial NanoPi M1 Plus supportJagan Teki2017-05-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NanoPi M1 Plus is designed and developed by FriendlyElec for professionals, enterprise users, makers and hobbyists using the Allwinner H3 SOC. NanoPi M1 Plus key features - Allwinner H3, Quad-core Cortex-A7@1.2GHz - 1GB DDR3 RAM - 8GB eMMC - microSD slot - 10/100/1000M Ethernet - Serial Debug Port - 5V 2A DC power-supply Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | ARM: dts: orange-pi-zero: add node for SPI NORSergey Matyukevich2017-05-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add node for SPI NOR flash on orange-pi-zero board. Disable this node by default and leave it to users to enable it if their board has SPI NOR flash chip populated. SPI NOR flash was optional in the first production batch in Dec 2016. In later batches flash chip was pre-populated. However there should be quite a few boards around which do not have flash chip. Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | ARM: sun7i: a20: cubietruck: Tie AXP209's USB power supply to USB PHYChen-Yu Tsai2017-05-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB PHY can use either a GPIO pin or the PMIC's USB power supply to sense VBUS. Since both options are available on the Cubietruck, add the missing property for the USB power supply to the USB PHY node. The device tree provides all usable options. Ultimately, which method is used is up to the driver implementation. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | ARM: sun6i: a31: hummingbird: Enable AXP221's ACIN power supplyChen-Yu Tsai2017-05-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ACIN pins of the AXP221 PMIC on the A31 Hummingbird are tied to the DC jack on the board through a 12V to 5V buck converter. Enable the ACIN power supply. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | ARM: sun4i: a10: cubieboard: Enable AXP209's ACIN power supplyChen-Yu Tsai2017-05-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ACIN pins of the AXP209 PMIC on the Cubieboard are tied to the DC jack on the board. Enable the ACIN power supply. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | ARM: sun7i: a20: bananapi-m1-plus: Enable AXP209's ACIN power supplyChen-Yu Tsai2017-05-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ACIN pins of the AXP209 PMIC on the Bananapi M1 Plus are tied to the "power input" micro USB connector next to the SATA connector on the board. Enable the ACIN power supply. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | ARM: sun7i: a20: cubieboard2: Enable AXP209's ACIN power supplyChen-Yu Tsai2017-05-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ACIN pins of the AXP209 PMIC on the Cubieboard 2 are tied to the DC jack on the board. Enable the ACIN power supply. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | ARM: sun7i: a20: cubieboard2: Move usb_otg node for alphabetical orderingChen-Yu Tsai2017-05-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We want to keep node references in alphabetical order, except for instances where node must be #included first. Move the usb_otg node reference so that all references to non-AXP209 device nodes are in alphabetical order. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | ARM: sun8i: a83t: cubietruck-plus: Enable SPDIF outputChen-Yu Tsai2017-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cubietruck Plus has an optical SPDIF out connector. Enable SPDIF audio output for this board. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | ARM: sun8i: a83t: cubietruck-plus: Add LED device nodesChen-Yu Tsai2017-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cubietruck Plus has 4 LEDs in different colors. Add device nodes for them. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | ARM: sun8i: a83t: Add device node for SPDIF transmitterChen-Yu Tsai2017-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A83T SoC has an SPDIF transmitter block. According to the vendor BSP kernel, it is compatible with the one found on the H3 SoC. Add a device node and pinmux setting for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | ARM: sun8i: a83t: Add device node for DMA controllerChen-Yu Tsai2017-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A83T SoC has a DMA controller that supports 8 DMA channels to and from various peripherals. Add a device node for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | ARM: dts: sunxi: Fix BCM43xx node nameFabio Estevam2017-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "bcrmf" is a typo and "wifi" is the preferred form to describe such node, so change it accordingly. Reported-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | ARM: sun8i: a83t: Set clock accuracy for 24MHz oscillatorChen-Yu Tsai2017-05-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The datasheets for Allwinner SoCs set strict requirements on the stability of the external crystal oscillators. Add the accuracy for the main 24MHz oscillator to the device tree. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 16:08:52 -0400