101 files changed, 1270 insertions, 289 deletions
diff --git a/tools/perf/Documentation/perf-list.txt b/tools/perf/Documentation/perf-list.txt
index 11300dbe35c5..236b9b97dfdb 100644
--- a/tools/perf/Documentation/perf-list.txt
+++ b/tools/perf/Documentation/perf-list.txt
@@ -18,6 +18,10 @@ various perf commands with the -e option.
 OPTIONS
 -------
+-d::
+--desc::
+Print extra event descriptions. (default)
 --no-desc::
 Don't print descriptions.
@@ -25,11 +29,13 @@ Don't print descriptions.
 --long-desc::
 Print longer event descriptions.
+--debug::
+Enable debugging output.
 --details::
 Print how named events are resolved internally into perf events, and also
 any extra expressions computed by perf stat.
 [[EVENT_MODIFIERS]]
 EVENT MODIFIERS
 ---------------
@@ -234,7 +240,7 @@ perf also supports group leader sampling using the :S specifier.
  perf record -e '{cycles,instructions}:S' ...
  perf report --group
-Normally all events in a event group sample, but with :S only
+Normally all events in an event group sample, but with :S only
 the first event (the leader) samples, and it only reads the values of the
 other events in the group.
diff --git a/tools/perf/Documentation/perf-record.txt b/tools/perf/Documentation/perf-record.txt
index 04168da4268e..246dee081efd 100644
--- a/tools/perf/Documentation/perf-record.txt
+++ b/tools/perf/Documentation/perf-record.txt
@@ -94,7 +94,7 @@ OPTIONS
          "perf report" to view group events together.
 --filter=<filter>::
-        Event filter. This option should follow a event selector (-e) which
+        Event filter. This option should follow an event selector (-e) which
        selects either tracepoint event(s) or a hardware trace PMU
        (e.g. Intel PT or CoreSight).
@@ -153,7 +153,7 @@ OPTIONS
 --exclude-perf::
        Don't record events issued by perf itself. This option should follow
-        a event selector (-e) which selects tracepoint event(s). It adds a
+        an event selector (-e) which selects tracepoint event(s). It adds a
        filter expression 'common_pid != $PERFPID' to filters. If other
        '--filter' exists, the new filter expression will be combined with
        them by '&&'.
diff --git a/tools/perf/Documentation/perf-stat.txt b/tools/perf/Documentation/perf-stat.txt
index 5dfe102fb5b5..b10a90b6a718 100644
--- a/tools/perf/Documentation/perf-stat.txt
+++ b/tools/perf/Documentation/perf-stat.txt
@@ -178,6 +178,9 @@ Print count deltas for fixed number of times.
 This option should be used together with "-I" option.
        example: 'perf stat -I 1000 --interval-count 2 -e cycles -a'
+--interval-clear::
+Clear the screen before next interval.
 --timeout msecs::
 Stop the 'perf stat' session and print count deltas after N milliseconds (minimum: 10 ms).
 This option is not supported with the "-I" option.
diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config
index b5ac356ba323..f6d1a03c7523 100644
--- a/tools/perf/Makefile.config
+++ b/tools/perf/Makefile.config
@@ -54,6 +54,8 @@ endif
 ifeq ($(SRCARCH),arm64)
  NO_PERF_REGS := 0
+  NO_SYSCALL_TABLE := 0
+  CFLAGS += -I$(OUTPUT)arch/arm64/include/generated
  LIBUNWIND_LIBS = -lunwind -lunwind-aarch64
 endif
@@ -207,8 +209,7 @@ ifdef PYTHON_CONFIG
  PYTHON_EMBED_LDOPTS := $(shell $(PYTHON_CONFIG_SQ) --ldflags 2>/dev/null)
  PYTHON_EMBED_LDFLAGS := $(call strip-libs,$(PYTHON_EMBED_LDOPTS))
  PYTHON_EMBED_LIBADD := $(call grep-libs,$(PYTHON_EMBED_LDOPTS)) -lutil
-  PYTHON_EMBED_CCOPTS := $(shell $(PYTHON_CONFIG_SQ) --cflags 2>/dev/null)
+  PYTHON_EMBED_CCOPTS := $(shell $(PYTHON_CONFIG_SQ) --includes 2>/dev/null)
-  PYTHON_EMBED_CCOPTS := $(filter-out -specs=%,$(PYTHON_EMBED_CCOPTS))
  FLAGS_PYTHON_EMBED := $(PYTHON_EMBED_CCOPTS) $(PYTHON_EMBED_LDOPTS)
 endif
@@ -906,8 +907,8 @@ bindir = $(abspath $(prefix)/$(bindir_relative))
 mandir = share/man
 infodir = share/info
 perfexecdir = libexec/perf-core
-perf_include_dir = lib/include/perf
+perf_include_dir = lib/perf/include
-perf_examples_dir = lib/examples/perf
+perf_examples_dir = lib/perf/examples
 sharedir = $(prefix)/share
 template_dir = share/perf-core/templates
 STRACE_GROUPS_DIR = share/perf-core/strace/groups
diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf
index ecc9fc952655..b3d1b12a5081 100644
--- a/tools/perf/Makefile.perf
+++ b/tools/perf/Makefile.perf
@@ -384,6 +384,8 @@ export INSTALL SHELL_PATH
 SHELL = $(SHELL_PATH)
+linux_uapi_dir := $(srctree)/tools/include/uapi/linux
 beauty_outdir := $(OUTPUT)trace/beauty/generated
 beauty_ioctl_outdir := $(beauty_outdir)/ioctl
 drm_ioctl_array := $(beauty_ioctl_outdir)/drm_ioctl_array.c
@@ -431,6 +433,12 @@ kvm_ioctl_tbl := $(srctree)/tools/perf/trace/beauty/kvm_ioctl.sh
 $(kvm_ioctl_array): $(kvm_hdr_dir)/kvm.h $(kvm_ioctl_tbl)
        $(Q)$(SHELL) '$(kvm_ioctl_tbl)' $(kvm_hdr_dir) > $@
+socket_ipproto_array := $(beauty_outdir)/socket_ipproto_array.c
+socket_ipproto_tbl := $(srctree)/tools/perf/trace/beauty/socket_ipproto.sh
+$(socket_ipproto_array): $(linux_uapi_dir)/in.h $(socket_ipproto_tbl)
+        $(Q)$(SHELL) '$(socket_ipproto_tbl)' $(linux_uapi_dir) > $@
 vhost_virtio_ioctl_array := $(beauty_ioctl_outdir)/vhost_virtio_ioctl_array.c
 vhost_virtio_hdr_dir := $(srctree)/tools/include/uapi/linux
 vhost_virtio_ioctl_tbl := $(srctree)/tools/perf/trace/beauty/vhost_virtio_ioctl.sh
@@ -566,6 +574,7 @@ prepare: $(OUTPUT)PERF-VERSION-FILE $(OUTPUT)common-cmds.h archheaders $(drm_ioc
        $(sndrv_ctl_ioctl_array) \
        $(kcmp_type_array) \
        $(kvm_ioctl_array) \
+        $(socket_ipproto_array) \
        $(vhost_virtio_ioctl_array) \
        $(madvise_behavior_array) \
        $(perf_ioctl_array) \
@@ -860,6 +869,7 @@ clean:: $(LIBTRACEEVENT)-clean $(LIBAPI)-clean $(LIBBPF)-clean $(LIBSUBCMD)-clea
                $(OUTPUT)$(sndrv_pcm_ioctl_array) \
                $(OUTPUT)$(kvm_ioctl_array) \
                $(OUTPUT)$(kcmp_type_array) \
+                $(OUTPUT)$(socket_ipproto_array) \
                $(OUTPUT)$(vhost_virtio_ioctl_array) \
                $(OUTPUT)$(perf_ioctl_array) \
                $(OUTPUT)$(prctl_option_array) \
diff --git a/tools/perf/arch/arm64/Makefile b/tools/perf/arch/arm64/Makefile
index 91de4860faad..f013b115dc86 100644
--- a/tools/perf/arch/arm64/Makefile
+++ b/tools/perf/arch/arm64/Makefile
@@ -4,3 +4,24 @@ PERF_HAVE_DWARF_REGS := 1
 endif
 PERF_HAVE_JITDUMP := 1
 PERF_HAVE_ARCH_REGS_QUERY_REGISTER_OFFSET := 1
+#
+# Syscall table generation for perf
+#
+out    := $(OUTPUT)arch/arm64/include/generated/asm
+header := $(out)/syscalls.c
+sysdef := $(srctree)/tools/include/uapi/asm-generic/unistd.h
+sysprf := $(srctree)/tools/perf/arch/arm64/entry/syscalls/
+systbl := $(sysprf)/mksyscalltbl
+# Create output directory if not already present
+_dummy := $(shell [ -d '$(out)' ] || mkdir -p '$(out)')
+$(header): $(sysdef) $(systbl)
+        $(Q)$(SHELL) '$(systbl)' '$(CC)' '$(HOSTCC)' $(sysdef) > $@
+clean::
+        $(call QUIET_CLEAN, arm64) $(RM) $(header)
+archheaders: $(header)
diff --git a/tools/perf/arch/arm64/entry/syscalls/mksyscalltbl b/tools/perf/arch/arm64/entry/syscalls/mksyscalltbl
new file mode 100755
index 000000000000..52e197317d3e
--- /dev/null
+++ b/tools/perf/arch/arm64/entry/syscalls/mksyscalltbl
@@ -0,0 +1,62 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0
+#
+# Generate system call table for perf. Derived from
+# powerpc script.
+#
+# Copyright IBM Corp. 2017
+# Author(s):  Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
+# Changed by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
+# Changed by: Kim Phillips <kim.phillips@arm.com>
+gcc=$1
+hostcc=$2
+input=$3
+if ! test -r $input; then
+        echo "Could not read input file" >&2
+        exit 1
+fi
+create_table_from_c()
+{
+        local sc nr last_sc
+        create_table_exe=`mktemp /tmp/create-table-XXXXXX`
+        {
+        cat <<-_EoHEADER
+                #include <stdio.h>
+                #define __ARCH_WANT_RENAMEAT
+                #include "$input"
+                int main(int argc, char *argv[])
+                {
+        _EoHEADER
+        while read sc nr; do
+                printf "%s\n" " printf(\"\\t[%d] = \\\"$sc\\\",\\n\", __NR_$sc);"
+                last_sc=$sc
+        done
+        printf "%s\n" " printf(\"#define SYSCALLTBL_ARM64_MAX_ID %d\\n\", __NR_$last_sc);"
+        printf "}\n"
+        } | $hostcc -o $create_table_exe -x c -
+        $create_table_exe
+        rm -f $create_table_exe
+}
+create_table()
+{
+        echo "static const char *syscalltbl_arm64[] = {"
+        create_table_from_c
+        echo "};"
+}
+$gcc -E -dM -x c  $input               \
+        |sed -ne 's/^#define __NR_//p' \
+        |sort -t' ' -k2 -nu            \
+        |create_table
diff --git a/tools/perf/arch/powerpc/util/skip-callchain-idx.c b/tools/perf/arch/powerpc/util/skip-callchain-idx.c
index 3598b8b75d27..7c6eeb4633fe 100644
--- a/tools/perf/arch/powerpc/util/skip-callchain-idx.c
+++ b/tools/perf/arch/powerpc/util/skip-callchain-idx.c
@@ -58,9 +58,13 @@ static int check_return_reg(int ra_regno, Dwarf_Frame *frame)
        }
        /*
-         * Check if return address is on the stack.
+         * Check if return address is on the stack. If return address
+         * is in a register (typically R0), it is yet to be saved on
+         * the stack.
         */
-        if (nops != 0 || ops != NULL)
+        if ((nops != 0 || ops != NULL) &&
+                !(nops == 1 && ops[0].atom == DW_OP_regx &&
+                        ops[0].number2 == 0 && ops[0].offset == 0))
                return 0;
        /*
@@ -243,10 +247,10 @@ int arch_skip_callchain_idx(struct thread *thread, struct ip_callchain *chain)
        u64 ip;
        u64 skip_slot = -1;
-        if (chain->nr < 3)
+        if (!chain || chain->nr < 3)
                return skip_slot;
-        ip = chain->ips[2];
+        ip = chain->ips[1];
        thread__find_symbol(thread, PERF_RECORD_MISC_USER, ip, &al);
diff --git a/tools/perf/arch/s390/util/kvm-stat.c b/tools/perf/arch/s390/util/kvm-stat.c
index d233e2eb9592..aaabab5e2830 100644
--- a/tools/perf/arch/s390/util/kvm-stat.c
+++ b/tools/perf/arch/s390/util/kvm-stat.c
@@ -102,7 +102,7 @@ const char * const kvm_skip_events[] = {
 int cpu_isa_init(struct perf_kvm_stat *kvm, const char *cpuid)
 {
-        if (strstr(cpuid, "IBM/S390")) {
+        if (strstr(cpuid, "IBM")) {
                kvm->exit_reasons = sie_exit_reasons;
                kvm->exit_reasons_isa = "SIE";
        } else
diff --git a/tools/perf/arch/x86/entry/syscalls/syscall_64.tbl b/tools/perf/arch/x86/entry/syscalls/syscall_64.tbl
index 4dfe42666d0c..f0b1709a5ffb 100644
--- a/tools/perf/arch/x86/entry/syscalls/syscall_64.tbl
+++ b/tools/perf/arch/x86/entry/syscalls/syscall_64.tbl
@@ -341,6 +341,8 @@
 330     common  pkey_alloc              __x64_sys_pkey_alloc
 331     common  pkey_free               __x64_sys_pkey_free
 332     common  statx                   __x64_sys_statx
+333     common  io_pgetevents           __x64_sys_io_pgetevents
+334     common  rseq                    __x64_sys_rseq
 #
 # x32-specific system call numbers start at 512 to avoid cache impact
diff --git a/tools/perf/arch/x86/util/perf_regs.c b/tools/perf/arch/x86/util/perf_regs.c
index 4b2caf6d48e7..fead6b3b4206 100644
--- a/tools/perf/arch/x86/util/perf_regs.c
+++ b/tools/perf/arch/x86/util/perf_regs.c
@@ -226,7 +226,7 @@ int arch_sdt_arg_parse_op(char *old_op, char **new_op)
                else if (rm[2].rm_so != rm[2].rm_eo)
                        prefix[0] = '+';
                else
-                        strncpy(prefix, "+0", 2);
+                        scnprintf(prefix, sizeof(prefix), "+0");
        }
        /* Rename register */
diff --git a/tools/perf/arch/x86/util/pmu.c b/tools/perf/arch/x86/util/pmu.c
index 63a74c32ddc5..e33ef5bc31c5 100644
--- a/tools/perf/arch/x86/util/pmu.c
+++ b/tools/perf/arch/x86/util/pmu.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 #include <string.h>
+#include <linux/stddef.h>
 #include <linux/perf_event.h>
 #include "../../util/intel-pt.h"
diff --git a/tools/perf/arch/x86/util/tsc.c b/tools/perf/arch/x86/util/tsc.c
index 06bae7023a51..950539f9a4f7 100644
--- a/tools/perf/arch/x86/util/tsc.c
+++ b/tools/perf/arch/x86/util/tsc.c
@@ -2,6 +2,7 @@
 #include <stdbool.h>
 #include <errno.h>
+#include <linux/stddef.h>
 #include <linux/perf_event.h>
 #include "../../perf.h"
diff --git a/tools/perf/bench/Build b/tools/perf/bench/Build
index 60bf11943047..eafce1a130a1 100644
--- a/tools/perf/bench/Build
+++ b/tools/perf/bench/Build
@@ -7,6 +7,7 @@ perf-y += futex-wake-parallel.o
 perf-y += futex-requeue.o
 perf-y += futex-lock-pi.o
+perf-$(CONFIG_X86_64) += mem-memcpy-x86-64-lib.o
 perf-$(CONFIG_X86_64) += mem-memcpy-x86-64-asm.o
 perf-$(CONFIG_X86_64) += mem-memset-x86-64-asm.o
diff --git a/tools/perf/bench/mem-memcpy-x86-64-asm.S b/tools/perf/bench/mem-memcpy-x86-64-asm.S
index b43f8d2a34ec..9ad015a1e202 100644
--- a/tools/perf/bench/mem-memcpy-x86-64-asm.S
+++ b/tools/perf/bench/mem-memcpy-x86-64-asm.S
@@ -6,6 +6,7 @@
 #define altinstr_replacement text
 #define globl p2align 4; .globl
 #define _ASM_EXTABLE_FAULT(x, y)
+#define _ASM_EXTABLE(x, y)
 #include "../../arch/x86/lib/memcpy_64.S"
 /*
diff --git a/tools/perf/bench/mem-memcpy-x86-64-lib.c b/tools/perf/bench/mem-memcpy-x86-64-lib.c
new file mode 100644
index 000000000000..4130734dde84
--- /dev/null
+++ b/tools/perf/bench/mem-memcpy-x86-64-lib.c
@@ -0,0 +1,24 @@
+/*
+ * From code in arch/x86/lib/usercopy_64.c, copied to keep tools/ copy
+ * of the kernel's arch/x86/lib/memcpy_64.s used in 'perf bench mem memcpy'
+ * happy.
+ */
+#include <linux/types.h>
+unsigned long __memcpy_mcsafe(void *dst, const void *src, size_t cnt);
+unsigned long mcsafe_handle_tail(char *to, char *from, unsigned len);
+unsigned long mcsafe_handle_tail(char *to, char *from, unsigned len)
+{
+        for (; len; --len, to++, from++) {
+                /*
+                 * Call the assembly routine back directly since
+                 * memcpy_mcsafe() may silently fallback to memcpy.
+                 */
+                unsigned long rem = __memcpy_mcsafe(to, from, 1);
+                if (rem)
+                        break;
+        }
+        return len;
+}
diff --git a/tools/perf/bench/numa.c b/tools/perf/bench/numa.c
index 63eb49082774..44195514b19e 100644
--- a/tools/perf/bench/numa.c
+++ b/tools/perf/bench/numa.c
@@ -1098,7 +1098,7 @@ static void *worker_thread(void *__tdata)
        u8 *global_data;
        u8 *process_data;
        u8 *thread_data;
-        u64 bytes_done;
+        u64 bytes_done, secs;
        long work_done;
        u32 l;
        struct rusage rusage;
@@ -1254,7 +1254,8 @@ static void *worker_thread(void *__tdata)
        timersub(&stop, &start0, &diff);
        td->runtime_ns = diff.tv_sec * NSEC_PER_SEC;
        td->runtime_ns += diff.tv_usec * NSEC_PER_USEC;
-        td->speed_gbs = bytes_done / (td->runtime_ns / NSEC_PER_SEC) / 1e9;
+        secs = td->runtime_ns / NSEC_PER_SEC;
+        td->speed_gbs = secs ? bytes_done / secs / 1e9 : 0;
        getrusage(RUSAGE_THREAD, &rusage);
        td->system_time_ns = rusage.ru_stime.tv_sec * NSEC_PER_SEC;
diff --git a/tools/perf/builtin-annotate.c b/tools/perf/builtin-annotate.c
index 5eb22cc56363..8180319285af 100644
--- a/tools/perf/builtin-annotate.c
+++ b/tools/perf/builtin-annotate.c
@@ -283,6 +283,15 @@ out_put:
        return ret;
 }
+static int process_feature_event(struct perf_tool *tool,
+                                 union perf_event *event,
+                                 struct perf_session *session)
+{
+        if (event->feat.feat_id < HEADER_LAST_FEATURE)
+                return perf_event__process_feature(tool, event, session);
+        return 0;
+}
 static int hist_entry__tty_annotate(struct hist_entry *he,
                                    struct perf_evsel *evsel,
                                    struct perf_annotate *ann)
@@ -471,7 +480,7 @@ int cmd_annotate(int argc, const char **argv)
                        .attr   = perf_event__process_attr,
                        .build_id = perf_event__process_build_id,
                        .tracing_data   = perf_event__process_tracing_data,
-                        .feature        = perf_event__process_feature,
+                        .feature        = process_feature_event,
                        .ordered_events = true,
                        .ordering_requires_timestamps = true,
                },
diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c
index 307b3594525f..f3aa9d02a5ab 100644
--- a/tools/perf/builtin-c2c.c
+++ b/tools/perf/builtin-c2c.c
@@ -56,16 +56,16 @@ struct c2c_hist_entry {
        struct compute_stats     cstats;
+        unsigned long            paddr;
+        unsigned long            paddr_cnt;
+        bool                     paddr_zero;
+        char                    *nodestr;
        /*
         * must be at the end,
         * because of its callchain dynamic entry
         */
        struct hist_entry       he;
-        unsigned long            paddr;
-        unsigned long            paddr_cnt;
-        bool                     paddr_zero;
-        char                    *nodestr;
 };
 static char const *coalesce_default = "pid,iaddr";
@@ -2193,7 +2193,7 @@ static void print_cacheline(struct c2c_hists *c2c_hists,
        fprintf(out, "%s\n", bf);
        fprintf(out, "  -------------------------------------------------------------\n");
-        hists__fprintf(&c2c_hists->hists, false, 0, 0, 0, out, true);
+        hists__fprintf(&c2c_hists->hists, false, 0, 0, 0, out, false);
 }
 static void print_pareto(FILE *out)
@@ -2268,7 +2268,7 @@ static void perf_c2c__hists_fprintf(FILE *out, struct perf_session *session)
        fprintf(out, "=================================================\n");
        fprintf(out, "#\n");
-        hists__fprintf(&c2c.hists.hists, true, 0, 0, 0, stdout, false);
+        hists__fprintf(&c2c.hists.hists, true, 0, 0, 0, stdout, true);
        fprintf(out, "\n");
        fprintf(out, "=================================================\n");
@@ -2349,6 +2349,9 @@ static int perf_c2c__browse_cacheline(struct hist_entry *he)
        " s             Toggle full length of symbol and source line columns \n"
        " q             Return back to cacheline list \n";
+        if (!he)
+                return 0;
        /* Display compact version first. */
        c2c.symbol_full = false;
diff --git a/tools/perf/builtin-diff.c b/tools/perf/builtin-diff.c
index d660cb7b222b..39db2ee32d48 100644
--- a/tools/perf/builtin-diff.c
+++ b/tools/perf/builtin-diff.c
@@ -696,7 +696,7 @@ static void hists__process(struct hists *hists)
        hists__output_resort(hists, NULL);
        hists__fprintf(hists, !quiet, 0, 0, 0, stdout,
-                       symbol_conf.use_callchain);
+                       !symbol_conf.use_callchain);
 }
 static void data__fprintf(void)
diff --git a/tools/perf/builtin-report.c b/tools/perf/builtin-report.c
index cdb5b6949832..02f7a3c27761 100644
--- a/tools/perf/builtin-report.c
+++ b/tools/perf/builtin-report.c
@@ -217,7 +217,8 @@ static int process_feature_event(struct perf_tool *tool,
        }
        /*
-         * All features are received, we can force the
+         * (feat_id = HEADER_LAST_FEATURE) is the end marker which
+         * means all features are received, now we can force the
         * group if needed.
         */
        setup_forced_leader(rep, session->evlist);
@@ -477,8 +478,8 @@ static int perf_evlist__tty_browse_hists(struct perf_evlist *evlist,
                hists__fprintf_nr_sample_events(hists, rep, evname, stdout);
                hists__fprintf(hists, !quiet, 0, 0, rep->min_percent, stdout,
-                               symbol_conf.use_callchain ||
+                               !(symbol_conf.use_callchain ||
-                               symbol_conf.show_branchflag_count);
+                                 symbol_conf.show_branchflag_count));
                fprintf(stdout, "\n\n");
        }
diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c
index b3bf35512d21..568ddfac3213 100644
--- a/tools/perf/builtin-script.c
+++ b/tools/perf/builtin-script.c
@@ -180,6 +180,18 @@ static struct {
                                  PERF_OUTPUT_EVNAME | PERF_OUTPUT_TRACE
        },
+        [PERF_TYPE_HW_CACHE] = {
+                .user_set = false,
+                .fields = PERF_OUTPUT_COMM | PERF_OUTPUT_TID |
+                              PERF_OUTPUT_CPU | PERF_OUTPUT_TIME |
+                              PERF_OUTPUT_EVNAME | PERF_OUTPUT_IP |
+                              PERF_OUTPUT_SYM | PERF_OUTPUT_SYMOFFSET |
+                              PERF_OUTPUT_DSO | PERF_OUTPUT_PERIOD,
+                .invalid_fields = PERF_OUTPUT_TRACE | PERF_OUTPUT_BPF_OUTPUT,
+        },
        [PERF_TYPE_RAW] = {
                .user_set = false,
@@ -1822,6 +1834,7 @@ static int process_attr(struct perf_tool *tool, union perf_event *event,
        struct perf_evlist *evlist;
        struct perf_evsel *evsel, *pos;
        int err;
+        static struct perf_evsel_script *es;
        err = perf_event__process_attr(tool, event, pevlist);
        if (err)
@@ -1830,6 +1843,19 @@ static int process_attr(struct perf_tool *tool, union perf_event *event,
        evlist = *pevlist;
        evsel = perf_evlist__last(*pevlist);
+        if (!evsel->priv) {
+                if (scr->per_event_dump) {
+                        evsel->priv = perf_evsel_script__new(evsel,
+                                                scr->session->data);
+                } else {
+                        es = zalloc(sizeof(*es));
+                        if (!es)
+                                return -ENOMEM;
+                        es->fp = stdout;
+                        evsel->priv = es;
+                }
+        }
        if (evsel->attr.type >= PERF_TYPE_MAX &&
            evsel->attr.type != PERF_TYPE_SYNTH)
                return 0;
@@ -3018,6 +3044,15 @@ int process_cpu_map_event(struct perf_tool *tool __maybe_unused,
        return set_maps(script);
 }
+static int process_feature_event(struct perf_tool *tool,
+                                 union perf_event *event,
+                                 struct perf_session *session)
+{
+        if (event->feat.feat_id < HEADER_LAST_FEATURE)
+                return perf_event__process_feature(tool, event, session);
+        return 0;
+}
 #ifdef HAVE_AUXTRACE_SUPPORT
 static int perf_script__process_auxtrace_info(struct perf_tool *tool,
                                              union perf_event *event,
@@ -3062,7 +3097,7 @@ int cmd_script(int argc, const char **argv)
                        .attr            = process_attr,
                        .event_update   = perf_event__process_event_update,
                        .tracing_data    = perf_event__process_tracing_data,
-                        .feature         = perf_event__process_feature,
+                        .feature         = process_feature_event,
                        .build_id        = perf_event__process_build_id,
                        .id_index        = perf_event__process_id_index,
                        .auxtrace_info   = perf_script__process_auxtrace_info,
@@ -3113,8 +3148,9 @@ int cmd_script(int argc, const char **argv)
                     "+field to add and -field to remove."
                     "Valid types: hw,sw,trace,raw,synth. "
                     "Fields: comm,tid,pid,time,cpu,event,trace,ip,sym,dso,"
-                     "addr,symoff,period,iregs,uregs,brstack,brstacksym,flags,"
+                     "addr,symoff,srcline,period,iregs,uregs,brstack,"
-                     "bpf-output,callindent,insn,insnlen,brstackinsn,synth,phys_addr",
+                     "brstacksym,flags,bpf-output,brstackinsn,brstackoff,"
+                     "callindent,insn,insnlen,synth,phys_addr,metric,misc",
                     parse_output_fields),
        OPT_BOOLEAN('a', "all-cpus", &system_wide,
                    "system-wide collection from all CPUs"),
diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c
index 096ccb25c11f..d097b5b47eb8 100644
--- a/tools/perf/builtin-stat.c
+++ b/tools/perf/builtin-stat.c
@@ -65,6 +65,7 @@
 #include "util/tool.h"
 #include "util/string2.h"
 #include "util/metricgroup.h"
+#include "util/top.h"
 #include "asm/bug.h"
 #include <linux/time64.h>
@@ -144,6 +145,8 @@ static struct target target = {
 typedef int (*aggr_get_id_t)(struct cpu_map *m, int cpu);
+#define METRIC_ONLY_LEN 20
 static int                      run_count                       =  1;
 static bool                     no_inherit                      = false;
 static volatile pid_t           child_pid                       = -1;
@@ -173,6 +176,7 @@ static struct cpu_map		*aggr_map;
 static aggr_get_id_t            aggr_get_id;
 static bool                     append_file;
 static bool                     interval_count;
+static bool                     interval_clear;
 static const char               *output_name;
 static int                      output_fd;
 static int                      print_free_counters_hint;
@@ -180,6 +184,7 @@ static int			print_mixed_hw_group_error;
 static u64                      *walltime_run;
 static bool                     ru_display                      = false;
 static struct rusage            ru_data;
+static unsigned int             metric_only_len                 = METRIC_ONLY_LEN;
 struct perf_stat {
        bool                     record;
@@ -291,18 +296,6 @@ static int create_perf_stat_counter(struct perf_evsel *evsel)
        return perf_evsel__open_per_thread(evsel, evsel_list->threads);
 }
-/*
- * Does the counter have nsecs as a unit?
- */
-static inline int nsec_counter(struct perf_evsel *evsel)
-{
-        if (perf_evsel__match(evsel, SOFTWARE, SW_CPU_CLOCK) ||
-            perf_evsel__match(evsel, SOFTWARE, SW_TASK_CLOCK))
-                return 1;
-        return 0;
-}
 static int process_synthesized_event(struct perf_tool *tool __maybe_unused,
                                     union perf_event *event,
                                     struct perf_sample *sample __maybe_unused,
@@ -967,8 +960,6 @@ static void print_metric_csv(void *ctx,
        fprintf(out, "%s%s%s%s", csv_sep, vals, csv_sep, unit);
 }
-#define METRIC_ONLY_LEN 20
 /* Filter out some columns that don't work well in metrics only mode */
 static bool valid_only_metric(const char *unit)
@@ -999,22 +990,20 @@ static void print_metric_only(void *ctx, const char *color, const char *fmt,
 {
        struct outstate *os = ctx;
        FILE *out = os->fh;
-        int n;
+        char buf[1024], str[1024];
-        char buf[1024];
+        unsigned mlen = metric_only_len;
-        unsigned mlen = METRIC_ONLY_LEN;
        if (!valid_only_metric(unit))
                return;
        unit = fixunit(buf, os->evsel, unit);
-        if (color)
-                n = color_fprintf(out, color, fmt, val);
-        else
-                n = fprintf(out, fmt, val);
-        if (n > METRIC_ONLY_LEN)
-                n = METRIC_ONLY_LEN;
        if (mlen < strlen(unit))
                mlen = strlen(unit) + 1;
-        fprintf(out, "%*s", mlen - n, "");
+        if (color)
+                mlen += strlen(color) + sizeof(PERF_COLOR_RESET) - 1;
+        color_snprintf(str, sizeof(str), color ?: "", fmt, val);
+        fprintf(out, "%*s ", mlen, str);
 }
 static void print_metric_only_csv(void *ctx, const char *color __maybe_unused,
@@ -1054,35 +1043,7 @@ static void print_metric_header(void *ctx, const char *color __maybe_unused,
        if (csv_output)
                fprintf(os->fh, "%s%s", unit, csv_sep);
        else
-                fprintf(os->fh, "%-*s ", METRIC_ONLY_LEN, unit);
+                fprintf(os->fh, "%*s ", metric_only_len, unit);
-}
-static void nsec_printout(int id, int nr, struct perf_evsel *evsel, double avg)
-{
-        FILE *output = stat_config.output;
-        double msecs = avg / NSEC_PER_MSEC;
-        const char *fmt_v, *fmt_n;
-        char name[25];
-        fmt_v = csv_output ? "%.6f%s" : "%18.6f%s";
-        fmt_n = csv_output ? "%s" : "%-25s";
-        aggr_printout(evsel, id, nr);
-        scnprintf(name, sizeof(name), "%s%s",
-                  perf_evsel__name(evsel), csv_output ? "" : " (msec)");
-        fprintf(output, fmt_v, msecs, csv_sep);
-        if (csv_output)
-                fprintf(output, "%s%s", evsel->unit, csv_sep);
-        else
-                fprintf(output, "%-*s%s", unit_width, evsel->unit, csv_sep);
-        fprintf(output, fmt_n, name);
-        if (evsel->cgrp)
-                fprintf(output, "%s%s", csv_sep, evsel->cgrp->name);
 }
 static int first_shadow_cpu(struct perf_evsel *evsel, int id)
@@ -1240,11 +1201,7 @@ static void printout(int id, int nr, struct perf_evsel *counter, double uval,
                return;
        }
-        if (metric_only)
+        if (!metric_only)
-                /* nothing */;
-        else if (nsec_counter(counter))
-                nsec_printout(id, nr, counter, uval);
-        else
                abs_printout(id, nr, counter, uval);
        out.print_metric = pm;
@@ -1330,7 +1287,7 @@ static void collect_all_aliases(struct perf_evsel *counter,
                    alias->scale != counter->scale ||
                    alias->cgrp != counter->cgrp ||
                    strcmp(alias->unit, counter->unit) ||
-                    nsec_counter(alias) != nsec_counter(counter))
+                    perf_evsel__is_clock(alias) != perf_evsel__is_clock(counter))
                        break;
                alias->merged_stat = true;
                cb(alias, data, false);
@@ -1704,9 +1661,12 @@ static void print_interval(char *prefix, struct timespec *ts)
        FILE *output = stat_config.output;
        static int num_print_interval;
+        if (interval_clear)
+                puts(CONSOLE_CLEAR);
        sprintf(prefix, "%6lu.%09lu%s", ts->tv_sec, ts->tv_nsec, csv_sep);
-        if (num_print_interval == 0 && !csv_output) {
+        if ((num_print_interval == 0 && !csv_output) || interval_clear) {
                switch (stat_config.aggr_mode) {
                case AGGR_SOCKET:
                        fprintf(output, "#           time socket cpus");
@@ -1719,7 +1679,7 @@ static void print_interval(char *prefix, struct timespec *ts)
                                fprintf(output, "             counts %*s events\n", unit_width, "unit");
                        break;
                case AGGR_NONE:
-                        fprintf(output, "#           time CPU");
+                        fprintf(output, "#           time CPU    ");
                        if (!metric_only)
                                fprintf(output, "                counts %*s events\n", unit_width, "unit");
                        break;
@@ -1738,7 +1698,7 @@ static void print_interval(char *prefix, struct timespec *ts)
                }
        }
-        if (num_print_interval == 0 && metric_only)
+        if ((num_print_interval == 0 || interval_clear) && metric_only)
                print_metric_headers(" ", true);
        if (++num_print_interval == 25)
                num_print_interval = 0;
@@ -2057,6 +2017,8 @@ static const struct option stat_options[] = {
                    "(overhead is possible for values <= 100ms)"),
        OPT_INTEGER(0, "interval-count", &stat_config.times,
                    "print counts for fixed number of times"),
+        OPT_BOOLEAN(0, "interval-clear", &interval_clear,
+                    "clear screen in between new interval"),
        OPT_UINTEGER(0, "timeout", &stat_config.timeout,
                    "stop workload and print counts after a timeout period in ms (>= 10ms)"),
        OPT_SET_UINT(0, "per-socket", &stat_config.aggr_mode,
@@ -2436,13 +2398,24 @@ static int add_default_attributes(void)
        (PERF_COUNT_HW_CACHE_OP_PREFETCH        <<  8) |
        (PERF_COUNT_HW_CACHE_RESULT_MISS        << 16)                          },
 };
+        struct parse_events_error errinfo;
        /* Set attrs if no event is selected and !null_run: */
        if (null_run)
                return 0;
        if (transaction_run) {
-                struct parse_events_error errinfo;
+                /* Handle -T as -M transaction. Once platform specific metrics
+                 * support has been added to the json files, all archictures
+                 * will use this approach. To determine transaction support
+                 * on an architecture test for such a metric name.
+                 */
+                if (metricgroup__has_metric("transaction")) {
+                        struct option opt = { .value = &evsel_list };
+                        return metricgroup__parse_groups(&opt, "transaction",
+                                                         &metric_events);
+                }
                if (pmu_have_event("cpu", "cycles-ct") &&
                    pmu_have_event("cpu", "el-start"))
@@ -2454,6 +2427,7 @@ static int add_default_attributes(void)
                                           &errinfo);
                if (err) {
                        fprintf(stderr, "Cannot set up transaction events\n");
+                        parse_events_print_error(&errinfo, transaction_attrs);
                        return -1;
                }
                return 0;
@@ -2479,10 +2453,11 @@ static int add_default_attributes(void)
                    pmu_have_event("msr", "smi")) {
                        if (!force_metric_only)
                                metric_only = true;
-                        err = parse_events(evsel_list, smi_cost_attrs, NULL);
+                        err = parse_events(evsel_list, smi_cost_attrs, &errinfo);
                } else {
                        fprintf(stderr, "To measure SMI cost, it needs "
                                "msr/aperf/, msr/smi/ and cpu/cycles/ support\n");
+                        parse_events_print_error(&errinfo, smi_cost_attrs);
                        return -1;
                }
                if (err) {
@@ -2517,12 +2492,13 @@ static int add_default_attributes(void)
                if (topdown_attrs[0] && str) {
                        if (warn)
                                arch_topdown_group_warn();
-                        err = parse_events(evsel_list, str, NULL);
+                        err = parse_events(evsel_list, str, &errinfo);
                        if (err) {
                                fprintf(stderr,
                                        "Cannot set up top down events %s: %d\n",
                                        str, err);
                                free(str);
+                                parse_events_print_error(&errinfo, str);
                                return -1;
                        }
                } else {
diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c
index ffdc2769ff9f..d21d8751e749 100644
--- a/tools/perf/builtin-top.c
+++ b/tools/perf/builtin-top.c
@@ -307,7 +307,7 @@ static void perf_top__print_sym_table(struct perf_top *top)
        hists__output_recalc_col_len(hists, top->print_entries - printed);
        putchar('\n');
        hists__fprintf(hists, false, top->print_entries - printed, win_width,
-                       top->min_percent, stdout, symbol_conf.use_callchain);
+                       top->min_percent, stdout, !symbol_conf.use_callchain);
 }
 static void prompt_integer(int *target, const char *msg)
diff --git a/tools/perf/builtin-trace.c b/tools/perf/builtin-trace.c
index 6a748eca2edb..88561eed7950 100644
--- a/tools/perf/builtin-trace.c
+++ b/tools/perf/builtin-trace.c
@@ -291,7 +291,7 @@ size_t strarray__scnprintf(struct strarray *sa, char *bf, size_t size, const cha
 {
        int idx = val - sa->offset;
-        if (idx < 0 || idx >= sa->nr_entries)
+        if (idx < 0 || idx >= sa->nr_entries || sa->entries[idx] == NULL)
                return scnprintf(bf, size, intfmt, val);
        return scnprintf(bf, size, "%s", sa->entries[idx]);
@@ -761,10 +761,12 @@ static struct syscall_fmt {
          .arg = { [0] = STRARRAY(resource, rlimit_resources), }, },
        { .name     = "socket",
          .arg = { [0] = STRARRAY(family, socket_families),
-                   [1] = { .scnprintf = SCA_SK_TYPE, /* type */ }, }, },
+                   [1] = { .scnprintf = SCA_SK_TYPE, /* type */ },
+                   [2] = { .scnprintf = SCA_SK_PROTO, /* protocol */ }, }, },
        { .name     = "socketpair",
          .arg = { [0] = STRARRAY(family, socket_families),
-                   [1] = { .scnprintf = SCA_SK_TYPE, /* type */ }, }, },
+                   [1] = { .scnprintf = SCA_SK_TYPE, /* type */ },
+                   [2] = { .scnprintf = SCA_SK_PROTO, /* protocol */ }, }, },
        { .name     = "stat", .alias = "newstat", },
        { .name     = "statx",
          .arg = { [0] = { .scnprintf = SCA_FDAT,        /* fdat */ },
@@ -2990,6 +2992,7 @@ static int trace__parse_events_option(const struct option *opt, const char *str,
                if (trace__validate_ev_qualifier(trace))
                        goto out;
+                trace->trace_syscalls = true;
        }
        err = 0;
@@ -3045,7 +3048,7 @@ int cmd_trace(int argc, const char **argv)
                },
                .output = stderr,
                .show_comm = true,
-                .trace_syscalls = true,
+                .trace_syscalls = false,
                .kernel_syscallchains = false,
                .max_stack = UINT_MAX,
        };
@@ -3191,13 +3194,7 @@ int cmd_trace(int argc, const char **argv)
        if (!trace.trace_syscalls && !trace.trace_pgfaults &&
            trace.evlist->nr_entries == 0 /* Was --events used? */) {
-                pr_err("Please specify something to trace.\n");
+                trace.trace_syscalls = true;
-                return -1;
-        }
-        if (!trace.trace_syscalls && trace.ev_qualifier) {
-                pr_err("The -e option can't be used with --no-syscalls.\n");
-                goto out;
        }
        if (output_name != NULL) {
diff --git a/tools/perf/check-headers.sh b/tools/perf/check-headers.sh
index 10f333e2e825..de28466c0186 100755
--- a/tools/perf/check-headers.sh
+++ b/tools/perf/check-headers.sh
@@ -7,6 +7,7 @@ include/uapi/drm/i915_drm.h
 include/uapi/linux/fcntl.h
 include/uapi/linux/kcmp.h
 include/uapi/linux/kvm.h
+include/uapi/linux/in.h
 include/uapi/linux/perf_event.h
 include/uapi/linux/prctl.h
 include/uapi/linux/sched.h
@@ -35,6 +36,7 @@ arch/s390/include/uapi/asm/ptrace.h
 arch/s390/include/uapi/asm/sie.h
 arch/arm/include/uapi/asm/kvm.h
 arch/arm64/include/uapi/asm/kvm.h
+arch/arm64/include/uapi/asm/unistd.h
 arch/alpha/include/uapi/asm/errno.h
 arch/mips/include/asm/errno.h
 arch/mips/include/uapi/asm/errno.h
@@ -53,6 +55,7 @@ include/uapi/asm-generic/errno.h
 include/uapi/asm-generic/errno-base.h
 include/uapi/asm-generic/ioctls.h
 include/uapi/asm-generic/mman-common.h
+include/uapi/asm-generic/unistd.h
 '
 check_2 () {
diff --git a/tools/perf/include/bpf/bpf.h b/tools/perf/include/bpf/bpf.h
index dd764ad5efdf..a63aa6241b7f 100644
--- a/tools/perf/include/bpf/bpf.h
+++ b/tools/perf/include/bpf/bpf.h
@@ -1,6 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0
 #ifndef _PERF_BPF_H
 #define _PERF_BPF_H
+#include <uapi/linux/bpf.h>
 #define SEC(NAME) __attribute__((section(NAME),  used))
 #define probe(function, vars) \
diff --git a/tools/perf/jvmti/jvmti_agent.c b/tools/perf/jvmti/jvmti_agent.c
index 0c6d1002b524..ac1bcdc17dae 100644
--- a/tools/perf/jvmti/jvmti_agent.c
+++ b/tools/perf/jvmti/jvmti_agent.c
@@ -35,6 +35,7 @@
 #include <sys/mman.h>
 #include <syscall.h> /* for gettid() */
 #include <err.h>
+#include <linux/kernel.h>
 #include "jvmti_agent.h"
 #include "../util/jitdump.h"
@@ -249,7 +250,7 @@ void *jvmti_open(void)
        /*
         * jitdump file name
         */
-        snprintf(dump_path, PATH_MAX, "%s/jit-%i.dump", jit_path, getpid());
+        scnprintf(dump_path, PATH_MAX, "%s/jit-%i.dump", jit_path, getpid());
        fd = open(dump_path, O_CREAT|O_TRUNC|O_RDWR, 0666);
        if (fd == -1)
diff --git a/tools/perf/perf.h b/tools/perf/perf.h
index a1a97956136f..21bf7f5a3cf5 100644
--- a/tools/perf/perf.h
+++ b/tools/perf/perf.h
@@ -5,6 +5,7 @@
 #include <time.h>
 #include <stdbool.h>
 #include <linux/types.h>
+#include <linux/stddef.h>
 #include <linux/perf_event.h>
 extern bool test_attr__enabled;
@@ -24,7 +25,9 @@ static inline unsigned long long rdclock(void)
        return ts.tv_sec * 1000000000ULL + ts.tv_nsec;
 }
+#ifndef MAX_NR_CPUS
 #define MAX_NR_CPUS                     1024
+#endif
 extern const char *input_name;
 extern bool perf_host, perf_guest;
diff --git a/tools/perf/pmu-events/Build b/tools/perf/pmu-events/Build
index 17783913d330..215ba30b8534 100644
--- a/tools/perf/pmu-events/Build
+++ b/tools/perf/pmu-events/Build
@@ -1,7 +1,7 @@
 hostprogs := jevents
 jevents-y       += json.o jsmn.o jevents.o
-CHOSTFLAGS_jevents.o    = -I$(srctree)/tools/include
+HOSTCFLAGS_jevents.o    = -I$(srctree)/tools/include
 pmu-events-y    += pmu-events.o
 JDIR            =  pmu-events/arch/$(SRCARCH)
 JSON            =  $(shell [ -d $(JDIR) ] &&                            \
diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
index bc03c06c3918..752e47eb6977 100644
--- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
+++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
@@ -12,6 +12,21 @@
        "ArchStdEvent": "L1D_CACHE_REFILL_WR",
    },
    {
+        "ArchStdEvent": "L1D_CACHE_REFILL_INNER",
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_REFILL_OUTER",
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_WB_CLEAN",
+    },
+    {
+        "ArchStdEvent": "L1D_CACHE_INVAL",
+    },
+    {
        "ArchStdEvent": "L1D_TLB_REFILL_RD",
    },
    {
@@ -24,9 +39,75 @@
        "ArchStdEvent": "L1D_TLB_WR",
    },
    {
+        "ArchStdEvent": "L2D_TLB_REFILL_RD",
+    },
+    {
+        "ArchStdEvent": "L2D_TLB_REFILL_WR",
+    },
+    {
+        "ArchStdEvent": "L2D_TLB_RD",
+    },
+    {
+        "ArchStdEvent": "L2D_TLB_WR",
+    },
+    {
        "ArchStdEvent": "BUS_ACCESS_RD",
-   },
+    },
-   {
+    {
        "ArchStdEvent": "BUS_ACCESS_WR",
-   }
+    },
+    {
+        "ArchStdEvent": "MEM_ACCESS_RD",
+    },
+    {
+        "ArchStdEvent": "MEM_ACCESS_WR",
+    },
+    {
+        "ArchStdEvent": "UNALIGNED_LD_SPEC",
+    },
+    {
+        "ArchStdEvent": "UNALIGNED_ST_SPEC",
+    },
+    {
+        "ArchStdEvent": "UNALIGNED_LDST_SPEC",
+    },
+    {
+        "ArchStdEvent": "EXC_UNDEF",
+    },
+    {
+        "ArchStdEvent": "EXC_SVC",
+    },
+    {
+        "ArchStdEvent": "EXC_PABORT",
+    },
+    {
+        "ArchStdEvent": "EXC_DABORT",
+    },
+    {
+        "ArchStdEvent": "EXC_IRQ",
+    },
+    {
+        "ArchStdEvent": "EXC_FIQ",
+    },
+    {
+        "ArchStdEvent": "EXC_SMC",
+    },
+    {
+        "ArchStdEvent": "EXC_HVC",
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_PABORT",
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_DABORT",
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_OTHER",
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_IRQ",
+    },
+    {
+        "ArchStdEvent": "EXC_TRAP_FIQ",
+    }
 ]
diff --git a/tools/perf/pmu-events/arch/s390/cf_z10/basic.json b/tools/perf/pmu-events/arch/s390/cf_z10/basic.json
index 8bf16759ca53..2dd8dafff2ef 100644
--- a/tools/perf/pmu-events/arch/s390/cf_z10/basic.json
+++ b/tools/perf/pmu-events/arch/s390/cf_z10/basic.json
@@ -1,71 +1,83 @@
 [
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "0",
                "EventName": "CPU_CYCLES",
                "BriefDescription": "CPU Cycles",
                "PublicDescription": "Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "1",
                "EventName": "INSTRUCTIONS",
                "BriefDescription": "Instructions",
                "PublicDescription": "Instruction Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "2",
                "EventName": "L1I_DIR_WRITES",
                "BriefDescription": "L1I Directory Writes",
                "PublicDescription": "Level-1 I-Cache Directory Write Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "3",
                "EventName": "L1I_PENALTY_CYCLES",
                "BriefDescription": "L1I Penalty Cycles",
                "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "4",
                "EventName": "L1D_DIR_WRITES",
                "BriefDescription": "L1D Directory Writes",
                "PublicDescription": "Level-1 D-Cache Directory Write Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "5",
                "EventName": "L1D_PENALTY_CYCLES",
                "BriefDescription": "L1D Penalty Cycles",
                "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "32",
                "EventName": "PROBLEM_STATE_CPU_CYCLES",
                "BriefDescription": "Problem-State CPU Cycles",
                "PublicDescription": "Problem-State Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "33",
                "EventName": "PROBLEM_STATE_INSTRUCTIONS",
                "BriefDescription": "Problem-State Instructions",
                "PublicDescription": "Problem-State Instruction Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "34",
                "EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
                "BriefDescription": "Problem-State L1I Directory Writes",
                "PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "35",
                "EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
                "BriefDescription": "Problem-State L1I Penalty Cycles",
                "PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "36",
                "EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
                "BriefDescription": "Problem-State L1D Directory Writes",
                "PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "37",
                "EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
                "BriefDescription": "Problem-State L1D Penalty Cycles",
diff --git a/tools/perf/pmu-events/arch/s390/cf_z10/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z10/crypto.json
index 7e5b72492141..db286f19e7b6 100644
--- a/tools/perf/pmu-events/arch/s390/cf_z10/crypto.json
+++ b/tools/perf/pmu-events/arch/s390/cf_z10/crypto.json
@@ -1,95 +1,111 @@
 [
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "64",
                "EventName": "PRNG_FUNCTIONS",
                "BriefDescription": "PRNG Functions",
                "PublicDescription": "Total number of the PRNG functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "65",
                "EventName": "PRNG_CYCLES",
                "BriefDescription": "PRNG Cycles",
                "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "66",
                "EventName": "PRNG_BLOCKED_FUNCTIONS",
                "BriefDescription": "PRNG Blocked Functions",
                "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "67",
                "EventName": "PRNG_BLOCKED_CYCLES",
                "BriefDescription": "PRNG Blocked Cycles",
                "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "68",
                "EventName": "SHA_FUNCTIONS",
                "BriefDescription": "SHA Functions",
                "PublicDescription": "Total number of SHA functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "69",
                "EventName": "SHA_CYCLES",
                "BriefDescription": "SHA Cycles",
                "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "70",
                "EventName": "SHA_BLOCKED_FUNCTIONS",
                "BriefDescription": "SHA Blocked Functions",
                "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "71",
                "EventName": "SHA_BLOCKED_CYCLES",
                "BriefDescription": "SHA Bloced Cycles",
                "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "72",
                "EventName": "DEA_FUNCTIONS",
                "BriefDescription": "DEA Functions",
                "PublicDescription": "Total number of the DEA functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "73",
                "EventName": "DEA_CYCLES",
                "BriefDescription": "DEA Cycles",
                "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "74",
                "EventName": "DEA_BLOCKED_FUNCTIONS",
                "BriefDescription": "DEA Blocked Functions",
                "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "75",
                "EventName": "DEA_BLOCKED_CYCLES",
                "BriefDescription": "DEA Blocked Cycles",
                "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "76",
                "EventName": "AES_FUNCTIONS",
                "BriefDescription": "AES Functions",
                "PublicDescription": "Total number of AES functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "77",
                "EventName": "AES_CYCLES",
                "BriefDescription": "AES Cycles",
                "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "78",
                "EventName": "AES_BLOCKED_FUNCTIONS",
                "BriefDescription": "AES Blocked Functions",
                "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "79",
                "EventName": "AES_BLOCKED_CYCLES",
                "BriefDescription": "AES Blocked Cycles",
diff --git a/tools/perf/pmu-events/arch/s390/cf_z10/extended.json b/tools/perf/pmu-events/arch/s390/cf_z10/extended.json
index 0feedb40f30f..b6b7f29ca831 100644
--- a/tools/perf/pmu-events/arch/s390/cf_z10/extended.json
+++ b/tools/perf/pmu-events/arch/s390/cf_z10/extended.json
@@ -1,107 +1,125 @@
 [
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "128",
                "EventName": "L1I_L2_SOURCED_WRITES",
                "BriefDescription": "L1I L2 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from the Level-2 (L1.5) cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "129",
                "EventName": "L1D_L2_SOURCED_WRITES",
                "BriefDescription": "L1D L2 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from the Level-2 (L1.5) cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "130",
                "EventName": "L1I_L3_LOCAL_WRITES",
                "BriefDescription": "L1I L3 Local Writes",
                "PublicDescription": "A directory write to the Level-1 I-Cache directory where the installed cache line was sourced from the Level-3 cache that is on the same book as the Instruction cache (Local L2 cache)"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "131",
                "EventName": "L1D_L3_LOCAL_WRITES",
                "BriefDescription": "L1D L3 Local Writes",
                "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installtion cache line was source from the Level-3 cache that is on the same book as the Data cache (Local L2 cache)"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "132",
                "EventName": "L1I_L3_REMOTE_WRITES",
                "BriefDescription": "L1I L3 Remote Writes",
                "PublicDescription": "A directory write to the Level-1 I-Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Instruction cache (Remote L2 cache)"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "133",
                "EventName": "L1D_L3_REMOTE_WRITES",
                "BriefDescription": "L1D L3 Remote Writes",
                "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Data cache (Remote L2 cache)"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "134",
                "EventName": "L1D_LMEM_SOURCED_WRITES",
                "BriefDescription": "L1D Local Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "135",
                "EventName": "L1I_LMEM_SOURCED_WRITES",
                "BriefDescription": "L1I Local Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 I-Cache where the installed cache line was sourced from memory that is attached to the s ame book as the Instruction cache (Local Memory)"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "136",
                "EventName": "L1D_RO_EXCL_WRITES",
                "BriefDescription": "L1D Read-only Exclusive Writes",
                "PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "137",
                "EventName": "L1I_CACHELINE_INVALIDATES",
                "BriefDescription": "L1I Cacheline Invalidates",
                "PublicDescription": "A cache line in the Level-1 I-Cache has been invalidated by a store on the same CPU as the Level-1 I-Cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "138",
                "EventName": "ITLB1_WRITES",
                "BriefDescription": "ITLB1 Writes",
                "PublicDescription": "A translation entry has been written into the Level-1 Instruction Translation Lookaside Buffer"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "139",
                "EventName": "DTLB1_WRITES",
                "BriefDescription": "DTLB1 Writes",
                "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "140",
                "EventName": "TLB2_PTE_WRITES",
                "BriefDescription": "TLB2 PTE Writes",
                "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "141",
                "EventName": "TLB2_CRSTE_WRITES",
                "BriefDescription": "TLB2 CRSTE Writes",
                "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "142",
                "EventName": "TLB2_CRSTE_HPAGE_WRITES",
                "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
                "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "145",
                "EventName": "ITLB1_MISSES",
                "BriefDescription": "ITLB1 Misses",
                "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "146",
                "EventName": "DTLB1_MISSES",
                "BriefDescription": "DTLB1 Misses",
                "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle an DTLB1 miss is in progress"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "147",
                "EventName": "L2C_STORES_SENT",
                "BriefDescription": "L2C Stores Sent",
diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/basic.json b/tools/perf/pmu-events/arch/s390/cf_z13/basic.json
index 8bf16759ca53..2dd8dafff2ef 100644
--- a/tools/perf/pmu-events/arch/s390/cf_z13/basic.json
+++ b/tools/perf/pmu-events/arch/s390/cf_z13/basic.json
@@ -1,71 +1,83 @@
 [
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "0",
                "EventName": "CPU_CYCLES",
                "BriefDescription": "CPU Cycles",
                "PublicDescription": "Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "1",
                "EventName": "INSTRUCTIONS",
                "BriefDescription": "Instructions",
                "PublicDescription": "Instruction Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "2",
                "EventName": "L1I_DIR_WRITES",
                "BriefDescription": "L1I Directory Writes",
                "PublicDescription": "Level-1 I-Cache Directory Write Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "3",
                "EventName": "L1I_PENALTY_CYCLES",
                "BriefDescription": "L1I Penalty Cycles",
                "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "4",
                "EventName": "L1D_DIR_WRITES",
                "BriefDescription": "L1D Directory Writes",
                "PublicDescription": "Level-1 D-Cache Directory Write Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "5",
                "EventName": "L1D_PENALTY_CYCLES",
                "BriefDescription": "L1D Penalty Cycles",
                "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "32",
                "EventName": "PROBLEM_STATE_CPU_CYCLES",
                "BriefDescription": "Problem-State CPU Cycles",
                "PublicDescription": "Problem-State Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "33",
                "EventName": "PROBLEM_STATE_INSTRUCTIONS",
                "BriefDescription": "Problem-State Instructions",
                "PublicDescription": "Problem-State Instruction Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "34",
                "EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
                "BriefDescription": "Problem-State L1I Directory Writes",
                "PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "35",
                "EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
                "BriefDescription": "Problem-State L1I Penalty Cycles",
                "PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "36",
                "EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
                "BriefDescription": "Problem-State L1D Directory Writes",
                "PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "37",
                "EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
                "BriefDescription": "Problem-State L1D Penalty Cycles",
diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z13/crypto.json
index 7e5b72492141..db286f19e7b6 100644
--- a/tools/perf/pmu-events/arch/s390/cf_z13/crypto.json
+++ b/tools/perf/pmu-events/arch/s390/cf_z13/crypto.json
@@ -1,95 +1,111 @@
 [
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "64",
                "EventName": "PRNG_FUNCTIONS",
                "BriefDescription": "PRNG Functions",
                "PublicDescription": "Total number of the PRNG functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "65",
                "EventName": "PRNG_CYCLES",
                "BriefDescription": "PRNG Cycles",
                "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "66",
                "EventName": "PRNG_BLOCKED_FUNCTIONS",
                "BriefDescription": "PRNG Blocked Functions",
                "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "67",
                "EventName": "PRNG_BLOCKED_CYCLES",
                "BriefDescription": "PRNG Blocked Cycles",
                "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "68",
                "EventName": "SHA_FUNCTIONS",
                "BriefDescription": "SHA Functions",
                "PublicDescription": "Total number of SHA functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "69",
                "EventName": "SHA_CYCLES",
                "BriefDescription": "SHA Cycles",
                "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "70",
                "EventName": "SHA_BLOCKED_FUNCTIONS",
                "BriefDescription": "SHA Blocked Functions",
                "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "71",
                "EventName": "SHA_BLOCKED_CYCLES",
                "BriefDescription": "SHA Bloced Cycles",
                "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "72",
                "EventName": "DEA_FUNCTIONS",
                "BriefDescription": "DEA Functions",
                "PublicDescription": "Total number of the DEA functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "73",
                "EventName": "DEA_CYCLES",
                "BriefDescription": "DEA Cycles",
                "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "74",
                "EventName": "DEA_BLOCKED_FUNCTIONS",
                "BriefDescription": "DEA Blocked Functions",
                "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "75",
                "EventName": "DEA_BLOCKED_CYCLES",
                "BriefDescription": "DEA Blocked Cycles",
                "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "76",
                "EventName": "AES_FUNCTIONS",
                "BriefDescription": "AES Functions",
                "PublicDescription": "Total number of AES functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "77",
                "EventName": "AES_CYCLES",
                "BriefDescription": "AES Cycles",
                "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "78",
                "EventName": "AES_BLOCKED_FUNCTIONS",
                "BriefDescription": "AES Blocked Functions",
                "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "79",
                "EventName": "AES_BLOCKED_CYCLES",
                "BriefDescription": "AES Blocked Cycles",
diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/extended.json b/tools/perf/pmu-events/arch/s390/cf_z13/extended.json
index 9a002b6967f1..436ce33f1182 100644
--- a/tools/perf/pmu-events/arch/s390/cf_z13/extended.json
+++ b/tools/perf/pmu-events/arch/s390/cf_z13/extended.json
@@ -1,335 +1,391 @@
 [
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "128",
                "EventName": "L1D_RO_EXCL_WRITES",
                "BriefDescription": "L1D Read-only Exclusive Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "129",
                "EventName": "DTLB1_WRITES",
                "BriefDescription": "DTLB1 Writes",
                "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "130",
                "EventName": "DTLB1_MISSES",
                "BriefDescription": "DTLB1 Misses",
                "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "131",
                "EventName": "DTLB1_HPAGE_WRITES",
                "BriefDescription": "DTLB1 One-Megabyte Page Writes",
                "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "132",
                "EventName": "DTLB1_GPAGE_WRITES",
                "BriefDescription": "DTLB1 Two-Gigabyte Page Writes",
                "PublicDescription": "Counter:132       Name:DTLB1_GPAGE_WRITES A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a two-gigabyte page."
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "133",
                "EventName": "L1D_L2D_SOURCED_WRITES",
                "BriefDescription": "L1D L2D Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "134",
                "EventName": "ITLB1_WRITES",
                "BriefDescription": "ITLB1 Writes",
                "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "135",
                "EventName": "ITLB1_MISSES",
                "BriefDescription": "ITLB1 Misses",
                "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "136",
                "EventName": "L1I_L2I_SOURCED_WRITES",
                "BriefDescription": "L1I L2I Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "137",
                "EventName": "TLB2_PTE_WRITES",
                "BriefDescription": "TLB2 PTE Writes",
                "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "138",
                "EventName": "TLB2_CRSTE_HPAGE_WRITES",
                "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
                "PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays for a one-megabyte large page translation"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "139",
                "EventName": "TLB2_CRSTE_WRITES",
                "BriefDescription": "TLB2 CRSTE Writes",
                "PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "140",
                "EventName": "TX_C_TEND",
                "BriefDescription": "Completed TEND instructions in constrained TX mode",
                "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "141",
                "EventName": "TX_NC_TEND",
                "BriefDescription": "Completed TEND instructions in non-constrained TX mode",
                "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "143",
                "EventName": "L1C_TLB1_MISSES",
                "BriefDescription": "L1C TLB1 Misses",
                "PublicDescription": "Increments by one for any cycle where a Level-1 cache or Level-1 TLB miss is in progress."
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "144",
                "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
                "BriefDescription": "L1D On-Chip L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "145",
                "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "146",
                "EventName": "L1D_ONNODE_L4_SOURCED_WRITES",
                "BriefDescription": "L1D On-Node L4 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-4 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "147",
                "EventName": "L1D_ONNODE_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1D On-Node L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "148",
                "EventName": "L1D_ONNODE_L3_SOURCED_WRITES",
                "BriefDescription": "L1D On-Node L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "149",
                "EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES",
                "BriefDescription": "L1D On-Drawer L4 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "150",
                "EventName": "L1D_ONDRAWER_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1D On-Drawer L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "151",
                "EventName": "L1D_ONDRAWER_L3_SOURCED_WRITES",
                "BriefDescription": "L1D On-Drawer L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "152",
                "EventName": "L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES",
                "BriefDescription": "L1D Off-Drawer Same-Column L4 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "153",
                "EventName": "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "154",
                "EventName": "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES",
                "BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "155",
                "EventName": "L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES",
                "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "156",
                "EventName": "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "157",
                "EventName": "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES",
                "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "158",
                "EventName": "L1D_ONNODE_MEM_SOURCED_WRITES",
                "BriefDescription": "L1D On-Node Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Node memory"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "159",
                "EventName": "L1D_ONDRAWER_MEM_SOURCED_WRITES",
                "BriefDescription": "L1D On-Drawer Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "160",
                "EventName": "L1D_OFFDRAWER_MEM_SOURCED_WRITES",
                "BriefDescription": "L1D Off-Drawer Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "161",
                "EventName": "L1D_ONCHIP_MEM_SOURCED_WRITES",
                "BriefDescription": "L1D On-Chip Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "162",
                "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
                "BriefDescription": "L1I On-Chip L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "163",
                "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "164",
                "EventName": "L1I_ONNODE_L4_SOURCED_WRITES",
                "BriefDescription": "L1I On-Chip L4 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-4 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "165",
                "EventName": "L1I_ONNODE_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1I On-Node L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "166",
                "EventName": "L1I_ONNODE_L3_SOURCED_WRITES",
                "BriefDescription": "L1I On-Node L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "167",
                "EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES",
                "BriefDescription": "L1I On-Drawer L4 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "168",
                "EventName": "L1I_ONDRAWER_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1I On-Drawer L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "169",
                "EventName": "L1I_ONDRAWER_L3_SOURCED_WRITES",
                "BriefDescription": "L1I On-Drawer L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "170",
                "EventName": "L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES",
                "BriefDescription": "L1I Off-Drawer Same-Column L4 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "171",
                "EventName": "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "172",
                "EventName": "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES",
                "BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "173",
                "EventName": "L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES",
                "BriefDescription": "L1I Off-Drawer Far-Column L4 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "174",
                "EventName": "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "175",
                "EventName": "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES",
                "BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "176",
                "EventName": "L1I_ONNODE_MEM_SOURCED_WRITES",
                "BriefDescription": "L1I On-Node Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Node memory"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "177",
                "EventName": "L1I_ONDRAWER_MEM_SOURCED_WRITES",
                "BriefDescription": "L1I On-Drawer Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "178",
                "EventName": "L1I_OFFDRAWER_MEM_SOURCED_WRITES",
                "BriefDescription": "L1I Off-Drawer Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "179",
                "EventName": "L1I_ONCHIP_MEM_SOURCED_WRITES",
                "BriefDescription": "L1I On-Chip Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "218",
                "EventName": "TX_NC_TABORT",
                "BriefDescription": "Aborted transactions in non-constrained TX mode",
                "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "219",
                "EventName": "TX_C_TABORT_NO_SPECIAL",
                "BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
                "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "220",
                "EventName": "TX_C_TABORT_SPECIAL",
                "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
                "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "448",
                "EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
                "BriefDescription": "Cycle count with one thread active",
                "PublicDescription": "Cycle count with one thread active"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "449",
                "EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
                "BriefDescription": "Cycle count with two threads active",
diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json
new file mode 100644
index 000000000000..1a0034f79f73
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json
@@ -0,0 +1,7 @@
+[
+  {
+    "BriefDescription": "Transaction count",
+    "MetricName": "transaction",
+    "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/basic.json b/tools/perf/pmu-events/arch/s390/cf_z14/basic.json
index 8f653c9d899d..17fb5241928b 100644
--- a/tools/perf/pmu-events/arch/s390/cf_z14/basic.json
+++ b/tools/perf/pmu-events/arch/s390/cf_z14/basic.json
@@ -1,47 +1,55 @@
 [
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "0",
                "EventName": "CPU_CYCLES",
                "BriefDescription": "CPU Cycles",
                "PublicDescription": "Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "1",
                "EventName": "INSTRUCTIONS",
                "BriefDescription": "Instructions",
                "PublicDescription": "Instruction Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "2",
                "EventName": "L1I_DIR_WRITES",
                "BriefDescription": "L1I Directory Writes",
                "PublicDescription": "Level-1 I-Cache Directory Write Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "3",
                "EventName": "L1I_PENALTY_CYCLES",
                "BriefDescription": "L1I Penalty Cycles",
                "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "4",
                "EventName": "L1D_DIR_WRITES",
                "BriefDescription": "L1D Directory Writes",
                "PublicDescription": "Level-1 D-Cache Directory Write Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "5",
                "EventName": "L1D_PENALTY_CYCLES",
                "BriefDescription": "L1D Penalty Cycles",
                "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "32",
                "EventName": "PROBLEM_STATE_CPU_CYCLES",
                "BriefDescription": "Problem-State CPU Cycles",
                "PublicDescription": "Problem-State Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "33",
                "EventName": "PROBLEM_STATE_INSTRUCTIONS",
                "BriefDescription": "Problem-State Instructions",
diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z14/crypto.json
index 7e5b72492141..db286f19e7b6 100644
--- a/tools/perf/pmu-events/arch/s390/cf_z14/crypto.json
+++ b/tools/perf/pmu-events/arch/s390/cf_z14/crypto.json
@@ -1,95 +1,111 @@
 [
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "64",
                "EventName": "PRNG_FUNCTIONS",
                "BriefDescription": "PRNG Functions",
                "PublicDescription": "Total number of the PRNG functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "65",
                "EventName": "PRNG_CYCLES",
                "BriefDescription": "PRNG Cycles",
                "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "66",
                "EventName": "PRNG_BLOCKED_FUNCTIONS",
                "BriefDescription": "PRNG Blocked Functions",
                "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "67",
                "EventName": "PRNG_BLOCKED_CYCLES",
                "BriefDescription": "PRNG Blocked Cycles",
                "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "68",
                "EventName": "SHA_FUNCTIONS",
                "BriefDescription": "SHA Functions",
                "PublicDescription": "Total number of SHA functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "69",
                "EventName": "SHA_CYCLES",
                "BriefDescription": "SHA Cycles",
                "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "70",
                "EventName": "SHA_BLOCKED_FUNCTIONS",
                "BriefDescription": "SHA Blocked Functions",
                "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "71",
                "EventName": "SHA_BLOCKED_CYCLES",
                "BriefDescription": "SHA Bloced Cycles",
                "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "72",
                "EventName": "DEA_FUNCTIONS",
                "BriefDescription": "DEA Functions",
                "PublicDescription": "Total number of the DEA functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "73",
                "EventName": "DEA_CYCLES",
                "BriefDescription": "DEA Cycles",
                "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "74",
                "EventName": "DEA_BLOCKED_FUNCTIONS",
                "BriefDescription": "DEA Blocked Functions",
                "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "75",
                "EventName": "DEA_BLOCKED_CYCLES",
                "BriefDescription": "DEA Blocked Cycles",
                "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "76",
                "EventName": "AES_FUNCTIONS",
                "BriefDescription": "AES Functions",
                "PublicDescription": "Total number of AES functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "77",
                "EventName": "AES_CYCLES",
                "BriefDescription": "AES Cycles",
                "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "78",
                "EventName": "AES_BLOCKED_FUNCTIONS",
                "BriefDescription": "AES Blocked Functions",
                "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "79",
                "EventName": "AES_BLOCKED_CYCLES",
                "BriefDescription": "AES Blocked Cycles",
diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/extended.json b/tools/perf/pmu-events/arch/s390/cf_z14/extended.json
index aa4dfb46b65b..e7a3524b748f 100644
--- a/tools/perf/pmu-events/arch/s390/cf_z14/extended.json
+++ b/tools/perf/pmu-events/arch/s390/cf_z14/extended.json
@@ -1,317 +1,370 @@
 [
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "128",
                "EventName": "L1D_RO_EXCL_WRITES",
                "BriefDescription": "L1D Read-only Exclusive Writes",
                "PublicDescription": "Counter:128       Name:L1D_RO_EXCL_WRITES A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "129",
                "EventName": "DTLB2_WRITES",
                "BriefDescription": "DTLB2 Writes",
                "PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "130",
                "EventName": "DTLB2_MISSES",
                "BriefDescription": "DTLB2 Misses",
                "PublicDescription": "A TLB2 miss is in progress for a request made by the data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "131",
                "EventName": "DTLB2_HPAGE_WRITES",
                "BriefDescription": "DTLB2 One-Megabyte Page Writes",
                "PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page or a Last Host Translation was done"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "132",
                "EventName": "DTLB2_GPAGE_WRITES",
                "BriefDescription": "DTLB2 Two-Gigabyte Page Writes",
                "PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "133",
                "EventName": "L1D_L2D_SOURCED_WRITES",
                "BriefDescription": "L1D L2D Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "134",
                "EventName": "ITLB2_WRITES",
                "BriefDescription": "ITLB2 Writes",
                "PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "135",
                "EventName": "ITLB2_MISSES",
                "BriefDescription": "ITLB2 Misses",
                "PublicDescription": "A TLB2 miss is in progress for a request made by the instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "136",
                "EventName": "L1I_L2I_SOURCED_WRITES",
                "BriefDescription": "L1I L2I Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "137",
                "EventName": "TLB2_PTE_WRITES",
                "BriefDescription": "TLB2 PTE Writes",
                "PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "138",
                "EventName": "TLB2_CRSTE_WRITES",
                "BriefDescription": "TLB2 CRSTE Writes",
                "PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "139",
                "EventName": "TLB2_ENGINES_BUSY",
                "BriefDescription": "TLB2 Engines Busy",
                "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "140",
                "EventName": "TX_C_TEND",
                "BriefDescription": "Completed TEND instructions in constrained TX mode",
                "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "141",
                "EventName": "TX_NC_TEND",
                "BriefDescription": "Completed TEND instructions in non-constrained TX mode",
                "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "143",
                "EventName": "L1C_TLB2_MISSES",
                "BriefDescription": "L1C TLB2 Misses",
                "PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "144",
                "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
                "BriefDescription": "L1D On-Chip L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "145",
                "EventName": "L1D_ONCHIP_MEMORY_SOURCED_WRITES",
                "BriefDescription": "L1D On-Chip Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "146",
                "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "147",
                "EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES",
                "BriefDescription": "L1D On-Cluster L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Cluster Level-3 cache withountervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "148",
                "EventName": "L1D_ONCLUSTER_MEMORY_SOURCED_WRITES",
                "BriefDescription": "L1D On-Cluster Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster memory"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "149",
                "EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1D On-Cluster L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "150",
                "EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES",
                "BriefDescription": "L1D Off-Cluster L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "151",
                "EventName": "L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES",
                "BriefDescription": "L1D Off-Cluster Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Cluster memory"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "152",
                "EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1D Off-Cluster L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "153",
                "EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES",
                "BriefDescription": "L1D Off-Drawer L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "154",
                "EventName": "L1D_OFFDRAWER_MEMORY_SOURCED_WRITES",
                "BriefDescription": "L1D Off-Drawer Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "155",
                "EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1D Off-Drawer L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "156",
                "EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES",
                "BriefDescription": "L1D On-Drawer L4 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer Level-4 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "157",
                "EventName": "L1D_OFFDRAWER_L4_SOURCED_WRITES",
                "BriefDescription": "L1D Off-Drawer L4 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "158",
                "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_RO",
                "BriefDescription": "L1D On-Chip L3 Sourced Writes read-only",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip L3 but a read-only invalidate was done to remove other copies of the cache line"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "162",
                "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
                "BriefDescription": "L1I On-Chip L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "163",
                "EventName": "L1I_ONCHIP_MEMORY_SOURCED_WRITES",
                "BriefDescription": "L1I On-Chip Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from On-Chip memory"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "164",
                "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "165",
                "EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES",
                "BriefDescription": "L1I On-Cluster L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "166",
                "EventName": "L1I_ONCLUSTER_MEMORY_SOURCED_WRITES",
                "BriefDescription": "L1I On-Cluster Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster memory"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "167",
                "EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1I On-Cluster L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Cluster Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "168",
                "EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES",
                "BriefDescription": "L1I Off-Cluster L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "169",
                "EventName": "L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES",
                "BriefDescription": "L1I Off-Cluster Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Cluster memory"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "170",
                "EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1I Off-Cluster L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "171",
                "EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES",
                "BriefDescription": "L1I Off-Drawer L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "172",
                "EventName": "L1I_OFFDRAWER_MEMORY_SOURCED_WRITES",
                "BriefDescription": "L1I Off-Drawer Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "173",
                "EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1I Off-Drawer L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "174",
                "EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES",
                "BriefDescription": "L1I On-Drawer L4 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer Level-4 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "175",
                "EventName": "L1I_OFFDRAWER_L4_SOURCED_WRITES",
                "BriefDescription": "L1I Off-Drawer L4 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "224",
                "EventName": "BCD_DFP_EXECUTION_SLOTS",
                "BriefDescription": "BCD DFP Execution Slots",
                "PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "225",
                "EventName": "VX_BCD_EXECUTION_SLOTS",
                "BriefDescription": "VX BCD Execution Slots",
                "PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "226",
                "EventName": "DECIMAL_INSTRUCTIONS",
                "BriefDescription": "Decimal Instructions",
                "PublicDescription": "Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "232",
                "EventName": "LAST_HOST_TRANSLATIONS",
                "BriefDescription": "Last host translation done",
                "PublicDescription": "Last Host Translation done"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "243",
                "EventName": "TX_NC_TABORT",
                "BriefDescription": "Aborted transactions in non-constrained TX mode",
                "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "244",
                "EventName": "TX_C_TABORT_NO_SPECIAL",
                "BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
                "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "245",
                "EventName": "TX_C_TABORT_SPECIAL",
                "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
                "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "448",
                "EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
                "BriefDescription": "Cycle count with one thread active",
                "PublicDescription": "Cycle count with one thread active"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "449",
                "EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
                "BriefDescription": "Cycle count with two threads active",
diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json
new file mode 100644
index 000000000000..1a0034f79f73
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json
@@ -0,0 +1,7 @@
+[
+  {
+    "BriefDescription": "Transaction count",
+    "MetricName": "transaction",
+    "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL"
+  }
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_z196/basic.json b/tools/perf/pmu-events/arch/s390/cf_z196/basic.json
index 8bf16759ca53..2dd8dafff2ef 100644
--- a/tools/perf/pmu-events/arch/s390/cf_z196/basic.json
+++ b/tools/perf/pmu-events/arch/s390/cf_z196/basic.json
@@ -1,71 +1,83 @@
 [
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "0",
                "EventName": "CPU_CYCLES",
                "BriefDescription": "CPU Cycles",
                "PublicDescription": "Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "1",
                "EventName": "INSTRUCTIONS",
                "BriefDescription": "Instructions",
                "PublicDescription": "Instruction Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "2",
                "EventName": "L1I_DIR_WRITES",
                "BriefDescription": "L1I Directory Writes",
                "PublicDescription": "Level-1 I-Cache Directory Write Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "3",
                "EventName": "L1I_PENALTY_CYCLES",
                "BriefDescription": "L1I Penalty Cycles",
                "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "4",
                "EventName": "L1D_DIR_WRITES",
                "BriefDescription": "L1D Directory Writes",
                "PublicDescription": "Level-1 D-Cache Directory Write Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "5",
                "EventName": "L1D_PENALTY_CYCLES",
                "BriefDescription": "L1D Penalty Cycles",
                "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "32",
                "EventName": "PROBLEM_STATE_CPU_CYCLES",
                "BriefDescription": "Problem-State CPU Cycles",
                "PublicDescription": "Problem-State Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "33",
                "EventName": "PROBLEM_STATE_INSTRUCTIONS",
                "BriefDescription": "Problem-State Instructions",
                "PublicDescription": "Problem-State Instruction Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "34",
                "EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
                "BriefDescription": "Problem-State L1I Directory Writes",
                "PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "35",
                "EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
                "BriefDescription": "Problem-State L1I Penalty Cycles",
                "PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "36",
                "EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
                "BriefDescription": "Problem-State L1D Directory Writes",
                "PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "37",
                "EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
                "BriefDescription": "Problem-State L1D Penalty Cycles",
diff --git a/tools/perf/pmu-events/arch/s390/cf_z196/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z196/crypto.json
index 7e5b72492141..db286f19e7b6 100644
--- a/tools/perf/pmu-events/arch/s390/cf_z196/crypto.json
+++ b/tools/perf/pmu-events/arch/s390/cf_z196/crypto.json
@@ -1,95 +1,111 @@
 [
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "64",
                "EventName": "PRNG_FUNCTIONS",
                "BriefDescription": "PRNG Functions",
                "PublicDescription": "Total number of the PRNG functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "65",
                "EventName": "PRNG_CYCLES",
                "BriefDescription": "PRNG Cycles",
                "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "66",
                "EventName": "PRNG_BLOCKED_FUNCTIONS",
                "BriefDescription": "PRNG Blocked Functions",
                "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "67",
                "EventName": "PRNG_BLOCKED_CYCLES",
                "BriefDescription": "PRNG Blocked Cycles",
                "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "68",
                "EventName": "SHA_FUNCTIONS",
                "BriefDescription": "SHA Functions",
                "PublicDescription": "Total number of SHA functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "69",
                "EventName": "SHA_CYCLES",
                "BriefDescription": "SHA Cycles",
                "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "70",
                "EventName": "SHA_BLOCKED_FUNCTIONS",
                "BriefDescription": "SHA Blocked Functions",
                "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "71",
                "EventName": "SHA_BLOCKED_CYCLES",
                "BriefDescription": "SHA Bloced Cycles",
                "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "72",
                "EventName": "DEA_FUNCTIONS",
                "BriefDescription": "DEA Functions",
                "PublicDescription": "Total number of the DEA functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "73",
                "EventName": "DEA_CYCLES",
                "BriefDescription": "DEA Cycles",
                "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "74",
                "EventName": "DEA_BLOCKED_FUNCTIONS",
                "BriefDescription": "DEA Blocked Functions",
                "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "75",
                "EventName": "DEA_BLOCKED_CYCLES",
                "BriefDescription": "DEA Blocked Cycles",
                "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "76",
                "EventName": "AES_FUNCTIONS",
                "BriefDescription": "AES Functions",
                "PublicDescription": "Total number of AES functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "77",
                "EventName": "AES_CYCLES",
                "BriefDescription": "AES Cycles",
                "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "78",
                "EventName": "AES_BLOCKED_FUNCTIONS",
                "BriefDescription": "AES Blocked Functions",
                "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "79",
                "EventName": "AES_BLOCKED_CYCLES",
                "BriefDescription": "AES Blocked Cycles",
diff --git a/tools/perf/pmu-events/arch/s390/cf_z196/extended.json b/tools/perf/pmu-events/arch/s390/cf_z196/extended.json
index b6d7fec7c2e7..b7b42a870bb0 100644
--- a/tools/perf/pmu-events/arch/s390/cf_z196/extended.json
+++ b/tools/perf/pmu-events/arch/s390/cf_z196/extended.json
@@ -1,143 +1,167 @@
 [
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "128",
                "EventName": "L1D_L2_SOURCED_WRITES",
                "BriefDescription": "L1D L2 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from the Level-2 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "129",
                "EventName": "L1I_L2_SOURCED_WRITES",
                "BriefDescription": "L1I L2 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from the Level-2 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "130",
                "EventName": "DTLB1_MISSES",
                "BriefDescription": "DTLB1 Misses",
                "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "131",
                "EventName": "ITLB1_MISSES",
                "BriefDescription": "ITLB1 Misses",
                "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle a ITLB1 miss is in progress."
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "133",
                "EventName": "L2C_STORES_SENT",
                "BriefDescription": "L2C Stores Sent",
                "PublicDescription": "Incremented by one for every store sent to Level-2 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "134",
                "EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES",
                "BriefDescription": "L1D Off-Book L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an Off Book Level-3 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "135",
                "EventName": "L1D_ONBOOK_L4_SOURCED_WRITES",
                "BriefDescription": "L1D On-Book L4 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an On Book Level-4 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "136",
                "EventName": "L1I_ONBOOK_L4_SOURCED_WRITES",
                "BriefDescription": "L1I On-Book L4 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an On Book Level-4 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "137",
                "EventName": "L1D_RO_EXCL_WRITES",
                "BriefDescription": "L1D Read-only Exclusive Writes",
                "PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "138",
                "EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES",
                "BriefDescription": "L1D Off-Book L4 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "139",
                "EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES",
                "BriefDescription": "L1I Off-Book L4 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "140",
                "EventName": "DTLB1_HPAGE_WRITES",
                "BriefDescription": "DTLB1 One-Megabyte Page Writes",
                "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "141",
                "EventName": "L1D_LMEM_SOURCED_WRITES",
                "BriefDescription": "L1D Local Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 D-Cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "142",
                "EventName": "L1I_LMEM_SOURCED_WRITES",
                "BriefDescription": "L1I Local Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 I-Cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "143",
                "EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES",
                "BriefDescription": "L1I Off-Book L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an Off Book Level-3 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "144",
                "EventName": "DTLB1_WRITES",
                "BriefDescription": "DTLB1 Writes",
                "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "145",
                "EventName": "ITLB1_WRITES",
                "BriefDescription": "ITLB1 Writes",
                "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "146",
                "EventName": "TLB2_PTE_WRITES",
                "BriefDescription": "TLB2 PTE Writes",
                "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "147",
                "EventName": "TLB2_CRSTE_HPAGE_WRITES",
                "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
                "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "148",
                "EventName": "TLB2_CRSTE_WRITES",
                "BriefDescription": "TLB2 CRSTE Writes",
                "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "150",
                "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
                "BriefDescription": "L1D On-Chip L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an On Chip Level-3 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "152",
                "EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES",
                "BriefDescription": "L1D Off-Chip L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "153",
                "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
                "BriefDescription": "L1I On-Chip L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an On Chip Level-3 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "155",
                "EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES",
                "BriefDescription": "L1I Off-Chip L3 Sourced Writes",
diff --git a/tools/perf/pmu-events/arch/s390/cf_zec12/basic.json b/tools/perf/pmu-events/arch/s390/cf_zec12/basic.json
index 8bf16759ca53..2dd8dafff2ef 100644
--- a/tools/perf/pmu-events/arch/s390/cf_zec12/basic.json
+++ b/tools/perf/pmu-events/arch/s390/cf_zec12/basic.json
@@ -1,71 +1,83 @@
 [
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "0",
                "EventName": "CPU_CYCLES",
                "BriefDescription": "CPU Cycles",
                "PublicDescription": "Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "1",
                "EventName": "INSTRUCTIONS",
                "BriefDescription": "Instructions",
                "PublicDescription": "Instruction Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "2",
                "EventName": "L1I_DIR_WRITES",
                "BriefDescription": "L1I Directory Writes",
                "PublicDescription": "Level-1 I-Cache Directory Write Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "3",
                "EventName": "L1I_PENALTY_CYCLES",
                "BriefDescription": "L1I Penalty Cycles",
                "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "4",
                "EventName": "L1D_DIR_WRITES",
                "BriefDescription": "L1D Directory Writes",
                "PublicDescription": "Level-1 D-Cache Directory Write Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "5",
                "EventName": "L1D_PENALTY_CYCLES",
                "BriefDescription": "L1D Penalty Cycles",
                "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "32",
                "EventName": "PROBLEM_STATE_CPU_CYCLES",
                "BriefDescription": "Problem-State CPU Cycles",
                "PublicDescription": "Problem-State Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "33",
                "EventName": "PROBLEM_STATE_INSTRUCTIONS",
                "BriefDescription": "Problem-State Instructions",
                "PublicDescription": "Problem-State Instruction Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "34",
                "EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
                "BriefDescription": "Problem-State L1I Directory Writes",
                "PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "35",
                "EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
                "BriefDescription": "Problem-State L1I Penalty Cycles",
                "PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "36",
                "EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
                "BriefDescription": "Problem-State L1D Directory Writes",
                "PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "37",
                "EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
                "BriefDescription": "Problem-State L1D Penalty Cycles",
diff --git a/tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json b/tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json
index 7e5b72492141..db286f19e7b6 100644
--- a/tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json
+++ b/tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json
@@ -1,95 +1,111 @@
 [
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "64",
                "EventName": "PRNG_FUNCTIONS",
                "BriefDescription": "PRNG Functions",
                "PublicDescription": "Total number of the PRNG functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "65",
                "EventName": "PRNG_CYCLES",
                "BriefDescription": "PRNG Cycles",
                "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "66",
                "EventName": "PRNG_BLOCKED_FUNCTIONS",
                "BriefDescription": "PRNG Blocked Functions",
                "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "67",
                "EventName": "PRNG_BLOCKED_CYCLES",
                "BriefDescription": "PRNG Blocked Cycles",
                "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "68",
                "EventName": "SHA_FUNCTIONS",
                "BriefDescription": "SHA Functions",
                "PublicDescription": "Total number of SHA functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "69",
                "EventName": "SHA_CYCLES",
                "BriefDescription": "SHA Cycles",
                "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "70",
                "EventName": "SHA_BLOCKED_FUNCTIONS",
                "BriefDescription": "SHA Blocked Functions",
                "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "71",
                "EventName": "SHA_BLOCKED_CYCLES",
                "BriefDescription": "SHA Bloced Cycles",
                "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "72",
                "EventName": "DEA_FUNCTIONS",
                "BriefDescription": "DEA Functions",
                "PublicDescription": "Total number of the DEA functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "73",
                "EventName": "DEA_CYCLES",
                "BriefDescription": "DEA Cycles",
                "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "74",
                "EventName": "DEA_BLOCKED_FUNCTIONS",
                "BriefDescription": "DEA Blocked Functions",
                "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "75",
                "EventName": "DEA_BLOCKED_CYCLES",
                "BriefDescription": "DEA Blocked Cycles",
                "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "76",
                "EventName": "AES_FUNCTIONS",
                "BriefDescription": "AES Functions",
                "PublicDescription": "Total number of AES functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "77",
                "EventName": "AES_CYCLES",
                "BriefDescription": "AES Cycles",
                "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "78",
                "EventName": "AES_BLOCKED_FUNCTIONS",
                "BriefDescription": "AES Blocked Functions",
                "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "79",
                "EventName": "AES_BLOCKED_CYCLES",
                "BriefDescription": "AES Blocked Cycles",
diff --git a/tools/perf/pmu-events/arch/s390/cf_zec12/extended.json b/tools/perf/pmu-events/arch/s390/cf_zec12/extended.json
index 8682126aabb2..162251037219 100644
--- a/tools/perf/pmu-events/arch/s390/cf_zec12/extended.json
+++ b/tools/perf/pmu-events/arch/s390/cf_zec12/extended.json
@@ -1,209 +1,244 @@
 [
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "128",
                "EventName": "DTLB1_MISSES",
                "BriefDescription": "DTLB1 Misses",
                "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "129",
                "EventName": "ITLB1_MISSES",
                "BriefDescription": "ITLB1 Misses",
                "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle a ITLB1 miss is in progress."
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "130",
                "EventName": "L1D_L2I_SOURCED_WRITES",
                "BriefDescription": "L1D L2I Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "131",
                "EventName": "L1I_L2I_SOURCED_WRITES",
                "BriefDescription": "L1I L2I Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "132",
                "EventName": "L1D_L2D_SOURCED_WRITES",
                "BriefDescription": "L1D L2D Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "133",
                "EventName": "DTLB1_WRITES",
                "BriefDescription": "DTLB1 Writes",
                "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "135",
                "EventName": "L1D_LMEM_SOURCED_WRITES",
                "BriefDescription": "L1D Local Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "137",
                "EventName": "L1I_LMEM_SOURCED_WRITES",
                "BriefDescription": "L1I Local Memory Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "138",
                "EventName": "L1D_RO_EXCL_WRITES",
                "BriefDescription": "L1D Read-only Exclusive Writes",
                "PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "139",
                "EventName": "DTLB1_HPAGE_WRITES",
                "BriefDescription": "DTLB1 One-Megabyte Page Writes",
                "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "140",
                "EventName": "ITLB1_WRITES",
                "BriefDescription": "ITLB1 Writes",
                "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "141",
                "EventName": "TLB2_PTE_WRITES",
                "BriefDescription": "TLB2 PTE Writes",
                "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "142",
                "EventName": "TLB2_CRSTE_HPAGE_WRITES",
                "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
                "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "143",
                "EventName": "TLB2_CRSTE_WRITES",
                "BriefDescription": "TLB2 CRSTE Writes",
                "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "144",
                "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
                "BriefDescription": "L1D On-Chip L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "145",
                "EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES",
                "BriefDescription": "L1D Off-Chip L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "146",
                "EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES",
                "BriefDescription": "L1D Off-Book L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "147",
                "EventName": "L1D_ONBOOK_L4_SOURCED_WRITES",
                "BriefDescription": "L1D On-Book L4 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Book Level-4 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "148",
                "EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES",
                "BriefDescription": "L1D Off-Book L4 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "149",
                "EventName": "TX_NC_TEND",
                "BriefDescription": "Completed TEND instructions in non-constrained TX mode",
                "PublicDescription": "A TEND instruction has completed in a nonconstrained transactional-execution mode"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "150",
                "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from a On Chip Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "151",
                "EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1D Off-Chip L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "152",
                "EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1D Off-Book L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "153",
                "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
                "BriefDescription": "L1I On-Chip L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "154",
                "EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES",
                "BriefDescription": "L1I Off-Chip L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "155",
                "EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES",
                "BriefDescription": "L1I Off-Book L3 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "156",
                "EventName": "L1I_ONBOOK_L4_SOURCED_WRITES",
                "BriefDescription": "L1I On-Book L4 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Book Level-4 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "157",
                "EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES",
                "BriefDescription": "L1I Off-Book L4 Sourced Writes",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "158",
                "EventName": "TX_C_TEND",
                "BriefDescription": "Completed TEND instructions in constrained TX mode",
                "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "159",
                "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "160",
                "EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1I Off-Chip L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "161",
                "EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES_IV",
                "BriefDescription": "L1I Off-Book L3 Sourced Writes with Intervention",
                "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "177",
                "EventName": "TX_NC_TABORT",
                "BriefDescription": "Aborted transactions in non-constrained TX mode",
                "PublicDescription": "A transaction abort has occurred in a nonconstrained transactional-execution mode"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "178",
                "EventName": "TX_C_TABORT_NO_SPECIAL",
                "BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
                "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete"
        },
        {
+                "Unit": "CPU-M-CF",
                "EventCode": "179",
                "EventName": "TX_C_TABORT_SPECIAL",
                "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
diff --git a/tools/perf/pmu-events/arch/s390/cf_zec12/transaction.json b/tools/perf/pmu-events/arch/s390/cf_zec12/transaction.json
new file mode 100644
index 000000000000..1a0034f79f73
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_zec12/transaction.json
@@ -0,0 +1,7 @@
+[
+  {
+    "BriefDescription": "Transaction count",
+    "MetricName": "transaction",
+    "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL"
+  }
+]
diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c
index db3a594ee1e4..68c92bb599ee 100644
--- a/tools/perf/pmu-events/jevents.c
+++ b/tools/perf/pmu-events/jevents.c
@@ -233,6 +233,8 @@ static struct map {
        { "QPI LL", "uncore_qpi" },
        { "SBO", "uncore_sbox" },
        { "iMPH-U", "uncore_arb" },
+        { "CPU-M-CF", "cpum_cf" },
+        { "CPU-M-SF", "cpum_sf" },
        {}
 };
diff --git a/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Core.py b/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Core.py
index 38dfb720fb6f..54ace2f6bc36 100644
--- a/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Core.py
+++ b/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Core.py
@@ -31,10 +31,8 @@ def flag_str(event_name, field_name, value):
    string = ""
    if flag_fields[event_name][field_name]:
-        print_delim = 0
+        print_delim = 0
-        keys = flag_fields[event_name][field_name]['values'].keys()
+        for idx in sorted(flag_fields[event_name][field_name]['values']):
-        keys.sort()
-        for idx in keys:
            if not value and not idx:
                string += flag_fields[event_name][field_name]['values'][idx]
                break
@@ -51,14 +49,12 @@ def symbol_str(event_name, field_name, value):
    string = ""
    if symbolic_fields[event_name][field_name]:
-        keys = symbolic_fields[event_name][field_name]['values'].keys()
+        for idx in sorted(symbolic_fields[event_name][field_name]['values']):
-        keys.sort()
-        for idx in keys:
            if not value and not idx:
-                string = symbolic_fields[event_name][field_name]['values'][idx]
+                string = symbolic_fields[event_name][field_name]['values'][idx]
                break
-            if (value == idx):
+            if (value == idx):
-                string = symbolic_fields[event_name][field_name]['values'][idx]
+                string = symbolic_fields[event_name][field_name]['values'][idx]
                break
    return string
@@ -74,19 +70,17 @@ def trace_flag_str(value):
    string = ""
    print_delim = 0
-    keys = trace_flags.keys()
+    for idx in trace_flags:
+        if not value and not idx:
-    for idx in keys:
+            string += "NONE"
-        if not value and not idx:
+            break
-            string += "NONE"
-            break
+        if idx and (value & idx) == idx:
+            if print_delim:
-        if idx and (value & idx) == idx:
+                string += " | ";
-            if print_delim:
+            string += trace_flags[idx]
-                string += " | ";
+            print_delim = 1
-            string += trace_flags[idx]
+            value &= ~idx
-            print_delim = 1
-            value &= ~idx
    return string
diff --git a/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py b/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py
index 81a56cd2b3c1..21a7a1298094 100755
--- a/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py
+++ b/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py
@@ -8,6 +8,7 @@
 # PerfEvent is the base class for all perf event sample, PebsEvent
 # is a HW base Intel x86 PEBS event, and user could add more SW/HW
 # event classes based on requirements.
+from __future__ import print_function
 import struct
@@ -44,7 +45,8 @@ class PerfEvent(object):
                PerfEvent.event_num += 1
        def show(self):
-                print "PMU event: name=%12s, symbol=%24s, comm=%8s, dso=%12s" % (self.name, self.symbol, self.comm, self.dso)
+                print("PMU event: name=%12s, symbol=%24s, comm=%8s, dso=%12s" %
+                      (self.name, self.symbol, self.comm, self.dso))
 #
 # Basic Intel PEBS (Precise Event-based Sampling) event, whose raw buffer
diff --git a/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/SchedGui.py b/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/SchedGui.py
index fdd92f699055..cac7b2542ee8 100644
--- a/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/SchedGui.py
+++ b/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/SchedGui.py
@@ -11,7 +11,7 @@
 try:
        import wx
 except ImportError:
-        raise ImportError, "You need to install the wxpython lib for this script"
+        raise ImportError("You need to install the wxpython lib for this script")
 class RootFrame(wx.Frame):
diff --git a/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py b/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py
index f6c84966e4f8..7384dcb628c4 100644
--- a/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py
+++ b/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py
@@ -5,6 +5,7 @@
 # This software may be distributed under the terms of the GNU General
 # Public License ("GPL") version 2 as published by the Free Software
 # Foundation.
+from __future__ import print_function
 import errno, os
@@ -33,7 +34,7 @@ def nsecs_str(nsecs):
    return str
 def add_stats(dict, key, value):
-        if not dict.has_key(key):
+        if key not in dict:
                dict[key] = (value, value, value, 1)
        else:
                min, max, avg, count = dict[key]
@@ -72,10 +73,10 @@ try:
 except:
        if not audit_package_warned:
                audit_package_warned = True
-                print "Install the audit-libs-python package to get syscall names.\n" \
+                print("Install the audit-libs-python package to get syscall names.\n"
-                    "For example:\n  # apt-get install python-audit (Ubuntu)" \
+                    "For example:\n  # apt-get install python-audit (Ubuntu)"
-                    "\n  # yum install audit-libs-python (Fedora)" \
+                    "\n  # yum install audit-libs-python (Fedora)"
-                    "\n  etc.\n"
+                    "\n  etc.\n")
 def syscall_name(id):
        try:
diff --git a/tools/perf/scripts/python/sched-migration.py b/tools/perf/scripts/python/sched-migration.py
index de66cb3b72c9..3473e7f66081 100644
--- a/tools/perf/scripts/python/sched-migration.py
+++ b/tools/perf/scripts/python/sched-migration.py
@@ -9,13 +9,17 @@
 # This software is distributed under the terms of the GNU General
 # Public License ("GPL") version 2 as published by the Free Software
 # Foundation.
+from __future__ import print_function
 import os
 import sys
 from collections import defaultdict
-from UserList import UserList
+try:
+    from UserList import UserList
+except ImportError:
+    # Python 3: UserList moved to the collections package
+    from collections import UserList
 sys.path.append(os.environ['PERF_EXEC_PATH'] + \
        '/scripts/python/Perf-Trace-Util/lib/Perf/Trace')
@@ -300,7 +304,7 @@ class TimeSliceList(UserList):
                if i == -1:
                        return
-                for i in xrange(i, len(self.data)):
+                for i in range(i, len(self.data)):
                        timeslice = self.data[i]
                        if timeslice.start > end:
                                return
@@ -336,8 +340,8 @@ class SchedEventProxy:
                on_cpu_task = self.current_tsk[headers.cpu]
                if on_cpu_task != -1 and on_cpu_task != prev_pid:
-                        print "Sched switch event rejected ts: %s cpu: %d prev: %s(%d) next: %s(%d)" % \
+                        print("Sched switch event rejected ts: %s cpu: %d prev: %s(%d) next: %s(%d)" % \
-                                (headers.ts_format(), headers.cpu, prev_comm, prev_pid, next_comm, next_pid)
+                                headers.ts_format(), headers.cpu, prev_comm, prev_pid, next_comm, next_pid)
                threads[prev_pid] = prev_comm
                threads[next_pid] = next_comm
diff --git a/tools/perf/tests/builtin-test.c b/tools/perf/tests/builtin-test.c
index 2bde505e2e7e..d7a5e1b9aa6f 100644
--- a/tools/perf/tests/builtin-test.c
+++ b/tools/perf/tests/builtin-test.c
@@ -385,7 +385,7 @@ static int test_and_print(struct test *t, bool force_skip, int subtest)
        if (!t->subtest.get_nr)
                pr_debug("%s:", t->desc);
        else
-                pr_debug("%s subtest %d:", t->desc, subtest);
+                pr_debug("%s subtest %d:", t->desc, subtest + 1);
        switch (err) {
        case TEST_OK:
@@ -422,7 +422,7 @@ static const char *shell_test__description(char *description, size_t size,
 #define for_each_shell_test(dir, base, ent)     \
        while ((ent = readdir(dir)) != NULL)    \
-                if (!is_directory(base, ent))
+                if (!is_directory(base, ent) && ent->d_name[0] != '.')
 static const char *shell_tests__dir(char *path, size_t size)
 {
diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-events.c
index 7d4077068454..3b97ac018d5a 100644
--- a/tools/perf/tests/parse-events.c
+++ b/tools/perf/tests/parse-events.c
@@ -1309,6 +1309,11 @@ static int test__checkevent_config_cache(struct perf_evlist *evlist)
        return 0;
 }
+static bool test__intel_pt_valid(void)
+{
+        return !!perf_pmu__find("intel_pt");
+}
 static int test__intel_pt(struct perf_evlist *evlist)
 {
        struct perf_evsel *evsel = perf_evlist__first(evlist);
@@ -1317,6 +1322,14 @@ static int test__intel_pt(struct perf_evlist *evlist)
        return 0;
 }
+static int test__checkevent_complex_name(struct perf_evlist *evlist)
+{
+        struct perf_evsel *evsel = perf_evlist__first(evlist);
+        TEST_ASSERT_VAL("wrong complex name parsing", strcmp(evsel->name, "COMPLEX_CYCLES_NAME:orig=cycles,desc=chip-clock-ticks") == 0);
+        return 0;
+}
 static int count_tracepoints(void)
 {
        struct dirent *events_ent;
@@ -1375,6 +1388,7 @@ struct evlist_test {
        const char *name;
        __u32 type;
        const int id;
+        bool (*valid)(void);
        int (*check)(struct perf_evlist *evlist);
 };
@@ -1648,9 +1662,15 @@ static struct evlist_test test__events[] = {
        },
        {
                .name  = "intel_pt//u",
+                .valid = test__intel_pt_valid,
                .check = test__intel_pt,
                .id    = 52,
        },
+        {
+                .name  = "cycles/name='COMPLEX_CYCLES_NAME:orig=cycles,desc=chip-clock-ticks'/Duk",
+                .check = test__checkevent_complex_name,
+                .id    = 53
+        }
 };
 static struct evlist_test test__events_pmu[] = {
@@ -1669,6 +1689,11 @@ static struct evlist_test test__events_pmu[] = {
                .check = test__checkevent_pmu_partial_time_callgraph,
                .id    = 2,
        },
+        {
+                .name  = "cpu/name='COMPLEX_CYCLES_NAME:orig=cycles,desc=chip-clock-ticks',period=0x1,event=0x2/ukp",
+                .check = test__checkevent_complex_name,
+                .id    = 3,
+        }
 };
 struct terms_test {
@@ -1686,17 +1711,24 @@ static struct terms_test test__terms[] = {
 static int test_event(struct evlist_test *e)
 {
+        struct parse_events_error err = { .idx = 0, };
        struct perf_evlist *evlist;
        int ret;
+        if (e->valid && !e->valid()) {
+                pr_debug("... SKIP");
+                return 0;
+        }
        evlist = perf_evlist__new();
        if (evlist == NULL)
                return -ENOMEM;
-        ret = parse_events(evlist, e->name, NULL);
+        ret = parse_events(evlist, e->name, &err);
        if (ret) {
-                pr_debug("failed to parse event '%s', err %d\n",
+                pr_debug("failed to parse event '%s', err %d, str '%s'\n",
-                         e->name, ret);
+                         e->name, ret, err.str);
+                parse_events_print_error(&err, e->name);
        } else {
                ret = e->check(evlist);
        }
@@ -1714,10 +1746,11 @@ static int test_events(struct evlist_test *events, unsigned cnt)
        for (i = 0; i < cnt; i++) {
                struct evlist_test *e = &events[i];
-                pr_debug("running test %d '%s'\n", e->id, e->name);
+                pr_debug("running test %d '%s'", e->id, e->name);
                ret1 = test_event(e);
                if (ret1)
                        ret2 = ret1;
+                pr_debug("\n");
        }
        return ret2;
@@ -1799,7 +1832,7 @@ static int test_pmu_events(void)
        }
        while (!ret && (ent = readdir(dir))) {
-                struct evlist_test e;
+                struct evlist_test e = { .id = 0, };
                char name[2 * NAME_MAX + 1 + 12 + 3];
                /* Names containing . are special and cannot be used directly */
diff --git a/tools/perf/tests/shell/record+probe_libc_inet_pton.sh b/tools/perf/tests/shell/record+probe_libc_inet_pton.sh
index 263057039693..3013ac8f83d0 100755
--- a/tools/perf/tests/shell/record+probe_libc_inet_pton.sh
+++ b/tools/perf/tests/shell/record+probe_libc_inet_pton.sh
@@ -13,36 +13,60 @@
 libc=$(grep -w libc /proc/self/maps | head -1 | sed -r 's/.*[[:space:]](\/.*)/\1/g')
 nm -Dg $libc 2>/dev/null | fgrep -q inet_pton || exit 254
+event_pattern='probe_libc:inet_pton(\_[[:digit:]]+)?'
+add_libc_inet_pton_event() {
+        event_name=$(perf probe -f -x $libc -a inet_pton 2>&1 | tail -n +2 | head -n -5 | \
+                        grep -P -o "$event_pattern(?=[[:space:]]\(on inet_pton in $libc\))")
+        if [ $? -ne 0 -o -z "$event_name" ] ; then
+                printf "FAIL: could not add event\n"
+                return 1
+        fi
+}
 trace_libc_inet_pton_backtrace() {
-        idx=0
-        expected[0]="ping[][0-9 \.:]+probe_libc:inet_pton: \([[:xdigit:]]+\)"
+        expected=`mktemp -u /tmp/expected.XXX`
-        expected[1]=".*inet_pton\+0x[[:xdigit:]]+[[:space:]]\($libc|inlined\)$"
+        echo "ping[][0-9 \.:]+$event_name: \([[:xdigit:]]+\)" > $expected
+        echo ".*inet_pton\+0x[[:xdigit:]]+[[:space:]]\($libc|inlined\)$" >> $expected
        case "$(uname -m)" in
        s390x)
                eventattr='call-graph=dwarf,max-stack=4'
-                expected[2]="gaih_inet.*\+0x[[:xdigit:]]+[[:space:]]\($libc|inlined\)$"
+                echo "gaih_inet.*\+0x[[:xdigit:]]+[[:space:]]\($libc|inlined\)$" >> $expected
-                expected[3]="(__GI_)?getaddrinfo\+0x[[:xdigit:]]+[[:space:]]\($libc|inlined\)$"
+                echo "(__GI_)?getaddrinfo\+0x[[:xdigit:]]+[[:space:]]\($libc|inlined\)$" >> $expected
-                expected[4]="main\+0x[[:xdigit:]]+[[:space:]]\(.*/bin/ping.*\)$"
+                echo "main\+0x[[:xdigit:]]+[[:space:]]\(.*/bin/ping.*\)$" >> $expected
+                ;;
+        ppc64|ppc64le)
+                eventattr='max-stack=4'
+                echo "gaih_inet.*\+0x[[:xdigit:]]+[[:space:]]\($libc\)$" >> $expected
+                echo "getaddrinfo\+0x[[:xdigit:]]+[[:space:]]\($libc\)$" >> $expected
+                echo ".*\+0x[[:xdigit:]]+[[:space:]]\(.*/bin/ping.*\)$" >> $expected
                ;;
        *)
                eventattr='max-stack=3'
-                expected[2]="getaddrinfo\+0x[[:xdigit:]]+[[:space:]]\($libc\)$"
+                echo "getaddrinfo\+0x[[:xdigit:]]+[[:space:]]\($libc\)$" >> $expected
-                expected[3]=".*\+0x[[:xdigit:]]+[[:space:]]\(.*/bin/ping.*\)$"
+                echo ".*\+0x[[:xdigit:]]+[[:space:]]\(.*/bin/ping.*\)$" >> $expected
                ;;
        esac
-        file=`mktemp -u /tmp/perf.data.XXX`
+        perf_data=`mktemp -u /tmp/perf.data.XXX`
+        perf_script=`mktemp -u /tmp/perf.script.XXX`
+        perf record -e $event_name/$eventattr/ -o $perf_data ping -6 -c 1 ::1 > /dev/null 2>&1
+        perf script -i $perf_data > $perf_script
-        perf record -e probe_libc:inet_pton/$eventattr/ -o $file ping -6 -c 1 ::1 > /dev/null 2>&1
+        exec 3<$perf_script
-        perf script -i $file | while read line ; do
+        exec 4<$expected
+        while read line <&3 && read -r pattern <&4; do
+                [ -z "$pattern" ] && break
                echo $line
-                echo "$line" | egrep -q "${expected[$idx]}"
+                echo "$line" | egrep -q "$pattern"
                if [ $? -ne 0 ] ; then
-                        printf "FAIL: expected backtrace entry %d \"%s\" got \"%s\"\n" $idx "${expected[$idx]}" "$line"
+                        printf "FAIL: expected backtrace entry \"%s\" got \"%s\"\n" "$pattern" "$line"
-                        exit 1
+                        return 1
                fi
-                let idx+=1
-                [ -z "${expected[$idx]}" ] && break
        done
        # If any statements are executed from this point onwards,
@@ -51,13 +75,20 @@ trace_libc_inet_pton_backtrace() {
        # even if the perf script output does not match.
 }
+delete_libc_inet_pton_event() {
+        if [ -n "$event_name" ] ; then
+                perf probe -q -d $event_name
+        fi
+}
 # Check for IPv6 interface existence
 ip a sh lo | fgrep -q inet6 || exit 2
 skip_if_no_perf_probe && \
-perf probe -q $libc inet_pton && \
+add_libc_inet_pton_event && \
 trace_libc_inet_pton_backtrace
 err=$?
-rm -f ${file}
+rm -f ${perf_data} ${perf_script} ${expected}
-perf probe -q -d probe_libc:inet_pton
+delete_libc_inet_pton_event
 exit $err
diff --git a/tools/perf/tests/shell/trace+probe_vfs_getname.sh b/tools/perf/tests/shell/trace+probe_vfs_getname.sh
index 55ad9793d544..4ce276efe6b4 100755
--- a/tools/perf/tests/shell/trace+probe_vfs_getname.sh
+++ b/tools/perf/tests/shell/trace+probe_vfs_getname.sh
@@ -17,7 +17,7 @@ skip_if_no_perf_probe || exit 2
 file=$(mktemp /tmp/temporary_file.XXXXX)
 trace_open_vfs_getname() {
-        evts=$(echo $(perf list syscalls:sys_enter_open* |& egrep 'open(at)? ' | sed -r 's/.*sys_enter_([a-z]+) +\[.*$/\1/') | sed 's/ /,/')
+        evts=$(echo $(perf list syscalls:sys_enter_open* 2>&1 | egrep 'open(at)? ' | sed -r 's/.*sys_enter_([a-z]+) +\[.*$/\1/') | sed 's/ /,/')
        perf trace -e $evts touch $file 2>&1 | \
        egrep " +[0-9]+\.[0-9]+ +\( +[0-9]+\.[0-9]+ ms\): +touch\/[0-9]+ open(at)?\((dfd: +CWD, +)?filename: +${file}, +flags: CREAT\|NOCTTY\|NONBLOCK\|WRONLY, +mode: +IRUGO\|IWUGO\) += +[0-9]+$"
 }
diff --git a/tools/perf/tests/topology.c b/tools/perf/tests/topology.c
index 40e30a26b23c..9497d02f69e6 100644
--- a/tools/perf/tests/topology.c
+++ b/tools/perf/tests/topology.c
@@ -45,6 +45,7 @@ static int session_write_header(char *path)
        perf_header__set_feat(&session->header, HEADER_CPU_TOPOLOGY);
        perf_header__set_feat(&session->header, HEADER_NRCPUS);
+        perf_header__set_feat(&session->header, HEADER_ARCH);
        session->header.data_size += DATA_SIZE;
diff --git a/tools/perf/trace/beauty/Build b/tools/perf/trace/beauty/Build
index 66330d4b739b..f528ba35e140 100644
--- a/tools/perf/trace/beauty/Build
+++ b/tools/perf/trace/beauty/Build
@@ -7,4 +7,5 @@ endif
 libperf-y += kcmp.o
 libperf-y += pkey_alloc.o
 libperf-y += prctl.o
+libperf-y += socket.o
 libperf-y += statx.o
diff --git a/tools/perf/trace/beauty/beauty.h b/tools/perf/trace/beauty/beauty.h
index 984a504d335c..9615af5d412b 100644
--- a/tools/perf/trace/beauty/beauty.h
+++ b/tools/perf/trace/beauty/beauty.h
@@ -106,6 +106,9 @@ size_t syscall_arg__scnprintf_prctl_arg2(char *bf, size_t size, struct syscall_a
 size_t syscall_arg__scnprintf_prctl_arg3(char *bf, size_t size, struct syscall_arg *arg);
 #define SCA_PRCTL_ARG3 syscall_arg__scnprintf_prctl_arg3
+size_t syscall_arg__scnprintf_socket_protocol(char *bf, size_t size, struct syscall_arg *arg);
+#define SCA_SK_PROTO syscall_arg__scnprintf_socket_protocol
 size_t syscall_arg__scnprintf_statx_flags(char *bf, size_t size, struct syscall_arg *arg);
 #define SCA_STATX_FLAGS syscall_arg__scnprintf_statx_flags
diff --git a/tools/perf/trace/beauty/drm_ioctl.sh b/tools/perf/trace/beauty/drm_ioctl.sh
index 2149d3a98e42..9d3816815e60 100755
--- a/tools/perf/trace/beauty/drm_ioctl.sh
+++ b/tools/perf/trace/beauty/drm_ioctl.sh
@@ -1,13 +1,14 @@
 #!/bin/sh
-drm_header_dir=$1
+[ $# -eq 1 ] && header_dir=$1 || header_dir=tools/include/uapi/drm/
 printf "#ifndef DRM_COMMAND_BASE\n"
-grep "#define DRM_COMMAND_BASE" $drm_header_dir/drm.h
+grep "#define DRM_COMMAND_BASE" $header_dir/drm.h
 printf "#endif\n"
 printf "static const char *drm_ioctl_cmds[] = {\n"
-grep "^#define DRM_IOCTL.*DRM_IO" $drm_header_dir/drm.h | \
+grep "^#define DRM_IOCTL.*DRM_IO" $header_dir/drm.h | \
        sed -r 's/^#define +DRM_IOCTL_([A-Z0-9_]+)[      ]+DRM_IO[A-Z]* *\( *(0x[[:xdigit:]]+),*.*/     [\2] = "\1",/g'
-grep "^#define DRM_I915_[A-Z_0-9]\+[     ]\+0x" $drm_header_dir/i915_drm.h | \
+grep "^#define DRM_I915_[A-Z_0-9]\+[     ]\+0x" $header_dir/i915_drm.h | \
        sed -r 's/^#define +DRM_I915_([A-Z0-9_]+)[       ]+(0x[[:xdigit:]]+)/\t[DRM_COMMAND_BASE + \2] = "I915_\1",/g'
 printf "};\n"
diff --git a/tools/perf/trace/beauty/kcmp_type.sh b/tools/perf/trace/beauty/kcmp_type.sh
index 40d063b8c082..a3c304caa336 100755
--- a/tools/perf/trace/beauty/kcmp_type.sh
+++ b/tools/perf/trace/beauty/kcmp_type.sh
@@ -1,6 +1,6 @@
 #!/bin/sh
-header_dir=$1
+[ $# -eq 1 ] && header_dir=$1 || header_dir=tools/include/uapi/linux/
 printf "static const char *kcmp_types[] = {\n"
 regex='^[[:space:]]+(KCMP_(\w+)),'
diff --git a/tools/perf/trace/beauty/kvm_ioctl.sh b/tools/perf/trace/beauty/kvm_ioctl.sh
index bd28817afced..c4699fd46bb6 100755
--- a/tools/perf/trace/beauty/kvm_ioctl.sh
+++ b/tools/perf/trace/beauty/kvm_ioctl.sh
@@ -1,10 +1,10 @@
 #!/bin/sh
-kvm_header_dir=$1
+[ $# -eq 1 ] && header_dir=$1 || header_dir=tools/include/uapi/linux/
 printf "static const char *kvm_ioctl_cmds[] = {\n"
 regex='^#[[:space:]]*define[[:space:]]+KVM_(\w+)[[:space:]]+_IO[RW]*\([[:space:]]*KVMIO[[:space:]]*,[[:space:]]*(0x[[:xdigit:]]+).*'
-egrep $regex ${kvm_header_dir}/kvm.h    | \
+egrep $regex ${header_dir}/kvm.h        | \
        sed -r "s/$regex/\2 \1/g"       | \
        egrep -v " ((ARM|PPC|S390)_|[GS]ET_(DEBUGREGS|PIT2|XSAVE|TSC_KHZ)|CREATE_SPAPR_TCE_64)" | \
        sort | xargs printf "\t[%s] = \"%s\",\n"
diff --git a/tools/perf/trace/beauty/madvise_behavior.sh b/tools/perf/trace/beauty/madvise_behavior.sh
index 60ef8640ee70..431639eb4d29 100755
--- a/tools/perf/trace/beauty/madvise_behavior.sh
+++ b/tools/perf/trace/beauty/madvise_behavior.sh
@@ -1,6 +1,6 @@
 #!/bin/sh
-header_dir=$1
+[ $# -eq 1 ] && header_dir=$1 || header_dir=tools/include/uapi/asm-generic/
 printf "static const char *madvise_advices[] = {\n"
 regex='^[[:space:]]*#[[:space:]]*define[[:space:]]+MADV_([[:alnum:]_]+)[[:space:]]+([[:digit:]]+)[[:space:]]*.*'
diff --git a/tools/perf/trace/beauty/perf_ioctl.sh b/tools/perf/trace/beauty/perf_ioctl.sh
index faea4237c793..6492c74df928 100755
--- a/tools/perf/trace/beauty/perf_ioctl.sh
+++ b/tools/perf/trace/beauty/perf_ioctl.sh
@@ -1,6 +1,6 @@
 #!/bin/sh
-header_dir=$1
+[ $# -eq 1 ] && header_dir=$1 || header_dir=tools/include/uapi/linux/
 printf "static const char *perf_ioctl_cmds[] = {\n"
 regex='^#[[:space:]]*define[[:space:]]+PERF_EVENT_IOC_(\w+)[[:space:]]+_IO[RW]*[[:space:]]*\([[:space:]]*.\$.[[:space:]]*,[[:space:]]*([[:digit:]]+).*'
diff --git a/tools/perf/trace/beauty/pkey_alloc_access_rights.sh b/tools/perf/trace/beauty/pkey_alloc_access_rights.sh
index 62e51a02b839..e0a51aeb20b2 100755
--- a/tools/perf/trace/beauty/pkey_alloc_access_rights.sh
+++ b/tools/perf/trace/beauty/pkey_alloc_access_rights.sh
@@ -1,6 +1,6 @@
 #!/bin/sh
-header_dir=$1
+[ $# -eq 1 ] && header_dir=$1 || header_dir=tools/include/uapi/asm-generic/
 printf "static const char *pkey_alloc_access_rights[] = {\n"
 regex='^[[:space:]]*#[[:space:]]*define[[:space:]]+PKEY_([[:alnum:]_]+)[[:space:]]+(0x[[:xdigit:]]+)[[:space:]]*'
diff --git a/tools/perf/trace/beauty/sndrv_ctl_ioctl.sh b/tools/perf/trace/beauty/sndrv_ctl_ioctl.sh
index aad5ab130539..eb511bb5fbd3 100755
--- a/tools/perf/trace/beauty/sndrv_ctl_ioctl.sh
+++ b/tools/perf/trace/beauty/sndrv_ctl_ioctl.sh
@@ -1,8 +1,8 @@
 #!/bin/sh
-sound_header_dir=$1
+[ $# -eq 1 ] && header_dir=$1 || header_dir=tools/include/uapi/sound/
 printf "static const char *sndrv_ctl_ioctl_cmds[] = {\n"
-grep "^#define[\t ]\+SNDRV_CTL_IOCTL_" $sound_header_dir/asound.h | \
+grep "^#define[\t ]\+SNDRV_CTL_IOCTL_" $header_dir/asound.h | \
        sed -r 's/^#define +SNDRV_CTL_IOCTL_([A-Z0-9_]+)[\t ]+_IO[RW]*\( *.U., *(0x[[:xdigit:]]+),?.*/\t[\2] = \"\1\",/g'
 printf "};\n"
diff --git a/tools/perf/trace/beauty/sndrv_pcm_ioctl.sh b/tools/perf/trace/beauty/sndrv_pcm_ioctl.sh
index b7e9ef6b2f55..6818392968b2 100755
--- a/tools/perf/trace/beauty/sndrv_pcm_ioctl.sh
+++ b/tools/perf/trace/beauty/sndrv_pcm_ioctl.sh
@@ -1,8 +1,8 @@
 #!/bin/sh
-sound_header_dir=$1
+[ $# -eq 1 ] && header_dir=$1 || header_dir=tools/include/uapi/sound/
 printf "static const char *sndrv_pcm_ioctl_cmds[] = {\n"
-grep "^#define[\t ]\+SNDRV_PCM_IOCTL_" $sound_header_dir/asound.h | \
+grep "^#define[\t ]\+SNDRV_PCM_IOCTL_" $header_dir/asound.h | \
        sed -r 's/^#define +SNDRV_PCM_IOCTL_([A-Z0-9_]+)[\t ]+_IO[RW]*\( *.A., *(0x[[:xdigit:]]+),?.*/\t[\2] = \"\1\",/g'
 printf "};\n"
diff --git a/tools/perf/trace/beauty/socket.c b/tools/perf/trace/beauty/socket.c
new file mode 100644
index 000000000000..65227269384b
--- /dev/null
+++ b/tools/perf/trace/beauty/socket.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * trace/beauty/socket.c
+ *
+ *  Copyright (C) 2018, Red Hat Inc, Arnaldo Carvalho de Melo <acme@redhat.com>
+ */
+#include "trace/beauty/beauty.h"
+#include <sys/types.h>
+#include <sys/socket.h>
+static size_t socket__scnprintf_ipproto(int protocol, char *bf, size_t size)
+{
+#include "trace/beauty/generated/socket_ipproto_array.c"
+        static DEFINE_STRARRAY(socket_ipproto);
+        return strarray__scnprintf(&strarray__socket_ipproto, bf, size, "%d", protocol);
+}
+size_t syscall_arg__scnprintf_socket_protocol(char *bf, size_t size, struct syscall_arg *arg)
+{
+        int domain = syscall_arg__val(arg, 0);
+        if (domain == AF_INET || domain == AF_INET6)
+                return socket__scnprintf_ipproto(arg->val, bf, size);
+        return syscall_arg__scnprintf_int(bf, size, arg);
+}
diff --git a/tools/perf/trace/beauty/socket_ipproto.sh b/tools/perf/trace/beauty/socket_ipproto.sh
new file mode 100755
index 000000000000..a3cc24633bec
--- /dev/null
+++ b/tools/perf/trace/beauty/socket_ipproto.sh
@@ -0,0 +1,11 @@
+#!/bin/sh
+[ $# -eq 1 ] && header_dir=$1 || header_dir=tools/include/uapi/linux/
+printf "static const char *socket_ipproto[] = {\n"
+regex='^[[:space:]]+IPPROTO_(\w+)[[:space:]]+=[[:space:]]+([[:digit:]]+),.*'
+egrep $regex ${header_dir}/in.h | \
+        sed -r "s/$regex/\2 \1/g"       | \
+        sort | xargs printf "\t[%s] = \"%s\",\n"
+printf "};\n"
diff --git a/tools/perf/trace/beauty/vhost_virtio_ioctl.sh b/tools/perf/trace/beauty/vhost_virtio_ioctl.sh
index 76f1de697787..0f6a5197d0be 100755
--- a/tools/perf/trace/beauty/vhost_virtio_ioctl.sh
+++ b/tools/perf/trace/beauty/vhost_virtio_ioctl.sh
@@ -1,17 +1,17 @@
 #!/bin/sh
-vhost_virtio_header_dir=$1
+[ $# -eq 1 ] && header_dir=$1 || header_dir=tools/include/uapi/linux/
 printf "static const char *vhost_virtio_ioctl_cmds[] = {\n"
 regex='^#[[:space:]]*define[[:space:]]+VHOST_(\w+)[[:space:]]+_IOW?\([[:space:]]*VHOST_VIRTIO[[:space:]]*,[[:space:]]*(0x[[:xdigit:]]+).*'
-egrep $regex ${vhost_virtio_header_dir}/vhost.h | \
+egrep $regex ${header_dir}/vhost.h | \
        sed -r "s/$regex/\2 \1/g"       | \
        sort | xargs printf "\t[%s] = \"%s\",\n"
 printf "};\n"
 printf "static const char *vhost_virtio_ioctl_read_cmds[] = {\n"
 regex='^#[[:space:]]*define[[:space:]]+VHOST_(\w+)[[:space:]]+_IOW?R\([[:space:]]*VHOST_VIRTIO[[:space:]]*,[[:space:]]*(0x[[:xdigit:]]+).*'
-egrep $regex ${vhost_virtio_header_dir}/vhost.h | \
+egrep $regex ${header_dir}/vhost.h | \
        sed -r "s/$regex/\2 \1/g"       | \
        sort | xargs printf "\t[%s] = \"%s\",\n"
 printf "};\n"
diff --git a/tools/perf/ui/gtk/hists.c b/tools/perf/ui/gtk/hists.c
index b085f1b3e34d..4ab663ec3e5e 100644
--- a/tools/perf/ui/gtk/hists.c
+++ b/tools/perf/ui/gtk/hists.c
@@ -382,7 +382,7 @@ static void perf_gtk__show_hists(GtkWidget *window, struct hists *hists,
                        gtk_tree_store_set(store, &iter, col_idx++, s, -1);
                }
-                if (hists__has_callchains(hists) &&
+                if (hist_entry__has_callchains(h) &&
                    symbol_conf.use_callchain && hists__has(hists, sym)) {
                        if (callchain_param.mode == CHAIN_GRAPH_REL)
                                total = symbol_conf.cumulate_callchain ?
diff --git a/tools/perf/ui/stdio/hist.c b/tools/perf/ui/stdio/hist.c
index 69b7a28f7a1c..74c4ae1f0a05 100644
--- a/tools/perf/ui/stdio/hist.c
+++ b/tools/perf/ui/stdio/hist.c
@@ -529,7 +529,7 @@ out:
 static int hist_entry__fprintf(struct hist_entry *he, size_t size,
                               char *bf, size_t bfsz, FILE *fp,
-                               bool use_callchain)
+                               bool ignore_callchains)
 {
        int ret;
        int callchain_ret = 0;
@@ -550,7 +550,7 @@ static int hist_entry__fprintf(struct hist_entry *he, size_t size,
        ret = fprintf(fp, "%s\n", bf);
-        if (hist_entry__has_callchains(he) && use_callchain)
+        if (hist_entry__has_callchains(he) && !ignore_callchains)
                callchain_ret = hist_entry_callchain__fprintf(he, total_period,
                                                              0, fp);
@@ -755,7 +755,7 @@ int hists__fprintf_headers(struct hists *hists, FILE *fp)
 size_t hists__fprintf(struct hists *hists, bool show_header, int max_rows,
                      int max_cols, float min_pcnt, FILE *fp,
-                      bool use_callchain)
+                      bool ignore_callchains)
 {
        struct rb_node *nd;
        size_t ret = 0;
@@ -799,7 +799,7 @@ size_t hists__fprintf(struct hists *hists, bool show_header, int max_rows,
                if (percent < min_pcnt)
                        continue;
-                ret += hist_entry__fprintf(h, max_cols, line, linesz, fp, use_callchain);
+                ret += hist_entry__fprintf(h, max_cols, line, linesz, fp, ignore_callchains);
                if (max_rows && ++nr_rows >= max_rows)
                        break;
diff --git a/tools/perf/util/bpf-loader.c b/tools/perf/util/bpf-loader.c
index cee658733e2c..3d02ae38ec56 100644
--- a/tools/perf/util/bpf-loader.c
+++ b/tools/perf/util/bpf-loader.c
@@ -747,7 +747,9 @@ int bpf__load(struct bpf_object *obj)
        err = bpf_object__load(obj);
        if (err) {
-                pr_debug("bpf: load objects failed\n");
+                char bf[128];
+                libbpf_strerror(err, bf, sizeof(bf));
+                pr_debug("bpf: load objects failed: err=%d: (%s)\n", err, bf);
                return err;
        }
        return 0;
diff --git a/tools/perf/util/c++/clang.cpp b/tools/perf/util/c++/clang.cpp
index bf31ceab33bd..89512504551b 100644
--- a/tools/perf/util/c++/clang.cpp
+++ b/tools/perf/util/c++/clang.cpp
@@ -146,8 +146,15 @@ getBPFObjectFromModule(llvm::Module *Module)
        raw_svector_ostream ostream(*Buffer);
        legacy::PassManager PM;
-        if (TargetMachine->addPassesToEmitFile(PM, ostream,
+        bool NotAdded;
-                                               TargetMachine::CGFT_ObjectFile)) {
+#if CLANG_VERSION_MAJOR < 7
+        NotAdded = TargetMachine->addPassesToEmitFile(PM, ostream,
+                                                      TargetMachine::CGFT_ObjectFile);
+#else
+        NotAdded = TargetMachine->addPassesToEmitFile(PM, ostream, nullptr,
+                                                      TargetMachine::CGFT_ObjectFile);
+#endif
+        if (NotAdded) {
                llvm::errs() << "TargetMachine can't emit a file of this type\n";
                return std::unique_ptr<llvm::SmallVectorImpl<char>>(nullptr);;
        }
diff --git a/tools/perf/util/comm.c b/tools/perf/util/comm.c
index 7798a2cc8a86..31279a7bd919 100644
--- a/tools/perf/util/comm.c
+++ b/tools/perf/util/comm.c
@@ -20,9 +20,10 @@ static struct rw_semaphore comm_str_lock = {.lock = PTHREAD_RWLOCK_INITIALIZER,}
 static struct comm_str *comm_str__get(struct comm_str *cs)
 {
-        if (cs)
+        if (cs && refcount_inc_not_zero(&cs->refcnt))
-                refcount_inc(&cs->refcnt);
+                return cs;
-        return cs;
+        return NULL;
 }
 static void comm_str__put(struct comm_str *cs)
@@ -67,9 +68,14 @@ struct comm_str *__comm_str__findnew(const char *str, struct rb_root *root)
                parent = *p;
                iter = rb_entry(parent, struct comm_str, rb_node);
+                /*
+                 * If we race with comm_str__put, iter->refcnt is 0
+                 * and it will be removed within comm_str__put call
+                 * shortly, ignore it in this search.
+                 */
                cmp = strcmp(str, iter->str);
-                if (!cmp)
+                if (!cmp && comm_str__get(iter))
-                        return comm_str__get(iter);
+                        return iter;
                if (cmp < 0)
                        p = &(*p)->rb_left;
diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
index 4d5fc374e730..938def6d0bb9 100644
--- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
+++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
@@ -31,6 +31,8 @@
 #endif
 #endif
+#define CS_ETM_INVAL_ADDR       0xdeadbeefdeadbeefUL
 struct cs_etm_decoder {
        void *data;
        void (*packet_printer)(const char *msg);
@@ -261,8 +263,8 @@ static void cs_etm_decoder__clear_buffer(struct cs_etm_decoder *decoder)
        decoder->tail = 0;
        decoder->packet_count = 0;
        for (i = 0; i < MAX_BUFFER; i++) {
-                decoder->packet_buffer[i].start_addr = 0xdeadbeefdeadbeefUL;
+                decoder->packet_buffer[i].start_addr = CS_ETM_INVAL_ADDR;
-                decoder->packet_buffer[i].end_addr = 0xdeadbeefdeadbeefUL;
+                decoder->packet_buffer[i].end_addr = CS_ETM_INVAL_ADDR;
                decoder->packet_buffer[i].last_instr_taken_branch = false;
                decoder->packet_buffer[i].exc = false;
                decoder->packet_buffer[i].exc_ret = false;
@@ -295,8 +297,8 @@ cs_etm_decoder__buffer_packet(struct cs_etm_decoder *decoder,
        decoder->packet_buffer[et].exc = false;
        decoder->packet_buffer[et].exc_ret = false;
        decoder->packet_buffer[et].cpu = *((int *)inode->priv);
-        decoder->packet_buffer[et].start_addr = 0xdeadbeefdeadbeefUL;
+        decoder->packet_buffer[et].start_addr = CS_ETM_INVAL_ADDR;
-        decoder->packet_buffer[et].end_addr = 0xdeadbeefdeadbeefUL;
+        decoder->packet_buffer[et].end_addr = CS_ETM_INVAL_ADDR;
        if (decoder->packet_count == MAX_BUFFER - 1)
                return OCSD_RESP_WAIT;
diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h
index 743f5f444304..612b5755f742 100644
--- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h
+++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h
@@ -23,6 +23,7 @@ struct cs_etm_buffer {
 };
 enum cs_etm_sample_type {
+        CS_ETM_EMPTY = 0,
        CS_ETM_RANGE = 1 << 0,
        CS_ETM_TRACE_ON = 1 << 1,
 };
diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c
index 822ba915d144..2ae640257fdb 100644
--- a/tools/perf/util/cs-etm.c
+++ b/tools/perf/util/cs-etm.c
@@ -494,6 +494,10 @@ static inline void cs_etm__reset_last_branch_rb(struct cs_etm_queue *etmq)
 static inline u64 cs_etm__last_executed_instr(struct cs_etm_packet *packet)
 {
+        /* Returns 0 for the CS_ETM_TRACE_ON packet */
+        if (packet->sample_type == CS_ETM_TRACE_ON)
+                return 0;
        /*
         * The packet records the execution range with an exclusive end address
         *
@@ -505,6 +509,15 @@ static inline u64 cs_etm__last_executed_instr(struct cs_etm_packet *packet)
        return packet->end_addr - A64_INSTR_SIZE;
 }
+static inline u64 cs_etm__first_executed_instr(struct cs_etm_packet *packet)
+{
+        /* Returns 0 for the CS_ETM_TRACE_ON packet */
+        if (packet->sample_type == CS_ETM_TRACE_ON)
+                return 0;
+        return packet->start_addr;
+}
 static inline u64 cs_etm__instr_count(const struct cs_etm_packet *packet)
 {
        /*
@@ -546,7 +559,7 @@ static void cs_etm__update_last_branch_rb(struct cs_etm_queue *etmq)
        be       = &bs->entries[etmq->last_branch_pos];
        be->from = cs_etm__last_executed_instr(etmq->prev_packet);
-        be->to   = etmq->packet->start_addr;
+        be->to   = cs_etm__first_executed_instr(etmq->packet);
        /* No support for mispredict */
        be->flags.mispred = 0;
        be->flags.predicted = 1;
@@ -701,7 +714,7 @@ static int cs_etm__synth_branch_sample(struct cs_etm_queue *etmq)
        sample.ip = cs_etm__last_executed_instr(etmq->prev_packet);
        sample.pid = etmq->pid;
        sample.tid = etmq->tid;
-        sample.addr = etmq->packet->start_addr;
+        sample.addr = cs_etm__first_executed_instr(etmq->packet);
        sample.id = etmq->etm->branches_id;
        sample.stream_id = etmq->etm->branches_id;
        sample.period = 1;
@@ -897,13 +910,23 @@ static int cs_etm__sample(struct cs_etm_queue *etmq)
                etmq->period_instructions = instrs_over;
        }
-        if (etm->sample_branches &&
+        if (etm->sample_branches && etmq->prev_packet) {
-            etmq->prev_packet &&
+                bool generate_sample = false;
-            etmq->prev_packet->sample_type == CS_ETM_RANGE &&
-            etmq->prev_packet->last_instr_taken_branch) {
+                /* Generate sample for tracing on packet */
-                ret = cs_etm__synth_branch_sample(etmq);
+                if (etmq->prev_packet->sample_type == CS_ETM_TRACE_ON)
-                if (ret)
+                        generate_sample = true;
-                        return ret;
+                /* Generate sample for branch taken packet */
+                if (etmq->prev_packet->sample_type == CS_ETM_RANGE &&
+                    etmq->prev_packet->last_instr_taken_branch)
+                        generate_sample = true;
+                if (generate_sample) {
+                        ret = cs_etm__synth_branch_sample(etmq);
+                        if (ret)
+                                return ret;
+                }
        }
        if (etm->sample_branches || etm->synth_opts.last_branch) {
@@ -922,10 +945,17 @@ static int cs_etm__sample(struct cs_etm_queue *etmq)
 static int cs_etm__flush(struct cs_etm_queue *etmq)
 {
        int err = 0;
+        struct cs_etm_auxtrace *etm = etmq->etm;
        struct cs_etm_packet *tmp;
+        if (!etmq->prev_packet)
+                return 0;
+        /* Handle start tracing packet */
+        if (etmq->prev_packet->sample_type == CS_ETM_EMPTY)
+                goto swap_packet;
        if (etmq->etm->synth_opts.last_branch &&
-            etmq->prev_packet &&
            etmq->prev_packet->sample_type == CS_ETM_RANGE) {
                /*
                 * Generate a last branch event for the branches left in the
@@ -939,8 +969,22 @@ static int cs_etm__flush(struct cs_etm_queue *etmq)
                err = cs_etm__synth_instruction_sample(
                        etmq, addr,
                        etmq->period_instructions);
+                if (err)
+                        return err;
                etmq->period_instructions = 0;
+        }
+        if (etm->sample_branches &&
+            etmq->prev_packet->sample_type == CS_ETM_RANGE) {
+                err = cs_etm__synth_branch_sample(etmq);
+                if (err)
+                        return err;
+        }
+swap_packet:
+        if (etmq->etm->synth_opts.last_branch) {
                /*
                 * Swap PACKET with PREV_PACKET: PACKET becomes PREV_PACKET for
                 * the next incoming packet.
@@ -1020,6 +1064,13 @@ static int cs_etm__run_decoder(struct cs_etm_queue *etmq)
                                         */
                                        cs_etm__flush(etmq);
                                        break;
+                                case CS_ETM_EMPTY:
+                                        /*
+                                         * Should not receive empty packet,
+                                         * report error.
+                                         */
+                                        pr_err("CS ETM Trace: empty packet\n");
+                                        return -EINVAL;
                                default:
                                        break;
                                }
diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
index 94fce4f537e9..ddf84b941abf 100644
--- a/tools/perf/util/evsel.c
+++ b/tools/perf/util/evsel.c
@@ -260,6 +260,17 @@ struct perf_evsel *perf_evsel__new_idx(struct perf_event_attr *attr, int idx)
                evsel->attr.sample_period = 1;
        }
+        if (perf_evsel__is_clock(evsel)) {
+                /*
+                 * The evsel->unit points to static alias->unit
+                 * so it's ok to use static string in here.
+                 */
+                static const char *unit = "msec";
+                evsel->unit = unit;
+                evsel->scale = 1e-6;
+        }
        return evsel;
 }
@@ -848,6 +859,12 @@ static void apply_config_terms(struct perf_evsel *evsel,
        }
 }
+static bool is_dummy_event(struct perf_evsel *evsel)
+{
+        return (evsel->attr.type == PERF_TYPE_SOFTWARE) &&
+               (evsel->attr.config == PERF_COUNT_SW_DUMMY);
+}
 /*
 * The enable_on_exec/disabled value strategy:
 *
@@ -1086,6 +1103,14 @@ void perf_evsel__config(struct perf_evsel *evsel, struct record_opts *opts,
                else
                        perf_evsel__reset_sample_bit(evsel, PERIOD);
        }
+        /*
+         * For initial_delay, a dummy event is added implicitly.
+         * The software event will trigger -EOPNOTSUPP error out,
+         * if BRANCH_STACK bit is set.
+         */
+        if (opts->initial_delay && is_dummy_event(evsel))
+                perf_evsel__reset_sample_bit(evsel, BRANCH_STACK);
 }
 static int perf_evsel__alloc_fd(struct perf_evsel *evsel, int ncpus, int nthreads)
diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h
index d277930b19a1..973c03167947 100644
--- a/tools/perf/util/evsel.h
+++ b/tools/perf/util/evsel.h
@@ -402,10 +402,13 @@ bool perf_evsel__is_function_event(struct perf_evsel *evsel);
 static inline bool perf_evsel__is_bpf_output(struct perf_evsel *evsel)
 {
-        struct perf_event_attr *attr = &evsel->attr;
+        return perf_evsel__match(evsel, SOFTWARE, SW_BPF_OUTPUT);
+}
-        return (attr->config == PERF_COUNT_SW_BPF_OUTPUT) &&
+static inline bool perf_evsel__is_clock(struct perf_evsel *evsel)
-                (attr->type == PERF_TYPE_SOFTWARE);
+{
+        return perf_evsel__match(evsel, SOFTWARE, SW_CPU_CLOCK) ||
+               perf_evsel__match(evsel, SOFTWARE, SW_TASK_CLOCK);
 }
 struct perf_attr_details {
diff --git a/tools/perf/util/header.c b/tools/perf/util/header.c
index 540cd2dcd3e7..5af58aac91ad 100644
--- a/tools/perf/util/header.c
+++ b/tools/perf/util/header.c
@@ -2129,6 +2129,7 @@ static int process_cpu_topology(struct feat_fd *ff, void *data __maybe_unused)
        int cpu_nr = ff->ph->env.nr_cpus_avail;
        u64 size = 0;
        struct perf_header *ph = ff->ph;
+        bool do_core_id_test = true;
        ph->env.cpu = calloc(cpu_nr, sizeof(*ph->env.cpu));
        if (!ph->env.cpu)
@@ -2183,6 +2184,13 @@ static int process_cpu_topology(struct feat_fd *ff, void *data __maybe_unused)
                return 0;
        }
+        /* On s390 the socket_id number is not related to the numbers of cpus.
+         * The socket_id number might be higher than the numbers of cpus.
+         * This depends on the configuration.
+         */
+        if (ph->env.arch && !strncmp(ph->env.arch, "s390", 4))
+                do_core_id_test = false;
        for (i = 0; i < (u32)cpu_nr; i++) {
                if (do_read_u32(ff, &nr))
                        goto free_cpu;
@@ -2192,7 +2200,7 @@ static int process_cpu_topology(struct feat_fd *ff, void *data __maybe_unused)
                if (do_read_u32(ff, &nr))
                        goto free_cpu;
-                if (nr != (u32)-1 && nr > (u32)cpu_nr) {
+                if (do_core_id_test && nr != (u32)-1 && nr > (u32)cpu_nr) {
                        pr_debug("socket_id number is too big."
                                 "You may need to upgrade the perf tool.\n");
                        goto free_cpu;
@@ -2579,7 +2587,7 @@ static const struct feature_ops feat_ops[HEADER_LAST_FEATURE] = {
        FEAT_OPR(NUMA_TOPOLOGY, numa_topology,  true),
        FEAT_OPN(BRANCH_STACK,  branch_stack,   false),
        FEAT_OPR(PMU_MAPPINGS,  pmu_mappings,   false),
-        FEAT_OPN(GROUP_DESC,    group_desc,     false),
+        FEAT_OPR(GROUP_DESC,    group_desc,     false),
        FEAT_OPN(AUXTRACE,      auxtrace,       false),
        FEAT_OPN(STAT,          stat,           false),
        FEAT_OPN(CACHE,         cache,          true),
@@ -3456,7 +3464,7 @@ int perf_event__process_feature(struct perf_tool *tool,
                pr_warning("invalid record type %d in pipe-mode\n", type);
                return 0;
        }
-        if (feat == HEADER_RESERVED || feat > HEADER_LAST_FEATURE) {
+        if (feat == HEADER_RESERVED || feat >= HEADER_LAST_FEATURE) {
                pr_warning("invalid record type %d in pipe-mode\n", type);
                return -1;
        }
diff --git a/tools/perf/util/header.h b/tools/perf/util/header.h
index 90d4577a92dc..6d7fe44aadc0 100644
--- a/tools/perf/util/header.h
+++ b/tools/perf/util/header.h
@@ -2,6 +2,7 @@
 #ifndef __PERF_HEADER_H
 #define __PERF_HEADER_H
+#include <linux/stddef.h>
 #include <linux/perf_event.h>
 #include <sys/types.h>
 #include <stdbool.h>
diff --git a/tools/perf/util/hist.c b/tools/perf/util/hist.c
index 52e8fda93a47..828cb9794c76 100644
--- a/tools/perf/util/hist.c
+++ b/tools/perf/util/hist.c
@@ -370,9 +370,11 @@ void hists__delete_entries(struct hists *hists)
 static int hist_entry__init(struct hist_entry *he,
                            struct hist_entry *template,
-                            bool sample_self)
+                            bool sample_self,
+                            size_t callchain_size)
 {
        *he = *template;
+        he->callchain_size = callchain_size;
        if (symbol_conf.cumulate_callchain) {
                he->stat_acc = malloc(sizeof(he->stat));
@@ -473,7 +475,7 @@ static struct hist_entry *hist_entry__new(struct hist_entry *template,
        he = ops->new(callchain_size);
        if (he) {
-                err = hist_entry__init(he, template, sample_self);
+                err = hist_entry__init(he, template, sample_self, callchain_size);
                if (err) {
                        ops->free(he);
                        he = NULL;
@@ -619,9 +621,11 @@ __hists__add_entry(struct hists *hists,
                .raw_data = sample->raw_data,
                .raw_size = sample->raw_size,
                .ops = ops,
-        };
+        }, *he = hists__findnew_entry(hists, &entry, al, sample_self);
-        return hists__findnew_entry(hists, &entry, al, sample_self);
+        if (!hists->has_callchains && he && he->callchain_size != 0)
+                hists->has_callchains = true;
+        return he;
 }
 struct hist_entry *hists__add_entry(struct hists *hists,
diff --git a/tools/perf/util/hist.h b/tools/perf/util/hist.h
index 06607c434949..3badd7f1e1b8 100644
--- a/tools/perf/util/hist.h
+++ b/tools/perf/util/hist.h
@@ -85,6 +85,7 @@ struct hists {
        struct events_stats     stats;
        u64                     event_stream;
        u16                     col_len[HISTC_NR_COLS];
+        bool                    has_callchains;
        int                     socket_filter;
        struct perf_hpp_list    *hpp_list;
        struct list_head        hpp_formats;
@@ -180,7 +181,7 @@ size_t events_stats__fprintf(struct events_stats *stats, FILE *fp);
 size_t hists__fprintf(struct hists *hists, bool show_header, int max_rows,
                      int max_cols, float min_pcnt, FILE *fp,
-                      bool use_callchain);
+                      bool ignore_callchains);
 size_t perf_evlist__fprintf_nr_events(struct perf_evlist *evlist, FILE *fp);
 void hists__filter_by_dso(struct hists *hists);
@@ -222,8 +223,7 @@ static inline struct hists *evsel__hists(struct perf_evsel *evsel)
 static __pure inline bool hists__has_callchains(struct hists *hists)
 {
-        const struct perf_evsel *evsel = hists_to_evsel(hists);
+        return hists->has_callchains;
-        return evsel__has_callchain(evsel);
 }
 int hists__init(void);
diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c b/tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c
index ba4c9dd18643..d426761a549d 100644
--- a/tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c
+++ b/tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c
@@ -366,7 +366,7 @@ static int intel_pt_get_cyc(unsigned int byte, const unsigned char *buf,
                if (len < offs)
                        return INTEL_PT_NEED_MORE_BYTES;
                byte = buf[offs++];
-                payload |= (byte >> 1) << shift;
+                payload |= ((uint64_t)byte >> 1) << shift;
        }
        packet->type = INTEL_PT_CYC;
diff --git a/tools/perf/util/llvm-utils.c b/tools/perf/util/llvm-utils.c
index 976e658e38dc..5e94857dfca2 100644
--- a/tools/perf/util/llvm-utils.c
+++ b/tools/perf/util/llvm-utils.c
@@ -266,16 +266,16 @@ static const char *kinc_fetch_script =
 "#!/usr/bin/env sh\n"
 "if ! test -d \"$KBUILD_DIR\"\n"
 "then\n"
-"       exit -1\n"
+"       exit 1\n"
 "fi\n"
 "if ! test -f \"$KBUILD_DIR/include/generated/autoconf.h\"\n"
 "then\n"
-"       exit -1\n"
+"       exit 1\n"
 "fi\n"
 "TMPDIR=`mktemp -d`\n"
 "if test -z \"$TMPDIR\"\n"
 "then\n"
-"    exit -1\n"
+"    exit 1\n"
 "fi\n"
 "cat << EOF > $TMPDIR/Makefile\n"
 "obj-y := dummy.o\n"
diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c
index e7b4a8b513f2..b300a3973448 100644
--- a/tools/perf/util/machine.c
+++ b/tools/perf/util/machine.c
@@ -408,23 +408,16 @@ out_err:
 }
 /*
- * Caller must eventually drop thread->refcnt returned with a successful
+ * Front-end cache - TID lookups come in blocks,
- * lookup/new thread inserted.
+ * so most of the time we dont have to look up
+ * the full rbtree:
 */
-static struct thread *____machine__findnew_thread(struct machine *machine,
+static struct thread*
-                                                  struct threads *threads,
+__threads__get_last_match(struct threads *threads, struct machine *machine,
-                                                  pid_t pid, pid_t tid,
+                          int pid, int tid)
-                                                  bool create)
 {
-        struct rb_node **p = &threads->entries.rb_node;
-        struct rb_node *parent = NULL;
        struct thread *th;
-        /*
-         * Front-end cache - TID lookups come in blocks,
-         * so most of the time we dont have to look up
-         * the full rbtree:
-         */
        th = threads->last_match;
        if (th != NULL) {
                if (th->tid == tid) {
@@ -435,12 +428,57 @@ static struct thread *____machine__findnew_thread(struct machine *machine,
                threads->last_match = NULL;
        }
+        return NULL;
+}
+static struct thread*
+threads__get_last_match(struct threads *threads, struct machine *machine,
+                        int pid, int tid)
+{
+        struct thread *th = NULL;
+        if (perf_singlethreaded)
+                th = __threads__get_last_match(threads, machine, pid, tid);
+        return th;
+}
+static void
+__threads__set_last_match(struct threads *threads, struct thread *th)
+{
+        threads->last_match = th;
+}
+static void
+threads__set_last_match(struct threads *threads, struct thread *th)
+{
+        if (perf_singlethreaded)
+                __threads__set_last_match(threads, th);
+}
+/*
+ * Caller must eventually drop thread->refcnt returned with a successful
+ * lookup/new thread inserted.
+ */
+static struct thread *____machine__findnew_thread(struct machine *machine,
+                                                  struct threads *threads,
+                                                  pid_t pid, pid_t tid,
+                                                  bool create)
+{
+        struct rb_node **p = &threads->entries.rb_node;
+        struct rb_node *parent = NULL;
+        struct thread *th;
+        th = threads__get_last_match(threads, machine, pid, tid);
+        if (th)
+                return th;
        while (*p != NULL) {
                parent = *p;
                th = rb_entry(parent, struct thread, rb_node);
                if (th->tid == tid) {
-                        threads->last_match = th;
+                        threads__set_last_match(threads, th);
                        machine__update_thread_pid(machine, th, pid);
                        return thread__get(th);
                }
@@ -477,7 +515,7 @@ static struct thread *____machine__findnew_thread(struct machine *machine,
                 * It is now in the rbtree, get a ref
                 */
                thread__get(th);
-                threads->last_match = th;
+                threads__set_last_match(threads, th);
                ++threads->nr;
        }
@@ -1635,7 +1673,7 @@ static void __machine__remove_thread(struct machine *machine, struct thread *th,
        struct threads *threads = machine__threads(machine, th->tid);
        if (threads->last_match == th)
-                threads->last_match = NULL;
+                threads__set_last_match(threads, NULL);
        BUG_ON(refcount_read(&th->refcnt) == 0);
        if (lock)
@@ -2272,6 +2310,7 @@ static int unwind_entry(struct unwind_entry *entry, void *arg)
 {
        struct callchain_cursor *cursor = arg;
        const char *srcline = NULL;
+        u64 addr;
        if (symbol_conf.hide_unresolved && entry->sym == NULL)
                return 0;
@@ -2279,7 +2318,13 @@ static int unwind_entry(struct unwind_entry *entry, void *arg)
        if (append_inlines(cursor, entry->map, entry->sym, entry->ip) == 0)
                return 0;
-        srcline = callchain_srcline(entry->map, entry->sym, entry->ip);
+        /*
+         * Convert entry->ip from a virtual address to an offset in
+         * its corresponding binary.
+         */
+        addr = map__map_ip(entry->map, entry->ip);
+        srcline = callchain_srcline(entry->map, entry->sym, addr);
        return callchain_cursor_append(cursor, entry->ip,
                                       entry->map, entry->sym,
                                       false, NULL, 0, 0, 0, srcline);
diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c
index 1ddc3d1d0147..a28f9b5cc4ff 100644
--- a/tools/perf/util/metricgroup.c
+++ b/tools/perf/util/metricgroup.c
@@ -326,8 +326,8 @@ void metricgroup__print(bool metrics, bool metricgroups, char *filter,
                                if (raw)
                                        s = (char *)pe->metric_name;
                                else {
-                                        if (asprintf(&s, "%s\n\t[%s]",
+                                        if (asprintf(&s, "%s\n%*s%s]",
-                                                     pe->metric_name, pe->desc) < 0)
+                                                     pe->metric_name, 8, "[", pe->desc) < 0)
                                                return;
                                }
@@ -490,3 +490,25 @@ out:
        metricgroup__free_egroups(&group_list);
        return ret;
 }
+bool metricgroup__has_metric(const char *metric)
+{
+        struct pmu_events_map *map = perf_pmu__find_map(NULL);
+        struct pmu_event *pe;
+        int i;
+        if (!map)
+                return false;
+        for (i = 0; ; i++) {
+                pe = &map->table[i];
+                if (!pe->name && !pe->metric_group && !pe->metric_name)
+                        break;
+                if (!pe->metric_expr)
+                        continue;
+                if (match_metric(pe->metric_name, metric))
+                        return true;
+        }
+        return false;
+}
diff --git a/tools/perf/util/metricgroup.h b/tools/perf/util/metricgroup.h
index 06854e125ee7..8a155dba0581 100644
--- a/tools/perf/util/metricgroup.h
+++ b/tools/perf/util/metricgroup.h
@@ -28,4 +28,5 @@ int metricgroup__parse_groups(const struct option *opt,
                        struct rblist *metric_events);
 void metricgroup__print(bool metrics, bool groups, char *filter, bool raw);
+bool metricgroup__has_metric(const char *metric);
 #endif
diff --git a/tools/perf/util/namespaces.h b/tools/perf/util/namespaces.h
index 760558dcfd18..cae1a9a39722 100644
--- a/tools/perf/util/namespaces.h
+++ b/tools/perf/util/namespaces.h
@@ -10,6 +10,7 @@
 #define __PERF_NAMESPACES_H
 #include <sys/types.h>
+#include <linux/stddef.h>
 #include <linux/perf_event.h>
 #include <linux/refcount.h>
 #include <linux/types.h>
diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y
index 155d2570274f..da8fe57691b8 100644
--- a/tools/perf/util/parse-events.y
+++ b/tools/perf/util/parse-events.y
@@ -227,11 +227,16 @@ event_def: event_pmu |
 event_pmu:
 PE_NAME opt_pmu_config
 {
+        struct parse_events_state *parse_state = _parse_state;
+        struct parse_events_error *error = parse_state->error;
        struct list_head *list, *orig_terms, *terms;
        if (parse_events_copy_term_list($2, &orig_terms))
                YYABORT;
+        if (error)
+                error->idx = @1.first_column;
        ALLOC_LIST(list);
        if (parse_events_add_pmu(_parse_state, list, $1, $2, false, false)) {
                struct perf_pmu *pmu = NULL;
diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
index d2fb597c9a8c..afd68524ffa9 100644
--- a/tools/perf/util/pmu.c
+++ b/tools/perf/util/pmu.c
@@ -234,6 +234,74 @@ static int perf_pmu__parse_snapshot(struct perf_pmu_alias *alias,
        return 0;
 }
+static void perf_pmu_assign_str(char *name, const char *field, char **old_str,
+                                char **new_str)
+{
+        if (!*old_str)
+                goto set_new;
+        if (*new_str) { /* Have new string, check with old */
+                if (strcasecmp(*old_str, *new_str))
+                        pr_debug("alias %s differs in field '%s'\n",
+                                 name, field);
+                zfree(old_str);
+        } else          /* Nothing new --> keep old string */
+                return;
+set_new:
+        *old_str = *new_str;
+        *new_str = NULL;
+}
+static void perf_pmu_update_alias(struct perf_pmu_alias *old,
+                                  struct perf_pmu_alias *newalias)
+{
+        perf_pmu_assign_str(old->name, "desc", &old->desc, &newalias->desc);
+        perf_pmu_assign_str(old->name, "long_desc", &old->long_desc,
+                            &newalias->long_desc);
+        perf_pmu_assign_str(old->name, "topic", &old->topic, &newalias->topic);
+        perf_pmu_assign_str(old->name, "metric_expr", &old->metric_expr,
+                            &newalias->metric_expr);
+        perf_pmu_assign_str(old->name, "metric_name", &old->metric_name,
+                            &newalias->metric_name);
+        perf_pmu_assign_str(old->name, "value", &old->str, &newalias->str);
+        old->scale = newalias->scale;
+        old->per_pkg = newalias->per_pkg;
+        old->snapshot = newalias->snapshot;
+        memcpy(old->unit, newalias->unit, sizeof(old->unit));
+}
+/* Delete an alias entry. */
+static void perf_pmu_free_alias(struct perf_pmu_alias *newalias)
+{
+        zfree(&newalias->name);
+        zfree(&newalias->desc);
+        zfree(&newalias->long_desc);
+        zfree(&newalias->topic);
+        zfree(&newalias->str);
+        zfree(&newalias->metric_expr);
+        zfree(&newalias->metric_name);
+        parse_events_terms__purge(&newalias->terms);
+        free(newalias);
+}
+/* Merge an alias, search in alias list. If this name is already
+ * present merge both of them to combine all information.
+ */
+static bool perf_pmu_merge_alias(struct perf_pmu_alias *newalias,
+                                 struct list_head *alist)
+{
+        struct perf_pmu_alias *a;
+        list_for_each_entry(a, alist, list) {
+                if (!strcasecmp(newalias->name, a->name)) {
+                        perf_pmu_update_alias(a, newalias);
+                        perf_pmu_free_alias(newalias);
+                        return true;
+                }
+        }
+        return false;
+}
 static int __perf_pmu__new_alias(struct list_head *list, char *dir, char *name,
                                 char *desc, char *val,
                                 char *long_desc, char *topic,
@@ -241,9 +309,11 @@ static int __perf_pmu__new_alias(struct list_head *list, char *dir, char *name,
                                 char *metric_expr,
                                 char *metric_name)
 {
+        struct parse_events_term *term;
        struct perf_pmu_alias *alias;
        int ret;
        int num;
+        char newval[256];
        alias = malloc(sizeof(*alias));
        if (!alias)
@@ -262,6 +332,27 @@ static int __perf_pmu__new_alias(struct list_head *list, char *dir, char *name,
                return ret;
        }
+        /* Scan event and remove leading zeroes, spaces, newlines, some
+         * platforms have terms specified as
+         * event=0x0091 (read from files ../<PMU>/events/<FILE>
+         * and terms specified as event=0x91 (read from JSON files).
+         *
+         * Rebuild string to make alias->str member comparable.
+         */
+        memset(newval, 0, sizeof(newval));
+        ret = 0;
+        list_for_each_entry(term, &alias->terms, list) {
+                if (ret)
+                        ret += scnprintf(newval + ret, sizeof(newval) - ret,
+                                         ",");
+                if (term->type_val == PARSE_EVENTS__TERM_TYPE_NUM)
+                        ret += scnprintf(newval + ret, sizeof(newval) - ret,
+                                         "%s=%#x", term->config, term->val.num);
+                else if (term->type_val == PARSE_EVENTS__TERM_TYPE_STR)
+                        ret += scnprintf(newval + ret, sizeof(newval) - ret,
+                                         "%s=%s", term->config, term->val.str);
+        }
        alias->name = strdup(name);
        if (dir) {
                /*
@@ -285,9 +376,10 @@ static int __perf_pmu__new_alias(struct list_head *list, char *dir, char *name,
                snprintf(alias->unit, sizeof(alias->unit), "%s", unit);
        }
        alias->per_pkg = perpkg && sscanf(perpkg, "%d", &num) == 1 && num == 1;
-        alias->str = strdup(val);
+        alias->str = strdup(newval);
-        list_add_tail(&alias->list, list);
+        if (!perf_pmu_merge_alias(alias, list))
+                list_add_tail(&alias->list, list);
        return 0;
 }
@@ -303,6 +395,9 @@ static int perf_pmu__new_alias(struct list_head *list, char *dir, char *name, FI
        buf[ret] = 0;
+        /* Remove trailing newline from sysfs file */
+        rtrim(buf);
        return __perf_pmu__new_alias(list, dir, name, NULL, buf, NULL, NULL, NULL,
                                     NULL, NULL, NULL);
 }
@@ -557,12 +652,6 @@ static int is_arm_pmu_core(const char *name)
        if (stat(path, &st) == 0)
                return 1;
-        /* Look for cpu sysfs (specific to s390) */
-        scnprintf(path, PATH_MAX, "%s/bus/event_source/devices/%s",
-                  sysfs, name);
-        if (stat(path, &st) == 0 && !strncmp(name, "cpum_", 5))
-                return 1;
        return 0;
 }
diff --git a/tools/perf/util/scripting-engines/trace-event-python.c b/tools/perf/util/scripting-engines/trace-event-python.c
index 46e9e19ab1ac..bc32e57d17be 100644
--- a/tools/perf/util/scripting-engines/trace-event-python.c
+++ b/tools/perf/util/scripting-engines/trace-event-python.c
@@ -908,14 +908,11 @@ static void python_process_tracepoint(struct perf_sample *sample,
        if (_PyTuple_Resize(&t, n) == -1)
                Py_FatalError("error resizing Python tuple");
-        if (!dict) {
+        if (!dict)
                call_object(handler, t, handler_name);
-        } else {
+        else
                call_object(handler, t, default_handler_name);
-                Py_DECREF(dict);
-        }
-        Py_XDECREF(all_entries_dict);
        Py_DECREF(t);
 }
@@ -1235,7 +1232,6 @@ static void python_process_general_event(struct perf_sample *sample,
        call_object(handler, t, handler_name);
-        Py_DECREF(dict);
        Py_DECREF(t);
 }
@@ -1627,6 +1623,7 @@ static int python_generate_script(struct pevent *pevent, const char *outfile)
        fprintf(ofp, "# See the perf-script-python Documentation for the list "
                "of available functions.\n\n");
+        fprintf(ofp, "from __future__ import print_function\n\n");
        fprintf(ofp, "import os\n");
        fprintf(ofp, "import sys\n\n");
@@ -1636,10 +1633,10 @@ static int python_generate_script(struct pevent *pevent, const char *outfile)
        fprintf(ofp, "from Core import *\n\n\n");
        fprintf(ofp, "def trace_begin():\n");
-        fprintf(ofp, "\tprint \"in trace_begin\"\n\n");
+        fprintf(ofp, "\tprint(\"in trace_begin\")\n\n");
        fprintf(ofp, "def trace_end():\n");
-        fprintf(ofp, "\tprint \"in trace_end\"\n\n");
+        fprintf(ofp, "\tprint(\"in trace_end\")\n\n");
        while ((event = trace_find_next_event(pevent, event))) {
                fprintf(ofp, "def %s__%s(", event->system, event->name);
@@ -1675,7 +1672,7 @@ static int python_generate_script(struct pevent *pevent, const char *outfile)
                        "common_secs, common_nsecs,\n\t\t\t"
                        "common_pid, common_comm)\n\n");
-                fprintf(ofp, "\t\tprint \"");
+                fprintf(ofp, "\t\tprint(\"");
                not_first = 0;
                count = 0;
@@ -1736,31 +1733,31 @@ static int python_generate_script(struct pevent *pevent, const char *outfile)
                                fprintf(ofp, "%s", f->name);
                }
-                fprintf(ofp, ")\n\n");
+                fprintf(ofp, "))\n\n");
-                fprintf(ofp, "\t\tprint 'Sample: {'+"
+                fprintf(ofp, "\t\tprint('Sample: {'+"
-                        "get_dict_as_string(perf_sample_dict['sample'], ', ')+'}'\n\n");
+                        "get_dict_as_string(perf_sample_dict['sample'], ', ')+'}')\n\n");
                fprintf(ofp, "\t\tfor node in common_callchain:");
                fprintf(ofp, "\n\t\t\tif 'sym' in node:");
-                fprintf(ofp, "\n\t\t\t\tprint \"\\t[%%x] %%s\" %% (node['ip'], node['sym']['name'])");
+                fprintf(ofp, "\n\t\t\t\tprint(\"\\t[%%x] %%s\" %% (node['ip'], node['sym']['name']))");
                fprintf(ofp, "\n\t\t\telse:");
-                fprintf(ofp, "\n\t\t\t\tprint \"\t[%%x]\" %% (node['ip'])\n\n");
+                fprintf(ofp, "\n\t\t\t\tprint(\"\t[%%x]\" %% (node['ip']))\n\n");
-                fprintf(ofp, "\t\tprint \"\\n\"\n\n");
+                fprintf(ofp, "\t\tprint()\n\n");
        }
        fprintf(ofp, "def trace_unhandled(event_name, context, "
                "event_fields_dict, perf_sample_dict):\n");
-        fprintf(ofp, "\t\tprint get_dict_as_string(event_fields_dict)\n");
+        fprintf(ofp, "\t\tprint(get_dict_as_string(event_fields_dict))\n");
-        fprintf(ofp, "\t\tprint 'Sample: {'+"
+        fprintf(ofp, "\t\tprint('Sample: {'+"
-                "get_dict_as_string(perf_sample_dict['sample'], ', ')+'}'\n\n");
+                "get_dict_as_string(perf_sample_dict['sample'], ', ')+'}')\n\n");
        fprintf(ofp, "def print_header("
                "event_name, cpu, secs, nsecs, pid, comm):\n"
-                "\tprint \"%%-20s %%5u %%05u.%%09u %%8u %%-20s \" %% \\\n\t"
+                "\tprint(\"%%-20s %%5u %%05u.%%09u %%8u %%-20s \" %% \\\n\t"
-                "(event_name, cpu, secs, nsecs, pid, comm),\n\n");
+                "(event_name, cpu, secs, nsecs, pid, comm), end=\"\")\n\n");
        fprintf(ofp, "def get_dict_as_string(a_dict, delimiter=' '):\n"
                "\treturn delimiter.join"
diff --git a/tools/perf/util/sort.h b/tools/perf/util/sort.h
index 7cf2d5cc038e..8bf302cafcec 100644
--- a/tools/perf/util/sort.h
+++ b/tools/perf/util/sort.h
@@ -112,6 +112,8 @@ struct hist_entry {
        char                    level;
        u8                      filtered;
+        u16                     callchain_size;
        union {
                /*
                 * Since perf diff only supports the stdio output, TUI
@@ -153,7 +155,7 @@ struct hist_entry {
 static __pure inline bool hist_entry__has_callchains(struct hist_entry *he)
 {
-        return hists__has_callchains(he->hists);
+        return he->callchain_size != 0;
 }
 static inline bool hist_entry__has_pairs(struct hist_entry *he)
diff --git a/tools/perf/util/stat-shadow.c b/tools/perf/util/stat-shadow.c
index 594d14a02b67..99990f5f2512 100644
--- a/tools/perf/util/stat-shadow.c
+++ b/tools/perf/util/stat-shadow.c
@@ -913,11 +913,10 @@ void perf_stat__print_shadow_stats(struct perf_evsel *evsel,
                        ratio = total / avg;
                print_metric(ctxp, NULL, "%8.0f", "cycles / elision", ratio);
-        } else if (perf_evsel__match(evsel, SOFTWARE, SW_TASK_CLOCK) ||
+        } else if (perf_evsel__is_clock(evsel)) {
-                   perf_evsel__match(evsel, SOFTWARE, SW_CPU_CLOCK)) {
                if ((ratio = avg_stats(&walltime_nsecs_stats)) != 0)
                        print_metric(ctxp, NULL, "%8.3f", "CPUs utilized",
-                                     avg / ratio);
+                                     avg / (ratio * evsel->scale));
                else
                        print_metric(ctxp, NULL, NULL, "CPUs utilized", 0);
        } else if (perf_stat_evsel__is(evsel, TOPDOWN_FETCH_BUBBLES)) {
diff --git a/tools/perf/util/syscalltbl.c b/tools/perf/util/syscalltbl.c
index 0ee7f568d60c..3393d7ee9401 100644
--- a/tools/perf/util/syscalltbl.c
+++ b/tools/perf/util/syscalltbl.c
@@ -38,6 +38,10 @@ static const char **syscalltbl_native = syscalltbl_powerpc_64;
 #include <asm/syscalls_32.c>
 const int syscalltbl_native_max_id = SYSCALLTBL_POWERPC_32_MAX_ID;
 static const char **syscalltbl_native = syscalltbl_powerpc_32;
+#elif defined(__aarch64__)
+#include <asm/syscalls.c>
+const int syscalltbl_native_max_id = SYSCALLTBL_ARM64_MAX_ID;
+static const char **syscalltbl_native = syscalltbl_arm64;
 #endif
 struct syscall {
diff --git a/tools/perf/util/unwind-libdw.c b/tools/perf/util/unwind-libdw.c
index 538db4e5d1e6..6f318b15950e 100644
--- a/tools/perf/util/unwind-libdw.c
+++ b/tools/perf/util/unwind-libdw.c
@@ -77,7 +77,7 @@ static int entry(u64 ip, struct unwind_info *ui)
        if (__report_module(&al, ip, ui))
                return -1;
-        e->ip  = al.addr;
+        e->ip  = ip;
        e->map = al.map;
        e->sym = al.sym;
diff --git a/tools/perf/util/unwind-libunwind-local.c b/tools/perf/util/unwind-libunwind-local.c
index 6a11bc7e6b27..79f521a552cf 100644
--- a/tools/perf/util/unwind-libunwind-local.c
+++ b/tools/perf/util/unwind-libunwind-local.c
@@ -575,7 +575,7 @@ static int entry(u64 ip, struct thread *thread,
        struct addr_location al;
        e.sym = thread__find_symbol(thread, PERF_RECORD_MISC_USER, ip, &al);
-        e.ip = al.addr;
+        e.ip  = ip;
        e.map = al.map;
        pr_debug("unwind: %s:ip = 0x%" PRIx64 " (0x%" PRIx64 ")\n",