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Diffstat (limited to 'sound/soc/dwc/designware_i2s.c')
-rw-r--r--sound/soc/dwc/designware_i2s.c49
1 files changed, 30 insertions, 19 deletions
diff --git a/sound/soc/dwc/designware_i2s.c b/sound/soc/dwc/designware_i2s.c
index b93168d4f648..8d18bbda661b 100644
--- a/sound/soc/dwc/designware_i2s.c
+++ b/sound/soc/dwc/designware_i2s.c
@@ -209,16 +209,9 @@ static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
209 209
210 switch (config->chan_nr) { 210 switch (config->chan_nr) {
211 case EIGHT_CHANNEL_SUPPORT: 211 case EIGHT_CHANNEL_SUPPORT:
212 ch_reg = 3;
213 break;
214 case SIX_CHANNEL_SUPPORT: 212 case SIX_CHANNEL_SUPPORT:
215 ch_reg = 2;
216 break;
217 case FOUR_CHANNEL_SUPPORT: 213 case FOUR_CHANNEL_SUPPORT:
218 ch_reg = 1;
219 break;
220 case TWO_CHANNEL_SUPPORT: 214 case TWO_CHANNEL_SUPPORT:
221 ch_reg = 0;
222 break; 215 break;
223 default: 216 default:
224 dev_err(dev->dev, "channel not supported\n"); 217 dev_err(dev->dev, "channel not supported\n");
@@ -227,18 +220,22 @@ static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
227 220
228 i2s_disable_channels(dev, substream->stream); 221 i2s_disable_channels(dev, substream->stream);
229 222
230 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 223 for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {
231 i2s_write_reg(dev->i2s_base, TCR(ch_reg), xfer_resolution); 224 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
232 i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02); 225 i2s_write_reg(dev->i2s_base, TCR(ch_reg),
233 irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); 226 xfer_resolution);
234 i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30); 227 i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02);
235 i2s_write_reg(dev->i2s_base, TER(ch_reg), 1); 228 irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
236 } else { 229 i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30);
237 i2s_write_reg(dev->i2s_base, RCR(ch_reg), xfer_resolution); 230 i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
238 i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07); 231 } else {
239 irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg)); 232 i2s_write_reg(dev->i2s_base, RCR(ch_reg),
240 i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03); 233 xfer_resolution);
241 i2s_write_reg(dev->i2s_base, RER(ch_reg), 1); 234 i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07);
235 irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
236 i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03);
237 i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
238 }
242 } 239 }
243 240
244 i2s_write_reg(dev->i2s_base, CCR, ccr); 241 i2s_write_reg(dev->i2s_base, CCR, ccr);
@@ -263,6 +260,19 @@ static void dw_i2s_shutdown(struct snd_pcm_substream *substream,
263 snd_soc_dai_set_dma_data(dai, substream, NULL); 260 snd_soc_dai_set_dma_data(dai, substream, NULL);
264} 261}
265 262
263static int dw_i2s_prepare(struct snd_pcm_substream *substream,
264 struct snd_soc_dai *dai)
265{
266 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
267
268 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
269 i2s_write_reg(dev->i2s_base, TXFFR, 1);
270 else
271 i2s_write_reg(dev->i2s_base, RXFFR, 1);
272
273 return 0;
274}
275
266static int dw_i2s_trigger(struct snd_pcm_substream *substream, 276static int dw_i2s_trigger(struct snd_pcm_substream *substream,
267 int cmd, struct snd_soc_dai *dai) 277 int cmd, struct snd_soc_dai *dai)
268{ 278{
@@ -294,6 +304,7 @@ static struct snd_soc_dai_ops dw_i2s_dai_ops = {
294 .startup = dw_i2s_startup, 304 .startup = dw_i2s_startup,
295 .shutdown = dw_i2s_shutdown, 305 .shutdown = dw_i2s_shutdown,
296 .hw_params = dw_i2s_hw_params, 306 .hw_params = dw_i2s_hw_params,
307 .prepare = dw_i2s_prepare,
297 .trigger = dw_i2s_trigger, 308 .trigger = dw_i2s_trigger,
298}; 309};
299 310