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-rw-r--r--sound/soc/codecs/88pm860x-codec.c20
-rw-r--r--sound/soc/codecs/Kconfig86
-rw-r--r--sound/soc/codecs/Makefile32
-rw-r--r--sound/soc/codecs/ab8500-codec.c12
-rw-r--r--sound/soc/codecs/ad1980.c39
-rw-r--r--sound/soc/codecs/adau1373.c7
-rw-r--r--sound/soc/codecs/adau1761-i2c.c60
-rw-r--r--sound/soc/codecs/adau1761-spi.c77
-rw-r--r--sound/soc/codecs/adau1761.c803
-rw-r--r--sound/soc/codecs/adau1761.h23
-rw-r--r--sound/soc/codecs/adau1781-i2c.c58
-rw-r--r--sound/soc/codecs/adau1781-spi.c75
-rw-r--r--sound/soc/codecs/adau1781.c511
-rw-r--r--sound/soc/codecs/adau1781.h23
-rw-r--r--sound/soc/codecs/adau17x1.c866
-rw-r--r--sound/soc/codecs/adau17x1.h124
-rw-r--r--sound/soc/codecs/adav80x.c12
-rw-r--r--sound/soc/codecs/ak4104.c62
-rw-r--r--sound/soc/codecs/ak4641.c4
-rw-r--r--sound/soc/codecs/ak4642.c75
-rw-r--r--sound/soc/codecs/alc5623.c22
-rw-r--r--sound/soc/codecs/arizona.h4
-rw-r--r--sound/soc/codecs/cq93vc.c10
-rw-r--r--sound/soc/codecs/cs4270.c2
-rw-r--r--sound/soc/codecs/cs4271.c4
-rw-r--r--sound/soc/codecs/cs42l51-i2c.c59
-rw-r--r--sound/soc/codecs/cs42l51.c80
-rw-r--r--sound/soc/codecs/cs42l51.h6
-rw-r--r--sound/soc/codecs/cs42l52.c18
-rw-r--r--sound/soc/codecs/cs42l56.c1419
-rw-r--r--sound/soc/codecs/cs42l56.h177
-rw-r--r--sound/soc/codecs/cs42l73.c6
-rw-r--r--sound/soc/codecs/cs42xx8.c3
-rw-r--r--sound/soc/codecs/da7210.c4
-rw-r--r--sound/soc/codecs/da7213.c4
-rw-r--r--sound/soc/codecs/da732x.c4
-rw-r--r--sound/soc/codecs/da9055.c2
-rw-r--r--sound/soc/codecs/hdmi.c1
-rw-r--r--sound/soc/codecs/lm4857.c4
-rw-r--r--sound/soc/codecs/max9768.c4
-rw-r--r--sound/soc/codecs/max98088.c12
-rw-r--r--sound/soc/codecs/max98090.c118
-rw-r--r--sound/soc/codecs/max98090.h2
-rw-r--r--sound/soc/codecs/max98095.c47
-rw-r--r--sound/soc/codecs/mc13783.c36
-rw-r--r--sound/soc/codecs/pcm1681.c4
-rw-r--r--sound/soc/codecs/pcm512x.c4
-rw-r--r--sound/soc/codecs/rl6231.c152
-rw-r--r--sound/soc/codecs/rl6231.h34
-rw-r--r--sound/soc/codecs/rt5631.c4
-rw-r--r--sound/soc/codecs/rt5640.c532
-rw-r--r--sound/soc/codecs/rt5640.h18
-rw-r--r--sound/soc/codecs/rt5645.c2378
-rw-r--r--sound/soc/codecs/rt5645.h2181
-rw-r--r--sound/soc/codecs/rt5651.c1818
-rw-r--r--sound/soc/codecs/rt5651.h2080
-rw-r--r--sound/soc/codecs/rt5677.c3498
-rw-r--r--sound/soc/codecs/rt5677.h1451
-rw-r--r--sound/soc/codecs/sgtl5000.c90
-rw-r--r--sound/soc/codecs/si476x.c14
-rw-r--r--sound/soc/codecs/sirf-audio-codec.c82
-rw-r--r--sound/soc/codecs/sirf-audio-codec.h50
-rw-r--r--sound/soc/codecs/sta32x.c4
-rw-r--r--sound/soc/codecs/sta350.c1311
-rw-r--r--sound/soc/codecs/sta350.h238
-rw-r--r--sound/soc/codecs/tas5086.c4
-rw-r--r--sound/soc/codecs/tlv320aic23-i2c.c1
-rw-r--r--sound/soc/codecs/tlv320aic23.c4
-rw-r--r--sound/soc/codecs/tlv320aic31xx.c3
-rw-r--r--sound/soc/codecs/tlv320aic3x.c11
-rw-r--r--sound/soc/codecs/tlv320dac33.c12
-rw-r--r--sound/soc/codecs/tpa6130a2.c1
-rw-r--r--sound/soc/codecs/twl4030.c10
-rw-r--r--sound/soc/codecs/twl6040.c8
-rw-r--r--sound/soc/codecs/wl1273.c12
-rw-r--r--sound/soc/codecs/wm2000.c8
-rw-r--r--sound/soc/codecs/wm2200.c4
-rw-r--r--sound/soc/codecs/wm5100.c4
-rw-r--r--sound/soc/codecs/wm5102.c26
-rw-r--r--sound/soc/codecs/wm5110.c35
-rw-r--r--sound/soc/codecs/wm8350.c14
-rw-r--r--sound/soc/codecs/wm8400.c12
-rw-r--r--sound/soc/codecs/wm8580.c2
-rw-r--r--sound/soc/codecs/wm8731.c11
-rw-r--r--sound/soc/codecs/wm8753.c4
-rw-r--r--sound/soc/codecs/wm8804.c11
-rw-r--r--sound/soc/codecs/wm8903.c4
-rw-r--r--sound/soc/codecs/wm8904.c14
-rw-r--r--sound/soc/codecs/wm8955.c13
-rw-r--r--sound/soc/codecs/wm8958-dsp2.c32
-rw-r--r--sound/soc/codecs/wm8960.c4
-rw-r--r--sound/soc/codecs/wm8962.c35
-rw-r--r--sound/soc/codecs/wm8962.h4
-rw-r--r--sound/soc/codecs/wm8983.c4
-rw-r--r--sound/soc/codecs/wm8985.c11
-rw-r--r--sound/soc/codecs/wm8988.c8
-rw-r--r--sound/soc/codecs/wm8990.c2
-rw-r--r--sound/soc/codecs/wm8991.c2
-rw-r--r--sound/soc/codecs/wm8994.c32
-rw-r--r--sound/soc/codecs/wm8995.c10
-rw-r--r--sound/soc/codecs/wm8996.c4
-rw-r--r--sound/soc/codecs/wm8997.c25
-rw-r--r--sound/soc/codecs/wm9081.c4
-rw-r--r--sound/soc/codecs/wm_adsp.c43
-rw-r--r--sound/soc/codecs/wm_hubs.c2
105 files changed, 20614 insertions, 796 deletions
diff --git a/sound/soc/codecs/88pm860x-codec.c b/sound/soc/codecs/88pm860x-codec.c
index b07e17160f94..3c4b10ff48c1 100644
--- a/sound/soc/codecs/88pm860x-codec.c
+++ b/sound/soc/codecs/88pm860x-codec.c
@@ -276,7 +276,7 @@ static int snd_soc_get_volsw_2r_st(struct snd_kcontrol *kcontrol,
276{ 276{
277 struct soc_mixer_control *mc = 277 struct soc_mixer_control *mc =
278 (struct soc_mixer_control *)kcontrol->private_value; 278 (struct soc_mixer_control *)kcontrol->private_value;
279 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 279 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
280 unsigned int reg = mc->reg; 280 unsigned int reg = mc->reg;
281 unsigned int reg2 = mc->rreg; 281 unsigned int reg2 = mc->rreg;
282 int val[2], val2[2], i; 282 int val[2], val2[2], i;
@@ -300,7 +300,7 @@ static int snd_soc_put_volsw_2r_st(struct snd_kcontrol *kcontrol,
300{ 300{
301 struct soc_mixer_control *mc = 301 struct soc_mixer_control *mc =
302 (struct soc_mixer_control *)kcontrol->private_value; 302 (struct soc_mixer_control *)kcontrol->private_value;
303 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 303 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
304 unsigned int reg = mc->reg; 304 unsigned int reg = mc->reg;
305 unsigned int reg2 = mc->rreg; 305 unsigned int reg2 = mc->rreg;
306 int err; 306 int err;
@@ -333,7 +333,7 @@ static int snd_soc_get_volsw_2r_out(struct snd_kcontrol *kcontrol,
333{ 333{
334 struct soc_mixer_control *mc = 334 struct soc_mixer_control *mc =
335 (struct soc_mixer_control *)kcontrol->private_value; 335 (struct soc_mixer_control *)kcontrol->private_value;
336 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 336 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
337 unsigned int reg = mc->reg; 337 unsigned int reg = mc->reg;
338 unsigned int reg2 = mc->rreg; 338 unsigned int reg2 = mc->rreg;
339 unsigned int shift = mc->shift; 339 unsigned int shift = mc->shift;
@@ -353,7 +353,7 @@ static int snd_soc_put_volsw_2r_out(struct snd_kcontrol *kcontrol,
353{ 353{
354 struct soc_mixer_control *mc = 354 struct soc_mixer_control *mc =
355 (struct soc_mixer_control *)kcontrol->private_value; 355 (struct soc_mixer_control *)kcontrol->private_value;
356 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 356 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
357 unsigned int reg = mc->reg; 357 unsigned int reg = mc->reg;
358 unsigned int reg2 = mc->rreg; 358 unsigned int reg2 = mc->rreg;
359 unsigned int shift = mc->shift; 359 unsigned int shift = mc->shift;
@@ -1327,10 +1327,6 @@ static int pm860x_probe(struct snd_soc_codec *codec)
1327 1327
1328 pm860x->codec = codec; 1328 pm860x->codec = codec;
1329 1329
1330 ret = snd_soc_codec_set_cache_io(codec, pm860x->regmap);
1331 if (ret)
1332 return ret;
1333
1334 for (i = 0; i < 4; i++) { 1330 for (i = 0; i < 4; i++) {
1335 ret = request_threaded_irq(pm860x->irq[i], NULL, 1331 ret = request_threaded_irq(pm860x->irq[i], NULL,
1336 pm860x_codec_handler, IRQF_ONESHOT, 1332 pm860x_codec_handler, IRQF_ONESHOT,
@@ -1362,10 +1358,18 @@ static int pm860x_remove(struct snd_soc_codec *codec)
1362 return 0; 1358 return 0;
1363} 1359}
1364 1360
1361static struct regmap *pm860x_get_regmap(struct device *dev)
1362{
1363 struct pm860x_priv *pm860x = dev_get_drvdata(dev);
1364
1365 return pm860x->regmap;
1366}
1367
1365static struct snd_soc_codec_driver soc_codec_dev_pm860x = { 1368static struct snd_soc_codec_driver soc_codec_dev_pm860x = {
1366 .probe = pm860x_probe, 1369 .probe = pm860x_probe,
1367 .remove = pm860x_remove, 1370 .remove = pm860x_remove,
1368 .set_bias_level = pm860x_set_bias_level, 1371 .set_bias_level = pm860x_set_bias_level,
1372 .get_regmap = pm860x_get_regmap,
1369 1373
1370 .controls = pm860x_snd_controls, 1374 .controls = pm860x_snd_controls,
1371 .num_controls = ARRAY_SIZE(pm860x_snd_controls), 1375 .num_controls = ARRAY_SIZE(pm860x_snd_controls),
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index f0e840137887..cbfa1e18f651 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -23,6 +23,10 @@ config SND_SOC_ALL_CODECS
23 select SND_SOC_AD1980 if SND_SOC_AC97_BUS 23 select SND_SOC_AD1980 if SND_SOC_AC97_BUS
24 select SND_SOC_AD73311 24 select SND_SOC_AD73311
25 select SND_SOC_ADAU1373 if I2C 25 select SND_SOC_ADAU1373 if I2C
26 select SND_SOC_ADAU1761_I2C if I2C
27 select SND_SOC_ADAU1761_SPI if SPI
28 select SND_SOC_ADAU1781_I2C if I2C
29 select SND_SOC_ADAU1781_SPI if SPI
26 select SND_SOC_ADAV801 if SPI_MASTER 30 select SND_SOC_ADAV801 if SPI_MASTER
27 select SND_SOC_ADAV803 if I2C 31 select SND_SOC_ADAV803 if I2C
28 select SND_SOC_ADAU1977_SPI if SPI_MASTER 32 select SND_SOC_ADAU1977_SPI if SPI_MASTER
@@ -39,8 +43,9 @@ config SND_SOC_ALL_CODECS
39 select SND_SOC_ALC5623 if I2C 43 select SND_SOC_ALC5623 if I2C
40 select SND_SOC_ALC5632 if I2C 44 select SND_SOC_ALC5632 if I2C
41 select SND_SOC_CQ0093VC if MFD_DAVINCI_VOICECODEC 45 select SND_SOC_CQ0093VC if MFD_DAVINCI_VOICECODEC
42 select SND_SOC_CS42L51 if I2C 46 select SND_SOC_CS42L51_I2C if I2C
43 select SND_SOC_CS42L52 if I2C 47 select SND_SOC_CS42L52 if I2C && INPUT
48 select SND_SOC_CS42L56 if I2C && INPUT
44 select SND_SOC_CS42L73 if I2C 49 select SND_SOC_CS42L73 if I2C
45 select SND_SOC_CS4270 if I2C 50 select SND_SOC_CS4270 if I2C
46 select SND_SOC_CS4271 if SND_SOC_I2C_AND_SPI 51 select SND_SOC_CS4271 if SND_SOC_I2C_AND_SPI
@@ -71,6 +76,9 @@ config SND_SOC_ALL_CODECS
71 select SND_SOC_PCM512x_SPI if SPI_MASTER 76 select SND_SOC_PCM512x_SPI if SPI_MASTER
72 select SND_SOC_RT5631 if I2C 77 select SND_SOC_RT5631 if I2C
73 select SND_SOC_RT5640 if I2C 78 select SND_SOC_RT5640 if I2C
79 select SND_SOC_RT5645 if I2C
80 select SND_SOC_RT5651 if I2C
81 select SND_SOC_RT5677 if I2C
74 select SND_SOC_SGTL5000 if I2C 82 select SND_SOC_SGTL5000 if I2C
75 select SND_SOC_SI476X if MFD_SI476X_CORE 83 select SND_SOC_SI476X if MFD_SI476X_CORE
76 select SND_SOC_SIRF_AUDIO_CODEC 84 select SND_SOC_SIRF_AUDIO_CODEC
@@ -80,6 +88,7 @@ config SND_SOC_ALL_CODECS
80 select SND_SOC_SSM2602_SPI if SPI_MASTER 88 select SND_SOC_SSM2602_SPI if SPI_MASTER
81 select SND_SOC_SSM2602_I2C if I2C 89 select SND_SOC_SSM2602_I2C if I2C
82 select SND_SOC_STA32X if I2C 90 select SND_SOC_STA32X if I2C
91 select SND_SOC_STA350 if I2C
83 select SND_SOC_STA529 if I2C 92 select SND_SOC_STA529 if I2C
84 select SND_SOC_STAC9766 if SND_SOC_AC97_BUS 93 select SND_SOC_STAC9766 if SND_SOC_AC97_BUS
85 select SND_SOC_TAS5086 if I2C 94 select SND_SOC_TAS5086 if I2C
@@ -127,7 +136,7 @@ config SND_SOC_ALL_CODECS
127 select SND_SOC_WM8955 if I2C 136 select SND_SOC_WM8955 if I2C
128 select SND_SOC_WM8960 if I2C 137 select SND_SOC_WM8960 if I2C
129 select SND_SOC_WM8961 if I2C 138 select SND_SOC_WM8961 if I2C
130 select SND_SOC_WM8962 if I2C 139 select SND_SOC_WM8962 if I2C && INPUT
131 select SND_SOC_WM8971 if I2C 140 select SND_SOC_WM8971 if I2C
132 select SND_SOC_WM8974 if I2C 141 select SND_SOC_WM8974 if I2C
133 select SND_SOC_WM8978 if I2C 142 select SND_SOC_WM8978 if I2C
@@ -210,13 +219,45 @@ config SND_SOC_AD1980
210config SND_SOC_AD73311 219config SND_SOC_AD73311
211 tristate 220 tristate
212 221
222config SND_SOC_ADAU1373
223 tristate
224
213config SND_SOC_ADAU1701 225config SND_SOC_ADAU1701
214 tristate "Analog Devices ADAU1701 CODEC" 226 tristate "Analog Devices ADAU1701 CODEC"
215 depends on I2C 227 depends on I2C
216 select SND_SOC_SIGMADSP 228 select SND_SOC_SIGMADSP
217 229
218config SND_SOC_ADAU1373 230config SND_SOC_ADAU17X1
231 tristate
232 select SND_SOC_SIGMADSP
233
234config SND_SOC_ADAU1761
235 tristate
236 select SND_SOC_ADAU17X1
237
238config SND_SOC_ADAU1761_I2C
239 tristate
240 select SND_SOC_ADAU1761
241 select REGMAP_I2C
242
243config SND_SOC_ADAU1761_SPI
244 tristate
245 select SND_SOC_ADAU1761
246 select REGMAP_SPI
247
248config SND_SOC_ADAU1781
249 select SND_SOC_ADAU17X1
250 tristate
251
252config SND_SOC_ADAU1781_I2C
253 tristate
254 select SND_SOC_ADAU1781
255 select REGMAP_I2C
256
257config SND_SOC_ADAU1781_SPI
219 tristate 258 tristate
259 select SND_SOC_ADAU1781
260 select REGMAP_SPI
220 261
221config SND_SOC_ADAU1977 262config SND_SOC_ADAU1977
222 tristate 263 tristate
@@ -269,7 +310,8 @@ config SND_SOC_AK5386
269 tristate "AKM AK5638 CODEC" 310 tristate "AKM AK5638 CODEC"
270 311
271config SND_SOC_ALC5623 312config SND_SOC_ALC5623
272 tristate 313 tristate "Realtek ALC5623 CODEC"
314 depends on I2C
273 315
274config SND_SOC_ALC5632 316config SND_SOC_ALC5632
275 tristate 317 tristate
@@ -280,9 +322,17 @@ config SND_SOC_CQ0093VC
280config SND_SOC_CS42L51 322config SND_SOC_CS42L51
281 tristate 323 tristate
282 324
325config SND_SOC_CS42L51_I2C
326 tristate
327 select SND_SOC_CS42L51
328
283config SND_SOC_CS42L52 329config SND_SOC_CS42L52
284 tristate "Cirrus Logic CS42L52 CODEC" 330 tristate "Cirrus Logic CS42L52 CODEC"
285 depends on I2C 331 depends on I2C && INPUT
332
333config SND_SOC_CS42L56
334 tristate "Cirrus Logic CS42L56 CODEC"
335 depends on I2C && INPUT
286 336
287config SND_SOC_CS42L73 337config SND_SOC_CS42L73
288 tristate "Cirrus Logic CS42L73 CODEC" 338 tristate "Cirrus Logic CS42L73 CODEC"
@@ -390,12 +440,30 @@ config SND_SOC_PCM512x_SPI
390 select SND_SOC_PCM512x 440 select SND_SOC_PCM512x
391 select REGMAP_SPI 441 select REGMAP_SPI
392 442
443config SND_SOC_RL6231
444 tristate
445 default y if SND_SOC_RT5640=y
446 default y if SND_SOC_RT5645=y
447 default y if SND_SOC_RT5651=y
448 default m if SND_SOC_RT5640=m
449 default m if SND_SOC_RT5645=m
450 default m if SND_SOC_RT5651=m
451
393config SND_SOC_RT5631 452config SND_SOC_RT5631
394 tristate 453 tristate
395 454
396config SND_SOC_RT5640 455config SND_SOC_RT5640
397 tristate 456 tristate
398 457
458config SND_SOC_RT5645
459 tristate
460
461config SND_SOC_RT5651
462 tristate
463
464config SND_SOC_RT5677
465 tristate
466
399#Freescale sgtl5000 codec 467#Freescale sgtl5000 codec
400config SND_SOC_SGTL5000 468config SND_SOC_SGTL5000
401 tristate "Freescale SGTL5000 CODEC" 469 tristate "Freescale SGTL5000 CODEC"
@@ -435,6 +503,10 @@ config SND_SOC_SSM2602_I2C
435config SND_SOC_STA32X 503config SND_SOC_STA32X
436 tristate 504 tristate
437 505
506config SND_SOC_STA350
507 tristate "STA350 speaker amplifier"
508 depends on I2C
509
438config SND_SOC_STA529 510config SND_SOC_STA529
439 tristate 511 tristate
440 512
@@ -598,7 +670,7 @@ config SND_SOC_WM8961
598 670
599config SND_SOC_WM8962 671config SND_SOC_WM8962
600 tristate "Wolfson Microelectronics WM8962 CODEC" 672 tristate "Wolfson Microelectronics WM8962 CODEC"
601 depends on I2C 673 depends on I2C && INPUT
602 674
603config SND_SOC_WM8971 675config SND_SOC_WM8971
604 tristate 676 tristate
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 3c4d275d064b..be3377b8d73f 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -7,8 +7,15 @@ snd-soc-ad193x-spi-objs := ad193x-spi.o
7snd-soc-ad193x-i2c-objs := ad193x-i2c.o 7snd-soc-ad193x-i2c-objs := ad193x-i2c.o
8snd-soc-ad1980-objs := ad1980.o 8snd-soc-ad1980-objs := ad1980.o
9snd-soc-ad73311-objs := ad73311.o 9snd-soc-ad73311-objs := ad73311.o
10snd-soc-adau1701-objs := adau1701.o
11snd-soc-adau1373-objs := adau1373.o 10snd-soc-adau1373-objs := adau1373.o
11snd-soc-adau1701-objs := adau1701.o
12snd-soc-adau17x1-objs := adau17x1.o
13snd-soc-adau1761-objs := adau1761.o
14snd-soc-adau1761-i2c-objs := adau1761-i2c.o
15snd-soc-adau1761-spi-objs := adau1761-spi.o
16snd-soc-adau1781-objs := adau1781.o
17snd-soc-adau1781-i2c-objs := adau1781-i2c.o
18snd-soc-adau1781-spi-objs := adau1781-spi.o
12snd-soc-adau1977-objs := adau1977.o 19snd-soc-adau1977-objs := adau1977.o
13snd-soc-adau1977-spi-objs := adau1977-spi.o 20snd-soc-adau1977-spi-objs := adau1977-spi.o
14snd-soc-adau1977-i2c-objs := adau1977-i2c.o 21snd-soc-adau1977-i2c-objs := adau1977-i2c.o
@@ -26,7 +33,9 @@ snd-soc-ak5386-objs := ak5386.o
26snd-soc-arizona-objs := arizona.o 33snd-soc-arizona-objs := arizona.o
27snd-soc-cq93vc-objs := cq93vc.o 34snd-soc-cq93vc-objs := cq93vc.o
28snd-soc-cs42l51-objs := cs42l51.o 35snd-soc-cs42l51-objs := cs42l51.o
36snd-soc-cs42l51-i2c-objs := cs42l51-i2c.o
29snd-soc-cs42l52-objs := cs42l52.o 37snd-soc-cs42l52-objs := cs42l52.o
38snd-soc-cs42l56-objs := cs42l56.o
30snd-soc-cs42l73-objs := cs42l73.o 39snd-soc-cs42l73-objs := cs42l73.o
31snd-soc-cs4270-objs := cs4270.o 40snd-soc-cs4270-objs := cs4270.o
32snd-soc-cs4271-objs := cs4271.o 41snd-soc-cs4271-objs := cs4271.o
@@ -58,8 +67,12 @@ snd-soc-pcm3008-objs := pcm3008.o
58snd-soc-pcm512x-objs := pcm512x.o 67snd-soc-pcm512x-objs := pcm512x.o
59snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o 68snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o
60snd-soc-pcm512x-spi-objs := pcm512x-spi.o 69snd-soc-pcm512x-spi-objs := pcm512x-spi.o
70snd-soc-rl6231-objs := rl6231.o
61snd-soc-rt5631-objs := rt5631.o 71snd-soc-rt5631-objs := rt5631.o
62snd-soc-rt5640-objs := rt5640.o 72snd-soc-rt5640-objs := rt5640.o
73snd-soc-rt5645-objs := rt5645.o
74snd-soc-rt5651-objs := rt5651.o
75snd-soc-rt5677-objs := rt5677.o
63snd-soc-sgtl5000-objs := sgtl5000.o 76snd-soc-sgtl5000-objs := sgtl5000.o
64snd-soc-alc5623-objs := alc5623.o 77snd-soc-alc5623-objs := alc5623.o
65snd-soc-alc5632-objs := alc5632.o 78snd-soc-alc5632-objs := alc5632.o
@@ -74,6 +87,7 @@ snd-soc-ssm2602-objs := ssm2602.o
74snd-soc-ssm2602-spi-objs := ssm2602-spi.o 87snd-soc-ssm2602-spi-objs := ssm2602-spi.o
75snd-soc-ssm2602-i2c-objs := ssm2602-i2c.o 88snd-soc-ssm2602-i2c-objs := ssm2602-i2c.o
76snd-soc-sta32x-objs := sta32x.o 89snd-soc-sta32x-objs := sta32x.o
90snd-soc-sta350-objs := sta350.o
77snd-soc-sta529-objs := sta529.o 91snd-soc-sta529-objs := sta529.o
78snd-soc-stac9766-objs := stac9766.o 92snd-soc-stac9766-objs := stac9766.o
79snd-soc-tas5086-objs := tas5086.o 93snd-soc-tas5086-objs := tas5086.o
@@ -157,10 +171,17 @@ obj-$(CONFIG_SND_SOC_AD193X_I2C) += snd-soc-ad193x-i2c.o
157obj-$(CONFIG_SND_SOC_AD1980) += snd-soc-ad1980.o 171obj-$(CONFIG_SND_SOC_AD1980) += snd-soc-ad1980.o
158obj-$(CONFIG_SND_SOC_AD73311) += snd-soc-ad73311.o 172obj-$(CONFIG_SND_SOC_AD73311) += snd-soc-ad73311.o
159obj-$(CONFIG_SND_SOC_ADAU1373) += snd-soc-adau1373.o 173obj-$(CONFIG_SND_SOC_ADAU1373) += snd-soc-adau1373.o
174obj-$(CONFIG_SND_SOC_ADAU1701) += snd-soc-adau1701.o
175obj-$(CONFIG_SND_SOC_ADAU17X1) += snd-soc-adau17x1.o
176obj-$(CONFIG_SND_SOC_ADAU1761) += snd-soc-adau1761.o
177obj-$(CONFIG_SND_SOC_ADAU1761_I2C) += snd-soc-adau1761-i2c.o
178obj-$(CONFIG_SND_SOC_ADAU1761_SPI) += snd-soc-adau1761-spi.o
179obj-$(CONFIG_SND_SOC_ADAU1781) += snd-soc-adau1781.o
180obj-$(CONFIG_SND_SOC_ADAU1781_I2C) += snd-soc-adau1781-i2c.o
181obj-$(CONFIG_SND_SOC_ADAU1781_SPI) += snd-soc-adau1781-spi.o
160obj-$(CONFIG_SND_SOC_ADAU1977) += snd-soc-adau1977.o 182obj-$(CONFIG_SND_SOC_ADAU1977) += snd-soc-adau1977.o
161obj-$(CONFIG_SND_SOC_ADAU1977_SPI) += snd-soc-adau1977-spi.o 183obj-$(CONFIG_SND_SOC_ADAU1977_SPI) += snd-soc-adau1977-spi.o
162obj-$(CONFIG_SND_SOC_ADAU1977_I2C) += snd-soc-adau1977-i2c.o 184obj-$(CONFIG_SND_SOC_ADAU1977_I2C) += snd-soc-adau1977-i2c.o
163obj-$(CONFIG_SND_SOC_ADAU1701) += snd-soc-adau1701.o
164obj-$(CONFIG_SND_SOC_ADAV80X) += snd-soc-adav80x.o 185obj-$(CONFIG_SND_SOC_ADAV80X) += snd-soc-adav80x.o
165obj-$(CONFIG_SND_SOC_ADAV801) += snd-soc-adav801.o 186obj-$(CONFIG_SND_SOC_ADAV801) += snd-soc-adav801.o
166obj-$(CONFIG_SND_SOC_ADAV803) += snd-soc-adav803.o 187obj-$(CONFIG_SND_SOC_ADAV803) += snd-soc-adav803.o
@@ -177,7 +198,9 @@ obj-$(CONFIG_SND_SOC_ALC5632) += snd-soc-alc5632.o
177obj-$(CONFIG_SND_SOC_ARIZONA) += snd-soc-arizona.o 198obj-$(CONFIG_SND_SOC_ARIZONA) += snd-soc-arizona.o
178obj-$(CONFIG_SND_SOC_CQ0093VC) += snd-soc-cq93vc.o 199obj-$(CONFIG_SND_SOC_CQ0093VC) += snd-soc-cq93vc.o
179obj-$(CONFIG_SND_SOC_CS42L51) += snd-soc-cs42l51.o 200obj-$(CONFIG_SND_SOC_CS42L51) += snd-soc-cs42l51.o
201obj-$(CONFIG_SND_SOC_CS42L51_I2C) += snd-soc-cs42l51-i2c.o
180obj-$(CONFIG_SND_SOC_CS42L52) += snd-soc-cs42l52.o 202obj-$(CONFIG_SND_SOC_CS42L52) += snd-soc-cs42l52.o
203obj-$(CONFIG_SND_SOC_CS42L56) += snd-soc-cs42l56.o
181obj-$(CONFIG_SND_SOC_CS42L73) += snd-soc-cs42l73.o 204obj-$(CONFIG_SND_SOC_CS42L73) += snd-soc-cs42l73.o
182obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o 205obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o
183obj-$(CONFIG_SND_SOC_CS4271) += snd-soc-cs4271.o 206obj-$(CONFIG_SND_SOC_CS4271) += snd-soc-cs4271.o
@@ -209,8 +232,12 @@ obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o
209obj-$(CONFIG_SND_SOC_PCM512x) += snd-soc-pcm512x.o 232obj-$(CONFIG_SND_SOC_PCM512x) += snd-soc-pcm512x.o
210obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd-soc-pcm512x-i2c.o 233obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd-soc-pcm512x-i2c.o
211obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o 234obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o
235obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o
212obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o 236obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o
213obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o 237obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o
238obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o
239obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o
240obj-$(CONFIG_SND_SOC_RT5677) += snd-soc-rt5677.o
214obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o 241obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o
215obj-$(CONFIG_SND_SOC_SIGMADSP) += snd-soc-sigmadsp.o 242obj-$(CONFIG_SND_SOC_SIGMADSP) += snd-soc-sigmadsp.o
216obj-$(CONFIG_SND_SOC_SI476X) += snd-soc-si476x.o 243obj-$(CONFIG_SND_SOC_SI476X) += snd-soc-si476x.o
@@ -221,6 +248,7 @@ obj-$(CONFIG_SND_SOC_SSM2602) += snd-soc-ssm2602.o
221obj-$(CONFIG_SND_SOC_SSM2602_SPI) += snd-soc-ssm2602-spi.o 248obj-$(CONFIG_SND_SOC_SSM2602_SPI) += snd-soc-ssm2602-spi.o
222obj-$(CONFIG_SND_SOC_SSM2602_I2C) += snd-soc-ssm2602-i2c.o 249obj-$(CONFIG_SND_SOC_SSM2602_I2C) += snd-soc-ssm2602-i2c.o
223obj-$(CONFIG_SND_SOC_STA32X) += snd-soc-sta32x.o 250obj-$(CONFIG_SND_SOC_STA32X) += snd-soc-sta32x.o
251obj-$(CONFIG_SND_SOC_STA350) += snd-soc-sta350.o
224obj-$(CONFIG_SND_SOC_STA529) += snd-soc-sta529.o 252obj-$(CONFIG_SND_SOC_STA529) += snd-soc-sta529.o
225obj-$(CONFIG_SND_SOC_STAC9766) += snd-soc-stac9766.o 253obj-$(CONFIG_SND_SOC_STAC9766) += snd-soc-stac9766.o
226obj-$(CONFIG_SND_SOC_TAS5086) += snd-soc-tas5086.o 254obj-$(CONFIG_SND_SOC_TAS5086) += snd-soc-tas5086.o
diff --git a/sound/soc/codecs/ab8500-codec.c b/sound/soc/codecs/ab8500-codec.c
index 1ad92cbf0b24..1fb4402bf72d 100644
--- a/sound/soc/codecs/ab8500-codec.c
+++ b/sound/soc/codecs/ab8500-codec.c
@@ -1139,7 +1139,7 @@ static void anc_configure(struct snd_soc_codec *codec,
1139static int sid_status_control_get(struct snd_kcontrol *kcontrol, 1139static int sid_status_control_get(struct snd_kcontrol *kcontrol,
1140 struct snd_ctl_elem_value *ucontrol) 1140 struct snd_ctl_elem_value *ucontrol)
1141{ 1141{
1142 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1142 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1143 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev); 1143 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1144 1144
1145 mutex_lock(&codec->mutex); 1145 mutex_lock(&codec->mutex);
@@ -1153,7 +1153,7 @@ static int sid_status_control_get(struct snd_kcontrol *kcontrol,
1153static int sid_status_control_put(struct snd_kcontrol *kcontrol, 1153static int sid_status_control_put(struct snd_kcontrol *kcontrol,
1154 struct snd_ctl_elem_value *ucontrol) 1154 struct snd_ctl_elem_value *ucontrol)
1155{ 1155{
1156 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1156 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1157 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev); 1157 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1158 unsigned int param, sidconf, val; 1158 unsigned int param, sidconf, val;
1159 int status = 1; 1159 int status = 1;
@@ -1208,7 +1208,7 @@ out:
1208static int anc_status_control_get(struct snd_kcontrol *kcontrol, 1208static int anc_status_control_get(struct snd_kcontrol *kcontrol,
1209 struct snd_ctl_elem_value *ucontrol) 1209 struct snd_ctl_elem_value *ucontrol)
1210{ 1210{
1211 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1211 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1212 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev); 1212 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1213 1213
1214 mutex_lock(&codec->mutex); 1214 mutex_lock(&codec->mutex);
@@ -1221,7 +1221,7 @@ static int anc_status_control_get(struct snd_kcontrol *kcontrol,
1221static int anc_status_control_put(struct snd_kcontrol *kcontrol, 1221static int anc_status_control_put(struct snd_kcontrol *kcontrol,
1222 struct snd_ctl_elem_value *ucontrol) 1222 struct snd_ctl_elem_value *ucontrol)
1223{ 1223{
1224 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1224 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1225 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev); 1225 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1226 struct device *dev = codec->dev; 1226 struct device *dev = codec->dev;
1227 bool apply_fir, apply_iir; 1227 bool apply_fir, apply_iir;
@@ -1306,7 +1306,7 @@ static int filter_control_info(struct snd_kcontrol *kcontrol,
1306static int filter_control_get(struct snd_kcontrol *kcontrol, 1306static int filter_control_get(struct snd_kcontrol *kcontrol,
1307 struct snd_ctl_elem_value *ucontrol) 1307 struct snd_ctl_elem_value *ucontrol)
1308{ 1308{
1309 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1309 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1310 struct filter_control *fc = 1310 struct filter_control *fc =
1311 (struct filter_control *)kcontrol->private_value; 1311 (struct filter_control *)kcontrol->private_value;
1312 unsigned int i; 1312 unsigned int i;
@@ -1322,7 +1322,7 @@ static int filter_control_get(struct snd_kcontrol *kcontrol,
1322static int filter_control_put(struct snd_kcontrol *kcontrol, 1322static int filter_control_put(struct snd_kcontrol *kcontrol,
1323 struct snd_ctl_elem_value *ucontrol) 1323 struct snd_ctl_elem_value *ucontrol)
1324{ 1324{
1325 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1325 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1326 struct filter_control *fc = 1326 struct filter_control *fc =
1327 (struct filter_control *)kcontrol->private_value; 1327 (struct filter_control *)kcontrol->private_value;
1328 unsigned int i; 1328 unsigned int i;
diff --git a/sound/soc/codecs/ad1980.c b/sound/soc/codecs/ad1980.c
index 34d965a4a040..304d3003339a 100644
--- a/sound/soc/codecs/ad1980.c
+++ b/sound/soc/codecs/ad1980.c
@@ -189,28 +189,27 @@ static struct snd_soc_dai_driver ad1980_dai = {
189 189
190static int ad1980_reset(struct snd_soc_codec *codec, int try_warm) 190static int ad1980_reset(struct snd_soc_codec *codec, int try_warm)
191{ 191{
192 u16 retry_cnt = 0; 192 unsigned int retry_cnt = 0;
193 193
194retry: 194 do {
195 if (try_warm && soc_ac97_ops->warm_reset) { 195 if (try_warm && soc_ac97_ops->warm_reset) {
196 soc_ac97_ops->warm_reset(codec->ac97); 196 soc_ac97_ops->warm_reset(codec->ac97);
197 if (ac97_read(codec, AC97_RESET) == 0x0090) 197 if (ac97_read(codec, AC97_RESET) == 0x0090)
198 return 1; 198 return 1;
199 } 199 }
200
201 soc_ac97_ops->reset(codec->ac97);
202 /* Set bit 16slot in register 74h, then every slot will has only 16
203 * bits. This command is sent out in 20bit mode, in which case the
204 * first nibble of data is eaten by the addr. (Tag is always 16 bit)*/
205 ac97_write(codec, AC97_AD_SERIAL_CFG, 0x9900);
206
207 if (ac97_read(codec, AC97_RESET) != 0x0090)
208 goto err;
209 return 0;
210 200
211err: 201 soc_ac97_ops->reset(codec->ac97);
212 while (retry_cnt++ < 10) 202 /*
213 goto retry; 203 * Set bit 16slot in register 74h, then every slot will has only
204 * 16 bits. This command is sent out in 20bit mode, in which
205 * case the first nibble of data is eaten by the addr. (Tag is
206 * always 16 bit)
207 */
208 ac97_write(codec, AC97_AD_SERIAL_CFG, 0x9900);
209
210 if (ac97_read(codec, AC97_RESET) == 0x0090)
211 return 0;
212 } while (retry_cnt++ < 10);
214 213
215 printk(KERN_ERR "AD1980 AC97 reset failed\n"); 214 printk(KERN_ERR "AD1980 AC97 reset failed\n");
216 return -EIO; 215 return -EIO;
diff --git a/sound/soc/codecs/adau1373.c b/sound/soc/codecs/adau1373.c
index 877f5737bb6b..1ff7d4d027e9 100644
--- a/sound/soc/codecs/adau1373.c
+++ b/sound/soc/codecs/adau1373.c
@@ -519,8 +519,7 @@ static const struct snd_kcontrol_new adau1373_controls[] = {
519 SOC_ENUM("HPF Channel", adau1373_hpf_channel_enum), 519 SOC_ENUM("HPF Channel", adau1373_hpf_channel_enum),
520 520
521 SOC_ENUM("Bass HPF Cutoff", adau1373_bass_hpf_cutoff_enum), 521 SOC_ENUM("Bass HPF Cutoff", adau1373_bass_hpf_cutoff_enum),
522 SOC_VALUE_ENUM("Bass Clip Level Threshold", 522 SOC_ENUM("Bass Clip Level Threshold", adau1373_bass_clip_level_enum),
523 adau1373_bass_clip_level_enum),
524 SOC_ENUM("Bass LPF Cutoff", adau1373_bass_lpf_cutoff_enum), 523 SOC_ENUM("Bass LPF Cutoff", adau1373_bass_lpf_cutoff_enum),
525 SOC_DOUBLE("Bass Playback Switch", ADAU1373_BASS2, 0, 1, 1, 0), 524 SOC_DOUBLE("Bass Playback Switch", ADAU1373_BASS2, 0, 1, 1, 0),
526 SOC_SINGLE_TLV("Bass Playback Volume", ADAU1373_BASS2, 2, 7, 0, 525 SOC_SINGLE_TLV("Bass Playback Volume", ADAU1373_BASS2, 2, 7, 0,
@@ -580,7 +579,7 @@ static SOC_ENUM_SINGLE_VIRT_DECL(adau1373_decimator_enum,
580 adau1373_decimator_text); 579 adau1373_decimator_text);
581 580
582static const struct snd_kcontrol_new adau1373_decimator_mux = 581static const struct snd_kcontrol_new adau1373_decimator_mux =
583 SOC_DAPM_ENUM_VIRT("Decimator Mux", adau1373_decimator_enum); 582 SOC_DAPM_ENUM("Decimator Mux", adau1373_decimator_enum);
584 583
585static const struct snd_kcontrol_new adau1373_left_adc_mixer_controls[] = { 584static const struct snd_kcontrol_new adau1373_left_adc_mixer_controls[] = {
586 SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_LADC_MIXER, 4, 1, 0), 585 SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_LADC_MIXER, 4, 1, 0),
@@ -694,7 +693,7 @@ static const struct snd_soc_dapm_widget adau1373_dapm_widgets[] = {
694 SND_SOC_DAPM_ADC("DMIC1", NULL, ADAU1373_DIGMICCTRL, 0, 0), 693 SND_SOC_DAPM_ADC("DMIC1", NULL, ADAU1373_DIGMICCTRL, 0, 0),
695 SND_SOC_DAPM_ADC("DMIC2", NULL, ADAU1373_DIGMICCTRL, 2, 0), 694 SND_SOC_DAPM_ADC("DMIC2", NULL, ADAU1373_DIGMICCTRL, 2, 0),
696 695
697 SND_SOC_DAPM_VIRT_MUX("Decimator Mux", SND_SOC_NOPM, 0, 0, 696 SND_SOC_DAPM_MUX("Decimator Mux", SND_SOC_NOPM, 0, 0,
698 &adau1373_decimator_mux), 697 &adau1373_decimator_mux),
699 698
700 SND_SOC_DAPM_SUPPLY("MICBIAS2", ADAU1373_PWDN_CTRL1, 5, 0, NULL, 0), 699 SND_SOC_DAPM_SUPPLY("MICBIAS2", ADAU1373_PWDN_CTRL1, 5, 0, NULL, 0),
diff --git a/sound/soc/codecs/adau1761-i2c.c b/sound/soc/codecs/adau1761-i2c.c
new file mode 100644
index 000000000000..862796dec693
--- /dev/null
+++ b/sound/soc/codecs/adau1761-i2c.c
@@ -0,0 +1,60 @@
1/*
2 * Driver for ADAU1761/ADAU1461/ADAU1761/ADAU1961 codec
3 *
4 * Copyright 2014 Analog Devices Inc.
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
6 *
7 * Licensed under the GPL-2.
8 */
9
10#include <linux/i2c.h>
11#include <linux/mod_devicetable.h>
12#include <linux/module.h>
13#include <linux/regmap.h>
14#include <sound/soc.h>
15
16#include "adau1761.h"
17
18static int adau1761_i2c_probe(struct i2c_client *client,
19 const struct i2c_device_id *id)
20{
21 struct regmap_config config;
22
23 config = adau1761_regmap_config;
24 config.val_bits = 8;
25 config.reg_bits = 16;
26
27 return adau1761_probe(&client->dev,
28 devm_regmap_init_i2c(client, &config),
29 id->driver_data, NULL);
30}
31
32static int adau1761_i2c_remove(struct i2c_client *client)
33{
34 snd_soc_unregister_codec(&client->dev);
35 return 0;
36}
37
38static const struct i2c_device_id adau1761_i2c_ids[] = {
39 { "adau1361", ADAU1361 },
40 { "adau1461", ADAU1761 },
41 { "adau1761", ADAU1761 },
42 { "adau1961", ADAU1361 },
43 { }
44};
45MODULE_DEVICE_TABLE(i2c, adau1761_i2c_ids);
46
47static struct i2c_driver adau1761_i2c_driver = {
48 .driver = {
49 .name = "adau1761",
50 .owner = THIS_MODULE,
51 },
52 .probe = adau1761_i2c_probe,
53 .remove = adau1761_i2c_remove,
54 .id_table = adau1761_i2c_ids,
55};
56module_i2c_driver(adau1761_i2c_driver);
57
58MODULE_DESCRIPTION("ASoC ADAU1361/ADAU1461/ADAU1761/ADAU1961 CODEC I2C driver");
59MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
60MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/adau1761-spi.c b/sound/soc/codecs/adau1761-spi.c
new file mode 100644
index 000000000000..cce2f11f1ffb
--- /dev/null
+++ b/sound/soc/codecs/adau1761-spi.c
@@ -0,0 +1,77 @@
1/*
2 * Driver for ADAU1761/ADAU1461/ADAU1761/ADAU1961 codec
3 *
4 * Copyright 2014 Analog Devices Inc.
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
6 *
7 * Licensed under the GPL-2.
8 */
9
10#include <linux/mod_devicetable.h>
11#include <linux/module.h>
12#include <linux/regmap.h>
13#include <linux/spi/spi.h>
14#include <sound/soc.h>
15
16#include "adau1761.h"
17
18static void adau1761_spi_switch_mode(struct device *dev)
19{
20 struct spi_device *spi = to_spi_device(dev);
21
22 /*
23 * To get the device into SPI mode CLATCH has to be pulled low three
24 * times. Do this by issuing three dummy reads.
25 */
26 spi_w8r8(spi, 0x00);
27 spi_w8r8(spi, 0x00);
28 spi_w8r8(spi, 0x00);
29}
30
31static int adau1761_spi_probe(struct spi_device *spi)
32{
33 const struct spi_device_id *id = spi_get_device_id(spi);
34 struct regmap_config config;
35
36 if (!id)
37 return -EINVAL;
38
39 config = adau1761_regmap_config;
40 config.val_bits = 8;
41 config.reg_bits = 24;
42 config.read_flag_mask = 0x1;
43
44 return adau1761_probe(&spi->dev,
45 devm_regmap_init_spi(spi, &config),
46 id->driver_data, adau1761_spi_switch_mode);
47}
48
49static int adau1761_spi_remove(struct spi_device *spi)
50{
51 snd_soc_unregister_codec(&spi->dev);
52 return 0;
53}
54
55static const struct spi_device_id adau1761_spi_id[] = {
56 { "adau1361", ADAU1361 },
57 { "adau1461", ADAU1761 },
58 { "adau1761", ADAU1761 },
59 { "adau1961", ADAU1361 },
60 { }
61};
62MODULE_DEVICE_TABLE(spi, adau1761_spi_id);
63
64static struct spi_driver adau1761_spi_driver = {
65 .driver = {
66 .name = "adau1761",
67 .owner = THIS_MODULE,
68 },
69 .probe = adau1761_spi_probe,
70 .remove = adau1761_spi_remove,
71 .id_table = adau1761_spi_id,
72};
73module_spi_driver(adau1761_spi_driver);
74
75MODULE_DESCRIPTION("ASoC ADAU1361/ADAU1461/ADAU1761/ADAU1961 CODEC SPI driver");
76MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
77MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/adau1761.c b/sound/soc/codecs/adau1761.c
new file mode 100644
index 000000000000..848cab839553
--- /dev/null
+++ b/sound/soc/codecs/adau1761.c
@@ -0,0 +1,803 @@
1/*
2 * Driver for ADAU1761/ADAU1461/ADAU1761/ADAU1961 codec
3 *
4 * Copyright 2011-2013 Analog Devices Inc.
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
6 *
7 * Licensed under the GPL-2 or later.
8 */
9
10#include <linux/module.h>
11#include <linux/init.h>
12#include <linux/i2c.h>
13#include <linux/spi/spi.h>
14#include <linux/slab.h>
15#include <sound/core.h>
16#include <sound/pcm.h>
17#include <sound/pcm_params.h>
18#include <sound/soc.h>
19#include <sound/tlv.h>
20#include <linux/platform_data/adau17x1.h>
21
22#include "adau17x1.h"
23#include "adau1761.h"
24
25#define ADAU1761_DIGMIC_JACKDETECT 0x4008
26#define ADAU1761_REC_MIXER_LEFT0 0x400a
27#define ADAU1761_REC_MIXER_LEFT1 0x400b
28#define ADAU1761_REC_MIXER_RIGHT0 0x400c
29#define ADAU1761_REC_MIXER_RIGHT1 0x400d
30#define ADAU1761_LEFT_DIFF_INPUT_VOL 0x400e
31#define ADAU1761_RIGHT_DIFF_INPUT_VOL 0x400f
32#define ADAU1761_PLAY_LR_MIXER_LEFT 0x4020
33#define ADAU1761_PLAY_MIXER_LEFT0 0x401c
34#define ADAU1761_PLAY_MIXER_LEFT1 0x401d
35#define ADAU1761_PLAY_MIXER_RIGHT0 0x401e
36#define ADAU1761_PLAY_MIXER_RIGHT1 0x401f
37#define ADAU1761_PLAY_LR_MIXER_RIGHT 0x4021
38#define ADAU1761_PLAY_MIXER_MONO 0x4022
39#define ADAU1761_PLAY_HP_LEFT_VOL 0x4023
40#define ADAU1761_PLAY_HP_RIGHT_VOL 0x4024
41#define ADAU1761_PLAY_LINE_LEFT_VOL 0x4025
42#define ADAU1761_PLAY_LINE_RIGHT_VOL 0x4026
43#define ADAU1761_PLAY_MONO_OUTPUT_VOL 0x4027
44#define ADAU1761_POP_CLICK_SUPPRESS 0x4028
45#define ADAU1761_JACK_DETECT_PIN 0x4031
46#define ADAU1761_DEJITTER 0x4036
47#define ADAU1761_CLK_ENABLE0 0x40f9
48#define ADAU1761_CLK_ENABLE1 0x40fa
49
50#define ADAU1761_DIGMIC_JACKDETECT_ACTIVE_LOW BIT(0)
51#define ADAU1761_DIGMIC_JACKDETECT_DIGMIC BIT(5)
52
53#define ADAU1761_DIFF_INPUT_VOL_LDEN BIT(0)
54
55#define ADAU1761_PLAY_MONO_OUTPUT_VOL_MODE_HP BIT(0)
56#define ADAU1761_PLAY_MONO_OUTPUT_VOL_UNMUTE BIT(1)
57
58#define ADAU1761_PLAY_HP_RIGHT_VOL_MODE_HP BIT(0)
59
60#define ADAU1761_PLAY_LINE_LEFT_VOL_MODE_HP BIT(0)
61
62#define ADAU1761_PLAY_LINE_RIGHT_VOL_MODE_HP BIT(0)
63
64
65#define ADAU1761_FIRMWARE "adau1761.bin"
66
67static const struct reg_default adau1761_reg_defaults[] = {
68 { ADAU1761_DEJITTER, 0x03 },
69 { ADAU1761_DIGMIC_JACKDETECT, 0x00 },
70 { ADAU1761_REC_MIXER_LEFT0, 0x00 },
71 { ADAU1761_REC_MIXER_LEFT1, 0x00 },
72 { ADAU1761_REC_MIXER_RIGHT0, 0x00 },
73 { ADAU1761_REC_MIXER_RIGHT1, 0x00 },
74 { ADAU1761_LEFT_DIFF_INPUT_VOL, 0x00 },
75 { ADAU1761_RIGHT_DIFF_INPUT_VOL, 0x00 },
76 { ADAU1761_PLAY_LR_MIXER_LEFT, 0x00 },
77 { ADAU1761_PLAY_MIXER_LEFT0, 0x00 },
78 { ADAU1761_PLAY_MIXER_LEFT1, 0x00 },
79 { ADAU1761_PLAY_MIXER_RIGHT0, 0x00 },
80 { ADAU1761_PLAY_MIXER_RIGHT1, 0x00 },
81 { ADAU1761_PLAY_LR_MIXER_RIGHT, 0x00 },
82 { ADAU1761_PLAY_MIXER_MONO, 0x00 },
83 { ADAU1761_PLAY_HP_LEFT_VOL, 0x00 },
84 { ADAU1761_PLAY_HP_RIGHT_VOL, 0x00 },
85 { ADAU1761_PLAY_LINE_LEFT_VOL, 0x00 },
86 { ADAU1761_PLAY_LINE_RIGHT_VOL, 0x00 },
87 { ADAU1761_PLAY_MONO_OUTPUT_VOL, 0x00 },
88 { ADAU1761_POP_CLICK_SUPPRESS, 0x00 },
89 { ADAU1761_JACK_DETECT_PIN, 0x00 },
90 { ADAU1761_CLK_ENABLE0, 0x00 },
91 { ADAU1761_CLK_ENABLE1, 0x00 },
92 { ADAU17X1_CLOCK_CONTROL, 0x00 },
93 { ADAU17X1_PLL_CONTROL, 0x00 },
94 { ADAU17X1_REC_POWER_MGMT, 0x00 },
95 { ADAU17X1_MICBIAS, 0x00 },
96 { ADAU17X1_SERIAL_PORT0, 0x00 },
97 { ADAU17X1_SERIAL_PORT1, 0x00 },
98 { ADAU17X1_CONVERTER0, 0x00 },
99 { ADAU17X1_CONVERTER1, 0x00 },
100 { ADAU17X1_LEFT_INPUT_DIGITAL_VOL, 0x00 },
101 { ADAU17X1_RIGHT_INPUT_DIGITAL_VOL, 0x00 },
102 { ADAU17X1_ADC_CONTROL, 0x00 },
103 { ADAU17X1_PLAY_POWER_MGMT, 0x00 },
104 { ADAU17X1_DAC_CONTROL0, 0x00 },
105 { ADAU17X1_DAC_CONTROL1, 0x00 },
106 { ADAU17X1_DAC_CONTROL2, 0x00 },
107 { ADAU17X1_SERIAL_PORT_PAD, 0xaa },
108 { ADAU17X1_CONTROL_PORT_PAD0, 0xaa },
109 { ADAU17X1_CONTROL_PORT_PAD1, 0x00 },
110 { ADAU17X1_DSP_SAMPLING_RATE, 0x01 },
111 { ADAU17X1_SERIAL_INPUT_ROUTE, 0x00 },
112 { ADAU17X1_SERIAL_OUTPUT_ROUTE, 0x00 },
113 { ADAU17X1_DSP_ENABLE, 0x00 },
114 { ADAU17X1_DSP_RUN, 0x00 },
115 { ADAU17X1_SERIAL_SAMPLING_RATE, 0x00 },
116};
117
118static const DECLARE_TLV_DB_SCALE(adau1761_sing_in_tlv, -1500, 300, 1);
119static const DECLARE_TLV_DB_SCALE(adau1761_diff_in_tlv, -1200, 75, 0);
120static const DECLARE_TLV_DB_SCALE(adau1761_out_tlv, -5700, 100, 0);
121static const DECLARE_TLV_DB_SCALE(adau1761_sidetone_tlv, -1800, 300, 1);
122static const DECLARE_TLV_DB_SCALE(adau1761_boost_tlv, -600, 600, 1);
123static const DECLARE_TLV_DB_SCALE(adau1761_pga_boost_tlv, -2000, 2000, 1);
124
125static const unsigned int adau1761_bias_select_values[] = {
126 0, 2, 3,
127};
128
129static const char * const adau1761_bias_select_text[] = {
130 "Normal operation", "Enhanced performance", "Power saving",
131};
132
133static const char * const adau1761_bias_select_extreme_text[] = {
134 "Normal operation", "Extreme power saving", "Enhanced performance",
135 "Power saving",
136};
137
138static SOC_ENUM_SINGLE_DECL(adau1761_adc_bias_enum,
139 ADAU17X1_REC_POWER_MGMT, 3, adau1761_bias_select_extreme_text);
140static SOC_ENUM_SINGLE_DECL(adau1761_hp_bias_enum,
141 ADAU17X1_PLAY_POWER_MGMT, 6, adau1761_bias_select_extreme_text);
142static SOC_ENUM_SINGLE_DECL(adau1761_dac_bias_enum,
143 ADAU17X1_PLAY_POWER_MGMT, 4, adau1761_bias_select_extreme_text);
144static SOC_VALUE_ENUM_SINGLE_DECL(adau1761_playback_bias_enum,
145 ADAU17X1_PLAY_POWER_MGMT, 2, 0x3, adau1761_bias_select_text,
146 adau1761_bias_select_values);
147static SOC_VALUE_ENUM_SINGLE_DECL(adau1761_capture_bias_enum,
148 ADAU17X1_REC_POWER_MGMT, 1, 0x3, adau1761_bias_select_text,
149 adau1761_bias_select_values);
150
151static const struct snd_kcontrol_new adau1761_jack_detect_controls[] = {
152 SOC_SINGLE("Speaker Auto-mute Switch", ADAU1761_DIGMIC_JACKDETECT,
153 4, 1, 0),
154};
155
156static const struct snd_kcontrol_new adau1761_differential_mode_controls[] = {
157 SOC_DOUBLE_R_TLV("Capture Volume", ADAU1761_LEFT_DIFF_INPUT_VOL,
158 ADAU1761_RIGHT_DIFF_INPUT_VOL, 2, 0x3f, 0,
159 adau1761_diff_in_tlv),
160 SOC_DOUBLE_R("Capture Switch", ADAU1761_LEFT_DIFF_INPUT_VOL,
161 ADAU1761_RIGHT_DIFF_INPUT_VOL, 1, 1, 0),
162
163 SOC_DOUBLE_R_TLV("PGA Boost Capture Volume", ADAU1761_REC_MIXER_LEFT1,
164 ADAU1761_REC_MIXER_RIGHT1, 3, 2, 0, adau1761_pga_boost_tlv),
165};
166
167static const struct snd_kcontrol_new adau1761_single_mode_controls[] = {
168 SOC_SINGLE_TLV("Input 1 Capture Volume", ADAU1761_REC_MIXER_LEFT0,
169 4, 7, 0, adau1761_sing_in_tlv),
170 SOC_SINGLE_TLV("Input 2 Capture Volume", ADAU1761_REC_MIXER_LEFT0,
171 1, 7, 0, adau1761_sing_in_tlv),
172 SOC_SINGLE_TLV("Input 3 Capture Volume", ADAU1761_REC_MIXER_RIGHT0,
173 4, 7, 0, adau1761_sing_in_tlv),
174 SOC_SINGLE_TLV("Input 4 Capture Volume", ADAU1761_REC_MIXER_RIGHT0,
175 1, 7, 0, adau1761_sing_in_tlv),
176};
177
178static const struct snd_kcontrol_new adau1761_controls[] = {
179 SOC_DOUBLE_R_TLV("Aux Capture Volume", ADAU1761_REC_MIXER_LEFT1,
180 ADAU1761_REC_MIXER_RIGHT1, 0, 7, 0, adau1761_sing_in_tlv),
181
182 SOC_DOUBLE_R_TLV("Headphone Playback Volume", ADAU1761_PLAY_HP_LEFT_VOL,
183 ADAU1761_PLAY_HP_RIGHT_VOL, 2, 0x3f, 0, adau1761_out_tlv),
184 SOC_DOUBLE_R("Headphone Playback Switch", ADAU1761_PLAY_HP_LEFT_VOL,
185 ADAU1761_PLAY_HP_RIGHT_VOL, 1, 1, 0),
186 SOC_DOUBLE_R_TLV("Lineout Playback Volume", ADAU1761_PLAY_LINE_LEFT_VOL,
187 ADAU1761_PLAY_LINE_RIGHT_VOL, 2, 0x3f, 0, adau1761_out_tlv),
188 SOC_DOUBLE_R("Lineout Playback Switch", ADAU1761_PLAY_LINE_LEFT_VOL,
189 ADAU1761_PLAY_LINE_RIGHT_VOL, 1, 1, 0),
190
191 SOC_ENUM("ADC Bias", adau1761_adc_bias_enum),
192 SOC_ENUM("DAC Bias", adau1761_dac_bias_enum),
193 SOC_ENUM("Capture Bias", adau1761_capture_bias_enum),
194 SOC_ENUM("Playback Bias", adau1761_playback_bias_enum),
195 SOC_ENUM("Headphone Bias", adau1761_hp_bias_enum),
196};
197
198static const struct snd_kcontrol_new adau1761_mono_controls[] = {
199 SOC_SINGLE_TLV("Mono Playback Volume", ADAU1761_PLAY_MONO_OUTPUT_VOL,
200 2, 0x3f, 0, adau1761_out_tlv),
201 SOC_SINGLE("Mono Playback Switch", ADAU1761_PLAY_MONO_OUTPUT_VOL,
202 1, 1, 0),
203};
204
205static const struct snd_kcontrol_new adau1761_left_mixer_controls[] = {
206 SOC_DAPM_SINGLE_AUTODISABLE("Left DAC Switch",
207 ADAU1761_PLAY_MIXER_LEFT0, 5, 1, 0),
208 SOC_DAPM_SINGLE_AUTODISABLE("Right DAC Switch",
209 ADAU1761_PLAY_MIXER_LEFT0, 6, 1, 0),
210 SOC_DAPM_SINGLE_TLV("Aux Bypass Volume",
211 ADAU1761_PLAY_MIXER_LEFT0, 1, 8, 0, adau1761_sidetone_tlv),
212 SOC_DAPM_SINGLE_TLV("Right Bypass Volume",
213 ADAU1761_PLAY_MIXER_LEFT1, 4, 8, 0, adau1761_sidetone_tlv),
214 SOC_DAPM_SINGLE_TLV("Left Bypass Volume",
215 ADAU1761_PLAY_MIXER_LEFT1, 0, 8, 0, adau1761_sidetone_tlv),
216};
217
218static const struct snd_kcontrol_new adau1761_right_mixer_controls[] = {
219 SOC_DAPM_SINGLE_AUTODISABLE("Left DAC Switch",
220 ADAU1761_PLAY_MIXER_RIGHT0, 5, 1, 0),
221 SOC_DAPM_SINGLE_AUTODISABLE("Right DAC Switch",
222 ADAU1761_PLAY_MIXER_RIGHT0, 6, 1, 0),
223 SOC_DAPM_SINGLE_TLV("Aux Bypass Volume",
224 ADAU1761_PLAY_MIXER_RIGHT0, 1, 8, 0, adau1761_sidetone_tlv),
225 SOC_DAPM_SINGLE_TLV("Right Bypass Volume",
226 ADAU1761_PLAY_MIXER_RIGHT1, 4, 8, 0, adau1761_sidetone_tlv),
227 SOC_DAPM_SINGLE_TLV("Left Bypass Volume",
228 ADAU1761_PLAY_MIXER_RIGHT1, 0, 8, 0, adau1761_sidetone_tlv),
229};
230
231static const struct snd_kcontrol_new adau1761_left_lr_mixer_controls[] = {
232 SOC_DAPM_SINGLE_TLV("Left Volume",
233 ADAU1761_PLAY_LR_MIXER_LEFT, 1, 2, 0, adau1761_boost_tlv),
234 SOC_DAPM_SINGLE_TLV("Right Volume",
235 ADAU1761_PLAY_LR_MIXER_LEFT, 3, 2, 0, adau1761_boost_tlv),
236};
237
238static const struct snd_kcontrol_new adau1761_right_lr_mixer_controls[] = {
239 SOC_DAPM_SINGLE_TLV("Left Volume",
240 ADAU1761_PLAY_LR_MIXER_RIGHT, 1, 2, 0, adau1761_boost_tlv),
241 SOC_DAPM_SINGLE_TLV("Right Volume",
242 ADAU1761_PLAY_LR_MIXER_RIGHT, 3, 2, 0, adau1761_boost_tlv),
243};
244
245static const char * const adau1761_input_mux_text[] = {
246 "ADC", "DMIC",
247};
248
249static SOC_ENUM_SINGLE_DECL(adau1761_input_mux_enum,
250 ADAU17X1_ADC_CONTROL, 2, adau1761_input_mux_text);
251
252static const struct snd_kcontrol_new adau1761_input_mux_control =
253 SOC_DAPM_ENUM("Input Select", adau1761_input_mux_enum);
254
255static int adau1761_dejitter_fixup(struct snd_soc_dapm_widget *w,
256 struct snd_kcontrol *kcontrol, int event)
257{
258 struct adau *adau = snd_soc_codec_get_drvdata(w->codec);
259
260 /* After any power changes have been made the dejitter circuit
261 * has to be reinitialized. */
262 regmap_write(adau->regmap, ADAU1761_DEJITTER, 0);
263 if (!adau->master)
264 regmap_write(adau->regmap, ADAU1761_DEJITTER, 3);
265
266 return 0;
267}
268
269static const struct snd_soc_dapm_widget adau1x61_dapm_widgets[] = {
270 SND_SOC_DAPM_MIXER("Left Input Mixer", ADAU1761_REC_MIXER_LEFT0, 0, 0,
271 NULL, 0),
272 SND_SOC_DAPM_MIXER("Right Input Mixer", ADAU1761_REC_MIXER_RIGHT0, 0, 0,
273 NULL, 0),
274
275 SOC_MIXER_ARRAY("Left Playback Mixer", ADAU1761_PLAY_MIXER_LEFT0,
276 0, 0, adau1761_left_mixer_controls),
277 SOC_MIXER_ARRAY("Right Playback Mixer", ADAU1761_PLAY_MIXER_RIGHT0,
278 0, 0, adau1761_right_mixer_controls),
279 SOC_MIXER_ARRAY("Left LR Playback Mixer", ADAU1761_PLAY_LR_MIXER_LEFT,
280 0, 0, adau1761_left_lr_mixer_controls),
281 SOC_MIXER_ARRAY("Right LR Playback Mixer", ADAU1761_PLAY_LR_MIXER_RIGHT,
282 0, 0, adau1761_right_lr_mixer_controls),
283
284 SND_SOC_DAPM_SUPPLY("Headphone", ADAU1761_PLAY_HP_LEFT_VOL,
285 0, 0, NULL, 0),
286
287 SND_SOC_DAPM_SUPPLY_S("SYSCLK", 2, SND_SOC_NOPM, 0, 0, NULL, 0),
288
289 SND_SOC_DAPM_POST("Dejitter fixup", adau1761_dejitter_fixup),
290
291 SND_SOC_DAPM_INPUT("LAUX"),
292 SND_SOC_DAPM_INPUT("RAUX"),
293 SND_SOC_DAPM_INPUT("LINP"),
294 SND_SOC_DAPM_INPUT("LINN"),
295 SND_SOC_DAPM_INPUT("RINP"),
296 SND_SOC_DAPM_INPUT("RINN"),
297
298 SND_SOC_DAPM_OUTPUT("LOUT"),
299 SND_SOC_DAPM_OUTPUT("ROUT"),
300 SND_SOC_DAPM_OUTPUT("LHP"),
301 SND_SOC_DAPM_OUTPUT("RHP"),
302};
303
304static const struct snd_soc_dapm_widget adau1761_mono_dapm_widgets[] = {
305 SND_SOC_DAPM_MIXER("Mono Playback Mixer", ADAU1761_PLAY_MIXER_MONO,
306 0, 0, NULL, 0),
307
308 SND_SOC_DAPM_OUTPUT("MONOOUT"),
309};
310
311static const struct snd_soc_dapm_widget adau1761_capless_dapm_widgets[] = {
312 SND_SOC_DAPM_SUPPLY_S("Headphone VGND", 1, ADAU1761_PLAY_MIXER_MONO,
313 0, 0, NULL, 0),
314};
315
316static const struct snd_soc_dapm_route adau1x61_dapm_routes[] = {
317 { "Left Input Mixer", NULL, "LINP" },
318 { "Left Input Mixer", NULL, "LINN" },
319 { "Left Input Mixer", NULL, "LAUX" },
320
321 { "Right Input Mixer", NULL, "RINP" },
322 { "Right Input Mixer", NULL, "RINN" },
323 { "Right Input Mixer", NULL, "RAUX" },
324
325 { "Left Playback Mixer", NULL, "Left Playback Enable"},
326 { "Right Playback Mixer", NULL, "Right Playback Enable"},
327 { "Left LR Playback Mixer", NULL, "Left Playback Enable"},
328 { "Right LR Playback Mixer", NULL, "Right Playback Enable"},
329
330 { "Left Playback Mixer", "Left DAC Switch", "Left DAC" },
331 { "Left Playback Mixer", "Right DAC Switch", "Right DAC" },
332
333 { "Right Playback Mixer", "Left DAC Switch", "Left DAC" },
334 { "Right Playback Mixer", "Right DAC Switch", "Right DAC" },
335
336 { "Left LR Playback Mixer", "Left Volume", "Left Playback Mixer" },
337 { "Left LR Playback Mixer", "Right Volume", "Right Playback Mixer" },
338
339 { "Right LR Playback Mixer", "Left Volume", "Left Playback Mixer" },
340 { "Right LR Playback Mixer", "Right Volume", "Right Playback Mixer" },
341
342 { "LHP", NULL, "Left Playback Mixer" },
343 { "RHP", NULL, "Right Playback Mixer" },
344
345 { "LHP", NULL, "Headphone" },
346 { "RHP", NULL, "Headphone" },
347
348 { "LOUT", NULL, "Left LR Playback Mixer" },
349 { "ROUT", NULL, "Right LR Playback Mixer" },
350
351 { "Left Playback Mixer", "Aux Bypass Volume", "LAUX" },
352 { "Left Playback Mixer", "Left Bypass Volume", "Left Input Mixer" },
353 { "Left Playback Mixer", "Right Bypass Volume", "Right Input Mixer" },
354 { "Right Playback Mixer", "Aux Bypass Volume", "RAUX" },
355 { "Right Playback Mixer", "Left Bypass Volume", "Left Input Mixer" },
356 { "Right Playback Mixer", "Right Bypass Volume", "Right Input Mixer" },
357};
358
359static const struct snd_soc_dapm_route adau1761_mono_dapm_routes[] = {
360 { "Mono Playback Mixer", NULL, "Left Playback Mixer" },
361 { "Mono Playback Mixer", NULL, "Right Playback Mixer" },
362
363 { "MONOOUT", NULL, "Mono Playback Mixer" },
364};
365
366static const struct snd_soc_dapm_route adau1761_capless_dapm_routes[] = {
367 { "Headphone", NULL, "Headphone VGND" },
368};
369
370static const struct snd_soc_dapm_widget adau1761_dmic_widgets[] = {
371 SND_SOC_DAPM_MUX("Left Decimator Mux", SND_SOC_NOPM, 0, 0,
372 &adau1761_input_mux_control),
373 SND_SOC_DAPM_MUX("Right Decimator Mux", SND_SOC_NOPM, 0, 0,
374 &adau1761_input_mux_control),
375
376 SND_SOC_DAPM_INPUT("DMIC"),
377};
378
379static const struct snd_soc_dapm_route adau1761_dmic_routes[] = {
380 { "Left Decimator Mux", "ADC", "Left Input Mixer" },
381 { "Left Decimator Mux", "DMIC", "DMIC" },
382 { "Right Decimator Mux", "ADC", "Right Input Mixer" },
383 { "Right Decimator Mux", "DMIC", "DMIC" },
384
385 { "Left Decimator", NULL, "Left Decimator Mux" },
386 { "Right Decimator", NULL, "Right Decimator Mux" },
387};
388
389static const struct snd_soc_dapm_route adau1761_no_dmic_routes[] = {
390 { "Left Decimator", NULL, "Left Input Mixer" },
391 { "Right Decimator", NULL, "Right Input Mixer" },
392};
393
394static const struct snd_soc_dapm_widget adau1761_dapm_widgets[] = {
395 SND_SOC_DAPM_SUPPLY("Serial Port Clock", ADAU1761_CLK_ENABLE0,
396 0, 0, NULL, 0),
397 SND_SOC_DAPM_SUPPLY("Serial Input Routing Clock", ADAU1761_CLK_ENABLE0,
398 1, 0, NULL, 0),
399 SND_SOC_DAPM_SUPPLY("Serial Output Routing Clock", ADAU1761_CLK_ENABLE0,
400 3, 0, NULL, 0),
401
402 SND_SOC_DAPM_SUPPLY("Decimator Resync Clock", ADAU1761_CLK_ENABLE0,
403 4, 0, NULL, 0),
404 SND_SOC_DAPM_SUPPLY("Interpolator Resync Clock", ADAU1761_CLK_ENABLE0,
405 2, 0, NULL, 0),
406
407 SND_SOC_DAPM_SUPPLY("Slew Clock", ADAU1761_CLK_ENABLE0, 6, 0, NULL, 0),
408
409 SND_SOC_DAPM_SUPPLY_S("Digital Clock 0", 1, ADAU1761_CLK_ENABLE1,
410 0, 0, NULL, 0),
411 SND_SOC_DAPM_SUPPLY_S("Digital Clock 1", 1, ADAU1761_CLK_ENABLE1,
412 1, 0, NULL, 0),
413};
414
415static const struct snd_soc_dapm_route adau1761_dapm_routes[] = {
416 { "Left Decimator", NULL, "Digital Clock 0", },
417 { "Right Decimator", NULL, "Digital Clock 0", },
418 { "Left DAC", NULL, "Digital Clock 0", },
419 { "Right DAC", NULL, "Digital Clock 0", },
420
421 { "AIFCLK", NULL, "Digital Clock 1" },
422
423 { "Playback", NULL, "Serial Port Clock" },
424 { "Capture", NULL, "Serial Port Clock" },
425 { "Playback", NULL, "Serial Input Routing Clock" },
426 { "Capture", NULL, "Serial Output Routing Clock" },
427
428 { "Left Decimator", NULL, "Decimator Resync Clock" },
429 { "Right Decimator", NULL, "Decimator Resync Clock" },
430 { "Left DAC", NULL, "Interpolator Resync Clock" },
431 { "Right DAC", NULL, "Interpolator Resync Clock" },
432
433 { "DSP", NULL, "Digital Clock 0" },
434
435 { "Slew Clock", NULL, "Digital Clock 0" },
436 { "Right Playback Mixer", NULL, "Slew Clock" },
437 { "Left Playback Mixer", NULL, "Slew Clock" },
438
439 { "Digital Clock 0", NULL, "SYSCLK" },
440 { "Digital Clock 1", NULL, "SYSCLK" },
441};
442
443static int adau1761_set_bias_level(struct snd_soc_codec *codec,
444 enum snd_soc_bias_level level)
445{
446 struct adau *adau = snd_soc_codec_get_drvdata(codec);
447
448 switch (level) {
449 case SND_SOC_BIAS_ON:
450 break;
451 case SND_SOC_BIAS_PREPARE:
452 break;
453 case SND_SOC_BIAS_STANDBY:
454 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
455 ADAU17X1_CLOCK_CONTROL_SYSCLK_EN,
456 ADAU17X1_CLOCK_CONTROL_SYSCLK_EN);
457 break;
458 case SND_SOC_BIAS_OFF:
459 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
460 ADAU17X1_CLOCK_CONTROL_SYSCLK_EN, 0);
461 break;
462
463 }
464 codec->dapm.bias_level = level;
465 return 0;
466}
467
468static enum adau1761_output_mode adau1761_get_lineout_mode(
469 struct snd_soc_codec *codec)
470{
471 struct adau1761_platform_data *pdata = codec->dev->platform_data;
472
473 if (pdata)
474 return pdata->lineout_mode;
475
476 return ADAU1761_OUTPUT_MODE_LINE;
477}
478
479static int adau1761_setup_digmic_jackdetect(struct snd_soc_codec *codec)
480{
481 struct adau1761_platform_data *pdata = codec->dev->platform_data;
482 struct adau *adau = snd_soc_codec_get_drvdata(codec);
483 enum adau1761_digmic_jackdet_pin_mode mode;
484 unsigned int val = 0;
485 int ret;
486
487 if (pdata)
488 mode = pdata->digmic_jackdetect_pin_mode;
489 else
490 mode = ADAU1761_DIGMIC_JACKDET_PIN_MODE_NONE;
491
492 switch (mode) {
493 case ADAU1761_DIGMIC_JACKDET_PIN_MODE_JACKDETECT:
494 switch (pdata->jackdetect_debounce_time) {
495 case ADAU1761_JACKDETECT_DEBOUNCE_5MS:
496 case ADAU1761_JACKDETECT_DEBOUNCE_10MS:
497 case ADAU1761_JACKDETECT_DEBOUNCE_20MS:
498 case ADAU1761_JACKDETECT_DEBOUNCE_40MS:
499 val |= pdata->jackdetect_debounce_time << 6;
500 break;
501 default:
502 return -EINVAL;
503 }
504 if (pdata->jackdetect_active_low)
505 val |= ADAU1761_DIGMIC_JACKDETECT_ACTIVE_LOW;
506
507 ret = snd_soc_add_codec_controls(codec,
508 adau1761_jack_detect_controls,
509 ARRAY_SIZE(adau1761_jack_detect_controls));
510 if (ret)
511 return ret;
512 case ADAU1761_DIGMIC_JACKDET_PIN_MODE_NONE: /* fallthrough */
513 ret = snd_soc_dapm_add_routes(&codec->dapm,
514 adau1761_no_dmic_routes,
515 ARRAY_SIZE(adau1761_no_dmic_routes));
516 if (ret)
517 return ret;
518 break;
519 case ADAU1761_DIGMIC_JACKDET_PIN_MODE_DIGMIC:
520 ret = snd_soc_dapm_new_controls(&codec->dapm,
521 adau1761_dmic_widgets,
522 ARRAY_SIZE(adau1761_dmic_widgets));
523 if (ret)
524 return ret;
525
526 ret = snd_soc_dapm_add_routes(&codec->dapm,
527 adau1761_dmic_routes,
528 ARRAY_SIZE(adau1761_dmic_routes));
529 if (ret)
530 return ret;
531
532 val |= ADAU1761_DIGMIC_JACKDETECT_DIGMIC;
533 break;
534 default:
535 return -EINVAL;
536 }
537
538 regmap_write(adau->regmap, ADAU1761_DIGMIC_JACKDETECT, val);
539
540 return 0;
541}
542
543static int adau1761_setup_headphone_mode(struct snd_soc_codec *codec)
544{
545 struct adau *adau = snd_soc_codec_get_drvdata(codec);
546 struct adau1761_platform_data *pdata = codec->dev->platform_data;
547 enum adau1761_output_mode mode;
548 int ret;
549
550 if (pdata)
551 mode = pdata->headphone_mode;
552 else
553 mode = ADAU1761_OUTPUT_MODE_HEADPHONE;
554
555 switch (mode) {
556 case ADAU1761_OUTPUT_MODE_LINE:
557 break;
558 case ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS:
559 regmap_update_bits(adau->regmap, ADAU1761_PLAY_MONO_OUTPUT_VOL,
560 ADAU1761_PLAY_MONO_OUTPUT_VOL_MODE_HP |
561 ADAU1761_PLAY_MONO_OUTPUT_VOL_UNMUTE,
562 ADAU1761_PLAY_MONO_OUTPUT_VOL_MODE_HP |
563 ADAU1761_PLAY_MONO_OUTPUT_VOL_UNMUTE);
564 /* fallthrough */
565 case ADAU1761_OUTPUT_MODE_HEADPHONE:
566 regmap_update_bits(adau->regmap, ADAU1761_PLAY_HP_RIGHT_VOL,
567 ADAU1761_PLAY_HP_RIGHT_VOL_MODE_HP,
568 ADAU1761_PLAY_HP_RIGHT_VOL_MODE_HP);
569 break;
570 default:
571 return -EINVAL;
572 }
573
574 if (mode == ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS) {
575 ret = snd_soc_dapm_new_controls(&codec->dapm,
576 adau1761_capless_dapm_widgets,
577 ARRAY_SIZE(adau1761_capless_dapm_widgets));
578 if (ret)
579 return ret;
580 ret = snd_soc_dapm_add_routes(&codec->dapm,
581 adau1761_capless_dapm_routes,
582 ARRAY_SIZE(adau1761_capless_dapm_routes));
583 } else {
584 ret = snd_soc_add_codec_controls(codec, adau1761_mono_controls,
585 ARRAY_SIZE(adau1761_mono_controls));
586 if (ret)
587 return ret;
588 ret = snd_soc_dapm_new_controls(&codec->dapm,
589 adau1761_mono_dapm_widgets,
590 ARRAY_SIZE(adau1761_mono_dapm_widgets));
591 if (ret)
592 return ret;
593 ret = snd_soc_dapm_add_routes(&codec->dapm,
594 adau1761_mono_dapm_routes,
595 ARRAY_SIZE(adau1761_mono_dapm_routes));
596 }
597
598 return ret;
599}
600
601static bool adau1761_readable_register(struct device *dev, unsigned int reg)
602{
603 switch (reg) {
604 case ADAU1761_DIGMIC_JACKDETECT:
605 case ADAU1761_REC_MIXER_LEFT0:
606 case ADAU1761_REC_MIXER_LEFT1:
607 case ADAU1761_REC_MIXER_RIGHT0:
608 case ADAU1761_REC_MIXER_RIGHT1:
609 case ADAU1761_LEFT_DIFF_INPUT_VOL:
610 case ADAU1761_RIGHT_DIFF_INPUT_VOL:
611 case ADAU1761_PLAY_LR_MIXER_LEFT:
612 case ADAU1761_PLAY_MIXER_LEFT0:
613 case ADAU1761_PLAY_MIXER_LEFT1:
614 case ADAU1761_PLAY_MIXER_RIGHT0:
615 case ADAU1761_PLAY_MIXER_RIGHT1:
616 case ADAU1761_PLAY_LR_MIXER_RIGHT:
617 case ADAU1761_PLAY_MIXER_MONO:
618 case ADAU1761_PLAY_HP_LEFT_VOL:
619 case ADAU1761_PLAY_HP_RIGHT_VOL:
620 case ADAU1761_PLAY_LINE_LEFT_VOL:
621 case ADAU1761_PLAY_LINE_RIGHT_VOL:
622 case ADAU1761_PLAY_MONO_OUTPUT_VOL:
623 case ADAU1761_POP_CLICK_SUPPRESS:
624 case ADAU1761_JACK_DETECT_PIN:
625 case ADAU1761_DEJITTER:
626 case ADAU1761_CLK_ENABLE0:
627 case ADAU1761_CLK_ENABLE1:
628 return true;
629 default:
630 break;
631 }
632
633 return adau17x1_readable_register(dev, reg);
634}
635
636static int adau1761_codec_probe(struct snd_soc_codec *codec)
637{
638 struct adau1761_platform_data *pdata = codec->dev->platform_data;
639 struct adau *adau = snd_soc_codec_get_drvdata(codec);
640 int ret;
641
642 ret = adau17x1_add_widgets(codec);
643 if (ret < 0)
644 return ret;
645
646 if (pdata && pdata->input_differential) {
647 regmap_update_bits(adau->regmap, ADAU1761_LEFT_DIFF_INPUT_VOL,
648 ADAU1761_DIFF_INPUT_VOL_LDEN,
649 ADAU1761_DIFF_INPUT_VOL_LDEN);
650 regmap_update_bits(adau->regmap, ADAU1761_RIGHT_DIFF_INPUT_VOL,
651 ADAU1761_DIFF_INPUT_VOL_LDEN,
652 ADAU1761_DIFF_INPUT_VOL_LDEN);
653 ret = snd_soc_add_codec_controls(codec,
654 adau1761_differential_mode_controls,
655 ARRAY_SIZE(adau1761_differential_mode_controls));
656 if (ret)
657 return ret;
658 } else {
659 ret = snd_soc_add_codec_controls(codec,
660 adau1761_single_mode_controls,
661 ARRAY_SIZE(adau1761_single_mode_controls));
662 if (ret)
663 return ret;
664 }
665
666 switch (adau1761_get_lineout_mode(codec)) {
667 case ADAU1761_OUTPUT_MODE_LINE:
668 break;
669 case ADAU1761_OUTPUT_MODE_HEADPHONE:
670 regmap_update_bits(adau->regmap, ADAU1761_PLAY_LINE_LEFT_VOL,
671 ADAU1761_PLAY_LINE_LEFT_VOL_MODE_HP,
672 ADAU1761_PLAY_LINE_LEFT_VOL_MODE_HP);
673 regmap_update_bits(adau->regmap, ADAU1761_PLAY_LINE_RIGHT_VOL,
674 ADAU1761_PLAY_LINE_RIGHT_VOL_MODE_HP,
675 ADAU1761_PLAY_LINE_RIGHT_VOL_MODE_HP);
676 break;
677 default:
678 return -EINVAL;
679 }
680
681 ret = adau1761_setup_headphone_mode(codec);
682 if (ret)
683 return ret;
684
685 ret = adau1761_setup_digmic_jackdetect(codec);
686 if (ret)
687 return ret;
688
689 if (adau->type == ADAU1761) {
690 ret = snd_soc_dapm_new_controls(&codec->dapm,
691 adau1761_dapm_widgets,
692 ARRAY_SIZE(adau1761_dapm_widgets));
693 if (ret)
694 return ret;
695
696 ret = snd_soc_dapm_add_routes(&codec->dapm,
697 adau1761_dapm_routes,
698 ARRAY_SIZE(adau1761_dapm_routes));
699 if (ret)
700 return ret;
701
702 ret = adau17x1_load_firmware(adau, codec->dev,
703 ADAU1761_FIRMWARE);
704 if (ret)
705 dev_warn(codec->dev, "Failed to firmware\n");
706 }
707
708 ret = adau17x1_add_routes(codec);
709 if (ret < 0)
710 return ret;
711
712 return 0;
713}
714
715static const struct snd_soc_codec_driver adau1761_codec_driver = {
716 .probe = adau1761_codec_probe,
717 .suspend = adau17x1_suspend,
718 .resume = adau17x1_resume,
719 .set_bias_level = adau1761_set_bias_level,
720
721 .controls = adau1761_controls,
722 .num_controls = ARRAY_SIZE(adau1761_controls),
723 .dapm_widgets = adau1x61_dapm_widgets,
724 .num_dapm_widgets = ARRAY_SIZE(adau1x61_dapm_widgets),
725 .dapm_routes = adau1x61_dapm_routes,
726 .num_dapm_routes = ARRAY_SIZE(adau1x61_dapm_routes),
727};
728
729#define ADAU1761_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
730 SNDRV_PCM_FMTBIT_S32_LE)
731
732static struct snd_soc_dai_driver adau1361_dai_driver = {
733 .name = "adau-hifi",
734 .playback = {
735 .stream_name = "Playback",
736 .channels_min = 2,
737 .channels_max = 4,
738 .rates = SNDRV_PCM_RATE_8000_96000,
739 .formats = ADAU1761_FORMATS,
740 },
741 .capture = {
742 .stream_name = "Capture",
743 .channels_min = 2,
744 .channels_max = 4,
745 .rates = SNDRV_PCM_RATE_8000_96000,
746 .formats = ADAU1761_FORMATS,
747 },
748 .ops = &adau17x1_dai_ops,
749};
750
751static struct snd_soc_dai_driver adau1761_dai_driver = {
752 .name = "adau-hifi",
753 .playback = {
754 .stream_name = "Playback",
755 .channels_min = 2,
756 .channels_max = 8,
757 .rates = SNDRV_PCM_RATE_8000_96000,
758 .formats = ADAU1761_FORMATS,
759 },
760 .capture = {
761 .stream_name = "Capture",
762 .channels_min = 2,
763 .channels_max = 8,
764 .rates = SNDRV_PCM_RATE_8000_96000,
765 .formats = ADAU1761_FORMATS,
766 },
767 .ops = &adau17x1_dai_ops,
768};
769
770int adau1761_probe(struct device *dev, struct regmap *regmap,
771 enum adau17x1_type type, void (*switch_mode)(struct device *dev))
772{
773 struct snd_soc_dai_driver *dai_drv;
774 int ret;
775
776 ret = adau17x1_probe(dev, regmap, type, switch_mode);
777 if (ret)
778 return ret;
779
780 if (type == ADAU1361)
781 dai_drv = &adau1361_dai_driver;
782 else
783 dai_drv = &adau1761_dai_driver;
784
785 return snd_soc_register_codec(dev, &adau1761_codec_driver, dai_drv, 1);
786}
787EXPORT_SYMBOL_GPL(adau1761_probe);
788
789const struct regmap_config adau1761_regmap_config = {
790 .val_bits = 8,
791 .reg_bits = 16,
792 .max_register = 0x40fa,
793 .reg_defaults = adau1761_reg_defaults,
794 .num_reg_defaults = ARRAY_SIZE(adau1761_reg_defaults),
795 .readable_reg = adau1761_readable_register,
796 .volatile_reg = adau17x1_volatile_register,
797 .cache_type = REGCACHE_RBTREE,
798};
799EXPORT_SYMBOL_GPL(adau1761_regmap_config);
800
801MODULE_DESCRIPTION("ASoC ADAU1361/ADAU1461/ADAU1761/ADAU1961 CODEC driver");
802MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
803MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/adau1761.h b/sound/soc/codecs/adau1761.h
new file mode 100644
index 000000000000..a9e0d288301e
--- /dev/null
+++ b/sound/soc/codecs/adau1761.h
@@ -0,0 +1,23 @@
1/*
2 * ADAU1361/ADAU1461/ADAU1761/ADAU1961 driver
3 *
4 * Copyright 2014 Analog Devices Inc.
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
6 *
7 * Licensed under the GPL-2.
8 */
9
10#ifndef __SOUND_SOC_CODECS_ADAU1761_H__
11#define __SOUND_SOC_CODECS_ADAU1761_H__
12
13#include <linux/regmap.h>
14#include "adau17x1.h"
15
16struct device;
17
18int adau1761_probe(struct device *dev, struct regmap *regmap,
19 enum adau17x1_type type, void (*switch_mode)(struct device *dev));
20
21extern const struct regmap_config adau1761_regmap_config;
22
23#endif
diff --git a/sound/soc/codecs/adau1781-i2c.c b/sound/soc/codecs/adau1781-i2c.c
new file mode 100644
index 000000000000..2ce4362ccec1
--- /dev/null
+++ b/sound/soc/codecs/adau1781-i2c.c
@@ -0,0 +1,58 @@
1/*
2 * Driver for ADAU1381/ADAU1781 CODEC
3 *
4 * Copyright 2014 Analog Devices Inc.
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
6 *
7 * Licensed under the GPL-2.
8 */
9
10#include <linux/i2c.h>
11#include <linux/mod_devicetable.h>
12#include <linux/module.h>
13#include <linux/regmap.h>
14#include <sound/soc.h>
15
16#include "adau1781.h"
17
18static int adau1781_i2c_probe(struct i2c_client *client,
19 const struct i2c_device_id *id)
20{
21 struct regmap_config config;
22
23 config = adau1781_regmap_config;
24 config.val_bits = 8;
25 config.reg_bits = 16;
26
27 return adau1781_probe(&client->dev,
28 devm_regmap_init_i2c(client, &config),
29 id->driver_data, NULL);
30}
31
32static int adau1781_i2c_remove(struct i2c_client *client)
33{
34 snd_soc_unregister_codec(&client->dev);
35 return 0;
36}
37
38static const struct i2c_device_id adau1781_i2c_ids[] = {
39 { "adau1381", ADAU1381 },
40 { "adau1781", ADAU1781 },
41 { }
42};
43MODULE_DEVICE_TABLE(i2c, adau1781_i2c_ids);
44
45static struct i2c_driver adau1781_i2c_driver = {
46 .driver = {
47 .name = "adau1781",
48 .owner = THIS_MODULE,
49 },
50 .probe = adau1781_i2c_probe,
51 .remove = adau1781_i2c_remove,
52 .id_table = adau1781_i2c_ids,
53};
54module_i2c_driver(adau1781_i2c_driver);
55
56MODULE_DESCRIPTION("ASoC ADAU1381/ADAU1781 CODEC I2C driver");
57MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
58MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/adau1781-spi.c b/sound/soc/codecs/adau1781-spi.c
new file mode 100644
index 000000000000..194686716bbe
--- /dev/null
+++ b/sound/soc/codecs/adau1781-spi.c
@@ -0,0 +1,75 @@
1/*
2 * Driver for ADAU1381/ADAU1781 CODEC
3 *
4 * Copyright 2014 Analog Devices Inc.
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
6 *
7 * Licensed under the GPL-2.
8 */
9
10#include <linux/mod_devicetable.h>
11#include <linux/module.h>
12#include <linux/regmap.h>
13#include <linux/spi/spi.h>
14#include <sound/soc.h>
15
16#include "adau1781.h"
17
18static void adau1781_spi_switch_mode(struct device *dev)
19{
20 struct spi_device *spi = to_spi_device(dev);
21
22 /*
23 * To get the device into SPI mode CLATCH has to be pulled low three
24 * times. Do this by issuing three dummy reads.
25 */
26 spi_w8r8(spi, 0x00);
27 spi_w8r8(spi, 0x00);
28 spi_w8r8(spi, 0x00);
29}
30
31static int adau1781_spi_probe(struct spi_device *spi)
32{
33 const struct spi_device_id *id = spi_get_device_id(spi);
34 struct regmap_config config;
35
36 if (!id)
37 return -EINVAL;
38
39 config = adau1781_regmap_config;
40 config.val_bits = 8;
41 config.reg_bits = 24;
42 config.read_flag_mask = 0x1;
43
44 return adau1781_probe(&spi->dev,
45 devm_regmap_init_spi(spi, &config),
46 id->driver_data, adau1781_spi_switch_mode);
47}
48
49static int adau1781_spi_remove(struct spi_device *spi)
50{
51 snd_soc_unregister_codec(&spi->dev);
52 return 0;
53}
54
55static const struct spi_device_id adau1781_spi_id[] = {
56 { "adau1381", ADAU1381 },
57 { "adau1781", ADAU1781 },
58 { }
59};
60MODULE_DEVICE_TABLE(spi, adau1781_spi_id);
61
62static struct spi_driver adau1781_spi_driver = {
63 .driver = {
64 .name = "adau1781",
65 .owner = THIS_MODULE,
66 },
67 .probe = adau1781_spi_probe,
68 .remove = adau1781_spi_remove,
69 .id_table = adau1781_spi_id,
70};
71module_spi_driver(adau1781_spi_driver);
72
73MODULE_DESCRIPTION("ASoC ADAU1381/ADAU1781 CODEC SPI driver");
74MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
75MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/adau1781.c b/sound/soc/codecs/adau1781.c
new file mode 100644
index 000000000000..045a61413840
--- /dev/null
+++ b/sound/soc/codecs/adau1781.c
@@ -0,0 +1,511 @@
1/*
2 * Driver for ADAU1781/ADAU1781 codec
3 *
4 * Copyright 2011-2013 Analog Devices Inc.
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
6 *
7 * Licensed under the GPL-2 or later.
8 */
9
10#include <linux/module.h>
11#include <linux/init.h>
12#include <linux/i2c.h>
13#include <linux/spi/spi.h>
14#include <linux/slab.h>
15#include <sound/core.h>
16#include <sound/pcm.h>
17#include <sound/pcm_params.h>
18#include <sound/soc.h>
19#include <sound/tlv.h>
20#include <linux/platform_data/adau17x1.h>
21
22#include "adau17x1.h"
23#include "adau1781.h"
24
25#define ADAU1781_DMIC_BEEP_CTRL 0x4008
26#define ADAU1781_LEFT_PGA 0x400e
27#define ADAU1781_RIGHT_PGA 0x400f
28#define ADAU1781_LEFT_PLAYBACK_MIXER 0x401c
29#define ADAU1781_RIGHT_PLAYBACK_MIXER 0x401e
30#define ADAU1781_MONO_PLAYBACK_MIXER 0x401f
31#define ADAU1781_LEFT_LINEOUT 0x4025
32#define ADAU1781_RIGHT_LINEOUT 0x4026
33#define ADAU1781_SPEAKER 0x4027
34#define ADAU1781_BEEP_ZC 0x4028
35#define ADAU1781_DEJITTER 0x4032
36#define ADAU1781_DIG_PWDN0 0x4080
37#define ADAU1781_DIG_PWDN1 0x4081
38
39#define ADAU1781_INPUT_DIFFERNTIAL BIT(3)
40
41#define ADAU1381_FIRMWARE "adau1381.bin"
42#define ADAU1781_FIRMWARE "adau1781.bin"
43
44static const struct reg_default adau1781_reg_defaults[] = {
45 { ADAU1781_DMIC_BEEP_CTRL, 0x00 },
46 { ADAU1781_LEFT_PGA, 0xc7 },
47 { ADAU1781_RIGHT_PGA, 0xc7 },
48 { ADAU1781_LEFT_PLAYBACK_MIXER, 0x00 },
49 { ADAU1781_RIGHT_PLAYBACK_MIXER, 0x00 },
50 { ADAU1781_MONO_PLAYBACK_MIXER, 0x00 },
51 { ADAU1781_LEFT_LINEOUT, 0x00 },
52 { ADAU1781_RIGHT_LINEOUT, 0x00 },
53 { ADAU1781_SPEAKER, 0x00 },
54 { ADAU1781_BEEP_ZC, 0x19 },
55 { ADAU1781_DEJITTER, 0x60 },
56 { ADAU1781_DIG_PWDN1, 0x0c },
57 { ADAU1781_DIG_PWDN1, 0x00 },
58 { ADAU17X1_CLOCK_CONTROL, 0x00 },
59 { ADAU17X1_PLL_CONTROL, 0x00 },
60 { ADAU17X1_REC_POWER_MGMT, 0x00 },
61 { ADAU17X1_MICBIAS, 0x04 },
62 { ADAU17X1_SERIAL_PORT0, 0x00 },
63 { ADAU17X1_SERIAL_PORT1, 0x00 },
64 { ADAU17X1_CONVERTER0, 0x00 },
65 { ADAU17X1_CONVERTER1, 0x00 },
66 { ADAU17X1_LEFT_INPUT_DIGITAL_VOL, 0x00 },
67 { ADAU17X1_RIGHT_INPUT_DIGITAL_VOL, 0x00 },
68 { ADAU17X1_ADC_CONTROL, 0x00 },
69 { ADAU17X1_PLAY_POWER_MGMT, 0x00 },
70 { ADAU17X1_DAC_CONTROL0, 0x00 },
71 { ADAU17X1_DAC_CONTROL1, 0x00 },
72 { ADAU17X1_DAC_CONTROL2, 0x00 },
73 { ADAU17X1_SERIAL_PORT_PAD, 0x00 },
74 { ADAU17X1_CONTROL_PORT_PAD0, 0x00 },
75 { ADAU17X1_CONTROL_PORT_PAD1, 0x00 },
76 { ADAU17X1_DSP_SAMPLING_RATE, 0x01 },
77 { ADAU17X1_SERIAL_INPUT_ROUTE, 0x00 },
78 { ADAU17X1_SERIAL_OUTPUT_ROUTE, 0x00 },
79 { ADAU17X1_DSP_ENABLE, 0x00 },
80 { ADAU17X1_DSP_RUN, 0x00 },
81 { ADAU17X1_SERIAL_SAMPLING_RATE, 0x00 },
82};
83
84static const DECLARE_TLV_DB_SCALE(adau1781_speaker_tlv, 0, 200, 0);
85
86static const DECLARE_TLV_DB_RANGE(adau1781_pga_tlv,
87 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
88 2, 3, TLV_DB_SCALE_ITEM(1000, 400, 0),
89 4, 4, TLV_DB_SCALE_ITEM(1700, 0, 0),
90 5, 7, TLV_DB_SCALE_ITEM(2000, 600, 0)
91);
92
93static const DECLARE_TLV_DB_RANGE(adau1781_beep_tlv,
94 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
95 2, 3, TLV_DB_SCALE_ITEM(1000, 400, 0),
96 4, 4, TLV_DB_SCALE_ITEM(-2300, 0, 0),
97 5, 7, TLV_DB_SCALE_ITEM(2000, 600, 0)
98);
99
100static const DECLARE_TLV_DB_SCALE(adau1781_sidetone_tlv, -1800, 300, 1);
101
102static const char * const adau1781_speaker_bias_select_text[] = {
103 "Normal operation", "Power saving", "Enhanced performance",
104};
105
106static const char * const adau1781_bias_select_text[] = {
107 "Normal operation", "Extreme power saving", "Power saving",
108 "Enhanced performance",
109};
110
111static SOC_ENUM_SINGLE_DECL(adau1781_adc_bias_enum,
112 ADAU17X1_REC_POWER_MGMT, 3, adau1781_bias_select_text);
113static SOC_ENUM_SINGLE_DECL(adau1781_speaker_bias_enum,
114 ADAU17X1_PLAY_POWER_MGMT, 6, adau1781_speaker_bias_select_text);
115static SOC_ENUM_SINGLE_DECL(adau1781_dac_bias_enum,
116 ADAU17X1_PLAY_POWER_MGMT, 4, adau1781_bias_select_text);
117static SOC_ENUM_SINGLE_DECL(adau1781_playback_bias_enum,
118 ADAU17X1_PLAY_POWER_MGMT, 2, adau1781_bias_select_text);
119static SOC_ENUM_SINGLE_DECL(adau1781_capture_bias_enum,
120 ADAU17X1_REC_POWER_MGMT, 1, adau1781_bias_select_text);
121
122static const struct snd_kcontrol_new adau1781_controls[] = {
123 SOC_SINGLE_TLV("Beep Capture Volume", ADAU1781_DMIC_BEEP_CTRL, 0, 7, 0,
124 adau1781_beep_tlv),
125 SOC_DOUBLE_R_TLV("PGA Capture Volume", ADAU1781_LEFT_PGA,
126 ADAU1781_RIGHT_PGA, 5, 7, 0, adau1781_pga_tlv),
127 SOC_DOUBLE_R("PGA Capture Switch", ADAU1781_LEFT_PGA,
128 ADAU1781_RIGHT_PGA, 1, 1, 0),
129
130 SOC_DOUBLE_R("Lineout Playback Switch", ADAU1781_LEFT_LINEOUT,
131 ADAU1781_RIGHT_LINEOUT, 1, 1, 0),
132 SOC_SINGLE("Beep ZC Switch", ADAU1781_BEEP_ZC, 0, 1, 0),
133
134 SOC_SINGLE("Mono Playback Switch", ADAU1781_MONO_PLAYBACK_MIXER,
135 0, 1, 0),
136 SOC_SINGLE_TLV("Mono Playback Volume", ADAU1781_SPEAKER, 6, 3, 0,
137 adau1781_speaker_tlv),
138
139 SOC_ENUM("ADC Bias", adau1781_adc_bias_enum),
140 SOC_ENUM("DAC Bias", adau1781_dac_bias_enum),
141 SOC_ENUM("Capture Bias", adau1781_capture_bias_enum),
142 SOC_ENUM("Playback Bias", adau1781_playback_bias_enum),
143 SOC_ENUM("Speaker Bias", adau1781_speaker_bias_enum),
144};
145
146static const struct snd_kcontrol_new adau1781_beep_mixer_controls[] = {
147 SOC_DAPM_SINGLE("Beep Capture Switch", ADAU1781_DMIC_BEEP_CTRL,
148 3, 1, 0),
149};
150
151static const struct snd_kcontrol_new adau1781_left_mixer_controls[] = {
152 SOC_DAPM_SINGLE_AUTODISABLE("Switch",
153 ADAU1781_LEFT_PLAYBACK_MIXER, 5, 1, 0),
154 SOC_DAPM_SINGLE_TLV("Beep Playback Volume",
155 ADAU1781_LEFT_PLAYBACK_MIXER, 1, 8, 0, adau1781_sidetone_tlv),
156};
157
158static const struct snd_kcontrol_new adau1781_right_mixer_controls[] = {
159 SOC_DAPM_SINGLE_AUTODISABLE("Switch",
160 ADAU1781_RIGHT_PLAYBACK_MIXER, 6, 1, 0),
161 SOC_DAPM_SINGLE_TLV("Beep Playback Volume",
162 ADAU1781_LEFT_PLAYBACK_MIXER, 1, 8, 0, adau1781_sidetone_tlv),
163};
164
165static const struct snd_kcontrol_new adau1781_mono_mixer_controls[] = {
166 SOC_DAPM_SINGLE_AUTODISABLE("Left Switch",
167 ADAU1781_MONO_PLAYBACK_MIXER, 7, 1, 0),
168 SOC_DAPM_SINGLE_AUTODISABLE("Right Switch",
169 ADAU1781_MONO_PLAYBACK_MIXER, 6, 1, 0),
170 SOC_DAPM_SINGLE_TLV("Beep Playback Volume",
171 ADAU1781_MONO_PLAYBACK_MIXER, 2, 8, 0, adau1781_sidetone_tlv),
172};
173
174static int adau1781_dejitter_fixup(struct snd_soc_dapm_widget *w,
175 struct snd_kcontrol *kcontrol, int event)
176{
177 struct snd_soc_codec *codec = w->codec;
178 struct adau *adau = snd_soc_codec_get_drvdata(codec);
179
180 /* After any power changes have been made the dejitter circuit
181 * has to be reinitialized. */
182 regmap_write(adau->regmap, ADAU1781_DEJITTER, 0);
183 if (!adau->master)
184 regmap_write(adau->regmap, ADAU1781_DEJITTER, 5);
185
186 return 0;
187}
188
189static const struct snd_soc_dapm_widget adau1781_dapm_widgets[] = {
190 SND_SOC_DAPM_PGA("Left PGA", ADAU1781_LEFT_PGA, 0, 0, NULL, 0),
191 SND_SOC_DAPM_PGA("Right PGA", ADAU1781_RIGHT_PGA, 0, 0, NULL, 0),
192
193 SND_SOC_DAPM_OUT_DRV("Speaker", ADAU1781_SPEAKER, 0, 0, NULL, 0),
194
195 SOC_MIXER_NAMED_CTL_ARRAY("Beep Mixer", ADAU17X1_MICBIAS, 4, 0,
196 adau1781_beep_mixer_controls),
197
198 SOC_MIXER_ARRAY("Left Lineout Mixer", SND_SOC_NOPM, 0, 0,
199 adau1781_left_mixer_controls),
200 SOC_MIXER_ARRAY("Right Lineout Mixer", SND_SOC_NOPM, 0, 0,
201 adau1781_right_mixer_controls),
202 SOC_MIXER_ARRAY("Mono Mixer", SND_SOC_NOPM, 0, 0,
203 adau1781_mono_mixer_controls),
204
205 SND_SOC_DAPM_SUPPLY("Serial Input Routing", ADAU1781_DIG_PWDN0,
206 2, 0, NULL, 0),
207 SND_SOC_DAPM_SUPPLY("Serial Output Routing", ADAU1781_DIG_PWDN0,
208 3, 0, NULL, 0),
209 SND_SOC_DAPM_SUPPLY("Clock Domain Transfer", ADAU1781_DIG_PWDN0,
210 5, 0, NULL, 0),
211 SND_SOC_DAPM_SUPPLY("Serial Ports", ADAU1781_DIG_PWDN0, 4, 0, NULL, 0),
212 SND_SOC_DAPM_SUPPLY("ADC Engine", ADAU1781_DIG_PWDN0, 7, 0, NULL, 0),
213 SND_SOC_DAPM_SUPPLY("DAC Engine", ADAU1781_DIG_PWDN1, 0, 0, NULL, 0),
214 SND_SOC_DAPM_SUPPLY("Digital Mic", ADAU1781_DIG_PWDN1, 1, 0, NULL, 0),
215
216 SND_SOC_DAPM_SUPPLY("Sound Engine", ADAU1781_DIG_PWDN0, 0, 0, NULL, 0),
217 SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, ADAU1781_DIG_PWDN0, 1, 0, NULL, 0),
218
219 SND_SOC_DAPM_SUPPLY("Zero Crossing Detector", ADAU1781_DIG_PWDN1, 2, 0,
220 NULL, 0),
221
222 SND_SOC_DAPM_POST("Dejitter fixup", adau1781_dejitter_fixup),
223
224 SND_SOC_DAPM_INPUT("BEEP"),
225
226 SND_SOC_DAPM_OUTPUT("AOUTL"),
227 SND_SOC_DAPM_OUTPUT("AOUTR"),
228 SND_SOC_DAPM_OUTPUT("SP"),
229 SND_SOC_DAPM_INPUT("LMIC"),
230 SND_SOC_DAPM_INPUT("RMIC"),
231};
232
233static const struct snd_soc_dapm_route adau1781_dapm_routes[] = {
234 { "Left Lineout Mixer", NULL, "Left Playback Enable" },
235 { "Right Lineout Mixer", NULL, "Right Playback Enable" },
236
237 { "Left Lineout Mixer", "Beep Playback Volume", "Beep Mixer" },
238 { "Left Lineout Mixer", "Switch", "Left DAC" },
239
240 { "Right Lineout Mixer", "Beep Playback Volume", "Beep Mixer" },
241 { "Right Lineout Mixer", "Switch", "Right DAC" },
242
243 { "Mono Mixer", "Beep Playback Volume", "Beep Mixer" },
244 { "Mono Mixer", "Right Switch", "Right DAC" },
245 { "Mono Mixer", "Left Switch", "Left DAC" },
246 { "Speaker", NULL, "Mono Mixer" },
247
248 { "Mono Mixer", NULL, "SYSCLK" },
249 { "Left Lineout Mixer", NULL, "SYSCLK" },
250 { "Left Lineout Mixer", NULL, "SYSCLK" },
251
252 { "Beep Mixer", "Beep Capture Switch", "BEEP" },
253 { "Beep Mixer", NULL, "Zero Crossing Detector" },
254
255 { "Left DAC", NULL, "DAC Engine" },
256 { "Right DAC", NULL, "DAC Engine" },
257
258 { "Sound Engine", NULL, "SYSCLK" },
259 { "DSP", NULL, "Sound Engine" },
260
261 { "Left Decimator", NULL, "ADC Engine" },
262 { "Right Decimator", NULL, "ADC Engine" },
263
264 { "AIFCLK", NULL, "SYSCLK" },
265
266 { "Playback", NULL, "Serial Input Routing" },
267 { "Playback", NULL, "Serial Ports" },
268 { "Playback", NULL, "Clock Domain Transfer" },
269 { "Capture", NULL, "Serial Output Routing" },
270 { "Capture", NULL, "Serial Ports" },
271 { "Capture", NULL, "Clock Domain Transfer" },
272
273 { "AOUTL", NULL, "Left Lineout Mixer" },
274 { "AOUTR", NULL, "Right Lineout Mixer" },
275 { "SP", NULL, "Speaker" },
276};
277
278static const struct snd_soc_dapm_route adau1781_adc_dapm_routes[] = {
279 { "Left PGA", NULL, "LMIC" },
280 { "Right PGA", NULL, "RMIC" },
281
282 { "Left Decimator", NULL, "Left PGA" },
283 { "Right Decimator", NULL, "Right PGA" },
284};
285
286static const char * const adau1781_dmic_select_text[] = {
287 "DMIC1", "DMIC2",
288};
289
290static SOC_ENUM_SINGLE_VIRT_DECL(adau1781_dmic_select_enum,
291 adau1781_dmic_select_text);
292
293static const struct snd_kcontrol_new adau1781_dmic_mux =
294 SOC_DAPM_ENUM("DMIC Select", adau1781_dmic_select_enum);
295
296static const struct snd_soc_dapm_widget adau1781_dmic_dapm_widgets[] = {
297 SND_SOC_DAPM_MUX("DMIC Select", SND_SOC_NOPM, 0, 0, &adau1781_dmic_mux),
298
299 SND_SOC_DAPM_ADC("DMIC1", NULL, ADAU1781_DMIC_BEEP_CTRL, 4, 0),
300 SND_SOC_DAPM_ADC("DMIC2", NULL, ADAU1781_DMIC_BEEP_CTRL, 5, 0),
301};
302
303static const struct snd_soc_dapm_route adau1781_dmic_dapm_routes[] = {
304 { "DMIC1", NULL, "LMIC" },
305 { "DMIC2", NULL, "RMIC" },
306
307 { "DMIC1", NULL, "Digital Mic" },
308 { "DMIC2", NULL, "Digital Mic" },
309
310 { "DMIC Select", "DMIC1", "DMIC1" },
311 { "DMIC Select", "DMIC2", "DMIC2" },
312
313 { "Left Decimator", NULL, "DMIC Select" },
314 { "Right Decimator", NULL, "DMIC Select" },
315};
316
317static int adau1781_set_bias_level(struct snd_soc_codec *codec,
318 enum snd_soc_bias_level level)
319{
320 struct adau *adau = snd_soc_codec_get_drvdata(codec);
321
322 switch (level) {
323 case SND_SOC_BIAS_ON:
324 break;
325 case SND_SOC_BIAS_PREPARE:
326 break;
327 case SND_SOC_BIAS_STANDBY:
328 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
329 ADAU17X1_CLOCK_CONTROL_SYSCLK_EN,
330 ADAU17X1_CLOCK_CONTROL_SYSCLK_EN);
331
332 /* Precharge */
333 regmap_update_bits(adau->regmap, ADAU1781_DIG_PWDN1, 0x8, 0x8);
334 break;
335 case SND_SOC_BIAS_OFF:
336 regmap_update_bits(adau->regmap, ADAU1781_DIG_PWDN1, 0xc, 0x0);
337 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
338 ADAU17X1_CLOCK_CONTROL_SYSCLK_EN, 0);
339 break;
340 }
341
342 codec->dapm.bias_level = level;
343 return 0;
344}
345
346static bool adau1781_readable_register(struct device *dev, unsigned int reg)
347{
348 switch (reg) {
349 case ADAU1781_DMIC_BEEP_CTRL:
350 case ADAU1781_LEFT_PGA:
351 case ADAU1781_RIGHT_PGA:
352 case ADAU1781_LEFT_PLAYBACK_MIXER:
353 case ADAU1781_RIGHT_PLAYBACK_MIXER:
354 case ADAU1781_MONO_PLAYBACK_MIXER:
355 case ADAU1781_LEFT_LINEOUT:
356 case ADAU1781_RIGHT_LINEOUT:
357 case ADAU1781_SPEAKER:
358 case ADAU1781_BEEP_ZC:
359 case ADAU1781_DEJITTER:
360 case ADAU1781_DIG_PWDN0:
361 case ADAU1781_DIG_PWDN1:
362 return true;
363 default:
364 break;
365 }
366
367 return adau17x1_readable_register(dev, reg);
368}
369
370static int adau1781_set_input_mode(struct adau *adau, unsigned int reg,
371 bool differential)
372{
373 unsigned int val;
374
375 if (differential)
376 val = ADAU1781_INPUT_DIFFERNTIAL;
377 else
378 val = 0;
379
380 return regmap_update_bits(adau->regmap, reg,
381 ADAU1781_INPUT_DIFFERNTIAL, val);
382}
383
384static int adau1781_codec_probe(struct snd_soc_codec *codec)
385{
386 struct adau1781_platform_data *pdata = dev_get_platdata(codec->dev);
387 struct adau *adau = snd_soc_codec_get_drvdata(codec);
388 const char *firmware;
389 int ret;
390
391 ret = adau17x1_add_widgets(codec);
392 if (ret)
393 return ret;
394
395 if (pdata) {
396 ret = adau1781_set_input_mode(adau, ADAU1781_LEFT_PGA,
397 pdata->left_input_differential);
398 if (ret)
399 return ret;
400 ret = adau1781_set_input_mode(adau, ADAU1781_RIGHT_PGA,
401 pdata->right_input_differential);
402 if (ret)
403 return ret;
404 }
405
406 if (pdata && pdata->use_dmic) {
407 ret = snd_soc_dapm_new_controls(&codec->dapm,
408 adau1781_dmic_dapm_widgets,
409 ARRAY_SIZE(adau1781_dmic_dapm_widgets));
410 if (ret)
411 return ret;
412 ret = snd_soc_dapm_add_routes(&codec->dapm,
413 adau1781_dmic_dapm_routes,
414 ARRAY_SIZE(adau1781_dmic_dapm_routes));
415 if (ret)
416 return ret;
417 } else {
418 ret = snd_soc_dapm_add_routes(&codec->dapm,
419 adau1781_adc_dapm_routes,
420 ARRAY_SIZE(adau1781_adc_dapm_routes));
421 if (ret)
422 return ret;
423 }
424
425 switch (adau->type) {
426 case ADAU1381:
427 firmware = ADAU1381_FIRMWARE;
428 break;
429 case ADAU1781:
430 firmware = ADAU1781_FIRMWARE;
431 break;
432 default:
433 return -EINVAL;
434 }
435
436 ret = adau17x1_add_routes(codec);
437 if (ret < 0)
438 return ret;
439
440 ret = adau17x1_load_firmware(adau, codec->dev, firmware);
441 if (ret)
442 dev_warn(codec->dev, "Failed to load firmware\n");
443
444 return 0;
445}
446
447static const struct snd_soc_codec_driver adau1781_codec_driver = {
448 .probe = adau1781_codec_probe,
449 .suspend = adau17x1_suspend,
450 .resume = adau17x1_resume,
451 .set_bias_level = adau1781_set_bias_level,
452
453 .controls = adau1781_controls,
454 .num_controls = ARRAY_SIZE(adau1781_controls),
455 .dapm_widgets = adau1781_dapm_widgets,
456 .num_dapm_widgets = ARRAY_SIZE(adau1781_dapm_widgets),
457 .dapm_routes = adau1781_dapm_routes,
458 .num_dapm_routes = ARRAY_SIZE(adau1781_dapm_routes),
459};
460
461#define ADAU1781_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
462 SNDRV_PCM_FMTBIT_S32_LE)
463
464static struct snd_soc_dai_driver adau1781_dai_driver = {
465 .name = "adau-hifi",
466 .playback = {
467 .stream_name = "Playback",
468 .channels_min = 2,
469 .channels_max = 8,
470 .rates = SNDRV_PCM_RATE_8000_96000,
471 .formats = ADAU1781_FORMATS,
472 },
473 .capture = {
474 .stream_name = "Capture",
475 .channels_min = 2,
476 .channels_max = 8,
477 .rates = SNDRV_PCM_RATE_8000_96000,
478 .formats = ADAU1781_FORMATS,
479 },
480 .ops = &adau17x1_dai_ops,
481};
482
483const struct regmap_config adau1781_regmap_config = {
484 .val_bits = 8,
485 .reg_bits = 16,
486 .max_register = 0x40f8,
487 .reg_defaults = adau1781_reg_defaults,
488 .num_reg_defaults = ARRAY_SIZE(adau1781_reg_defaults),
489 .readable_reg = adau1781_readable_register,
490 .volatile_reg = adau17x1_volatile_register,
491 .cache_type = REGCACHE_RBTREE,
492};
493EXPORT_SYMBOL_GPL(adau1781_regmap_config);
494
495int adau1781_probe(struct device *dev, struct regmap *regmap,
496 enum adau17x1_type type, void (*switch_mode)(struct device *dev))
497{
498 int ret;
499
500 ret = adau17x1_probe(dev, regmap, type, switch_mode);
501 if (ret)
502 return ret;
503
504 return snd_soc_register_codec(dev, &adau1781_codec_driver,
505 &adau1781_dai_driver, 1);
506}
507EXPORT_SYMBOL_GPL(adau1781_probe);
508
509MODULE_DESCRIPTION("ASoC ADAU1381/ADAU1781 driver");
510MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
511MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/adau1781.h b/sound/soc/codecs/adau1781.h
new file mode 100644
index 000000000000..2b96e0a9ff2e
--- /dev/null
+++ b/sound/soc/codecs/adau1781.h
@@ -0,0 +1,23 @@
1/*
2 * ADAU1381/ADAU1781 driver
3 *
4 * Copyright 2014 Analog Devices Inc.
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
6 *
7 * Licensed under the GPL-2.
8 */
9
10#ifndef __SOUND_SOC_CODECS_ADAU1781_H__
11#define __SOUND_SOC_CODECS_ADAU1781_H__
12
13#include <linux/regmap.h>
14#include "adau17x1.h"
15
16struct device;
17
18int adau1781_probe(struct device *dev, struct regmap *regmap,
19 enum adau17x1_type type, void (*switch_mode)(struct device *dev));
20
21extern const struct regmap_config adau1781_regmap_config;
22
23#endif
diff --git a/sound/soc/codecs/adau17x1.c b/sound/soc/codecs/adau17x1.c
new file mode 100644
index 000000000000..2961fae9670a
--- /dev/null
+++ b/sound/soc/codecs/adau17x1.c
@@ -0,0 +1,866 @@
1/*
2 * Common code for ADAU1X61 and ADAU1X81 codecs
3 *
4 * Copyright 2011-2014 Analog Devices Inc.
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
6 *
7 * Licensed under the GPL-2 or later.
8 */
9
10#include <linux/module.h>
11#include <linux/init.h>
12#include <linux/delay.h>
13#include <linux/slab.h>
14#include <sound/core.h>
15#include <sound/pcm.h>
16#include <sound/pcm_params.h>
17#include <sound/soc.h>
18#include <sound/tlv.h>
19#include <linux/gcd.h>
20#include <linux/i2c.h>
21#include <linux/spi/spi.h>
22#include <linux/regmap.h>
23
24#include "sigmadsp.h"
25#include "adau17x1.h"
26
27static const char * const adau17x1_capture_mixer_boost_text[] = {
28 "Normal operation", "Boost Level 1", "Boost Level 2", "Boost Level 3",
29};
30
31static SOC_ENUM_SINGLE_DECL(adau17x1_capture_boost_enum,
32 ADAU17X1_REC_POWER_MGMT, 5, adau17x1_capture_mixer_boost_text);
33
34static const char * const adau17x1_mic_bias_mode_text[] = {
35 "Normal operation", "High performance",
36};
37
38static SOC_ENUM_SINGLE_DECL(adau17x1_mic_bias_mode_enum,
39 ADAU17X1_MICBIAS, 3, adau17x1_mic_bias_mode_text);
40
41static const DECLARE_TLV_DB_MINMAX(adau17x1_digital_tlv, -9563, 0);
42
43static const struct snd_kcontrol_new adau17x1_controls[] = {
44 SOC_DOUBLE_R_TLV("Digital Capture Volume",
45 ADAU17X1_LEFT_INPUT_DIGITAL_VOL,
46 ADAU17X1_RIGHT_INPUT_DIGITAL_VOL,
47 0, 0xff, 1, adau17x1_digital_tlv),
48 SOC_DOUBLE_R_TLV("Digital Playback Volume", ADAU17X1_DAC_CONTROL1,
49 ADAU17X1_DAC_CONTROL2, 0, 0xff, 1, adau17x1_digital_tlv),
50
51 SOC_SINGLE("ADC High Pass Filter Switch", ADAU17X1_ADC_CONTROL,
52 5, 1, 0),
53 SOC_SINGLE("Playback De-emphasis Switch", ADAU17X1_DAC_CONTROL0,
54 2, 1, 0),
55
56 SOC_ENUM("Capture Boost", adau17x1_capture_boost_enum),
57
58 SOC_ENUM("Mic Bias Mode", adau17x1_mic_bias_mode_enum),
59};
60
61static int adau17x1_pll_event(struct snd_soc_dapm_widget *w,
62 struct snd_kcontrol *kcontrol, int event)
63{
64 struct adau *adau = snd_soc_codec_get_drvdata(w->codec);
65 int ret;
66
67 if (SND_SOC_DAPM_EVENT_ON(event)) {
68 adau->pll_regs[5] = 1;
69 } else {
70 adau->pll_regs[5] = 0;
71 /* Bypass the PLL when disabled, otherwise registers will become
72 * inaccessible. */
73 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
74 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL, 0);
75 }
76
77 /* The PLL register is 6 bytes long and can only be written at once. */
78 ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
79 adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
80
81 if (SND_SOC_DAPM_EVENT_ON(event)) {
82 mdelay(5);
83 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
84 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL,
85 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL);
86 }
87
88 return 0;
89}
90
91static const char * const adau17x1_mono_stereo_text[] = {
92 "Stereo",
93 "Mono Left Channel (L+R)",
94 "Mono Right Channel (L+R)",
95 "Mono (L+R)",
96};
97
98static SOC_ENUM_SINGLE_DECL(adau17x1_dac_mode_enum,
99 ADAU17X1_DAC_CONTROL0, 6, adau17x1_mono_stereo_text);
100
101static const struct snd_kcontrol_new adau17x1_dac_mode_mux =
102 SOC_DAPM_ENUM("DAC Mono-Stereo-Mode", adau17x1_dac_mode_enum);
103
104static const struct snd_soc_dapm_widget adau17x1_dapm_widgets[] = {
105 SND_SOC_DAPM_SUPPLY_S("PLL", 3, SND_SOC_NOPM, 0, 0, adau17x1_pll_event,
106 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
107
108 SND_SOC_DAPM_SUPPLY("AIFCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
109
110 SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU17X1_MICBIAS, 0, 0, NULL, 0),
111
112 SND_SOC_DAPM_SUPPLY("Left Playback Enable", ADAU17X1_PLAY_POWER_MGMT,
113 0, 0, NULL, 0),
114 SND_SOC_DAPM_SUPPLY("Right Playback Enable", ADAU17X1_PLAY_POWER_MGMT,
115 1, 0, NULL, 0),
116
117 SND_SOC_DAPM_MUX("Left DAC Mode Mux", SND_SOC_NOPM, 0, 0,
118 &adau17x1_dac_mode_mux),
119 SND_SOC_DAPM_MUX("Right DAC Mode Mux", SND_SOC_NOPM, 0, 0,
120 &adau17x1_dac_mode_mux),
121
122 SND_SOC_DAPM_ADC("Left Decimator", NULL, ADAU17X1_ADC_CONTROL, 0, 0),
123 SND_SOC_DAPM_ADC("Right Decimator", NULL, ADAU17X1_ADC_CONTROL, 1, 0),
124 SND_SOC_DAPM_DAC("Left DAC", NULL, ADAU17X1_DAC_CONTROL0, 0, 0),
125 SND_SOC_DAPM_DAC("Right DAC", NULL, ADAU17X1_DAC_CONTROL0, 1, 0),
126};
127
128static const struct snd_soc_dapm_route adau17x1_dapm_routes[] = {
129 { "Left Decimator", NULL, "SYSCLK" },
130 { "Right Decimator", NULL, "SYSCLK" },
131 { "Left DAC", NULL, "SYSCLK" },
132 { "Right DAC", NULL, "SYSCLK" },
133 { "Capture", NULL, "SYSCLK" },
134 { "Playback", NULL, "SYSCLK" },
135
136 { "Left DAC", NULL, "Left DAC Mode Mux" },
137 { "Right DAC", NULL, "Right DAC Mode Mux" },
138
139 { "Capture", NULL, "AIFCLK" },
140 { "Playback", NULL, "AIFCLK" },
141};
142
143static const struct snd_soc_dapm_route adau17x1_dapm_pll_route = {
144 "SYSCLK", NULL, "PLL",
145};
146
147/*
148 * The MUX register for the Capture and Playback MUXs selects either DSP as
149 * source/destination or one of the TDM slots. The TDM slot is selected via
150 * snd_soc_dai_set_tdm_slot(), so we only expose whether to go to the DSP or
151 * directly to the DAI interface with this control.
152 */
153static int adau17x1_dsp_mux_enum_put(struct snd_kcontrol *kcontrol,
154 struct snd_ctl_elem_value *ucontrol)
155{
156 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
157 struct adau *adau = snd_soc_codec_get_drvdata(codec);
158 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
159 struct snd_soc_dapm_update update;
160 unsigned int stream = e->shift_l;
161 unsigned int val, change;
162 int reg;
163
164 if (ucontrol->value.enumerated.item[0] >= e->items)
165 return -EINVAL;
166
167 switch (ucontrol->value.enumerated.item[0]) {
168 case 0:
169 val = 0;
170 adau->dsp_bypass[stream] = false;
171 break;
172 default:
173 val = (adau->tdm_slot[stream] * 2) + 1;
174 adau->dsp_bypass[stream] = true;
175 break;
176 }
177
178 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
179 reg = ADAU17X1_SERIAL_INPUT_ROUTE;
180 else
181 reg = ADAU17X1_SERIAL_OUTPUT_ROUTE;
182
183 change = snd_soc_test_bits(codec, reg, 0xff, val);
184 if (change) {
185 update.kcontrol = kcontrol;
186 update.mask = 0xff;
187 update.reg = reg;
188 update.val = val;
189
190 snd_soc_dapm_mux_update_power(&codec->dapm, kcontrol,
191 ucontrol->value.enumerated.item[0], e, &update);
192 }
193
194 return change;
195}
196
197static int adau17x1_dsp_mux_enum_get(struct snd_kcontrol *kcontrol,
198 struct snd_ctl_elem_value *ucontrol)
199{
200 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
201 struct adau *adau = snd_soc_codec_get_drvdata(codec);
202 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
203 unsigned int stream = e->shift_l;
204 unsigned int reg, val;
205 int ret;
206
207 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
208 reg = ADAU17X1_SERIAL_INPUT_ROUTE;
209 else
210 reg = ADAU17X1_SERIAL_OUTPUT_ROUTE;
211
212 ret = regmap_read(adau->regmap, reg, &val);
213 if (ret)
214 return ret;
215
216 if (val != 0)
217 val = 1;
218 ucontrol->value.enumerated.item[0] = val;
219
220 return 0;
221}
222
223#define DECLARE_ADAU17X1_DSP_MUX_CTRL(_name, _label, _stream, _text) \
224 const struct snd_kcontrol_new _name = \
225 SOC_DAPM_ENUM_EXT(_label, (const struct soc_enum)\
226 SOC_ENUM_SINGLE(SND_SOC_NOPM, _stream, \
227 ARRAY_SIZE(_text), _text), \
228 adau17x1_dsp_mux_enum_get, adau17x1_dsp_mux_enum_put)
229
230static const char * const adau17x1_dac_mux_text[] = {
231 "DSP",
232 "AIFIN",
233};
234
235static const char * const adau17x1_capture_mux_text[] = {
236 "DSP",
237 "Decimator",
238};
239
240static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_dac_mux, "DAC Playback Mux",
241 SNDRV_PCM_STREAM_PLAYBACK, adau17x1_dac_mux_text);
242
243static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_capture_mux, "Capture Mux",
244 SNDRV_PCM_STREAM_CAPTURE, adau17x1_capture_mux_text);
245
246static const struct snd_soc_dapm_widget adau17x1_dsp_dapm_widgets[] = {
247 SND_SOC_DAPM_PGA("DSP", ADAU17X1_DSP_RUN, 0, 0, NULL, 0),
248 SND_SOC_DAPM_SIGGEN("DSP Siggen"),
249
250 SND_SOC_DAPM_MUX("DAC Playback Mux", SND_SOC_NOPM, 0, 0,
251 &adau17x1_dac_mux),
252 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
253 &adau17x1_capture_mux),
254};
255
256static const struct snd_soc_dapm_route adau17x1_dsp_dapm_routes[] = {
257 { "DAC Playback Mux", "DSP", "DSP" },
258 { "DAC Playback Mux", "AIFIN", "Playback" },
259
260 { "Left DAC Mode Mux", "Stereo", "DAC Playback Mux" },
261 { "Left DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
262 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "DAC Playback Mux" },
263 { "Right DAC Mode Mux", "Stereo", "DAC Playback Mux" },
264 { "Right DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
265 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "DAC Playback Mux" },
266
267 { "Capture Mux", "DSP", "DSP" },
268 { "Capture Mux", "Decimator", "Left Decimator" },
269 { "Capture Mux", "Decimator", "Right Decimator" },
270
271 { "Capture", NULL, "Capture Mux" },
272
273 { "DSP", NULL, "DSP Siggen" },
274
275 { "DSP", NULL, "Left Decimator" },
276 { "DSP", NULL, "Right Decimator" },
277};
278
279static const struct snd_soc_dapm_route adau17x1_no_dsp_dapm_routes[] = {
280 { "Left DAC Mode Mux", "Stereo", "Playback" },
281 { "Left DAC Mode Mux", "Mono (L+R)", "Playback" },
282 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "Playback" },
283 { "Right DAC Mode Mux", "Stereo", "Playback" },
284 { "Right DAC Mode Mux", "Mono (L+R)", "Playback" },
285 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "Playback" },
286 { "Capture", NULL, "Left Decimator" },
287 { "Capture", NULL, "Right Decimator" },
288};
289
290bool adau17x1_has_dsp(struct adau *adau)
291{
292 switch (adau->type) {
293 case ADAU1761:
294 case ADAU1381:
295 case ADAU1781:
296 return true;
297 default:
298 return false;
299 }
300}
301EXPORT_SYMBOL_GPL(adau17x1_has_dsp);
302
303static int adau17x1_hw_params(struct snd_pcm_substream *substream,
304 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
305{
306 struct snd_soc_codec *codec = dai->codec;
307 struct adau *adau = snd_soc_codec_get_drvdata(codec);
308 unsigned int val, div, dsp_div;
309 unsigned int freq;
310
311 if (adau->clk_src == ADAU17X1_CLK_SRC_PLL)
312 freq = adau->pll_freq;
313 else
314 freq = adau->sysclk;
315
316 if (freq % params_rate(params) != 0)
317 return -EINVAL;
318
319 switch (freq / params_rate(params)) {
320 case 1024: /* fs */
321 div = 0;
322 dsp_div = 1;
323 break;
324 case 6144: /* fs / 6 */
325 div = 1;
326 dsp_div = 6;
327 break;
328 case 4096: /* fs / 4 */
329 div = 2;
330 dsp_div = 5;
331 break;
332 case 3072: /* fs / 3 */
333 div = 3;
334 dsp_div = 4;
335 break;
336 case 2048: /* fs / 2 */
337 div = 4;
338 dsp_div = 3;
339 break;
340 case 1536: /* fs / 1.5 */
341 div = 5;
342 dsp_div = 2;
343 break;
344 case 512: /* fs / 0.5 */
345 div = 6;
346 dsp_div = 0;
347 break;
348 default:
349 return -EINVAL;
350 }
351
352 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
353 ADAU17X1_CONVERTER0_CONVSR_MASK, div);
354 if (adau17x1_has_dsp(adau)) {
355 regmap_write(adau->regmap, ADAU17X1_SERIAL_SAMPLING_RATE, div);
356 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dsp_div);
357 }
358
359 if (adau->dai_fmt != SND_SOC_DAIFMT_RIGHT_J)
360 return 0;
361
362 switch (params_format(params)) {
363 case SNDRV_PCM_FORMAT_S16_LE:
364 val = ADAU17X1_SERIAL_PORT1_DELAY16;
365 break;
366 case SNDRV_PCM_FORMAT_S24_LE:
367 val = ADAU17X1_SERIAL_PORT1_DELAY8;
368 break;
369 case SNDRV_PCM_FORMAT_S32_LE:
370 val = ADAU17X1_SERIAL_PORT1_DELAY0;
371 break;
372 default:
373 return -EINVAL;
374 }
375
376 return regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
377 ADAU17X1_SERIAL_PORT1_DELAY_MASK, val);
378}
379
380static int adau17x1_set_dai_pll(struct snd_soc_dai *dai, int pll_id,
381 int source, unsigned int freq_in, unsigned int freq_out)
382{
383 struct snd_soc_codec *codec = dai->codec;
384 struct adau *adau = snd_soc_codec_get_drvdata(codec);
385 unsigned int r, n, m, i, j;
386 unsigned int div;
387 int ret;
388
389 if (freq_in < 8000000 || freq_in > 27000000)
390 return -EINVAL;
391
392 if (!freq_out) {
393 r = 0;
394 n = 0;
395 m = 0;
396 div = 0;
397 } else {
398 if (freq_out % freq_in != 0) {
399 div = DIV_ROUND_UP(freq_in, 13500000);
400 freq_in /= div;
401 r = freq_out / freq_in;
402 i = freq_out % freq_in;
403 j = gcd(i, freq_in);
404 n = i / j;
405 m = freq_in / j;
406 div--;
407 } else {
408 r = freq_out / freq_in;
409 n = 0;
410 m = 0;
411 div = 0;
412 }
413 if (n > 0xffff || m > 0xffff || div > 3 || r > 8 || r < 2)
414 return -EINVAL;
415 }
416
417 adau->pll_regs[0] = m >> 8;
418 adau->pll_regs[1] = m & 0xff;
419 adau->pll_regs[2] = n >> 8;
420 adau->pll_regs[3] = n & 0xff;
421 adau->pll_regs[4] = (r << 3) | (div << 1);
422 if (m != 0)
423 adau->pll_regs[4] |= 1; /* Fractional mode */
424
425 /* The PLL register is 6 bytes long and can only be written at once. */
426 ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
427 adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
428 if (ret)
429 return ret;
430
431 adau->pll_freq = freq_out;
432
433 return 0;
434}
435
436static int adau17x1_set_dai_sysclk(struct snd_soc_dai *dai,
437 int clk_id, unsigned int freq, int dir)
438{
439 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
440 struct snd_soc_dapm_context *dapm = &dai->codec->dapm;
441
442 switch (clk_id) {
443 case ADAU17X1_CLK_SRC_MCLK:
444 case ADAU17X1_CLK_SRC_PLL:
445 break;
446 default:
447 return -EINVAL;
448 }
449
450 adau->sysclk = freq;
451
452 if (adau->clk_src != clk_id) {
453 if (clk_id == ADAU17X1_CLK_SRC_PLL) {
454 snd_soc_dapm_add_routes(dapm,
455 &adau17x1_dapm_pll_route, 1);
456 } else {
457 snd_soc_dapm_del_routes(dapm,
458 &adau17x1_dapm_pll_route, 1);
459 }
460 }
461
462 adau->clk_src = clk_id;
463
464 return 0;
465}
466
467static int adau17x1_set_dai_fmt(struct snd_soc_dai *dai,
468 unsigned int fmt)
469{
470 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
471 unsigned int ctrl0, ctrl1;
472 int lrclk_pol;
473
474 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
475 case SND_SOC_DAIFMT_CBM_CFM:
476 ctrl0 = ADAU17X1_SERIAL_PORT0_MASTER;
477 adau->master = true;
478 break;
479 case SND_SOC_DAIFMT_CBS_CFS:
480 ctrl0 = 0;
481 adau->master = false;
482 break;
483 default:
484 return -EINVAL;
485 }
486
487 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
488 case SND_SOC_DAIFMT_I2S:
489 lrclk_pol = 0;
490 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1;
491 break;
492 case SND_SOC_DAIFMT_LEFT_J:
493 case SND_SOC_DAIFMT_RIGHT_J:
494 lrclk_pol = 1;
495 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0;
496 break;
497 case SND_SOC_DAIFMT_DSP_A:
498 lrclk_pol = 1;
499 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE;
500 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1;
501 break;
502 case SND_SOC_DAIFMT_DSP_B:
503 lrclk_pol = 1;
504 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE;
505 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0;
506 break;
507 default:
508 return -EINVAL;
509 }
510
511 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
512 case SND_SOC_DAIFMT_NB_NF:
513 break;
514 case SND_SOC_DAIFMT_IB_NF:
515 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL;
516 break;
517 case SND_SOC_DAIFMT_NB_IF:
518 lrclk_pol = !lrclk_pol;
519 break;
520 case SND_SOC_DAIFMT_IB_IF:
521 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL;
522 lrclk_pol = !lrclk_pol;
523 break;
524 default:
525 return -EINVAL;
526 }
527
528 if (lrclk_pol)
529 ctrl0 |= ADAU17X1_SERIAL_PORT0_LRCLK_POL;
530
531 regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT0, ctrl0);
532 regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT1, ctrl1);
533
534 adau->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
535
536 return 0;
537}
538
539static int adau17x1_set_dai_tdm_slot(struct snd_soc_dai *dai,
540 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
541{
542 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
543 unsigned int ser_ctrl0, ser_ctrl1;
544 unsigned int conv_ctrl0, conv_ctrl1;
545
546 /* I2S mode */
547 if (slots == 0) {
548 slots = 2;
549 rx_mask = 3;
550 tx_mask = 3;
551 slot_width = 32;
552 }
553
554 switch (slots) {
555 case 2:
556 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_STEREO;
557 break;
558 case 4:
559 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM4;
560 break;
561 case 8:
562 if (adau->type == ADAU1361)
563 return -EINVAL;
564
565 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM8;
566 break;
567 default:
568 return -EINVAL;
569 }
570
571 switch (slot_width * slots) {
572 case 32:
573 if (adau->type == ADAU1761)
574 return -EINVAL;
575
576 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK32;
577 break;
578 case 64:
579 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK64;
580 break;
581 case 48:
582 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK48;
583 break;
584 case 128:
585 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK128;
586 break;
587 case 256:
588 if (adau->type == ADAU1361)
589 return -EINVAL;
590
591 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK256;
592 break;
593 default:
594 return -EINVAL;
595 }
596
597 switch (rx_mask) {
598 case 0x03:
599 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(1);
600 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 0;
601 break;
602 case 0x0c:
603 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(2);
604 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 1;
605 break;
606 case 0x30:
607 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(3);
608 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 2;
609 break;
610 case 0xc0:
611 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(4);
612 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 3;
613 break;
614 default:
615 return -EINVAL;
616 }
617
618 switch (tx_mask) {
619 case 0x03:
620 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(1);
621 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 0;
622 break;
623 case 0x0c:
624 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(2);
625 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 1;
626 break;
627 case 0x30:
628 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(3);
629 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 2;
630 break;
631 case 0xc0:
632 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(4);
633 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 3;
634 break;
635 default:
636 return -EINVAL;
637 }
638
639 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
640 ADAU17X1_CONVERTER0_DAC_PAIR_MASK, conv_ctrl0);
641 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER1,
642 ADAU17X1_CONVERTER1_ADC_PAIR_MASK, conv_ctrl1);
643 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT0,
644 ADAU17X1_SERIAL_PORT0_TDM_MASK, ser_ctrl0);
645 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
646 ADAU17X1_SERIAL_PORT1_BCLK_MASK, ser_ctrl1);
647
648 if (!adau17x1_has_dsp(adau))
649 return 0;
650
651 if (adau->dsp_bypass[SNDRV_PCM_STREAM_PLAYBACK]) {
652 regmap_write(adau->regmap, ADAU17X1_SERIAL_INPUT_ROUTE,
653 (adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] * 2) + 1);
654 }
655
656 if (adau->dsp_bypass[SNDRV_PCM_STREAM_CAPTURE]) {
657 regmap_write(adau->regmap, ADAU17X1_SERIAL_OUTPUT_ROUTE,
658 (adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] * 2) + 1);
659 }
660
661 return 0;
662}
663
664const struct snd_soc_dai_ops adau17x1_dai_ops = {
665 .hw_params = adau17x1_hw_params,
666 .set_sysclk = adau17x1_set_dai_sysclk,
667 .set_fmt = adau17x1_set_dai_fmt,
668 .set_pll = adau17x1_set_dai_pll,
669 .set_tdm_slot = adau17x1_set_dai_tdm_slot,
670};
671EXPORT_SYMBOL_GPL(adau17x1_dai_ops);
672
673int adau17x1_set_micbias_voltage(struct snd_soc_codec *codec,
674 enum adau17x1_micbias_voltage micbias)
675{
676 struct adau *adau = snd_soc_codec_get_drvdata(codec);
677
678 switch (micbias) {
679 case ADAU17X1_MICBIAS_0_90_AVDD:
680 case ADAU17X1_MICBIAS_0_65_AVDD:
681 break;
682 default:
683 return -EINVAL;
684 }
685
686 return regmap_write(adau->regmap, ADAU17X1_MICBIAS, micbias << 2);
687}
688EXPORT_SYMBOL_GPL(adau17x1_set_micbias_voltage);
689
690bool adau17x1_readable_register(struct device *dev, unsigned int reg)
691{
692 switch (reg) {
693 case ADAU17X1_CLOCK_CONTROL:
694 case ADAU17X1_PLL_CONTROL:
695 case ADAU17X1_REC_POWER_MGMT:
696 case ADAU17X1_MICBIAS:
697 case ADAU17X1_SERIAL_PORT0:
698 case ADAU17X1_SERIAL_PORT1:
699 case ADAU17X1_CONVERTER0:
700 case ADAU17X1_CONVERTER1:
701 case ADAU17X1_LEFT_INPUT_DIGITAL_VOL:
702 case ADAU17X1_RIGHT_INPUT_DIGITAL_VOL:
703 case ADAU17X1_ADC_CONTROL:
704 case ADAU17X1_PLAY_POWER_MGMT:
705 case ADAU17X1_DAC_CONTROL0:
706 case ADAU17X1_DAC_CONTROL1:
707 case ADAU17X1_DAC_CONTROL2:
708 case ADAU17X1_SERIAL_PORT_PAD:
709 case ADAU17X1_CONTROL_PORT_PAD0:
710 case ADAU17X1_CONTROL_PORT_PAD1:
711 case ADAU17X1_DSP_SAMPLING_RATE:
712 case ADAU17X1_SERIAL_INPUT_ROUTE:
713 case ADAU17X1_SERIAL_OUTPUT_ROUTE:
714 case ADAU17X1_DSP_ENABLE:
715 case ADAU17X1_DSP_RUN:
716 case ADAU17X1_SERIAL_SAMPLING_RATE:
717 return true;
718 default:
719 break;
720 }
721 return false;
722}
723EXPORT_SYMBOL_GPL(adau17x1_readable_register);
724
725bool adau17x1_volatile_register(struct device *dev, unsigned int reg)
726{
727 /* SigmaDSP parameter and program memory */
728 if (reg < 0x4000)
729 return true;
730
731 switch (reg) {
732 /* The PLL register is 6 bytes long */
733 case ADAU17X1_PLL_CONTROL:
734 case ADAU17X1_PLL_CONTROL + 1:
735 case ADAU17X1_PLL_CONTROL + 2:
736 case ADAU17X1_PLL_CONTROL + 3:
737 case ADAU17X1_PLL_CONTROL + 4:
738 case ADAU17X1_PLL_CONTROL + 5:
739 return true;
740 default:
741 break;
742 }
743
744 return false;
745}
746EXPORT_SYMBOL_GPL(adau17x1_volatile_register);
747
748int adau17x1_load_firmware(struct adau *adau, struct device *dev,
749 const char *firmware)
750{
751 int ret;
752 int dspsr;
753
754 ret = regmap_read(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, &dspsr);
755 if (ret)
756 return ret;
757
758 regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 1);
759 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, 0xf);
760
761 ret = process_sigma_firmware_regmap(dev, adau->regmap, firmware);
762 if (ret) {
763 regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 0);
764 return ret;
765 }
766 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dspsr);
767
768 return 0;
769}
770EXPORT_SYMBOL_GPL(adau17x1_load_firmware);
771
772int adau17x1_add_widgets(struct snd_soc_codec *codec)
773{
774 struct adau *adau = snd_soc_codec_get_drvdata(codec);
775 int ret;
776
777 ret = snd_soc_add_codec_controls(codec, adau17x1_controls,
778 ARRAY_SIZE(adau17x1_controls));
779 if (ret)
780 return ret;
781 ret = snd_soc_dapm_new_controls(&codec->dapm, adau17x1_dapm_widgets,
782 ARRAY_SIZE(adau17x1_dapm_widgets));
783 if (ret)
784 return ret;
785
786 if (adau17x1_has_dsp(adau)) {
787 ret = snd_soc_dapm_new_controls(&codec->dapm,
788 adau17x1_dsp_dapm_widgets,
789 ARRAY_SIZE(adau17x1_dsp_dapm_widgets));
790 }
791 return ret;
792}
793EXPORT_SYMBOL_GPL(adau17x1_add_widgets);
794
795int adau17x1_add_routes(struct snd_soc_codec *codec)
796{
797 struct adau *adau = snd_soc_codec_get_drvdata(codec);
798 int ret;
799
800 ret = snd_soc_dapm_add_routes(&codec->dapm, adau17x1_dapm_routes,
801 ARRAY_SIZE(adau17x1_dapm_routes));
802 if (ret)
803 return ret;
804
805 if (adau17x1_has_dsp(adau)) {
806 ret = snd_soc_dapm_add_routes(&codec->dapm,
807 adau17x1_dsp_dapm_routes,
808 ARRAY_SIZE(adau17x1_dsp_dapm_routes));
809 } else {
810 ret = snd_soc_dapm_add_routes(&codec->dapm,
811 adau17x1_no_dsp_dapm_routes,
812 ARRAY_SIZE(adau17x1_no_dsp_dapm_routes));
813 }
814 return ret;
815}
816EXPORT_SYMBOL_GPL(adau17x1_add_routes);
817
818int adau17x1_suspend(struct snd_soc_codec *codec)
819{
820 codec->driver->set_bias_level(codec, SND_SOC_BIAS_OFF);
821 return 0;
822}
823EXPORT_SYMBOL_GPL(adau17x1_suspend);
824
825int adau17x1_resume(struct snd_soc_codec *codec)
826{
827 struct adau *adau = snd_soc_codec_get_drvdata(codec);
828
829 if (adau->switch_mode)
830 adau->switch_mode(codec->dev);
831
832 codec->driver->set_bias_level(codec, SND_SOC_BIAS_STANDBY);
833 regcache_sync(adau->regmap);
834
835 return 0;
836}
837EXPORT_SYMBOL_GPL(adau17x1_resume);
838
839int adau17x1_probe(struct device *dev, struct regmap *regmap,
840 enum adau17x1_type type, void (*switch_mode)(struct device *dev))
841{
842 struct adau *adau;
843
844 if (IS_ERR(regmap))
845 return PTR_ERR(regmap);
846
847 adau = devm_kzalloc(dev, sizeof(*adau), GFP_KERNEL);
848 if (!adau)
849 return -ENOMEM;
850
851 adau->regmap = regmap;
852 adau->switch_mode = switch_mode;
853 adau->type = type;
854
855 dev_set_drvdata(dev, adau);
856
857 if (switch_mode)
858 switch_mode(dev);
859
860 return 0;
861}
862EXPORT_SYMBOL_GPL(adau17x1_probe);
863
864MODULE_DESCRIPTION("ASoC ADAU1X61/ADAU1X81 common code");
865MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
866MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/adau17x1.h b/sound/soc/codecs/adau17x1.h
new file mode 100644
index 000000000000..3ffabaf4c7a8
--- /dev/null
+++ b/sound/soc/codecs/adau17x1.h
@@ -0,0 +1,124 @@
1#ifndef __ADAU17X1_H__
2#define __ADAU17X1_H__
3
4#include <linux/regmap.h>
5#include <linux/platform_data/adau17x1.h>
6
7enum adau17x1_type {
8 ADAU1361,
9 ADAU1761,
10 ADAU1381,
11 ADAU1781,
12};
13
14enum adau17x1_pll {
15 ADAU17X1_PLL,
16};
17
18enum adau17x1_pll_src {
19 ADAU17X1_PLL_SRC_MCLK,
20};
21
22enum adau17x1_clk_src {
23 ADAU17X1_CLK_SRC_MCLK,
24 ADAU17X1_CLK_SRC_PLL,
25};
26
27struct adau {
28 unsigned int sysclk;
29 unsigned int pll_freq;
30
31 enum adau17x1_clk_src clk_src;
32 enum adau17x1_type type;
33 void (*switch_mode)(struct device *dev);
34
35 unsigned int dai_fmt;
36
37 uint8_t pll_regs[6];
38
39 bool master;
40
41 unsigned int tdm_slot[2];
42 bool dsp_bypass[2];
43
44 struct regmap *regmap;
45};
46
47int adau17x1_add_widgets(struct snd_soc_codec *codec);
48int adau17x1_add_routes(struct snd_soc_codec *codec);
49int adau17x1_probe(struct device *dev, struct regmap *regmap,
50 enum adau17x1_type type, void (*switch_mode)(struct device *dev));
51int adau17x1_set_micbias_voltage(struct snd_soc_codec *codec,
52 enum adau17x1_micbias_voltage micbias);
53bool adau17x1_readable_register(struct device *dev, unsigned int reg);
54bool adau17x1_volatile_register(struct device *dev, unsigned int reg);
55int adau17x1_suspend(struct snd_soc_codec *codec);
56int adau17x1_resume(struct snd_soc_codec *codec);
57
58extern const struct snd_soc_dai_ops adau17x1_dai_ops;
59
60int adau17x1_load_firmware(struct adau *adau, struct device *dev,
61 const char *firmware);
62bool adau17x1_has_dsp(struct adau *adau);
63
64#define ADAU17X1_CLOCK_CONTROL 0x4000
65#define ADAU17X1_PLL_CONTROL 0x4002
66#define ADAU17X1_REC_POWER_MGMT 0x4009
67#define ADAU17X1_MICBIAS 0x4010
68#define ADAU17X1_SERIAL_PORT0 0x4015
69#define ADAU17X1_SERIAL_PORT1 0x4016
70#define ADAU17X1_CONVERTER0 0x4017
71#define ADAU17X1_CONVERTER1 0x4018
72#define ADAU17X1_LEFT_INPUT_DIGITAL_VOL 0x401a
73#define ADAU17X1_RIGHT_INPUT_DIGITAL_VOL 0x401b
74#define ADAU17X1_ADC_CONTROL 0x4019
75#define ADAU17X1_PLAY_POWER_MGMT 0x4029
76#define ADAU17X1_DAC_CONTROL0 0x402a
77#define ADAU17X1_DAC_CONTROL1 0x402b
78#define ADAU17X1_DAC_CONTROL2 0x402c
79#define ADAU17X1_SERIAL_PORT_PAD 0x402d
80#define ADAU17X1_CONTROL_PORT_PAD0 0x402f
81#define ADAU17X1_CONTROL_PORT_PAD1 0x4030
82#define ADAU17X1_DSP_SAMPLING_RATE 0x40eb
83#define ADAU17X1_SERIAL_INPUT_ROUTE 0x40f2
84#define ADAU17X1_SERIAL_OUTPUT_ROUTE 0x40f3
85#define ADAU17X1_DSP_ENABLE 0x40f5
86#define ADAU17X1_DSP_RUN 0x40f6
87#define ADAU17X1_SERIAL_SAMPLING_RATE 0x40f8
88
89#define ADAU17X1_SERIAL_PORT0_BCLK_POL BIT(4)
90#define ADAU17X1_SERIAL_PORT0_LRCLK_POL BIT(3)
91#define ADAU17X1_SERIAL_PORT0_MASTER BIT(0)
92
93#define ADAU17X1_SERIAL_PORT1_DELAY1 0x00
94#define ADAU17X1_SERIAL_PORT1_DELAY0 0x01
95#define ADAU17X1_SERIAL_PORT1_DELAY8 0x02
96#define ADAU17X1_SERIAL_PORT1_DELAY16 0x03
97#define ADAU17X1_SERIAL_PORT1_DELAY_MASK 0x03
98
99#define ADAU17X1_CLOCK_CONTROL_INFREQ_MASK 0x6
100#define ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL BIT(3)
101#define ADAU17X1_CLOCK_CONTROL_SYSCLK_EN BIT(0)
102
103#define ADAU17X1_SERIAL_PORT1_BCLK32 (0x0 << 5)
104#define ADAU17X1_SERIAL_PORT1_BCLK48 (0x1 << 5)
105#define ADAU17X1_SERIAL_PORT1_BCLK64 (0x2 << 5)
106#define ADAU17X1_SERIAL_PORT1_BCLK128 (0x3 << 5)
107#define ADAU17X1_SERIAL_PORT1_BCLK256 (0x4 << 5)
108#define ADAU17X1_SERIAL_PORT1_BCLK_MASK (0x7 << 5)
109
110#define ADAU17X1_SERIAL_PORT0_STEREO (0x0 << 1)
111#define ADAU17X1_SERIAL_PORT0_TDM4 (0x1 << 1)
112#define ADAU17X1_SERIAL_PORT0_TDM8 (0x2 << 1)
113#define ADAU17X1_SERIAL_PORT0_TDM_MASK (0x3 << 1)
114#define ADAU17X1_SERIAL_PORT0_PULSE_MODE BIT(5)
115
116#define ADAU17X1_CONVERTER0_DAC_PAIR(x) (((x) - 1) << 5)
117#define ADAU17X1_CONVERTER0_DAC_PAIR_MASK (0x3 << 5)
118#define ADAU17X1_CONVERTER1_ADC_PAIR(x) ((x) - 1)
119#define ADAU17X1_CONVERTER1_ADC_PAIR_MASK 0x3
120
121#define ADAU17X1_CONVERTER0_CONVSR_MASK 0x7
122
123
124#endif
diff --git a/sound/soc/codecs/adav80x.c b/sound/soc/codecs/adav80x.c
index 5062e34ee8dc..c43b93fdf0df 100644
--- a/sound/soc/codecs/adav80x.c
+++ b/sound/soc/codecs/adav80x.c
@@ -172,14 +172,14 @@ static ADAV80X_MUX_ENUM_DECL(adav80x_capture_enum, ADAV80X_DPATH_CTRL1, 3);
172static ADAV80X_MUX_ENUM_DECL(adav80x_dac_enum, ADAV80X_DPATH_CTRL2, 3); 172static ADAV80X_MUX_ENUM_DECL(adav80x_dac_enum, ADAV80X_DPATH_CTRL2, 3);
173 173
174static const struct snd_kcontrol_new adav80x_aux_capture_mux_ctrl = 174static const struct snd_kcontrol_new adav80x_aux_capture_mux_ctrl =
175 SOC_DAPM_VALUE_ENUM("Route", adav80x_aux_capture_enum); 175 SOC_DAPM_ENUM("Route", adav80x_aux_capture_enum);
176static const struct snd_kcontrol_new adav80x_capture_mux_ctrl = 176static const struct snd_kcontrol_new adav80x_capture_mux_ctrl =
177 SOC_DAPM_VALUE_ENUM("Route", adav80x_capture_enum); 177 SOC_DAPM_ENUM("Route", adav80x_capture_enum);
178static const struct snd_kcontrol_new adav80x_dac_mux_ctrl = 178static const struct snd_kcontrol_new adav80x_dac_mux_ctrl =
179 SOC_DAPM_VALUE_ENUM("Route", adav80x_dac_enum); 179 SOC_DAPM_ENUM("Route", adav80x_dac_enum);
180 180
181#define ADAV80X_MUX(name, ctrl) \ 181#define ADAV80X_MUX(name, ctrl) \
182 SND_SOC_DAPM_VALUE_MUX(name, SND_SOC_NOPM, 0, 0, ctrl) 182 SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
183 183
184static const struct snd_soc_dapm_widget adav80x_dapm_widgets[] = { 184static const struct snd_soc_dapm_widget adav80x_dapm_widgets[] = {
185 SND_SOC_DAPM_DAC("DAC", NULL, ADAV80X_DAC_CTRL1, 7, 1), 185 SND_SOC_DAPM_DAC("DAC", NULL, ADAV80X_DAC_CTRL1, 7, 1),
@@ -315,7 +315,7 @@ static int adav80x_set_deemph(struct snd_soc_codec *codec)
315static int adav80x_put_deemph(struct snd_kcontrol *kcontrol, 315static int adav80x_put_deemph(struct snd_kcontrol *kcontrol,
316 struct snd_ctl_elem_value *ucontrol) 316 struct snd_ctl_elem_value *ucontrol)
317{ 317{
318 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 318 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
319 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 319 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec);
320 unsigned int deemph = ucontrol->value.enumerated.item[0]; 320 unsigned int deemph = ucontrol->value.enumerated.item[0];
321 321
@@ -330,7 +330,7 @@ static int adav80x_put_deemph(struct snd_kcontrol *kcontrol,
330static int adav80x_get_deemph(struct snd_kcontrol *kcontrol, 330static int adav80x_get_deemph(struct snd_kcontrol *kcontrol,
331 struct snd_ctl_elem_value *ucontrol) 331 struct snd_ctl_elem_value *ucontrol)
332{ 332{
333 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 333 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
334 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 334 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec);
335 335
336 ucontrol->value.enumerated.item[0] = adav80x->deemph; 336 ucontrol->value.enumerated.item[0] = adav80x->deemph;
diff --git a/sound/soc/codecs/ak4104.c b/sound/soc/codecs/ak4104.c
index 10adf25d4c14..1fd7f72b2a62 100644
--- a/sound/soc/codecs/ak4104.c
+++ b/sound/soc/codecs/ak4104.c
@@ -11,13 +11,14 @@
11 11
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/slab.h> 13#include <linux/slab.h>
14#include <sound/core.h>
15#include <sound/soc.h>
16#include <sound/initval.h>
17#include <linux/spi/spi.h> 14#include <linux/spi/spi.h>
18#include <linux/of_device.h> 15#include <linux/of_device.h>
19#include <linux/of_gpio.h> 16#include <linux/of_gpio.h>
17#include <linux/regulator/consumer.h>
20#include <sound/asoundef.h> 18#include <sound/asoundef.h>
19#include <sound/core.h>
20#include <sound/soc.h>
21#include <sound/initval.h>
21 22
22/* AK4104 registers addresses */ 23/* AK4104 registers addresses */
23#define AK4104_REG_CONTROL1 0x00 24#define AK4104_REG_CONTROL1 0x00
@@ -47,6 +48,7 @@
47 48
48struct ak4104_private { 49struct ak4104_private {
49 struct regmap *regmap; 50 struct regmap *regmap;
51 struct regulator *regulator;
50}; 52};
51 53
52static const struct snd_soc_dapm_widget ak4104_dapm_widgets[] = { 54static const struct snd_soc_dapm_widget ak4104_dapm_widgets[] = {
@@ -174,20 +176,30 @@ static int ak4104_probe(struct snd_soc_codec *codec)
174 struct ak4104_private *ak4104 = snd_soc_codec_get_drvdata(codec); 176 struct ak4104_private *ak4104 = snd_soc_codec_get_drvdata(codec);
175 int ret; 177 int ret;
176 178
179 ret = regulator_enable(ak4104->regulator);
180 if (ret < 0) {
181 dev_err(codec->dev, "Unable to enable regulator: %d\n", ret);
182 return ret;
183 }
184
177 /* set power-up and non-reset bits */ 185 /* set power-up and non-reset bits */
178 ret = regmap_update_bits(ak4104->regmap, AK4104_REG_CONTROL1, 186 ret = regmap_update_bits(ak4104->regmap, AK4104_REG_CONTROL1,
179 AK4104_CONTROL1_PW | AK4104_CONTROL1_RSTN, 187 AK4104_CONTROL1_PW | AK4104_CONTROL1_RSTN,
180 AK4104_CONTROL1_PW | AK4104_CONTROL1_RSTN); 188 AK4104_CONTROL1_PW | AK4104_CONTROL1_RSTN);
181 if (ret < 0) 189 if (ret < 0)
182 return ret; 190 goto exit_disable_regulator;
183 191
184 /* enable transmitter */ 192 /* enable transmitter */
185 ret = regmap_update_bits(ak4104->regmap, AK4104_REG_TX, 193 ret = regmap_update_bits(ak4104->regmap, AK4104_REG_TX,
186 AK4104_TX_TXE, AK4104_TX_TXE); 194 AK4104_TX_TXE, AK4104_TX_TXE);
187 if (ret < 0) 195 if (ret < 0)
188 return ret; 196 goto exit_disable_regulator;
189 197
190 return 0; 198 return 0;
199
200exit_disable_regulator:
201 regulator_disable(ak4104->regulator);
202 return ret;
191} 203}
192 204
193static int ak4104_remove(struct snd_soc_codec *codec) 205static int ak4104_remove(struct snd_soc_codec *codec)
@@ -196,13 +208,42 @@ static int ak4104_remove(struct snd_soc_codec *codec)
196 208
197 regmap_update_bits(ak4104->regmap, AK4104_REG_CONTROL1, 209 regmap_update_bits(ak4104->regmap, AK4104_REG_CONTROL1,
198 AK4104_CONTROL1_PW | AK4104_CONTROL1_RSTN, 0); 210 AK4104_CONTROL1_PW | AK4104_CONTROL1_RSTN, 0);
211 regulator_disable(ak4104->regulator);
199 212
200 return 0; 213 return 0;
201} 214}
202 215
216#ifdef CONFIG_PM
217static int ak4104_soc_suspend(struct snd_soc_codec *codec)
218{
219 struct ak4104_private *priv = snd_soc_codec_get_drvdata(codec);
220
221 regulator_disable(priv->regulator);
222
223 return 0;
224}
225
226static int ak4104_soc_resume(struct snd_soc_codec *codec)
227{
228 struct ak4104_private *priv = snd_soc_codec_get_drvdata(codec);
229 int ret;
230
231 ret = regulator_enable(priv->regulator);
232 if (ret < 0)
233 return ret;
234
235 return 0;
236}
237#else
238#define ak4104_soc_suspend NULL
239#define ak4104_soc_resume NULL
240#endif /* CONFIG_PM */
241
203static struct snd_soc_codec_driver soc_codec_device_ak4104 = { 242static struct snd_soc_codec_driver soc_codec_device_ak4104 = {
204 .probe = ak4104_probe, 243 .probe = ak4104_probe,
205 .remove = ak4104_remove, 244 .remove = ak4104_remove,
245 .suspend = ak4104_soc_suspend,
246 .resume = ak4104_soc_resume,
206 247
207 .dapm_widgets = ak4104_dapm_widgets, 248 .dapm_widgets = ak4104_dapm_widgets,
208 .num_dapm_widgets = ARRAY_SIZE(ak4104_dapm_widgets), 249 .num_dapm_widgets = ARRAY_SIZE(ak4104_dapm_widgets),
@@ -239,6 +280,13 @@ static int ak4104_spi_probe(struct spi_device *spi)
239 if (ak4104 == NULL) 280 if (ak4104 == NULL)
240 return -ENOMEM; 281 return -ENOMEM;
241 282
283 ak4104->regulator = devm_regulator_get(&spi->dev, "vdd");
284 if (IS_ERR(ak4104->regulator)) {
285 ret = PTR_ERR(ak4104->regulator);
286 dev_err(&spi->dev, "Unable to get Vdd regulator: %d\n", ret);
287 return ret;
288 }
289
242 ak4104->regmap = devm_regmap_init_spi(spi, &ak4104_regmap); 290 ak4104->regmap = devm_regmap_init_spi(spi, &ak4104_regmap);
243 if (IS_ERR(ak4104->regmap)) { 291 if (IS_ERR(ak4104->regmap)) {
244 ret = PTR_ERR(ak4104->regmap); 292 ret = PTR_ERR(ak4104->regmap);
diff --git a/sound/soc/codecs/ak4641.c b/sound/soc/codecs/ak4641.c
index 868c0e2da1ec..7afe8f482088 100644
--- a/sound/soc/codecs/ak4641.c
+++ b/sound/soc/codecs/ak4641.c
@@ -74,7 +74,7 @@ static int ak4641_set_deemph(struct snd_soc_codec *codec)
74static int ak4641_put_deemph(struct snd_kcontrol *kcontrol, 74static int ak4641_put_deemph(struct snd_kcontrol *kcontrol,
75 struct snd_ctl_elem_value *ucontrol) 75 struct snd_ctl_elem_value *ucontrol)
76{ 76{
77 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 77 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
78 struct ak4641_priv *ak4641 = snd_soc_codec_get_drvdata(codec); 78 struct ak4641_priv *ak4641 = snd_soc_codec_get_drvdata(codec);
79 int deemph = ucontrol->value.enumerated.item[0]; 79 int deemph = ucontrol->value.enumerated.item[0];
80 80
@@ -89,7 +89,7 @@ static int ak4641_put_deemph(struct snd_kcontrol *kcontrol,
89static int ak4641_get_deemph(struct snd_kcontrol *kcontrol, 89static int ak4641_get_deemph(struct snd_kcontrol *kcontrol,
90 struct snd_ctl_elem_value *ucontrol) 90 struct snd_ctl_elem_value *ucontrol)
91{ 91{
92 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 92 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
93 struct ak4641_priv *ak4641 = snd_soc_codec_get_drvdata(codec); 93 struct ak4641_priv *ak4641 = snd_soc_codec_get_drvdata(codec);
94 94
95 ucontrol->value.enumerated.item[0] = ak4641->deemph; 95 ucontrol->value.enumerated.item[0] = ak4641->deemph;
diff --git a/sound/soc/codecs/ak4642.c b/sound/soc/codecs/ak4642.c
index 92655cc189ae..3ba4c0f11418 100644
--- a/sound/soc/codecs/ak4642.c
+++ b/sound/soc/codecs/ak4642.c
@@ -98,7 +98,7 @@
98#define MGAIN0 (1 << 0) /* MIC amp gain*/ 98#define MGAIN0 (1 << 0) /* MIC amp gain*/
99 99
100/* TIMER */ 100/* TIMER */
101#define ZTM(param) ((param & 0x3) << 4) /* ALC Zoro Crossing TimeOut */ 101#define ZTM(param) ((param & 0x3) << 4) /* ALC Zero Crossing TimeOut */
102#define WTM(param) (((param & 0x4) << 4) | ((param & 0x3) << 2)) 102#define WTM(param) (((param & 0x4) << 4) | ((param & 0x3) << 2))
103 103
104/* ALC_CTL1 */ 104/* ALC_CTL1 */
@@ -134,6 +134,15 @@
134/* MD_CTL4 */ 134/* MD_CTL4 */
135#define DACH (1 << 0) 135#define DACH (1 << 0)
136 136
137struct ak4642_drvdata {
138 const struct regmap_config *regmap_config;
139 int extended_frequencies;
140};
141
142struct ak4642_priv {
143 const struct ak4642_drvdata *drvdata;
144};
145
137/* 146/*
138 * Playback Volume (table 39) 147 * Playback Volume (table 39)
139 * 148 *
@@ -148,6 +157,8 @@ static const struct snd_kcontrol_new ak4642_snd_controls[] = {
148 157
149 SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC, 158 SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
150 0, 0xFF, 1, out_tlv), 159 0, 0xFF, 1, out_tlv),
160 SOC_SINGLE("ALC Capture Switch", ALC_CTL1, 5, 1, 0),
161 SOC_SINGLE("ALC Capture ZC Switch", ALC_CTL1, 4, 1, 1),
151}; 162};
152 163
153static const struct snd_kcontrol_new ak4642_headphone_control = 164static const struct snd_kcontrol_new ak4642_headphone_control =
@@ -287,7 +298,9 @@ static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
287 int clk_id, unsigned int freq, int dir) 298 int clk_id, unsigned int freq, int dir)
288{ 299{
289 struct snd_soc_codec *codec = codec_dai->codec; 300 struct snd_soc_codec *codec = codec_dai->codec;
301 struct ak4642_priv *priv = snd_soc_codec_get_drvdata(codec);
290 u8 pll; 302 u8 pll;
303 int extended_freq = 0;
291 304
292 switch (freq) { 305 switch (freq) {
293 case 11289600: 306 case 11289600:
@@ -308,9 +321,25 @@ static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
308 case 27000000: 321 case 27000000:
309 pll = PLL3 | PLL2 | PLL0; 322 pll = PLL3 | PLL2 | PLL0;
310 break; 323 break;
324 case 19200000:
325 pll = PLL3;
326 extended_freq = 1;
327 break;
328 case 13000000:
329 pll = PLL3 | PLL2 | PLL1;
330 extended_freq = 1;
331 break;
332 case 26000000:
333 pll = PLL3 | PLL2 | PLL1 | PLL0;
334 extended_freq = 1;
335 break;
311 default: 336 default:
312 return -EINVAL; 337 return -EINVAL;
313 } 338 }
339
340 if (extended_freq && !priv->drvdata->extended_frequencies)
341 return -EINVAL;
342
314 snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll); 343 snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll);
315 344
316 return 0; 345 return 0;
@@ -505,30 +534,52 @@ static const struct regmap_config ak4648_regmap = {
505 .num_reg_defaults = ARRAY_SIZE(ak4648_reg), 534 .num_reg_defaults = ARRAY_SIZE(ak4648_reg),
506}; 535};
507 536
537static const struct ak4642_drvdata ak4642_drvdata = {
538 .regmap_config = &ak4642_regmap,
539};
540
541static const struct ak4642_drvdata ak4643_drvdata = {
542 .regmap_config = &ak4642_regmap,
543};
544
545static const struct ak4642_drvdata ak4648_drvdata = {
546 .regmap_config = &ak4648_regmap,
547 .extended_frequencies = 1,
548};
549
508static struct of_device_id ak4642_of_match[]; 550static struct of_device_id ak4642_of_match[];
509static int ak4642_i2c_probe(struct i2c_client *i2c, 551static int ak4642_i2c_probe(struct i2c_client *i2c,
510 const struct i2c_device_id *id) 552 const struct i2c_device_id *id)
511{ 553{
512 struct device_node *np = i2c->dev.of_node; 554 struct device_node *np = i2c->dev.of_node;
513 const struct regmap_config *regmap_config = NULL; 555 const struct ak4642_drvdata *drvdata = NULL;
514 struct regmap *regmap; 556 struct regmap *regmap;
557 struct ak4642_priv *priv;
515 558
516 if (np) { 559 if (np) {
517 const struct of_device_id *of_id; 560 const struct of_device_id *of_id;
518 561
519 of_id = of_match_device(ak4642_of_match, &i2c->dev); 562 of_id = of_match_device(ak4642_of_match, &i2c->dev);
520 if (of_id) 563 if (of_id)
521 regmap_config = of_id->data; 564 drvdata = of_id->data;
522 } else { 565 } else {
523 regmap_config = (const struct regmap_config *)id->driver_data; 566 drvdata = (const struct ak4642_drvdata *)id->driver_data;
524 } 567 }
525 568
526 if (!regmap_config) { 569 if (!drvdata) {
527 dev_err(&i2c->dev, "Unknown device type\n"); 570 dev_err(&i2c->dev, "Unknown device type\n");
528 return -EINVAL; 571 return -EINVAL;
529 } 572 }
530 573
531 regmap = devm_regmap_init_i2c(i2c, regmap_config); 574 priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
575 if (!priv)
576 return -ENOMEM;
577
578 priv->drvdata = drvdata;
579
580 i2c_set_clientdata(i2c, priv);
581
582 regmap = devm_regmap_init_i2c(i2c, drvdata->regmap_config);
532 if (IS_ERR(regmap)) 583 if (IS_ERR(regmap))
533 return PTR_ERR(regmap); 584 return PTR_ERR(regmap);
534 585
@@ -543,17 +594,17 @@ static int ak4642_i2c_remove(struct i2c_client *client)
543} 594}
544 595
545static struct of_device_id ak4642_of_match[] = { 596static struct of_device_id ak4642_of_match[] = {
546 { .compatible = "asahi-kasei,ak4642", .data = &ak4642_regmap}, 597 { .compatible = "asahi-kasei,ak4642", .data = &ak4642_drvdata},
547 { .compatible = "asahi-kasei,ak4643", .data = &ak4642_regmap}, 598 { .compatible = "asahi-kasei,ak4643", .data = &ak4643_drvdata},
548 { .compatible = "asahi-kasei,ak4648", .data = &ak4648_regmap}, 599 { .compatible = "asahi-kasei,ak4648", .data = &ak4648_drvdata},
549 {}, 600 {},
550}; 601};
551MODULE_DEVICE_TABLE(of, ak4642_of_match); 602MODULE_DEVICE_TABLE(of, ak4642_of_match);
552 603
553static const struct i2c_device_id ak4642_i2c_id[] = { 604static const struct i2c_device_id ak4642_i2c_id[] = {
554 { "ak4642", (kernel_ulong_t)&ak4642_regmap }, 605 { "ak4642", (kernel_ulong_t)&ak4642_drvdata },
555 { "ak4643", (kernel_ulong_t)&ak4642_regmap }, 606 { "ak4643", (kernel_ulong_t)&ak4643_drvdata },
556 { "ak4648", (kernel_ulong_t)&ak4648_regmap }, 607 { "ak4648", (kernel_ulong_t)&ak4648_drvdata },
557 { } 608 { }
558}; 609};
559MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id); 610MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);
diff --git a/sound/soc/codecs/alc5623.c b/sound/soc/codecs/alc5623.c
index f500905e9373..9d0755aa1d16 100644
--- a/sound/soc/codecs/alc5623.c
+++ b/sound/soc/codecs/alc5623.c
@@ -23,6 +23,7 @@
23#include <linux/i2c.h> 23#include <linux/i2c.h>
24#include <linux/regmap.h> 24#include <linux/regmap.h>
25#include <linux/slab.h> 25#include <linux/slab.h>
26#include <linux/of.h>
26#include <sound/core.h> 27#include <sound/core.h>
27#include <sound/pcm.h> 28#include <sound/pcm.h>
28#include <sound/pcm_params.h> 29#include <sound/pcm_params.h>
@@ -998,8 +999,10 @@ static int alc5623_i2c_probe(struct i2c_client *client,
998{ 999{
999 struct alc5623_platform_data *pdata; 1000 struct alc5623_platform_data *pdata;
1000 struct alc5623_priv *alc5623; 1001 struct alc5623_priv *alc5623;
1002 struct device_node *np;
1001 unsigned int vid1, vid2; 1003 unsigned int vid1, vid2;
1002 int ret; 1004 int ret;
1005 u32 val32;
1003 1006
1004 alc5623 = devm_kzalloc(&client->dev, sizeof(struct alc5623_priv), 1007 alc5623 = devm_kzalloc(&client->dev, sizeof(struct alc5623_priv),
1005 GFP_KERNEL); 1008 GFP_KERNEL);
@@ -1018,13 +1021,13 @@ static int alc5623_i2c_probe(struct i2c_client *client,
1018 dev_err(&client->dev, "failed to read vendor ID1: %d\n", ret); 1021 dev_err(&client->dev, "failed to read vendor ID1: %d\n", ret);
1019 return ret; 1022 return ret;
1020 } 1023 }
1021 vid1 = ((vid1 & 0xff) << 8) | (vid1 >> 8);
1022 1024
1023 ret = regmap_read(alc5623->regmap, ALC5623_VENDOR_ID2, &vid2); 1025 ret = regmap_read(alc5623->regmap, ALC5623_VENDOR_ID2, &vid2);
1024 if (ret < 0) { 1026 if (ret < 0) {
1025 dev_err(&client->dev, "failed to read vendor ID2: %d\n", ret); 1027 dev_err(&client->dev, "failed to read vendor ID2: %d\n", ret);
1026 return ret; 1028 return ret;
1027 } 1029 }
1030 vid2 >>= 8;
1028 1031
1029 if ((vid1 != 0x10ec) || (vid2 != id->driver_data)) { 1032 if ((vid1 != 0x10ec) || (vid2 != id->driver_data)) {
1030 dev_err(&client->dev, "unknown or wrong codec\n"); 1033 dev_err(&client->dev, "unknown or wrong codec\n");
@@ -1040,6 +1043,16 @@ static int alc5623_i2c_probe(struct i2c_client *client,
1040 if (pdata) { 1043 if (pdata) {
1041 alc5623->add_ctrl = pdata->add_ctrl; 1044 alc5623->add_ctrl = pdata->add_ctrl;
1042 alc5623->jack_det_ctrl = pdata->jack_det_ctrl; 1045 alc5623->jack_det_ctrl = pdata->jack_det_ctrl;
1046 } else {
1047 if (client->dev.of_node) {
1048 np = client->dev.of_node;
1049 ret = of_property_read_u32(np, "add-ctrl", &val32);
1050 if (!ret)
1051 alc5623->add_ctrl = val32;
1052 ret = of_property_read_u32(np, "jack-det-ctrl", &val32);
1053 if (!ret)
1054 alc5623->jack_det_ctrl = val32;
1055 }
1043 } 1056 }
1044 1057
1045 alc5623->id = vid2; 1058 alc5623->id = vid2;
@@ -1081,11 +1094,18 @@ static const struct i2c_device_id alc5623_i2c_table[] = {
1081}; 1094};
1082MODULE_DEVICE_TABLE(i2c, alc5623_i2c_table); 1095MODULE_DEVICE_TABLE(i2c, alc5623_i2c_table);
1083 1096
1097static const struct of_device_id alc5623_of_match[] = {
1098 { .compatible = "realtek,alc5623", },
1099 { }
1100};
1101MODULE_DEVICE_TABLE(of, alc5623_of_match);
1102
1084/* i2c codec control layer */ 1103/* i2c codec control layer */
1085static struct i2c_driver alc5623_i2c_driver = { 1104static struct i2c_driver alc5623_i2c_driver = {
1086 .driver = { 1105 .driver = {
1087 .name = "alc562x-codec", 1106 .name = "alc562x-codec",
1088 .owner = THIS_MODULE, 1107 .owner = THIS_MODULE,
1108 .of_match_table = of_match_ptr(alc5623_of_match),
1089 }, 1109 },
1090 .probe = alc5623_i2c_probe, 1110 .probe = alc5623_i2c_probe,
1091 .remove = alc5623_i2c_remove, 1111 .remove = alc5623_i2c_remove,
diff --git a/sound/soc/codecs/arizona.h b/sound/soc/codecs/arizona.h
index 16df0f913353..05ae17f5bca3 100644
--- a/sound/soc/codecs/arizona.h
+++ b/sound/soc/codecs/arizona.h
@@ -107,7 +107,7 @@ extern int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS];
107 107
108#define ARIZONA_MUX_CTL_DECL(name) \ 108#define ARIZONA_MUX_CTL_DECL(name) \
109 const struct snd_kcontrol_new name##_mux = \ 109 const struct snd_kcontrol_new name##_mux = \
110 SOC_DAPM_VALUE_ENUM("Route", name##_enum) 110 SOC_DAPM_ENUM("Route", name##_enum)
111 111
112#define ARIZONA_MUX_ENUMS(name, base_reg) \ 112#define ARIZONA_MUX_ENUMS(name, base_reg) \
113 static ARIZONA_MUX_ENUM_DECL(name##_enum, base_reg); \ 113 static ARIZONA_MUX_ENUM_DECL(name##_enum, base_reg); \
@@ -128,7 +128,7 @@ extern int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS];
128 ARIZONA_MUX_ENUMS(name##_aux6, base_reg + 40) 128 ARIZONA_MUX_ENUMS(name##_aux6, base_reg + 40)
129 129
130#define ARIZONA_MUX(name, ctrl) \ 130#define ARIZONA_MUX(name, ctrl) \
131 SND_SOC_DAPM_VALUE_MUX(name, SND_SOC_NOPM, 0, 0, ctrl) 131 SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
132 132
133#define ARIZONA_MUX_WIDGETS(name, name_str) \ 133#define ARIZONA_MUX_WIDGETS(name, name_str) \
134 ARIZONA_MUX(name_str " Input", &name##_mux) 134 ARIZONA_MUX(name_str " Input", &name##_mux)
diff --git a/sound/soc/codecs/cq93vc.c b/sound/soc/codecs/cq93vc.c
index 1e25c7af853b..537327c7f7f1 100644
--- a/sound/soc/codecs/cq93vc.c
+++ b/sound/soc/codecs/cq93vc.c
@@ -139,8 +139,6 @@ static int cq93vc_probe(struct snd_soc_codec *codec)
139 139
140 davinci_vc->cq93vc.codec = codec; 140 davinci_vc->cq93vc.codec = codec;
141 141
142 snd_soc_codec_set_cache_io(codec, davinci_vc->regmap);
143
144 /* Off, with power on */ 142 /* Off, with power on */
145 cq93vc_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 143 cq93vc_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
146 144
@@ -154,11 +152,19 @@ static int cq93vc_remove(struct snd_soc_codec *codec)
154 return 0; 152 return 0;
155} 153}
156 154
155static struct regmap *cq93vc_get_regmap(struct device *dev)
156{
157 struct davinci_vc *davinci_vc = dev->platform_data;
158
159 return davinci_vc->regmap;
160}
161
157static struct snd_soc_codec_driver soc_codec_dev_cq93vc = { 162static struct snd_soc_codec_driver soc_codec_dev_cq93vc = {
158 .set_bias_level = cq93vc_set_bias_level, 163 .set_bias_level = cq93vc_set_bias_level,
159 .probe = cq93vc_probe, 164 .probe = cq93vc_probe,
160 .remove = cq93vc_remove, 165 .remove = cq93vc_remove,
161 .resume = cq93vc_resume, 166 .resume = cq93vc_resume,
167 .get_regmap = cq93vc_get_regmap,
162 .controls = cq93vc_snd_controls, 168 .controls = cq93vc_snd_controls,
163 .num_controls = ARRAY_SIZE(cq93vc_snd_controls), 169 .num_controls = ARRAY_SIZE(cq93vc_snd_controls),
164}; 170};
diff --git a/sound/soc/codecs/cs4270.c b/sound/soc/codecs/cs4270.c
index 3920e6264948..9947a9583679 100644
--- a/sound/soc/codecs/cs4270.c
+++ b/sound/soc/codecs/cs4270.c
@@ -438,7 +438,7 @@ static int cs4270_dai_mute(struct snd_soc_dai *dai, int mute)
438static int cs4270_soc_put_mute(struct snd_kcontrol *kcontrol, 438static int cs4270_soc_put_mute(struct snd_kcontrol *kcontrol,
439 struct snd_ctl_elem_value *ucontrol) 439 struct snd_ctl_elem_value *ucontrol)
440{ 440{
441 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 441 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
442 struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec); 442 struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec);
443 int left = !ucontrol->value.integer.value[0]; 443 int left = !ucontrol->value.integer.value[0];
444 int right = !ucontrol->value.integer.value[1]; 444 int right = !ucontrol->value.integer.value[1];
diff --git a/sound/soc/codecs/cs4271.c b/sound/soc/codecs/cs4271.c
index aef4965750c7..93cec52f4733 100644
--- a/sound/soc/codecs/cs4271.c
+++ b/sound/soc/codecs/cs4271.c
@@ -284,7 +284,7 @@ static int cs4271_set_deemph(struct snd_soc_codec *codec)
284static int cs4271_get_deemph(struct snd_kcontrol *kcontrol, 284static int cs4271_get_deemph(struct snd_kcontrol *kcontrol,
285 struct snd_ctl_elem_value *ucontrol) 285 struct snd_ctl_elem_value *ucontrol)
286{ 286{
287 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 287 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
288 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 288 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
289 289
290 ucontrol->value.enumerated.item[0] = cs4271->deemph; 290 ucontrol->value.enumerated.item[0] = cs4271->deemph;
@@ -294,7 +294,7 @@ static int cs4271_get_deemph(struct snd_kcontrol *kcontrol,
294static int cs4271_put_deemph(struct snd_kcontrol *kcontrol, 294static int cs4271_put_deemph(struct snd_kcontrol *kcontrol,
295 struct snd_ctl_elem_value *ucontrol) 295 struct snd_ctl_elem_value *ucontrol)
296{ 296{
297 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 297 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
298 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 298 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
299 299
300 cs4271->deemph = ucontrol->value.enumerated.item[0]; 300 cs4271->deemph = ucontrol->value.enumerated.item[0];
diff --git a/sound/soc/codecs/cs42l51-i2c.c b/sound/soc/codecs/cs42l51-i2c.c
new file mode 100644
index 000000000000..cee51ae177c1
--- /dev/null
+++ b/sound/soc/codecs/cs42l51-i2c.c
@@ -0,0 +1,59 @@
1/*
2 * cs42l56.c -- CS42L51 ALSA SoC I2C audio driver
3 *
4 * Copyright 2014 CirrusLogic, Inc.
5 *
6 * Author: Brian Austin <brian.austin@cirrus.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <linux/i2c.h>
15#include <linux/module.h>
16#include <sound/soc.h>
17
18#include "cs42l51.h"
19
20static struct i2c_device_id cs42l51_i2c_id[] = {
21 {"cs42l51", 0},
22 {}
23};
24MODULE_DEVICE_TABLE(i2c, cs42l51_i2c_id);
25
26static int cs42l51_i2c_probe(struct i2c_client *i2c,
27 const struct i2c_device_id *id)
28{
29 struct regmap_config config;
30
31 config = cs42l51_regmap;
32 config.val_bits = 8;
33 config.reg_bits = 8;
34
35 return cs42l51_probe(&i2c->dev, devm_regmap_init_i2c(i2c, &config));
36}
37
38static int cs42l51_i2c_remove(struct i2c_client *i2c)
39{
40 snd_soc_unregister_codec(&i2c->dev);
41
42 return 0;
43}
44
45static struct i2c_driver cs42l51_i2c_driver = {
46 .driver = {
47 .name = "cs42l51",
48 .owner = THIS_MODULE,
49 },
50 .probe = cs42l51_i2c_probe,
51 .remove = cs42l51_i2c_remove,
52 .id_table = cs42l51_i2c_id,
53};
54
55module_i2c_driver(cs42l51_i2c_driver);
56
57MODULE_DESCRIPTION("ASoC CS42L51 I2C Driver");
58MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
59MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/cs42l51.c b/sound/soc/codecs/cs42l51.c
index 6c0da2baa154..09488d97de60 100644
--- a/sound/soc/codecs/cs42l51.c
+++ b/sound/soc/codecs/cs42l51.c
@@ -29,7 +29,6 @@
29#include <sound/initval.h> 29#include <sound/initval.h>
30#include <sound/pcm_params.h> 30#include <sound/pcm_params.h>
31#include <sound/pcm.h> 31#include <sound/pcm.h>
32#include <linux/i2c.h>
33#include <linux/regmap.h> 32#include <linux/regmap.h>
34 33
35#include "cs42l51.h" 34#include "cs42l51.h"
@@ -55,7 +54,7 @@ struct cs42l51_private {
55static int cs42l51_get_chan_mix(struct snd_kcontrol *kcontrol, 54static int cs42l51_get_chan_mix(struct snd_kcontrol *kcontrol,
56 struct snd_ctl_elem_value *ucontrol) 55 struct snd_ctl_elem_value *ucontrol)
57{ 56{
58 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 57 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
59 unsigned long value = snd_soc_read(codec, CS42L51_PCM_MIXER)&3; 58 unsigned long value = snd_soc_read(codec, CS42L51_PCM_MIXER)&3;
60 59
61 switch (value) { 60 switch (value) {
@@ -83,7 +82,7 @@ static int cs42l51_get_chan_mix(struct snd_kcontrol *kcontrol,
83static int cs42l51_set_chan_mix(struct snd_kcontrol *kcontrol, 82static int cs42l51_set_chan_mix(struct snd_kcontrol *kcontrol,
84 struct snd_ctl_elem_value *ucontrol) 83 struct snd_ctl_elem_value *ucontrol)
85{ 84{
86 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 85 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
87 unsigned char val; 86 unsigned char val;
88 87
89 switch (ucontrol->value.integer.value[0]) { 88 switch (ucontrol->value.integer.value[0]) {
@@ -483,7 +482,7 @@ static struct snd_soc_dai_driver cs42l51_dai = {
483 .ops = &cs42l51_dai_ops, 482 .ops = &cs42l51_dai_ops,
484}; 483};
485 484
486static int cs42l51_probe(struct snd_soc_codec *codec) 485static int cs42l51_codec_probe(struct snd_soc_codec *codec)
487{ 486{
488 int ret, reg; 487 int ret, reg;
489 488
@@ -504,7 +503,7 @@ static int cs42l51_probe(struct snd_soc_codec *codec)
504} 503}
505 504
506static struct snd_soc_codec_driver soc_codec_device_cs42l51 = { 505static struct snd_soc_codec_driver soc_codec_device_cs42l51 = {
507 .probe = cs42l51_probe, 506 .probe = cs42l51_codec_probe,
508 507
509 .controls = cs42l51_snd_controls, 508 .controls = cs42l51_snd_controls,
510 .num_controls = ARRAY_SIZE(cs42l51_snd_controls), 509 .num_controls = ARRAY_SIZE(cs42l51_snd_controls),
@@ -514,91 +513,56 @@ static struct snd_soc_codec_driver soc_codec_device_cs42l51 = {
514 .num_dapm_routes = ARRAY_SIZE(cs42l51_routes), 513 .num_dapm_routes = ARRAY_SIZE(cs42l51_routes),
515}; 514};
516 515
517static const struct regmap_config cs42l51_regmap = { 516const struct regmap_config cs42l51_regmap = {
518 .reg_bits = 8,
519 .val_bits = 8,
520
521 .max_register = CS42L51_CHARGE_FREQ, 517 .max_register = CS42L51_CHARGE_FREQ,
522 .cache_type = REGCACHE_RBTREE, 518 .cache_type = REGCACHE_RBTREE,
523}; 519};
520EXPORT_SYMBOL_GPL(cs42l51_regmap);
524 521
525static int cs42l51_i2c_probe(struct i2c_client *i2c_client, 522int cs42l51_probe(struct device *dev, struct regmap *regmap)
526 const struct i2c_device_id *id)
527{ 523{
528 struct cs42l51_private *cs42l51; 524 struct cs42l51_private *cs42l51;
529 struct regmap *regmap;
530 unsigned int val; 525 unsigned int val;
531 int ret; 526 int ret;
532 527
533 regmap = devm_regmap_init_i2c(i2c_client, &cs42l51_regmap); 528 if (IS_ERR(regmap))
534 if (IS_ERR(regmap)) { 529 return PTR_ERR(regmap);
535 ret = PTR_ERR(regmap); 530
536 dev_err(&i2c_client->dev, "Failed to create regmap: %d\n", 531 cs42l51 = devm_kzalloc(dev, sizeof(struct cs42l51_private),
537 ret); 532 GFP_KERNEL);
538 return ret; 533 if (!cs42l51)
539 } 534 return -ENOMEM;
535
536 dev_set_drvdata(dev, cs42l51);
540 537
541 /* Verify that we have a CS42L51 */ 538 /* Verify that we have a CS42L51 */
542 ret = regmap_read(regmap, CS42L51_CHIP_REV_ID, &val); 539 ret = regmap_read(regmap, CS42L51_CHIP_REV_ID, &val);
543 if (ret < 0) { 540 if (ret < 0) {
544 dev_err(&i2c_client->dev, "failed to read I2C\n"); 541 dev_err(dev, "failed to read I2C\n");
545 goto error; 542 goto error;
546 } 543 }
547 544
548 if ((val != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_A)) && 545 if ((val != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_A)) &&
549 (val != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_B))) { 546 (val != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_B))) {
550 dev_err(&i2c_client->dev, "Invalid chip id: %x\n", val); 547 dev_err(dev, "Invalid chip id: %x\n", val);
551 ret = -ENODEV; 548 ret = -ENODEV;
552 goto error; 549 goto error;
553 } 550 }
551 dev_info(dev, "Cirrus Logic CS42L51, Revision: %02X\n",
552 val & CS42L51_CHIP_REV_MASK);
554 553
555 dev_info(&i2c_client->dev, "found device cs42l51 rev %d\n", 554 ret = snd_soc_register_codec(dev,
556 val & 7);
557
558 cs42l51 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l51_private),
559 GFP_KERNEL);
560 if (!cs42l51)
561 return -ENOMEM;
562
563 i2c_set_clientdata(i2c_client, cs42l51);
564
565 ret = snd_soc_register_codec(&i2c_client->dev,
566 &soc_codec_device_cs42l51, &cs42l51_dai, 1); 555 &soc_codec_device_cs42l51, &cs42l51_dai, 1);
567error: 556error:
568 return ret; 557 return ret;
569} 558}
570 559EXPORT_SYMBOL_GPL(cs42l51_probe);
571static int cs42l51_i2c_remove(struct i2c_client *client)
572{
573 snd_soc_unregister_codec(&client->dev);
574 return 0;
575}
576
577static const struct i2c_device_id cs42l51_id[] = {
578 {"cs42l51", 0},
579 {}
580};
581MODULE_DEVICE_TABLE(i2c, cs42l51_id);
582 560
583static const struct of_device_id cs42l51_of_match[] = { 561static const struct of_device_id cs42l51_of_match[] = {
584 { .compatible = "cirrus,cs42l51", }, 562 { .compatible = "cirrus,cs42l51", },
585 { } 563 { }
586}; 564};
587MODULE_DEVICE_TABLE(of, cs42l51_of_match); 565MODULE_DEVICE_TABLE(of, cs42l51_of_match);
588
589static struct i2c_driver cs42l51_i2c_driver = {
590 .driver = {
591 .name = "cs42l51-codec",
592 .owner = THIS_MODULE,
593 .of_match_table = cs42l51_of_match,
594 },
595 .id_table = cs42l51_id,
596 .probe = cs42l51_i2c_probe,
597 .remove = cs42l51_i2c_remove,
598};
599
600module_i2c_driver(cs42l51_i2c_driver);
601
602MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>"); 566MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
603MODULE_DESCRIPTION("Cirrus Logic CS42L51 ALSA SoC Codec Driver"); 567MODULE_DESCRIPTION("Cirrus Logic CS42L51 ALSA SoC Codec Driver");
604MODULE_LICENSE("GPL"); 568MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/cs42l51.h b/sound/soc/codecs/cs42l51.h
index 2beeb171db4b..8c55bf384bc6 100644
--- a/sound/soc/codecs/cs42l51.h
+++ b/sound/soc/codecs/cs42l51.h
@@ -18,9 +18,15 @@
18#ifndef _CS42L51_H 18#ifndef _CS42L51_H
19#define _CS42L51_H 19#define _CS42L51_H
20 20
21struct device;
22
23extern const struct regmap_config cs42l51_regmap;
24int cs42l51_probe(struct device *dev, struct regmap *regmap);
25
21#define CS42L51_CHIP_ID 0x1B 26#define CS42L51_CHIP_ID 0x1B
22#define CS42L51_CHIP_REV_A 0x00 27#define CS42L51_CHIP_REV_A 0x00
23#define CS42L51_CHIP_REV_B 0x01 28#define CS42L51_CHIP_REV_B 0x01
29#define CS42L51_CHIP_REV_MASK 0x07
24 30
25#define CS42L51_CHIP_REV_ID 0x01 31#define CS42L51_CHIP_REV_ID 0x01
26#define CS42L51_MK_CHIP_REV(a, b) ((a)<<3|(b)) 32#define CS42L51_MK_CHIP_REV(a, b) ((a)<<3|(b))
diff --git a/sound/soc/codecs/cs42l52.c b/sound/soc/codecs/cs42l52.c
index 460d35547a68..071fc77f2f06 100644
--- a/sound/soc/codecs/cs42l52.c
+++ b/sound/soc/codecs/cs42l52.c
@@ -50,11 +50,9 @@ struct cs42l52_private {
50 u8 mclksel; 50 u8 mclksel;
51 u32 mclk; 51 u32 mclk;
52 u8 flags; 52 u8 flags;
53#if IS_ENABLED(CONFIG_INPUT)
54 struct input_dev *beep; 53 struct input_dev *beep;
55 struct work_struct beep_work; 54 struct work_struct beep_work;
56 int beep_rate; 55 int beep_rate;
57#endif
58}; 56};
59 57
60static const struct reg_default cs42l52_reg_defaults[] = { 58static const struct reg_default cs42l52_reg_defaults[] = {
@@ -962,7 +960,6 @@ static int cs42l52_resume(struct snd_soc_codec *codec)
962 return 0; 960 return 0;
963} 961}
964 962
965#if IS_ENABLED(CONFIG_INPUT)
966static int beep_rates[] = { 963static int beep_rates[] = {
967 261, 522, 585, 667, 706, 774, 889, 1000, 964 261, 522, 585, 667, 706, 774, 889, 1000,
968 1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182 965 1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182
@@ -1096,15 +1093,6 @@ static void cs42l52_free_beep(struct snd_soc_codec *codec)
1096 snd_soc_update_bits(codec, CS42L52_BEEP_TONE_CTL, 1093 snd_soc_update_bits(codec, CS42L52_BEEP_TONE_CTL,
1097 CS42L52_BEEP_EN_MASK, 0); 1094 CS42L52_BEEP_EN_MASK, 0);
1098} 1095}
1099#else
1100static void cs42l52_init_beep(struct snd_soc_codec *codec)
1101{
1102}
1103
1104static void cs42l52_free_beep(struct snd_soc_codec *codec)
1105{
1106}
1107#endif
1108 1096
1109static int cs42l52_probe(struct snd_soc_codec *codec) 1097static int cs42l52_probe(struct snd_soc_codec *codec)
1110{ 1098{
@@ -1229,8 +1217,10 @@ static int cs42l52_i2c_probe(struct i2c_client *i2c_client,
1229 } 1217 }
1230 1218
1231 if (cs42l52->pdata.reset_gpio) { 1219 if (cs42l52->pdata.reset_gpio) {
1232 ret = gpio_request_one(cs42l52->pdata.reset_gpio, 1220 ret = devm_gpio_request_one(&i2c_client->dev,
1233 GPIOF_OUT_INIT_HIGH, "CS42L52 /RST"); 1221 cs42l52->pdata.reset_gpio,
1222 GPIOF_OUT_INIT_HIGH,
1223 "CS42L52 /RST");
1234 if (ret < 0) { 1224 if (ret < 0) {
1235 dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n", 1225 dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n",
1236 cs42l52->pdata.reset_gpio, ret); 1226 cs42l52->pdata.reset_gpio, ret);
diff --git a/sound/soc/codecs/cs42l56.c b/sound/soc/codecs/cs42l56.c
new file mode 100644
index 000000000000..fdc4bd27b0df
--- /dev/null
+++ b/sound/soc/codecs/cs42l56.c
@@ -0,0 +1,1419 @@
1/*
2 * cs42l56.c -- CS42L56 ALSA SoC audio driver
3 *
4 * Copyright 2014 CirrusLogic, Inc.
5 *
6 * Author: Brian Austin <brian.austin@cirrus.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
21#include <linux/input.h>
22#include <linux/regmap.h>
23#include <linux/slab.h>
24#include <linux/workqueue.h>
25#include <linux/platform_device.h>
26#include <linux/regulator/consumer.h>
27#include <linux/of_device.h>
28#include <linux/of_gpio.h>
29#include <sound/core.h>
30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/soc.h>
33#include <sound/soc-dapm.h>
34#include <sound/initval.h>
35#include <sound/tlv.h>
36#include <sound/cs42l56.h>
37#include "cs42l56.h"
38
39#define CS42L56_NUM_SUPPLIES 3
40static const char *const cs42l56_supply_names[CS42L56_NUM_SUPPLIES] = {
41 "VA",
42 "VCP",
43 "VLDO",
44};
45
46struct cs42l56_private {
47 struct regmap *regmap;
48 struct snd_soc_codec *codec;
49 struct device *dev;
50 struct cs42l56_platform_data pdata;
51 struct regulator_bulk_data supplies[CS42L56_NUM_SUPPLIES];
52 u32 mclk;
53 u8 mclk_prediv;
54 u8 mclk_div2;
55 u8 mclk_ratio;
56 u8 iface;
57 u8 iface_fmt;
58 u8 iface_inv;
59#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
60 struct input_dev *beep;
61 struct work_struct beep_work;
62 int beep_rate;
63#endif
64};
65
66static const struct reg_default cs42l56_reg_defaults[] = {
67 { 1, 0x56 }, /* r01 - ID 1 */
68 { 2, 0x04 }, /* r02 - ID 2 */
69 { 3, 0x7f }, /* r03 - Power Ctl 1 */
70 { 4, 0xff }, /* r04 - Power Ctl 2 */
71 { 5, 0x00 }, /* ro5 - Clocking Ctl 1 */
72 { 6, 0x0b }, /* r06 - Clocking Ctl 2 */
73 { 7, 0x00 }, /* r07 - Serial Format */
74 { 8, 0x05 }, /* r08 - Class H Ctl */
75 { 9, 0x0c }, /* r09 - Misc Ctl */
76 { 10, 0x80 }, /* r0a - INT Status */
77 { 11, 0x00 }, /* r0b - Playback Ctl */
78 { 12, 0x0c }, /* r0c - DSP Mute Ctl */
79 { 13, 0x00 }, /* r0d - ADCA Mixer Volume */
80 { 14, 0x00 }, /* r0e - ADCB Mixer Volume */
81 { 15, 0x00 }, /* r0f - PCMA Mixer Volume */
82 { 16, 0x00 }, /* r10 - PCMB Mixer Volume */
83 { 17, 0x00 }, /* r11 - Analog Input Advisory Volume */
84 { 18, 0x00 }, /* r12 - Digital Input Advisory Volume */
85 { 19, 0x00 }, /* r13 - Master A Volume */
86 { 20, 0x00 }, /* r14 - Master B Volume */
87 { 21, 0x00 }, /* r15 - Beep Freq / On Time */
88 { 22, 0x00 }, /* r16 - Beep Volume / Off Time */
89 { 23, 0x00 }, /* r17 - Beep Tone Ctl */
90 { 24, 0x88 }, /* r18 - Tone Ctl */
91 { 25, 0x00 }, /* r19 - Channel Mixer & Swap */
92 { 26, 0x00 }, /* r1a - AIN Ref Config / ADC Mux */
93 { 27, 0xa0 }, /* r1b - High-Pass Filter Ctl */
94 { 28, 0x00 }, /* r1c - Misc ADC Ctl */
95 { 29, 0x00 }, /* r1d - Gain & Bias Ctl */
96 { 30, 0x00 }, /* r1e - PGAA Mux & Volume */
97 { 31, 0x00 }, /* r1f - PGAB Mux & Volume */
98 { 32, 0x00 }, /* r20 - ADCA Attenuator */
99 { 33, 0x00 }, /* r21 - ADCB Attenuator */
100 { 34, 0x00 }, /* r22 - ALC Enable & Attack Rate */
101 { 35, 0xbf }, /* r23 - ALC Release Rate */
102 { 36, 0x00 }, /* r24 - ALC Threshold */
103 { 37, 0x00 }, /* r25 - Noise Gate Ctl */
104 { 38, 0x00 }, /* r26 - ALC, Limiter, SFT, ZeroCross */
105 { 39, 0x00 }, /* r27 - Analog Mute, LO & HP Mux */
106 { 40, 0x00 }, /* r28 - HP A Volume */
107 { 41, 0x00 }, /* r29 - HP B Volume */
108 { 42, 0x00 }, /* r2a - LINEOUT A Volume */
109 { 43, 0x00 }, /* r2b - LINEOUT B Volume */
110 { 44, 0x00 }, /* r2c - Limit Threshold Ctl */
111 { 45, 0x7f }, /* r2d - Limiter Ctl & Release Rate */
112 { 46, 0x00 }, /* r2e - Limiter Attack Rate */
113};
114
115static bool cs42l56_readable_register(struct device *dev, unsigned int reg)
116{
117 switch (reg) {
118 case CS42L56_CHIP_ID_1:
119 case CS42L56_CHIP_ID_2:
120 case CS42L56_PWRCTL_1:
121 case CS42L56_PWRCTL_2:
122 case CS42L56_CLKCTL_1:
123 case CS42L56_CLKCTL_2:
124 case CS42L56_SERIAL_FMT:
125 case CS42L56_CLASSH_CTL:
126 case CS42L56_MISC_CTL:
127 case CS42L56_INT_STATUS:
128 case CS42L56_PLAYBACK_CTL:
129 case CS42L56_DSP_MUTE_CTL:
130 case CS42L56_ADCA_MIX_VOLUME:
131 case CS42L56_ADCB_MIX_VOLUME:
132 case CS42L56_PCMA_MIX_VOLUME:
133 case CS42L56_PCMB_MIX_VOLUME:
134 case CS42L56_ANAINPUT_ADV_VOLUME:
135 case CS42L56_DIGINPUT_ADV_VOLUME:
136 case CS42L56_MASTER_A_VOLUME:
137 case CS42L56_MASTER_B_VOLUME:
138 case CS42L56_BEEP_FREQ_ONTIME:
139 case CS42L56_BEEP_FREQ_OFFTIME:
140 case CS42L56_BEEP_TONE_CFG:
141 case CS42L56_TONE_CTL:
142 case CS42L56_CHAN_MIX_SWAP:
143 case CS42L56_AIN_REFCFG_ADC_MUX:
144 case CS42L56_HPF_CTL:
145 case CS42L56_MISC_ADC_CTL:
146 case CS42L56_GAIN_BIAS_CTL:
147 case CS42L56_PGAA_MUX_VOLUME:
148 case CS42L56_PGAB_MUX_VOLUME:
149 case CS42L56_ADCA_ATTENUATOR:
150 case CS42L56_ADCB_ATTENUATOR:
151 case CS42L56_ALC_EN_ATTACK_RATE:
152 case CS42L56_ALC_RELEASE_RATE:
153 case CS42L56_ALC_THRESHOLD:
154 case CS42L56_NOISE_GATE_CTL:
155 case CS42L56_ALC_LIM_SFT_ZC:
156 case CS42L56_AMUTE_HPLO_MUX:
157 case CS42L56_HPA_VOLUME:
158 case CS42L56_HPB_VOLUME:
159 case CS42L56_LOA_VOLUME:
160 case CS42L56_LOB_VOLUME:
161 case CS42L56_LIM_THRESHOLD_CTL:
162 case CS42L56_LIM_CTL_RELEASE_RATE:
163 case CS42L56_LIM_ATTACK_RATE:
164 return true;
165 default:
166 return false;
167 }
168}
169
170static bool cs42l56_volatile_register(struct device *dev, unsigned int reg)
171{
172 switch (reg) {
173 case CS42L56_INT_STATUS:
174 return 1;
175 default:
176 return 0;
177 }
178}
179
180static DECLARE_TLV_DB_SCALE(beep_tlv, -5000, 200, 0);
181static DECLARE_TLV_DB_SCALE(hl_tlv, -6000, 50, 0);
182static DECLARE_TLV_DB_SCALE(adv_tlv, -10200, 50, 0);
183static DECLARE_TLV_DB_SCALE(adc_tlv, -9600, 100, 0);
184static DECLARE_TLV_DB_SCALE(tone_tlv, -1050, 150, 0);
185static DECLARE_TLV_DB_SCALE(preamp_tlv, 0, 1000, 0);
186static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
187
188static const unsigned int ngnb_tlv[] = {
189 TLV_DB_RANGE_HEAD(2),
190 0, 1, TLV_DB_SCALE_ITEM(-8200, 600, 0),
191 2, 5, TLV_DB_SCALE_ITEM(-7600, 300, 0),
192};
193static const unsigned int ngb_tlv[] = {
194 TLV_DB_RANGE_HEAD(2),
195 0, 2, TLV_DB_SCALE_ITEM(-6400, 600, 0),
196 3, 7, TLV_DB_SCALE_ITEM(-4600, 300, 0),
197};
198static const unsigned int alc_tlv[] = {
199 TLV_DB_RANGE_HEAD(2),
200 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
201 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0),
202};
203
204static const char * const beep_config_text[] = {
205 "Off", "Single", "Multiple", "Continuous"
206};
207
208static const struct soc_enum beep_config_enum =
209 SOC_ENUM_SINGLE(CS42L56_BEEP_TONE_CFG, 6,
210 ARRAY_SIZE(beep_config_text), beep_config_text);
211
212static const char * const beep_pitch_text[] = {
213 "C4", "C5", "D5", "E5", "F5", "G5", "A5", "B5",
214 "C6", "D6", "E6", "F6", "G6", "A6", "B6", "C7"
215};
216
217static const struct soc_enum beep_pitch_enum =
218 SOC_ENUM_SINGLE(CS42L56_BEEP_FREQ_ONTIME, 4,
219 ARRAY_SIZE(beep_pitch_text), beep_pitch_text);
220
221static const char * const beep_ontime_text[] = {
222 "86 ms", "430 ms", "780 ms", "1.20 s", "1.50 s",
223 "1.80 s", "2.20 s", "2.50 s", "2.80 s", "3.20 s",
224 "3.50 s", "3.80 s", "4.20 s", "4.50 s", "4.80 s", "5.20 s"
225};
226
227static const struct soc_enum beep_ontime_enum =
228 SOC_ENUM_SINGLE(CS42L56_BEEP_FREQ_ONTIME, 0,
229 ARRAY_SIZE(beep_ontime_text), beep_ontime_text);
230
231static const char * const beep_offtime_text[] = {
232 "1.23 s", "2.58 s", "3.90 s", "5.20 s",
233 "6.60 s", "8.05 s", "9.35 s", "10.80 s"
234};
235
236static const struct soc_enum beep_offtime_enum =
237 SOC_ENUM_SINGLE(CS42L56_BEEP_FREQ_OFFTIME, 5,
238 ARRAY_SIZE(beep_offtime_text), beep_offtime_text);
239
240static const char * const beep_treble_text[] = {
241 "5kHz", "7kHz", "10kHz", "15kHz"
242};
243
244static const struct soc_enum beep_treble_enum =
245 SOC_ENUM_SINGLE(CS42L56_BEEP_TONE_CFG, 3,
246 ARRAY_SIZE(beep_treble_text), beep_treble_text);
247
248static const char * const beep_bass_text[] = {
249 "50Hz", "100Hz", "200Hz", "250Hz"
250};
251
252static const struct soc_enum beep_bass_enum =
253 SOC_ENUM_SINGLE(CS42L56_BEEP_TONE_CFG, 1,
254 ARRAY_SIZE(beep_bass_text), beep_bass_text);
255
256static const char * const adc_swap_text[] = {
257 "None", "A+B/2", "A-B/2", "Swap"
258};
259
260static const struct soc_enum adc_swap_enum =
261 SOC_ENUM_SINGLE(CS42L56_MISC_ADC_CTL, 3,
262 ARRAY_SIZE(adc_swap_text), adc_swap_text);
263
264static const char * const pgaa_mux_text[] = {
265 "AIN1A", "AIN2A", "AIN3A"};
266
267static const struct soc_enum pgaa_mux_enum =
268 SOC_ENUM_SINGLE(CS42L56_PGAA_MUX_VOLUME, 0,
269 ARRAY_SIZE(pgaa_mux_text),
270 pgaa_mux_text);
271
272static const struct snd_kcontrol_new pgaa_mux =
273 SOC_DAPM_ENUM("Route", pgaa_mux_enum);
274
275static const char * const pgab_mux_text[] = {
276 "AIN1B", "AIN2B", "AIN3B"};
277
278static const struct soc_enum pgab_mux_enum =
279 SOC_ENUM_SINGLE(CS42L56_PGAB_MUX_VOLUME, 0,
280 ARRAY_SIZE(pgab_mux_text),
281 pgab_mux_text);
282
283static const struct snd_kcontrol_new pgab_mux =
284 SOC_DAPM_ENUM("Route", pgab_mux_enum);
285
286static const char * const adca_mux_text[] = {
287 "PGAA", "AIN1A", "AIN2A", "AIN3A"};
288
289static const struct soc_enum adca_mux_enum =
290 SOC_ENUM_SINGLE(CS42L56_AIN_REFCFG_ADC_MUX, 0,
291 ARRAY_SIZE(adca_mux_text),
292 adca_mux_text);
293
294static const struct snd_kcontrol_new adca_mux =
295 SOC_DAPM_ENUM("Route", adca_mux_enum);
296
297static const char * const adcb_mux_text[] = {
298 "PGAB", "AIN1B", "AIN2B", "AIN3B"};
299
300static const struct soc_enum adcb_mux_enum =
301 SOC_ENUM_SINGLE(CS42L56_AIN_REFCFG_ADC_MUX, 2,
302 ARRAY_SIZE(adcb_mux_text),
303 adcb_mux_text);
304
305static const struct snd_kcontrol_new adcb_mux =
306 SOC_DAPM_ENUM("Route", adcb_mux_enum);
307
308static const char * const left_swap_text[] = {
309 "Left", "LR 2", "Right"};
310
311static const char * const right_swap_text[] = {
312 "Right", "LR 2", "Left"};
313
314static const unsigned int swap_values[] = { 0, 1, 3 };
315
316static const struct soc_enum adca_swap_enum =
317 SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX_SWAP, 0, 3,
318 ARRAY_SIZE(left_swap_text),
319 left_swap_text,
320 swap_values);
321
322static const struct soc_enum pcma_swap_enum =
323 SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX_SWAP, 4, 3,
324 ARRAY_SIZE(left_swap_text),
325 left_swap_text,
326 swap_values);
327
328static const struct soc_enum adcb_swap_enum =
329 SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX_SWAP, 2, 3,
330 ARRAY_SIZE(right_swap_text),
331 right_swap_text,
332 swap_values);
333
334static const struct soc_enum pcmb_swap_enum =
335 SOC_VALUE_ENUM_SINGLE(CS42L56_CHAN_MIX_SWAP, 6, 3,
336 ARRAY_SIZE(right_swap_text),
337 right_swap_text,
338 swap_values);
339
340static const struct snd_kcontrol_new hpa_switch =
341 SOC_DAPM_SINGLE("Switch", CS42L56_PWRCTL_2, 6, 1, 1);
342
343static const struct snd_kcontrol_new hpb_switch =
344 SOC_DAPM_SINGLE("Switch", CS42L56_PWRCTL_2, 4, 1, 1);
345
346static const struct snd_kcontrol_new loa_switch =
347 SOC_DAPM_SINGLE("Switch", CS42L56_PWRCTL_2, 2, 1, 1);
348
349static const struct snd_kcontrol_new lob_switch =
350 SOC_DAPM_SINGLE("Switch", CS42L56_PWRCTL_2, 0, 1, 1);
351
352static const char * const hploa_input_text[] = {
353 "DACA", "PGAA"};
354
355static const struct soc_enum lineouta_input_enum =
356 SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX, 2,
357 ARRAY_SIZE(hploa_input_text),
358 hploa_input_text);
359
360static const struct snd_kcontrol_new lineouta_input =
361 SOC_DAPM_ENUM("Route", lineouta_input_enum);
362
363static const struct soc_enum hpa_input_enum =
364 SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX, 0,
365 ARRAY_SIZE(hploa_input_text),
366 hploa_input_text);
367
368static const struct snd_kcontrol_new hpa_input =
369 SOC_DAPM_ENUM("Route", hpa_input_enum);
370
371static const char * const hplob_input_text[] = {
372 "DACB", "PGAB"};
373
374static const struct soc_enum lineoutb_input_enum =
375 SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX, 3,
376 ARRAY_SIZE(hplob_input_text),
377 hplob_input_text);
378
379static const struct snd_kcontrol_new lineoutb_input =
380 SOC_DAPM_ENUM("Route", lineoutb_input_enum);
381
382static const struct soc_enum hpb_input_enum =
383 SOC_ENUM_SINGLE(CS42L56_AMUTE_HPLO_MUX, 1,
384 ARRAY_SIZE(hplob_input_text),
385 hplob_input_text);
386
387static const struct snd_kcontrol_new hpb_input =
388 SOC_DAPM_ENUM("Route", hpb_input_enum);
389
390static const char * const dig_mux_text[] = {
391 "ADC", "DSP"};
392
393static const struct soc_enum dig_mux_enum =
394 SOC_ENUM_SINGLE(CS42L56_MISC_CTL, 7,
395 ARRAY_SIZE(dig_mux_text),
396 dig_mux_text);
397
398static const struct snd_kcontrol_new dig_mux =
399 SOC_DAPM_ENUM("Route", dig_mux_enum);
400
401static const char * const hpf_freq_text[] = {
402 "1.8Hz", "119Hz", "236Hz", "464Hz"
403};
404
405static const struct soc_enum hpfa_freq_enum =
406 SOC_ENUM_SINGLE(CS42L56_HPF_CTL, 0,
407 ARRAY_SIZE(hpf_freq_text), hpf_freq_text);
408
409static const struct soc_enum hpfb_freq_enum =
410 SOC_ENUM_SINGLE(CS42L56_HPF_CTL, 2,
411 ARRAY_SIZE(hpf_freq_text), hpf_freq_text);
412
413static const char * const ng_delay_text[] = {
414 "50ms", "100ms", "150ms", "200ms"
415};
416
417static const struct soc_enum ng_delay_enum =
418 SOC_ENUM_SINGLE(CS42L56_NOISE_GATE_CTL, 0,
419 ARRAY_SIZE(ng_delay_text), ng_delay_text);
420
421static const struct snd_kcontrol_new cs42l56_snd_controls[] = {
422
423 SOC_DOUBLE_R_SX_TLV("Master Volume", CS42L56_MASTER_A_VOLUME,
424 CS42L56_MASTER_B_VOLUME, 0, 0x34, 0xfd, adv_tlv),
425 SOC_DOUBLE("Master Mute Switch", CS42L56_DSP_MUTE_CTL, 0, 1, 1, 1),
426
427 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume", CS42L56_ADCA_MIX_VOLUME,
428 CS42L56_ADCB_MIX_VOLUME, 0, 0x88, 0xa9, hl_tlv),
429 SOC_DOUBLE("ADC Mixer Mute Switch", CS42L56_DSP_MUTE_CTL, 6, 7, 1, 1),
430
431 SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume", CS42L56_PCMA_MIX_VOLUME,
432 CS42L56_PCMB_MIX_VOLUME, 0, 0x88, 0xa9, hl_tlv),
433 SOC_DOUBLE("PCM Mixer Mute Switch", CS42L56_DSP_MUTE_CTL, 4, 5, 1, 1),
434
435 SOC_SINGLE_TLV("Analog Advisory Volume",
436 CS42L56_ANAINPUT_ADV_VOLUME, 0, 0x00, 1, adv_tlv),
437 SOC_SINGLE_TLV("Digital Advisory Volume",
438 CS42L56_DIGINPUT_ADV_VOLUME, 0, 0x00, 1, adv_tlv),
439
440 SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42L56_PGAA_MUX_VOLUME,
441 CS42L56_PGAB_MUX_VOLUME, 0, 0x34, 0xfd, pga_tlv),
442 SOC_DOUBLE_R_TLV("ADC Volume", CS42L56_ADCA_ATTENUATOR,
443 CS42L56_ADCB_ATTENUATOR, 0, 0x00, 1, adc_tlv),
444 SOC_DOUBLE("ADC Mute Switch", CS42L56_MISC_ADC_CTL, 2, 3, 1, 1),
445 SOC_DOUBLE("ADC Boost Switch", CS42L56_GAIN_BIAS_CTL, 3, 2, 1, 1),
446
447 SOC_DOUBLE_R_SX_TLV("Headphone Volume", CS42L56_HPA_VOLUME,
448 CS42L56_HPA_VOLUME, 0, 0x44, 0x55, hl_tlv),
449 SOC_DOUBLE_R_SX_TLV("LineOut Volume", CS42L56_LOA_VOLUME,
450 CS42L56_LOA_VOLUME, 0, 0x44, 0x55, hl_tlv),
451
452 SOC_SINGLE_TLV("Bass Shelving Volume", CS42L56_TONE_CTL,
453 0, 0x00, 1, tone_tlv),
454 SOC_SINGLE_TLV("Treble Shelving Volume", CS42L56_TONE_CTL,
455 4, 0x00, 1, tone_tlv),
456
457 SOC_DOUBLE_TLV("PGA Preamp Volume", CS42L56_GAIN_BIAS_CTL,
458 4, 6, 0x02, 1, preamp_tlv),
459
460 SOC_SINGLE("DSP Switch", CS42L56_PLAYBACK_CTL, 7, 1, 1),
461 SOC_SINGLE("Gang Playback Switch", CS42L56_PLAYBACK_CTL, 4, 1, 1),
462 SOC_SINGLE("Gang ADC Switch", CS42L56_MISC_ADC_CTL, 7, 1, 1),
463 SOC_SINGLE("Gang PGA Switch", CS42L56_MISC_ADC_CTL, 6, 1, 1),
464
465 SOC_SINGLE("PCMA Invert", CS42L56_PLAYBACK_CTL, 2, 1, 1),
466 SOC_SINGLE("PCMB Invert", CS42L56_PLAYBACK_CTL, 3, 1, 1),
467 SOC_SINGLE("ADCA Invert", CS42L56_MISC_ADC_CTL, 2, 1, 1),
468 SOC_SINGLE("ADCB Invert", CS42L56_MISC_ADC_CTL, 3, 1, 1),
469
470 SOC_ENUM("PCMA Swap", pcma_swap_enum),
471 SOC_ENUM("PCMB Swap", pcmb_swap_enum),
472 SOC_ENUM("ADCA Swap", adca_swap_enum),
473 SOC_ENUM("ADCB Swap", adcb_swap_enum),
474
475 SOC_DOUBLE("HPF Switch", CS42L56_HPF_CTL, 5, 7, 1, 1),
476 SOC_DOUBLE("HPF Freeze Switch", CS42L56_HPF_CTL, 4, 6, 1, 1),
477 SOC_ENUM("HPFA Corner Freq", hpfa_freq_enum),
478 SOC_ENUM("HPFB Corner Freq", hpfb_freq_enum),
479
480 SOC_SINGLE("Analog Soft Ramp", CS42L56_MISC_CTL, 4, 1, 1),
481 SOC_DOUBLE("Analog Soft Ramp Disable", CS42L56_ALC_LIM_SFT_ZC,
482 7, 5, 1, 1),
483 SOC_SINGLE("Analog Zero Cross", CS42L56_MISC_CTL, 3, 1, 1),
484 SOC_DOUBLE("Analog Zero Cross Disable", CS42L56_ALC_LIM_SFT_ZC,
485 6, 4, 1, 1),
486 SOC_SINGLE("Digital Soft Ramp", CS42L56_MISC_CTL, 2, 1, 1),
487 SOC_SINGLE("Digital Soft Ramp Disable", CS42L56_ALC_LIM_SFT_ZC,
488 3, 1, 1),
489
490 SOC_SINGLE("HL Deemphasis", CS42L56_PLAYBACK_CTL, 6, 1, 1),
491
492 SOC_SINGLE("ALC Switch", CS42L56_ALC_EN_ATTACK_RATE, 6, 1, 1),
493 SOC_SINGLE("ALC Limit All Switch", CS42L56_ALC_RELEASE_RATE, 7, 1, 1),
494 SOC_SINGLE_RANGE("ALC Attack", CS42L56_ALC_EN_ATTACK_RATE,
495 0, 0, 0x3f, 0),
496 SOC_SINGLE_RANGE("ALC Release", CS42L56_ALC_RELEASE_RATE,
497 0, 0x3f, 0, 0),
498 SOC_SINGLE_TLV("ALC MAX", CS42L56_ALC_THRESHOLD,
499 5, 0x07, 1, alc_tlv),
500 SOC_SINGLE_TLV("ALC MIN", CS42L56_ALC_THRESHOLD,
501 2, 0x07, 1, alc_tlv),
502
503 SOC_SINGLE("Limiter Switch", CS42L56_LIM_CTL_RELEASE_RATE, 7, 1, 1),
504 SOC_SINGLE("Limit All Switch", CS42L56_LIM_CTL_RELEASE_RATE, 6, 1, 1),
505 SOC_SINGLE_RANGE("Limiter Attack", CS42L56_LIM_ATTACK_RATE,
506 0, 0, 0x3f, 0),
507 SOC_SINGLE_RANGE("Limiter Release", CS42L56_LIM_CTL_RELEASE_RATE,
508 0, 0x3f, 0, 0),
509 SOC_SINGLE_TLV("Limiter MAX", CS42L56_LIM_THRESHOLD_CTL,
510 5, 0x07, 1, alc_tlv),
511 SOC_SINGLE_TLV("Limiter Cushion", CS42L56_ALC_THRESHOLD,
512 2, 0x07, 1, alc_tlv),
513
514 SOC_SINGLE("NG Switch", CS42L56_NOISE_GATE_CTL, 6, 1, 1),
515 SOC_SINGLE("NG All Switch", CS42L56_NOISE_GATE_CTL, 7, 1, 1),
516 SOC_SINGLE("NG Boost Switch", CS42L56_NOISE_GATE_CTL, 5, 1, 1),
517 SOC_SINGLE_TLV("NG Unboost Threshold", CS42L56_NOISE_GATE_CTL,
518 2, 0x07, 1, ngnb_tlv),
519 SOC_SINGLE_TLV("NG Boost Threshold", CS42L56_NOISE_GATE_CTL,
520 2, 0x07, 1, ngb_tlv),
521 SOC_ENUM("NG Delay", ng_delay_enum),
522
523 SOC_ENUM("Beep Config", beep_config_enum),
524 SOC_ENUM("Beep Pitch", beep_pitch_enum),
525 SOC_ENUM("Beep on Time", beep_ontime_enum),
526 SOC_ENUM("Beep off Time", beep_offtime_enum),
527 SOC_SINGLE_SX_TLV("Beep Volume", CS42L56_BEEP_FREQ_OFFTIME,
528 0, 0x07, 0x23, beep_tlv),
529 SOC_SINGLE("Beep Tone Ctl Switch", CS42L56_BEEP_TONE_CFG, 0, 1, 1),
530 SOC_ENUM("Beep Treble Corner Freq", beep_treble_enum),
531 SOC_ENUM("Beep Bass Corner Freq", beep_bass_enum),
532
533};
534
535static const struct snd_soc_dapm_widget cs42l56_dapm_widgets[] = {
536
537 SND_SOC_DAPM_SIGGEN("Beep"),
538 SND_SOC_DAPM_SUPPLY("VBUF", CS42L56_PWRCTL_1, 5, 1, NULL, 0),
539 SND_SOC_DAPM_MICBIAS("MIC1 Bias", CS42L56_PWRCTL_1, 4, 1),
540 SND_SOC_DAPM_SUPPLY("Charge Pump", CS42L56_PWRCTL_1, 3, 1, NULL, 0),
541
542 SND_SOC_DAPM_INPUT("AIN1A"),
543 SND_SOC_DAPM_INPUT("AIN2A"),
544 SND_SOC_DAPM_INPUT("AIN1B"),
545 SND_SOC_DAPM_INPUT("AIN2B"),
546 SND_SOC_DAPM_INPUT("AIN3A"),
547 SND_SOC_DAPM_INPUT("AIN3B"),
548
549 SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0,
550 SND_SOC_NOPM, 0, 0),
551
552 SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0,
553 SND_SOC_NOPM, 0, 0),
554
555 SND_SOC_DAPM_MUX("Digital Output Mux", SND_SOC_NOPM,
556 0, 0, &dig_mux),
557
558 SND_SOC_DAPM_PGA("PGAA", SND_SOC_NOPM, 0, 0, NULL, 0),
559 SND_SOC_DAPM_PGA("PGAB", SND_SOC_NOPM, 0, 0, NULL, 0),
560 SND_SOC_DAPM_MUX("PGAA Input Mux",
561 SND_SOC_NOPM, 0, 0, &pgaa_mux),
562 SND_SOC_DAPM_MUX("PGAB Input Mux",
563 SND_SOC_NOPM, 0, 0, &pgab_mux),
564
565 SND_SOC_DAPM_MUX("ADCA Mux", SND_SOC_NOPM,
566 0, 0, &adca_mux),
567 SND_SOC_DAPM_MUX("ADCB Mux", SND_SOC_NOPM,
568 0, 0, &adcb_mux),
569
570 SND_SOC_DAPM_ADC("ADCA", NULL, CS42L56_PWRCTL_1, 1, 1),
571 SND_SOC_DAPM_ADC("ADCB", NULL, CS42L56_PWRCTL_1, 2, 1),
572
573 SND_SOC_DAPM_DAC("DACA", NULL, SND_SOC_NOPM, 0, 0),
574 SND_SOC_DAPM_DAC("DACB", NULL, SND_SOC_NOPM, 0, 0),
575
576 SND_SOC_DAPM_OUTPUT("HPA"),
577 SND_SOC_DAPM_OUTPUT("LOA"),
578 SND_SOC_DAPM_OUTPUT("HPB"),
579 SND_SOC_DAPM_OUTPUT("LOB"),
580
581 SND_SOC_DAPM_SWITCH("Headphone Right",
582 CS42L56_PWRCTL_2, 4, 1, &hpb_switch),
583 SND_SOC_DAPM_SWITCH("Headphone Left",
584 CS42L56_PWRCTL_2, 6, 1, &hpa_switch),
585
586 SND_SOC_DAPM_SWITCH("Lineout Right",
587 CS42L56_PWRCTL_2, 0, 1, &lob_switch),
588 SND_SOC_DAPM_SWITCH("Lineout Left",
589 CS42L56_PWRCTL_2, 2, 1, &loa_switch),
590
591 SND_SOC_DAPM_MUX("LINEOUTA Input Mux", SND_SOC_NOPM,
592 0, 0, &lineouta_input),
593 SND_SOC_DAPM_MUX("LINEOUTB Input Mux", SND_SOC_NOPM,
594 0, 0, &lineoutb_input),
595 SND_SOC_DAPM_MUX("HPA Input Mux", SND_SOC_NOPM,
596 0, 0, &hpa_input),
597 SND_SOC_DAPM_MUX("HPB Input Mux", SND_SOC_NOPM,
598 0, 0, &hpb_input),
599
600};
601
602static const struct snd_soc_dapm_route cs42l56_audio_map[] = {
603
604 {"HiFi Capture", "DSP", "Digital Output Mux"},
605 {"HiFi Capture", "ADC", "Digital Output Mux"},
606
607 {"Digital Output Mux", NULL, "ADCA"},
608 {"Digital Output Mux", NULL, "ADCB"},
609
610 {"ADCB", NULL, "ADCB Mux"},
611 {"ADCA", NULL, "ADCA Mux"},
612
613 {"ADCA Mux", NULL, "AIN3A"},
614 {"ADCA Mux", NULL, "AIN2A"},
615 {"ADCA Mux", NULL, "AIN1A"},
616 {"ADCA Mux", NULL, "PGAA"},
617 {"ADCB Mux", NULL, "AIN3B"},
618 {"ADCB Mux", NULL, "AIN2B"},
619 {"ADCB Mux", NULL, "AIN1B"},
620 {"ADCB Mux", NULL, "PGAB"},
621
622 {"PGAA", "AIN1A", "PGAA Input Mux"},
623 {"PGAA", "AIN2A", "PGAA Input Mux"},
624 {"PGAA", "AIN3A", "PGAA Input Mux"},
625 {"PGAB", "AIN1B", "PGAB Input Mux"},
626 {"PGAB", "AIN2B", "PGAB Input Mux"},
627 {"PGAB", "AIN3B", "PGAB Input Mux"},
628
629 {"PGAA Input Mux", NULL, "AIN1A"},
630 {"PGAA Input Mux", NULL, "AIN2A"},
631 {"PGAA Input Mux", NULL, "AIN3A"},
632 {"PGAB Input Mux", NULL, "AIN1B"},
633 {"PGAB Input Mux", NULL, "AIN2B"},
634 {"PGAB Input Mux", NULL, "AIN3B"},
635
636 {"LOB", NULL, "Lineout Right"},
637 {"LOA", NULL, "Lineout Left"},
638
639 {"Lineout Right", "Switch", "LINEOUTB Input Mux"},
640 {"Lineout Left", "Switch", "LINEOUTA Input Mux"},
641
642 {"LINEOUTA Input Mux", "PGAA", "PGAA"},
643 {"LINEOUTB Input Mux", "PGAB", "PGAB"},
644 {"LINEOUTA Input Mux", "DACA", "DACA"},
645 {"LINEOUTB Input Mux", "DACB", "DACB"},
646
647 {"HPA", NULL, "Headphone Left"},
648 {"HPB", NULL, "Headphone Right"},
649
650 {"Headphone Right", "Switch", "HPB Input Mux"},
651 {"Headphone Left", "Switch", "HPA Input Mux"},
652
653 {"HPA Input Mux", "PGAA", "PGAA"},
654 {"HPB Input Mux", "PGAB", "PGAB"},
655 {"HPA Input Mux", "DACA", "DACA"},
656 {"HPB Input Mux", "DACB", "DACB"},
657
658 {"DACB", NULL, "HiFi Playback"},
659 {"DACA", NULL, "HiFi Playback"},
660
661};
662
663struct cs42l56_clk_para {
664 u32 mclk;
665 u32 srate;
666 u8 ratio;
667};
668
669static const struct cs42l56_clk_para clk_ratio_table[] = {
670 /* 8k */
671 { 6000000, 8000, CS42L56_MCLK_LRCLK_768 },
672 { 6144000, 8000, CS42L56_MCLK_LRCLK_750 },
673 { 12000000, 8000, CS42L56_MCLK_LRCLK_768 },
674 { 12288000, 8000, CS42L56_MCLK_LRCLK_750 },
675 { 24000000, 8000, CS42L56_MCLK_LRCLK_768 },
676 { 24576000, 8000, CS42L56_MCLK_LRCLK_750 },
677 /* 11.025k */
678 { 5644800, 11025, CS42L56_MCLK_LRCLK_512},
679 { 11289600, 11025, CS42L56_MCLK_LRCLK_512},
680 { 22579200, 11025, CS42L56_MCLK_LRCLK_512 },
681 /* 11.0294k */
682 { 6000000, 110294, CS42L56_MCLK_LRCLK_544 },
683 { 12000000, 110294, CS42L56_MCLK_LRCLK_544 },
684 { 24000000, 110294, CS42L56_MCLK_LRCLK_544 },
685 /* 12k */
686 { 6000000, 12000, CS42L56_MCLK_LRCLK_500 },
687 { 6144000, 12000, CS42L56_MCLK_LRCLK_512 },
688 { 12000000, 12000, CS42L56_MCLK_LRCLK_500 },
689 { 12288000, 12000, CS42L56_MCLK_LRCLK_512 },
690 { 24000000, 12000, CS42L56_MCLK_LRCLK_500 },
691 { 24576000, 12000, CS42L56_MCLK_LRCLK_512 },
692 /* 16k */
693 { 6000000, 16000, CS42L56_MCLK_LRCLK_375 },
694 { 6144000, 16000, CS42L56_MCLK_LRCLK_384 },
695 { 12000000, 16000, CS42L56_MCLK_LRCLK_375 },
696 { 12288000, 16000, CS42L56_MCLK_LRCLK_384 },
697 { 24000000, 16000, CS42L56_MCLK_LRCLK_375 },
698 { 24576000, 16000, CS42L56_MCLK_LRCLK_384 },
699 /* 22.050k */
700 { 5644800, 22050, CS42L56_MCLK_LRCLK_256 },
701 { 11289600, 22050, CS42L56_MCLK_LRCLK_256 },
702 { 22579200, 22050, CS42L56_MCLK_LRCLK_256 },
703 /* 22.0588k */
704 { 6000000, 220588, CS42L56_MCLK_LRCLK_272 },
705 { 12000000, 220588, CS42L56_MCLK_LRCLK_272 },
706 { 24000000, 220588, CS42L56_MCLK_LRCLK_272 },
707 /* 24k */
708 { 6000000, 24000, CS42L56_MCLK_LRCLK_250 },
709 { 6144000, 24000, CS42L56_MCLK_LRCLK_256 },
710 { 12000000, 24000, CS42L56_MCLK_LRCLK_250 },
711 { 12288000, 24000, CS42L56_MCLK_LRCLK_256 },
712 { 24000000, 24000, CS42L56_MCLK_LRCLK_250 },
713 { 24576000, 24000, CS42L56_MCLK_LRCLK_256 },
714 /* 32k */
715 { 6000000, 32000, CS42L56_MCLK_LRCLK_187P5 },
716 { 6144000, 32000, CS42L56_MCLK_LRCLK_192 },
717 { 12000000, 32000, CS42L56_MCLK_LRCLK_187P5 },
718 { 12288000, 32000, CS42L56_MCLK_LRCLK_192 },
719 { 24000000, 32000, CS42L56_MCLK_LRCLK_187P5 },
720 { 24576000, 32000, CS42L56_MCLK_LRCLK_192 },
721 /* 44.118k */
722 { 6000000, 44118, CS42L56_MCLK_LRCLK_136 },
723 { 12000000, 44118, CS42L56_MCLK_LRCLK_136 },
724 { 24000000, 44118, CS42L56_MCLK_LRCLK_136 },
725 /* 44.1k */
726 { 5644800, 44100, CS42L56_MCLK_LRCLK_128 },
727 { 11289600, 44100, CS42L56_MCLK_LRCLK_128 },
728 { 22579200, 44100, CS42L56_MCLK_LRCLK_128 },
729 /* 48k */
730 { 6000000, 48000, CS42L56_MCLK_LRCLK_125 },
731 { 6144000, 48000, CS42L56_MCLK_LRCLK_128 },
732 { 12000000, 48000, CS42L56_MCLK_LRCLK_125 },
733 { 12288000, 48000, CS42L56_MCLK_LRCLK_128 },
734 { 24000000, 48000, CS42L56_MCLK_LRCLK_125 },
735 { 24576000, 48000, CS42L56_MCLK_LRCLK_128 },
736};
737
738static int cs42l56_get_mclk_ratio(int mclk, int rate)
739{
740 int i;
741
742 for (i = 0; i < ARRAY_SIZE(clk_ratio_table); i++) {
743 if (clk_ratio_table[i].mclk == mclk &&
744 clk_ratio_table[i].srate == rate)
745 return clk_ratio_table[i].ratio;
746 }
747 return -EINVAL;
748}
749
750static int cs42l56_set_sysclk(struct snd_soc_dai *codec_dai,
751 int clk_id, unsigned int freq, int dir)
752{
753 struct snd_soc_codec *codec = codec_dai->codec;
754 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
755
756 switch (freq) {
757 case CS42L56_MCLK_5P6448MHZ:
758 case CS42L56_MCLK_6MHZ:
759 case CS42L56_MCLK_6P144MHZ:
760 cs42l56->mclk_div2 = 0;
761 cs42l56->mclk_prediv = 0;
762 break;
763 case CS42L56_MCLK_11P2896MHZ:
764 case CS42L56_MCLK_12MHZ:
765 case CS42L56_MCLK_12P288MHZ:
766 cs42l56->mclk_div2 = CS42L56_MCLK_DIV2;
767 cs42l56->mclk_prediv = 0;
768 break;
769 case CS42L56_MCLK_22P5792MHZ:
770 case CS42L56_MCLK_24MHZ:
771 case CS42L56_MCLK_24P576MHZ:
772 cs42l56->mclk_div2 = CS42L56_MCLK_DIV2;
773 cs42l56->mclk_prediv = CS42L56_MCLK_PREDIV;
774 break;
775 default:
776 return -EINVAL;
777 }
778 cs42l56->mclk = freq;
779
780 snd_soc_update_bits(codec, CS42L56_CLKCTL_1,
781 CS42L56_MCLK_PREDIV_MASK,
782 cs42l56->mclk_prediv);
783 snd_soc_update_bits(codec, CS42L56_CLKCTL_1,
784 CS42L56_MCLK_DIV2_MASK,
785 cs42l56->mclk_div2);
786
787 return 0;
788}
789
790static int cs42l56_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
791{
792 struct snd_soc_codec *codec = codec_dai->codec;
793 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
794
795 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
796 case SND_SOC_DAIFMT_CBM_CFM:
797 cs42l56->iface = CS42L56_MASTER_MODE;
798 break;
799 case SND_SOC_DAIFMT_CBS_CFS:
800 cs42l56->iface = CS42L56_SLAVE_MODE;
801 break;
802 default:
803 return -EINVAL;
804 }
805
806 /* interface format */
807 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
808 case SND_SOC_DAIFMT_I2S:
809 cs42l56->iface_fmt = CS42L56_DIG_FMT_I2S;
810 break;
811 case SND_SOC_DAIFMT_LEFT_J:
812 cs42l56->iface_fmt = CS42L56_DIG_FMT_LEFT_J;
813 break;
814 default:
815 return -EINVAL;
816 }
817
818 /* sclk inversion */
819 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
820 case SND_SOC_DAIFMT_NB_NF:
821 cs42l56->iface_inv = 0;
822 break;
823 case SND_SOC_DAIFMT_IB_NF:
824 cs42l56->iface_inv = CS42L56_SCLK_INV;
825 break;
826 default:
827 return -EINVAL;
828 }
829
830 snd_soc_update_bits(codec, CS42L56_CLKCTL_1,
831 CS42L56_MS_MODE_MASK, cs42l56->iface);
832 snd_soc_update_bits(codec, CS42L56_SERIAL_FMT,
833 CS42L56_DIG_FMT_MASK, cs42l56->iface_fmt);
834 snd_soc_update_bits(codec, CS42L56_CLKCTL_1,
835 CS42L56_SCLK_INV_MASK, cs42l56->iface_inv);
836 return 0;
837}
838
839static int cs42l56_digital_mute(struct snd_soc_dai *dai, int mute)
840{
841 struct snd_soc_codec *codec = dai->codec;
842
843 if (mute) {
844 /* Hit the DSP Mixer first */
845 snd_soc_update_bits(codec, CS42L56_DSP_MUTE_CTL,
846 CS42L56_ADCAMIX_MUTE_MASK |
847 CS42L56_ADCBMIX_MUTE_MASK |
848 CS42L56_PCMAMIX_MUTE_MASK |
849 CS42L56_PCMBMIX_MUTE_MASK |
850 CS42L56_MSTB_MUTE_MASK |
851 CS42L56_MSTA_MUTE_MASK,
852 CS42L56_MUTE_ALL);
853 /* Mute ADC's */
854 snd_soc_update_bits(codec, CS42L56_MISC_ADC_CTL,
855 CS42L56_ADCA_MUTE_MASK |
856 CS42L56_ADCB_MUTE_MASK,
857 CS42L56_MUTE_ALL);
858 /* HP And LO */
859 snd_soc_update_bits(codec, CS42L56_HPA_VOLUME,
860 CS42L56_HP_MUTE_MASK, CS42L56_MUTE_ALL);
861 snd_soc_update_bits(codec, CS42L56_HPB_VOLUME,
862 CS42L56_HP_MUTE_MASK, CS42L56_MUTE_ALL);
863 snd_soc_update_bits(codec, CS42L56_LOA_VOLUME,
864 CS42L56_LO_MUTE_MASK, CS42L56_MUTE_ALL);
865 snd_soc_update_bits(codec, CS42L56_LOB_VOLUME,
866 CS42L56_LO_MUTE_MASK, CS42L56_MUTE_ALL);
867 } else {
868 snd_soc_update_bits(codec, CS42L56_DSP_MUTE_CTL,
869 CS42L56_ADCAMIX_MUTE_MASK |
870 CS42L56_ADCBMIX_MUTE_MASK |
871 CS42L56_PCMAMIX_MUTE_MASK |
872 CS42L56_PCMBMIX_MUTE_MASK |
873 CS42L56_MSTB_MUTE_MASK |
874 CS42L56_MSTA_MUTE_MASK,
875 CS42L56_UNMUTE);
876
877 snd_soc_update_bits(codec, CS42L56_MISC_ADC_CTL,
878 CS42L56_ADCA_MUTE_MASK |
879 CS42L56_ADCB_MUTE_MASK,
880 CS42L56_UNMUTE);
881
882 snd_soc_update_bits(codec, CS42L56_HPA_VOLUME,
883 CS42L56_HP_MUTE_MASK, CS42L56_UNMUTE);
884 snd_soc_update_bits(codec, CS42L56_HPB_VOLUME,
885 CS42L56_HP_MUTE_MASK, CS42L56_UNMUTE);
886 snd_soc_update_bits(codec, CS42L56_LOA_VOLUME,
887 CS42L56_LO_MUTE_MASK, CS42L56_UNMUTE);
888 snd_soc_update_bits(codec, CS42L56_LOB_VOLUME,
889 CS42L56_LO_MUTE_MASK, CS42L56_UNMUTE);
890 }
891 return 0;
892}
893
894static int cs42l56_pcm_hw_params(struct snd_pcm_substream *substream,
895 struct snd_pcm_hw_params *params,
896 struct snd_soc_dai *dai)
897{
898 struct snd_soc_codec *codec = dai->codec;
899 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
900 int ratio;
901
902 ratio = cs42l56_get_mclk_ratio(cs42l56->mclk, params_rate(params));
903 if (ratio >= 0) {
904 snd_soc_update_bits(codec, CS42L56_CLKCTL_2,
905 CS42L56_CLK_RATIO_MASK, ratio);
906 } else {
907 dev_err(codec->dev, "unsupported mclk/sclk/lrclk ratio\n");
908 return -EINVAL;
909 }
910
911 return 0;
912}
913
914static int cs42l56_set_bias_level(struct snd_soc_codec *codec,
915 enum snd_soc_bias_level level)
916{
917 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
918 int ret;
919
920 switch (level) {
921 case SND_SOC_BIAS_ON:
922 break;
923 case SND_SOC_BIAS_PREPARE:
924 snd_soc_update_bits(codec, CS42L56_CLKCTL_1,
925 CS42L56_MCLK_DIS_MASK, 0);
926 snd_soc_update_bits(codec, CS42L56_PWRCTL_1,
927 CS42L56_PDN_ALL_MASK, 0);
928 break;
929 case SND_SOC_BIAS_STANDBY:
930 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
931 regcache_cache_only(cs42l56->regmap, false);
932 regcache_sync(cs42l56->regmap);
933 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l56->supplies),
934 cs42l56->supplies);
935 if (ret != 0) {
936 dev_err(cs42l56->dev,
937 "Failed to enable regulators: %d\n",
938 ret);
939 return ret;
940 }
941 }
942 snd_soc_update_bits(codec, CS42L56_PWRCTL_1,
943 CS42L56_PDN_ALL_MASK, 1);
944 break;
945 case SND_SOC_BIAS_OFF:
946 snd_soc_update_bits(codec, CS42L56_PWRCTL_1,
947 CS42L56_PDN_ALL_MASK, 1);
948 snd_soc_update_bits(codec, CS42L56_CLKCTL_1,
949 CS42L56_MCLK_DIS_MASK, 1);
950 regcache_cache_only(cs42l56->regmap, true);
951 regulator_bulk_disable(ARRAY_SIZE(cs42l56->supplies),
952 cs42l56->supplies);
953 break;
954 }
955 codec->dapm.bias_level = level;
956
957 return 0;
958}
959
960#define CS42L56_RATES (SNDRV_PCM_RATE_8000_48000)
961
962#define CS42L56_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
963 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
964 SNDRV_PCM_FMTBIT_S32_LE)
965
966
967static struct snd_soc_dai_ops cs42l56_ops = {
968 .hw_params = cs42l56_pcm_hw_params,
969 .digital_mute = cs42l56_digital_mute,
970 .set_fmt = cs42l56_set_dai_fmt,
971 .set_sysclk = cs42l56_set_sysclk,
972};
973
974static struct snd_soc_dai_driver cs42l56_dai = {
975 .name = "cs42l56",
976 .playback = {
977 .stream_name = "HiFi Playback",
978 .channels_min = 1,
979 .channels_max = 2,
980 .rates = CS42L56_RATES,
981 .formats = CS42L56_FORMATS,
982 },
983 .capture = {
984 .stream_name = "HiFi Capture",
985 .channels_min = 1,
986 .channels_max = 2,
987 .rates = CS42L56_RATES,
988 .formats = CS42L56_FORMATS,
989 },
990 .ops = &cs42l56_ops,
991};
992
993static int cs42l56_suspend(struct snd_soc_codec *codec)
994{
995 cs42l56_set_bias_level(codec, SND_SOC_BIAS_OFF);
996
997 return 0;
998}
999
1000static int cs42l56_resume(struct snd_soc_codec *codec)
1001{
1002 cs42l56_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1003
1004 return 0;
1005}
1006
1007static int beep_freq[] = {
1008 261, 522, 585, 667, 706, 774, 889, 1000,
1009 1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182
1010};
1011
1012static void cs42l56_beep_work(struct work_struct *work)
1013{
1014 struct cs42l56_private *cs42l56 =
1015 container_of(work, struct cs42l56_private, beep_work);
1016 struct snd_soc_codec *codec = cs42l56->codec;
1017 struct snd_soc_dapm_context *dapm = &codec->dapm;
1018 int i;
1019 int val = 0;
1020 int best = 0;
1021
1022 if (cs42l56->beep_rate) {
1023 for (i = 0; i < ARRAY_SIZE(beep_freq); i++) {
1024 if (abs(cs42l56->beep_rate - beep_freq[i]) <
1025 abs(cs42l56->beep_rate - beep_freq[best]))
1026 best = i;
1027 }
1028
1029 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
1030 beep_freq[best], cs42l56->beep_rate);
1031
1032 val = (best << CS42L56_BEEP_RATE_SHIFT);
1033
1034 snd_soc_dapm_enable_pin(dapm, "Beep");
1035 } else {
1036 dev_dbg(codec->dev, "Disabling beep\n");
1037 snd_soc_dapm_disable_pin(dapm, "Beep");
1038 }
1039
1040 snd_soc_update_bits(codec, CS42L56_BEEP_FREQ_ONTIME,
1041 CS42L56_BEEP_FREQ_MASK, val);
1042
1043 snd_soc_dapm_sync(dapm);
1044}
1045
1046/* For usability define a way of injecting beep events for the device -
1047 * many systems will not have a keyboard.
1048 */
1049static int cs42l56_beep_event(struct input_dev *dev, unsigned int type,
1050 unsigned int code, int hz)
1051{
1052 struct snd_soc_codec *codec = input_get_drvdata(dev);
1053 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
1054
1055 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
1056
1057 switch (code) {
1058 case SND_BELL:
1059 if (hz)
1060 hz = 261;
1061 case SND_TONE:
1062 break;
1063 default:
1064 return -1;
1065 }
1066
1067 /* Kick the beep from a workqueue */
1068 cs42l56->beep_rate = hz;
1069 schedule_work(&cs42l56->beep_work);
1070 return 0;
1071}
1072
1073static ssize_t cs42l56_beep_set(struct device *dev,
1074 struct device_attribute *attr,
1075 const char *buf, size_t count)
1076{
1077 struct cs42l56_private *cs42l56 = dev_get_drvdata(dev);
1078 long int time;
1079 int ret;
1080
1081 ret = kstrtol(buf, 10, &time);
1082 if (ret != 0)
1083 return ret;
1084
1085 input_event(cs42l56->beep, EV_SND, SND_TONE, time);
1086
1087 return count;
1088}
1089
1090static DEVICE_ATTR(beep, 0200, NULL, cs42l56_beep_set);
1091
1092static void cs42l56_init_beep(struct snd_soc_codec *codec)
1093{
1094 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
1095 int ret;
1096
1097 cs42l56->beep = devm_input_allocate_device(codec->dev);
1098 if (!cs42l56->beep) {
1099 dev_err(codec->dev, "Failed to allocate beep device\n");
1100 return;
1101 }
1102
1103 INIT_WORK(&cs42l56->beep_work, cs42l56_beep_work);
1104 cs42l56->beep_rate = 0;
1105
1106 cs42l56->beep->name = "CS42L56 Beep Generator";
1107 cs42l56->beep->phys = dev_name(codec->dev);
1108 cs42l56->beep->id.bustype = BUS_I2C;
1109
1110 cs42l56->beep->evbit[0] = BIT_MASK(EV_SND);
1111 cs42l56->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
1112 cs42l56->beep->event = cs42l56_beep_event;
1113 cs42l56->beep->dev.parent = codec->dev;
1114 input_set_drvdata(cs42l56->beep, codec);
1115
1116 ret = input_register_device(cs42l56->beep);
1117 if (ret != 0) {
1118 cs42l56->beep = NULL;
1119 dev_err(codec->dev, "Failed to register beep device\n");
1120 }
1121
1122 ret = device_create_file(codec->dev, &dev_attr_beep);
1123 if (ret != 0) {
1124 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
1125 ret);
1126 }
1127}
1128
1129static void cs42l56_free_beep(struct snd_soc_codec *codec)
1130{
1131 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
1132
1133 device_remove_file(codec->dev, &dev_attr_beep);
1134 cancel_work_sync(&cs42l56->beep_work);
1135 cs42l56->beep = NULL;
1136
1137 snd_soc_update_bits(codec, CS42L56_BEEP_TONE_CFG,
1138 CS42L56_BEEP_EN_MASK, 0);
1139}
1140
1141static int cs42l56_probe(struct snd_soc_codec *codec)
1142{
1143 cs42l56_init_beep(codec);
1144
1145 cs42l56_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1146
1147 return 0;
1148}
1149
1150static int cs42l56_remove(struct snd_soc_codec *codec)
1151{
1152 struct cs42l56_private *cs42l56 = snd_soc_codec_get_drvdata(codec);
1153
1154 cs42l56_free_beep(codec);
1155 cs42l56_set_bias_level(codec, SND_SOC_BIAS_OFF);
1156 regulator_bulk_free(ARRAY_SIZE(cs42l56->supplies), cs42l56->supplies);
1157
1158 return 0;
1159}
1160
1161static struct snd_soc_codec_driver soc_codec_dev_cs42l56 = {
1162 .probe = cs42l56_probe,
1163 .remove = cs42l56_remove,
1164 .suspend = cs42l56_suspend,
1165 .resume = cs42l56_resume,
1166 .set_bias_level = cs42l56_set_bias_level,
1167
1168 .dapm_widgets = cs42l56_dapm_widgets,
1169 .num_dapm_widgets = ARRAY_SIZE(cs42l56_dapm_widgets),
1170 .dapm_routes = cs42l56_audio_map,
1171 .num_dapm_routes = ARRAY_SIZE(cs42l56_audio_map),
1172
1173 .controls = cs42l56_snd_controls,
1174 .num_controls = ARRAY_SIZE(cs42l56_snd_controls),
1175};
1176
1177static struct regmap_config cs42l56_regmap = {
1178 .reg_bits = 8,
1179 .val_bits = 8,
1180
1181 .max_register = CS42L56_MAX_REGISTER,
1182 .reg_defaults = cs42l56_reg_defaults,
1183 .num_reg_defaults = ARRAY_SIZE(cs42l56_reg_defaults),
1184 .readable_reg = cs42l56_readable_register,
1185 .volatile_reg = cs42l56_volatile_register,
1186 .cache_type = REGCACHE_RBTREE,
1187};
1188
1189static int cs42l56_handle_of_data(struct i2c_client *i2c_client,
1190 struct cs42l56_platform_data *pdata)
1191{
1192 struct device_node *np = i2c_client->dev.of_node;
1193 u32 val32;
1194
1195 if (of_property_read_bool(np, "cirrus,ain1a-reference-cfg"))
1196 pdata->ain1a_ref_cfg = true;
1197
1198 if (of_property_read_bool(np, "cirrus,ain2a-reference-cfg"))
1199 pdata->ain2a_ref_cfg = true;
1200
1201 if (of_property_read_bool(np, "cirrus,ain1b-reference-cfg"))
1202 pdata->ain1b_ref_cfg = true;
1203
1204 if (of_property_read_bool(np, "cirrus,ain2b-reference-cfg"))
1205 pdata->ain2b_ref_cfg = true;
1206
1207 if (of_property_read_u32(np, "cirrus,micbias-lvl", &val32) >= 0)
1208 pdata->micbias_lvl = val32;
1209
1210 if (of_property_read_u32(np, "cirrus,chgfreq-divisor", &val32) >= 0)
1211 pdata->chgfreq = val32;
1212
1213 if (of_property_read_u32(np, "cirrus,adaptive-pwr-cfg", &val32) >= 0)
1214 pdata->adaptive_pwr = val32;
1215
1216 if (of_property_read_u32(np, "cirrus,hpf-left-freq", &val32) >= 0)
1217 pdata->hpfa_freq = val32;
1218
1219 if (of_property_read_u32(np, "cirrus,hpf-left-freq", &val32) >= 0)
1220 pdata->hpfb_freq = val32;
1221
1222 pdata->gpio_nreset = of_get_named_gpio(np, "cirrus,gpio-nreset", 0);
1223
1224 return 0;
1225}
1226
1227static int cs42l56_i2c_probe(struct i2c_client *i2c_client,
1228 const struct i2c_device_id *id)
1229{
1230 struct cs42l56_private *cs42l56;
1231 struct cs42l56_platform_data *pdata =
1232 dev_get_platdata(&i2c_client->dev);
1233 int ret, i;
1234 unsigned int devid = 0;
1235 unsigned int alpha_rev, metal_rev;
1236 unsigned int reg;
1237
1238 cs42l56 = devm_kzalloc(&i2c_client->dev,
1239 sizeof(struct cs42l56_private),
1240 GFP_KERNEL);
1241 if (cs42l56 == NULL)
1242 return -ENOMEM;
1243 cs42l56->dev = &i2c_client->dev;
1244
1245 cs42l56->regmap = devm_regmap_init_i2c(i2c_client, &cs42l56_regmap);
1246 if (IS_ERR(cs42l56->regmap)) {
1247 ret = PTR_ERR(cs42l56->regmap);
1248 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1249 return ret;
1250 }
1251
1252 if (pdata) {
1253 cs42l56->pdata = *pdata;
1254 } else {
1255 pdata = devm_kzalloc(&i2c_client->dev,
1256 sizeof(struct cs42l56_platform_data),
1257 GFP_KERNEL);
1258 if (!pdata) {
1259 dev_err(&i2c_client->dev,
1260 "could not allocate pdata\n");
1261 return -ENOMEM;
1262 }
1263 if (i2c_client->dev.of_node) {
1264 ret = cs42l56_handle_of_data(i2c_client,
1265 &cs42l56->pdata);
1266 if (ret != 0)
1267 return ret;
1268 }
1269 cs42l56->pdata = *pdata;
1270 }
1271
1272 if (cs42l56->pdata.gpio_nreset) {
1273 ret = gpio_request_one(cs42l56->pdata.gpio_nreset,
1274 GPIOF_OUT_INIT_HIGH, "CS42L56 /RST");
1275 if (ret < 0) {
1276 dev_err(&i2c_client->dev,
1277 "Failed to request /RST %d: %d\n",
1278 cs42l56->pdata.gpio_nreset, ret);
1279 return ret;
1280 }
1281 gpio_set_value_cansleep(cs42l56->pdata.gpio_nreset, 0);
1282 gpio_set_value_cansleep(cs42l56->pdata.gpio_nreset, 1);
1283 }
1284
1285
1286 i2c_set_clientdata(i2c_client, cs42l56);
1287
1288 for (i = 0; i < ARRAY_SIZE(cs42l56->supplies); i++)
1289 cs42l56->supplies[i].supply = cs42l56_supply_names[i];
1290
1291 ret = devm_regulator_bulk_get(&i2c_client->dev,
1292 ARRAY_SIZE(cs42l56->supplies),
1293 cs42l56->supplies);
1294 if (ret != 0) {
1295 dev_err(&i2c_client->dev,
1296 "Failed to request supplies: %d\n", ret);
1297 return ret;
1298 }
1299
1300 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l56->supplies),
1301 cs42l56->supplies);
1302 if (ret != 0) {
1303 dev_err(&i2c_client->dev,
1304 "Failed to enable supplies: %d\n", ret);
1305 return ret;
1306 }
1307
1308 regcache_cache_bypass(cs42l56->regmap, true);
1309
1310 ret = regmap_read(cs42l56->regmap, CS42L56_CHIP_ID_1, &reg);
1311 devid = reg & CS42L56_CHIP_ID_MASK;
1312 if (devid != CS42L56_DEVID) {
1313 dev_err(&i2c_client->dev,
1314 "CS42L56 Device ID (%X). Expected %X\n",
1315 devid, CS42L56_DEVID);
1316 goto err_enable;
1317 }
1318 alpha_rev = reg & CS42L56_AREV_MASK;
1319 metal_rev = reg & CS42L56_MTLREV_MASK;
1320
1321 dev_info(&i2c_client->dev, "Cirrus Logic CS42L56 ");
1322 dev_info(&i2c_client->dev, "Alpha Rev %X Metal Rev %X\n",
1323 alpha_rev, metal_rev);
1324
1325 regcache_cache_bypass(cs42l56->regmap, false);
1326
1327 if (cs42l56->pdata.ain1a_ref_cfg)
1328 regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1329 CS42L56_AIN1A_REF_MASK, 1);
1330
1331 if (cs42l56->pdata.ain1b_ref_cfg)
1332 regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1333 CS42L56_AIN1B_REF_MASK, 1);
1334
1335 if (cs42l56->pdata.ain2a_ref_cfg)
1336 regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1337 CS42L56_AIN2A_REF_MASK, 1);
1338
1339 if (cs42l56->pdata.ain2b_ref_cfg)
1340 regmap_update_bits(cs42l56->regmap, CS42L56_AIN_REFCFG_ADC_MUX,
1341 CS42L56_AIN2B_REF_MASK, 1);
1342
1343 if (cs42l56->pdata.micbias_lvl)
1344 regmap_update_bits(cs42l56->regmap, CS42L56_GAIN_BIAS_CTL,
1345 CS42L56_MIC_BIAS_MASK,
1346 cs42l56->pdata.micbias_lvl);
1347
1348 if (cs42l56->pdata.chgfreq)
1349 regmap_update_bits(cs42l56->regmap, CS42L56_CLASSH_CTL,
1350 CS42L56_CHRG_FREQ_MASK,
1351 cs42l56->pdata.chgfreq);
1352
1353 if (cs42l56->pdata.hpfb_freq)
1354 regmap_update_bits(cs42l56->regmap, CS42L56_HPF_CTL,
1355 CS42L56_HPFB_FREQ_MASK,
1356 cs42l56->pdata.hpfb_freq);
1357
1358 if (cs42l56->pdata.hpfa_freq)
1359 regmap_update_bits(cs42l56->regmap, CS42L56_HPF_CTL,
1360 CS42L56_HPFA_FREQ_MASK,
1361 cs42l56->pdata.hpfa_freq);
1362
1363 if (cs42l56->pdata.adaptive_pwr)
1364 regmap_update_bits(cs42l56->regmap, CS42L56_CLASSH_CTL,
1365 CS42L56_ADAPT_PWR_MASK,
1366 cs42l56->pdata.adaptive_pwr);
1367
1368 ret = snd_soc_register_codec(&i2c_client->dev,
1369 &soc_codec_dev_cs42l56, &cs42l56_dai, 1);
1370 if (ret < 0)
1371 return ret;
1372
1373 return 0;
1374
1375err_enable:
1376 regulator_bulk_disable(ARRAY_SIZE(cs42l56->supplies),
1377 cs42l56->supplies);
1378 return ret;
1379}
1380
1381static int cs42l56_i2c_remove(struct i2c_client *client)
1382{
1383 struct cs42l56_private *cs42l56 = i2c_get_clientdata(client);
1384
1385 snd_soc_unregister_codec(&client->dev);
1386 regulator_bulk_disable(ARRAY_SIZE(cs42l56->supplies),
1387 cs42l56->supplies);
1388 return 0;
1389}
1390
1391static const struct of_device_id cs42l56_of_match[] = {
1392 { .compatible = "cirrus,cs42l56", },
1393 { }
1394};
1395MODULE_DEVICE_TABLE(of, cs42l56_of_match);
1396
1397
1398static const struct i2c_device_id cs42l56_id[] = {
1399 { "cs42l56", 0 },
1400 { }
1401};
1402MODULE_DEVICE_TABLE(i2c, cs42l56_id);
1403
1404static struct i2c_driver cs42l56_i2c_driver = {
1405 .driver = {
1406 .name = "cs42l56",
1407 .owner = THIS_MODULE,
1408 .of_match_table = cs42l56_of_match,
1409 },
1410 .id_table = cs42l56_id,
1411 .probe = cs42l56_i2c_probe,
1412 .remove = cs42l56_i2c_remove,
1413};
1414
1415module_i2c_driver(cs42l56_i2c_driver);
1416
1417MODULE_DESCRIPTION("ASoC CS42L56 driver");
1418MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1419MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/cs42l56.h b/sound/soc/codecs/cs42l56.h
new file mode 100644
index 000000000000..5025ec9be9b2
--- /dev/null
+++ b/sound/soc/codecs/cs42l56.h
@@ -0,0 +1,177 @@
1/*
2 * cs42l52.h -- CS42L56 ALSA SoC audio driver
3 *
4 * Copyright 2014 CirrusLogic, Inc.
5 *
6 * Author: Brian Austin <brian.austin@cirrus.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#ifndef __CS42L56_H__
15#define __CS42L56_H__
16
17#define CS42L56_CHIP_ID_1 0x01
18#define CS42L56_CHIP_ID_2 0x02
19#define CS42L56_PWRCTL_1 0x03
20#define CS42L56_PWRCTL_2 0x04
21#define CS42L56_CLKCTL_1 0x05
22#define CS42L56_CLKCTL_2 0x06
23#define CS42L56_SERIAL_FMT 0x07
24#define CS42L56_CLASSH_CTL 0x08
25#define CS42L56_MISC_CTL 0x09
26#define CS42L56_INT_STATUS 0x0a
27#define CS42L56_PLAYBACK_CTL 0x0b
28#define CS42L56_DSP_MUTE_CTL 0x0c
29#define CS42L56_ADCA_MIX_VOLUME 0x0d
30#define CS42L56_ADCB_MIX_VOLUME 0x0e
31#define CS42L56_PCMA_MIX_VOLUME 0x0f
32#define CS42L56_PCMB_MIX_VOLUME 0x10
33#define CS42L56_ANAINPUT_ADV_VOLUME 0x11
34#define CS42L56_DIGINPUT_ADV_VOLUME 0x12
35#define CS42L56_MASTER_A_VOLUME 0x13
36#define CS42L56_MASTER_B_VOLUME 0x14
37#define CS42L56_BEEP_FREQ_ONTIME 0x15
38#define CS42L56_BEEP_FREQ_OFFTIME 0x16
39#define CS42L56_BEEP_TONE_CFG 0x17
40#define CS42L56_TONE_CTL 0x18
41#define CS42L56_CHAN_MIX_SWAP 0x19
42#define CS42L56_AIN_REFCFG_ADC_MUX 0x1a
43#define CS42L56_HPF_CTL 0x1b
44#define CS42L56_MISC_ADC_CTL 0x1c
45#define CS42L56_GAIN_BIAS_CTL 0x1d
46#define CS42L56_PGAA_MUX_VOLUME 0x1e
47#define CS42L56_PGAB_MUX_VOLUME 0x1f
48#define CS42L56_ADCA_ATTENUATOR 0x20
49#define CS42L56_ADCB_ATTENUATOR 0x21
50#define CS42L56_ALC_EN_ATTACK_RATE 0x22
51#define CS42L56_ALC_RELEASE_RATE 0x23
52#define CS42L56_ALC_THRESHOLD 0x24
53#define CS42L56_NOISE_GATE_CTL 0x25
54#define CS42L56_ALC_LIM_SFT_ZC 0x26
55#define CS42L56_AMUTE_HPLO_MUX 0x27
56#define CS42L56_HPA_VOLUME 0x28
57#define CS42L56_HPB_VOLUME 0x29
58#define CS42L56_LOA_VOLUME 0x2a
59#define CS42L56_LOB_VOLUME 0x2b
60#define CS42L56_LIM_THRESHOLD_CTL 0x2c
61#define CS42L56_LIM_CTL_RELEASE_RATE 0x2d
62#define CS42L56_LIM_ATTACK_RATE 0x2e
63
64/* Device ID and Rev ID Masks */
65#define CS42L56_DEVID 0x56
66#define CS42L56_CHIP_ID_MASK 0xff
67#define CS42L56_AREV_MASK 0x1c
68#define CS42L56_MTLREV_MASK 0x03
69
70/* Power bit masks */
71#define CS42L56_PDN_ALL_MASK 0x01
72#define CS42L56_PDN_ADCA_MASK 0x02
73#define CS42L56_PDN_ADCB_MASK 0x04
74#define CS42L56_PDN_CHRG_MASK 0x08
75#define CS42L56_PDN_BIAS_MASK 0x10
76#define CS42L56_PDN_VBUF_MASK 0x20
77#define CS42L56_PDN_LOA_MASK 0x03
78#define CS42L56_PDN_LOB_MASK 0x0c
79#define CS42L56_PDN_HPA_MASK 0x30
80#define CS42L56_PDN_HPB_MASK 0xc0
81
82/* serial port and clk masks */
83#define CS42L56_MASTER_MODE 0x40
84#define CS42L56_SLAVE_MODE 0
85#define CS42L56_MS_MODE_MASK 0x40
86#define CS42L56_SCLK_INV 0x20
87#define CS42L56_SCLK_INV_MASK 0x20
88#define CS42L56_SCLK_MCLK_MASK 0x18
89#define CS42L56_MCLK_PREDIV 0x04
90#define CS42L56_MCLK_PREDIV_MASK 0x04
91#define CS42L56_MCLK_DIV2 0x02
92#define CS42L56_MCLK_DIV2_MASK 0x02
93#define CS42L56_MCLK_DIS_MASK 0x01
94#define CS42L56_CLK_AUTO_MASK 0x20
95#define CS42L56_CLK_RATIO_MASK 0x1f
96#define CS42L56_DIG_FMT_I2S 0
97#define CS42L56_DIG_FMT_LEFT_J 0x08
98#define CS42L56_DIG_FMT_MASK 0x08
99
100/* Class H and misc ctl masks */
101#define CS42L56_ADAPT_PWR_MASK 0xc0
102#define CS42L56_CHRG_FREQ_MASK 0x0f
103#define CS42L56_DIG_MUX_MASK 0x80
104#define CS42L56_ANLGSFT_MASK 0x10
105#define CS42L56_ANLGZC_MASK 0x08
106#define CS42L56_DIGSFT_MASK 0x04
107#define CS42L56_FREEZE_MASK 0x01
108#define CS42L56_MIC_BIAS_MASK 0x03
109#define CS42L56_HPFA_FREQ_MASK 0x03
110#define CS42L56_HPFB_FREQ_MASK 0xc0
111#define CS42L56_AIN1A_REF_MASK 0x10
112#define CS42L56_AIN2A_REF_MASK 0x40
113#define CS42L56_AIN1B_REF_MASK 0x20
114#define CS42L56_AIN2B_REF_MASK 0x80
115
116/* Playback Capture ctl masks */
117#define CS42L56_PDN_DSP_MASK 0x80
118#define CS42L56_DEEMPH_MASK 0x40
119#define CS42L56_PLYBCK_GANG_MASK 0x10
120#define CS42L56_PCM_INV_MASK 0x0c
121#define CS42L56_MUTE_ALL 0xff
122#define CS42L56_UNMUTE 0
123#define CS42L56_ADCAMIX_MUTE_MASK 0x40
124#define CS42L56_ADCBMIX_MUTE_MASK 0x80
125#define CS42L56_PCMAMIX_MUTE_MASK 0x10
126#define CS42L56_PCMBMIX_MUTE_MASK 0x20
127#define CS42L56_MSTB_MUTE_MASK 0x02
128#define CS42L56_MSTA_MUTE_MASK 0x01
129#define CS42L56_ADCA_MUTE_MASK 0x01
130#define CS42L56_ADCB_MUTE_MASK 0x02
131#define CS42L56_HP_MUTE_MASK 0x80
132#define CS42L56_LO_MUTE_MASK 0x80
133
134/* Beep masks */
135#define CS42L56_BEEP_FREQ_MASK 0xf0
136#define CS42L56_BEEP_ONTIME_MASK 0x0f
137#define CS42L56_BEEP_OFFTIME_MASK 0xe0
138#define CS42L56_BEEP_CFG_MASK 0xc0
139#define CS42L56_BEEP_TREBCF_MASK 0x18
140#define CS42L56_BEEP_BASSCF_MASK 0x06
141#define CS42L56_BEEP_TCEN_MASK 0x01
142#define CS42L56_BEEP_RATE_SHIFT 4
143#define CS42L56_BEEP_EN_MASK 0x3f
144
145
146/* Supported MCLKS */
147#define CS42L56_MCLK_5P6448MHZ 5644800
148#define CS42L56_MCLK_6MHZ 6000000
149#define CS42L56_MCLK_6P144MHZ 6144000
150#define CS42L56_MCLK_11P2896MHZ 11289600
151#define CS42L56_MCLK_12MHZ 12000000
152#define CS42L56_MCLK_12P288MHZ 12288000
153#define CS42L56_MCLK_22P5792MHZ 22579200
154#define CS42L56_MCLK_24MHZ 24000000
155#define CS42L56_MCLK_24P576MHZ 24576000
156
157/* Clock ratios */
158#define CS42L56_MCLK_LRCLK_128 0x08
159#define CS42L56_MCLK_LRCLK_125 0x09
160#define CS42L56_MCLK_LRCLK_136 0x0b
161#define CS42L56_MCLK_LRCLK_192 0x0c
162#define CS42L56_MCLK_LRCLK_187P5 0x0d
163#define CS42L56_MCLK_LRCLK_256 0x10
164#define CS42L56_MCLK_LRCLK_250 0x11
165#define CS42L56_MCLK_LRCLK_272 0x13
166#define CS42L56_MCLK_LRCLK_384 0x14
167#define CS42L56_MCLK_LRCLK_375 0x15
168#define CS42L56_MCLK_LRCLK_512 0x18
169#define CS42L56_MCLK_LRCLK_500 0x19
170#define CS42L56_MCLK_LRCLK_544 0x1b
171#define CS42L56_MCLK_LRCLK_750 0x1c
172#define CS42L56_MCLK_LRCLK_768 0x1d
173
174
175#define CS42L56_MAX_REGISTER 0x34
176
177#endif
diff --git a/sound/soc/codecs/cs42l73.c b/sound/soc/codecs/cs42l73.c
index 0ee60a19a263..ae3717992d56 100644
--- a/sound/soc/codecs/cs42l73.c
+++ b/sound/soc/codecs/cs42l73.c
@@ -1443,8 +1443,10 @@ static int cs42l73_i2c_probe(struct i2c_client *i2c_client,
1443 i2c_set_clientdata(i2c_client, cs42l73); 1443 i2c_set_clientdata(i2c_client, cs42l73);
1444 1444
1445 if (cs42l73->pdata.reset_gpio) { 1445 if (cs42l73->pdata.reset_gpio) {
1446 ret = gpio_request_one(cs42l73->pdata.reset_gpio, 1446 ret = devm_gpio_request_one(&i2c_client->dev,
1447 GPIOF_OUT_INIT_HIGH, "CS42L73 /RST"); 1447 cs42l73->pdata.reset_gpio,
1448 GPIOF_OUT_INIT_HIGH,
1449 "CS42L73 /RST");
1448 if (ret < 0) { 1450 if (ret < 0) {
1449 dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n", 1451 dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n",
1450 cs42l73->pdata.reset_gpio, ret); 1452 cs42l73->pdata.reset_gpio, ret);
diff --git a/sound/soc/codecs/cs42xx8.c b/sound/soc/codecs/cs42xx8.c
index 85020322eee7..a25bc6061a30 100644
--- a/sound/soc/codecs/cs42xx8.c
+++ b/sound/soc/codecs/cs42xx8.c
@@ -248,8 +248,7 @@ static int cs42xx8_hw_params(struct snd_pcm_substream *substream,
248 struct snd_pcm_hw_params *params, 248 struct snd_pcm_hw_params *params,
249 struct snd_soc_dai *dai) 249 struct snd_soc_dai *dai)
250{ 250{
251 struct snd_soc_pcm_runtime *rtd = substream->private_data; 251 struct snd_soc_codec *codec = dai->codec;
252 struct snd_soc_codec *codec = rtd->codec;
253 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec); 252 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec);
254 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 253 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
255 u32 ratio = cs42xx8->sysclk / params_rate(params); 254 u32 ratio = cs42xx8->sysclk / params_rate(params);
diff --git a/sound/soc/codecs/da7210.c b/sound/soc/codecs/da7210.c
index 137e8ebc092c..21810e5f3321 100644
--- a/sound/soc/codecs/da7210.c
+++ b/sound/soc/codecs/da7210.c
@@ -335,7 +335,7 @@ static SOC_ENUM_SINGLE_DECL(da7210_hp_mode_sel,
335static int da7210_put_alc_sw(struct snd_kcontrol *kcontrol, 335static int da7210_put_alc_sw(struct snd_kcontrol *kcontrol,
336 struct snd_ctl_elem_value *ucontrol) 336 struct snd_ctl_elem_value *ucontrol)
337{ 337{
338 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 338 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
339 339
340 if (ucontrol->value.integer.value[0]) { 340 if (ucontrol->value.integer.value[0]) {
341 /* Check if noise suppression is enabled */ 341 /* Check if noise suppression is enabled */
@@ -358,7 +358,7 @@ static int da7210_put_alc_sw(struct snd_kcontrol *kcontrol,
358static int da7210_put_noise_sup_sw(struct snd_kcontrol *kcontrol, 358static int da7210_put_noise_sup_sw(struct snd_kcontrol *kcontrol,
359 struct snd_ctl_elem_value *ucontrol) 359 struct snd_ctl_elem_value *ucontrol)
360{ 360{
361 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 361 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
362 u8 val; 362 u8 val;
363 363
364 if (ucontrol->value.integer.value[0]) { 364 if (ucontrol->value.integer.value[0]) {
diff --git a/sound/soc/codecs/da7213.c b/sound/soc/codecs/da7213.c
index 738fa18a50d2..9ec577f0edb4 100644
--- a/sound/soc/codecs/da7213.c
+++ b/sound/soc/codecs/da7213.c
@@ -345,7 +345,7 @@ static void da7213_alc_calib(struct snd_soc_codec *codec)
345static int da7213_put_mixin_gain(struct snd_kcontrol *kcontrol, 345static int da7213_put_mixin_gain(struct snd_kcontrol *kcontrol,
346 struct snd_ctl_elem_value *ucontrol) 346 struct snd_ctl_elem_value *ucontrol)
347{ 347{
348 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 348 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
349 struct da7213_priv *da7213 = snd_soc_codec_get_drvdata(codec); 349 struct da7213_priv *da7213 = snd_soc_codec_get_drvdata(codec);
350 int ret; 350 int ret;
351 351
@@ -361,7 +361,7 @@ static int da7213_put_mixin_gain(struct snd_kcontrol *kcontrol,
361static int da7213_put_alc_sw(struct snd_kcontrol *kcontrol, 361static int da7213_put_alc_sw(struct snd_kcontrol *kcontrol,
362 struct snd_ctl_elem_value *ucontrol) 362 struct snd_ctl_elem_value *ucontrol)
363{ 363{
364 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 364 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
365 struct da7213_priv *da7213 = snd_soc_codec_get_drvdata(codec); 365 struct da7213_priv *da7213 = snd_soc_codec_get_drvdata(codec);
366 366
367 /* Force ALC offset calibration if enabling ALC */ 367 /* Force ALC offset calibration if enabling ALC */
diff --git a/sound/soc/codecs/da732x.c b/sound/soc/codecs/da732x.c
index 48f3fef68484..2fae31cb0067 100644
--- a/sound/soc/codecs/da732x.c
+++ b/sound/soc/codecs/da732x.c
@@ -332,7 +332,7 @@ static SOC_ENUM_SINGLE_DECL(da732x_adc2_voice_filter_enum,
332static int da732x_hpf_set(struct snd_kcontrol *kcontrol, 332static int da732x_hpf_set(struct snd_kcontrol *kcontrol,
333 struct snd_ctl_elem_value *ucontrol) 333 struct snd_ctl_elem_value *ucontrol)
334{ 334{
335 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 335 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
336 struct soc_enum *enum_ctrl = (struct soc_enum *)kcontrol->private_value; 336 struct soc_enum *enum_ctrl = (struct soc_enum *)kcontrol->private_value;
337 unsigned int reg = enum_ctrl->reg; 337 unsigned int reg = enum_ctrl->reg;
338 unsigned int sel = ucontrol->value.integer.value[0]; 338 unsigned int sel = ucontrol->value.integer.value[0];
@@ -360,7 +360,7 @@ static int da732x_hpf_set(struct snd_kcontrol *kcontrol,
360static int da732x_hpf_get(struct snd_kcontrol *kcontrol, 360static int da732x_hpf_get(struct snd_kcontrol *kcontrol,
361 struct snd_ctl_elem_value *ucontrol) 361 struct snd_ctl_elem_value *ucontrol)
362{ 362{
363 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 363 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
364 struct soc_enum *enum_ctrl = (struct soc_enum *)kcontrol->private_value; 364 struct soc_enum *enum_ctrl = (struct soc_enum *)kcontrol->private_value;
365 unsigned int reg = enum_ctrl->reg; 365 unsigned int reg = enum_ctrl->reg;
366 int val; 366 int val;
diff --git a/sound/soc/codecs/da9055.c b/sound/soc/codecs/da9055.c
index 4ff06b50fbba..ad19cc56702b 100644
--- a/sound/soc/codecs/da9055.c
+++ b/sound/soc/codecs/da9055.c
@@ -484,7 +484,7 @@ static int da9055_get_alc_data(struct snd_soc_codec *codec, u8 reg_val)
484static int da9055_put_alc_sw(struct snd_kcontrol *kcontrol, 484static int da9055_put_alc_sw(struct snd_kcontrol *kcontrol,
485 struct snd_ctl_elem_value *ucontrol) 485 struct snd_ctl_elem_value *ucontrol)
486{ 486{
487 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 487 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
488 u8 reg_val, adc_left, adc_right, mic_left, mic_right; 488 u8 reg_val, adc_left, adc_right, mic_left, mic_right;
489 int avg_left_data, avg_right_data, offset_l, offset_r; 489 int avg_left_data, avg_right_data, offset_l, offset_r;
490 490
diff --git a/sound/soc/codecs/hdmi.c b/sound/soc/codecs/hdmi.c
index 9cb1c7d3e1dc..1087fd5f9917 100644
--- a/sound/soc/codecs/hdmi.c
+++ b/sound/soc/codecs/hdmi.c
@@ -20,6 +20,7 @@
20 */ 20 */
21#include <linux/module.h> 21#include <linux/module.h>
22#include <sound/soc.h> 22#include <sound/soc.h>
23#include <linux/of.h>
23#include <linux/of_device.h> 24#include <linux/of_device.h>
24 25
25#define DRV_NAME "hdmi-audio-codec" 26#define DRV_NAME "hdmi-audio-codec"
diff --git a/sound/soc/codecs/lm4857.c b/sound/soc/codecs/lm4857.c
index 4f048db9f55f..a924bb9d7886 100644
--- a/sound/soc/codecs/lm4857.c
+++ b/sound/soc/codecs/lm4857.c
@@ -49,7 +49,7 @@ static const struct reg_default lm4857_default_regs[] = {
49static int lm4857_get_mode(struct snd_kcontrol *kcontrol, 49static int lm4857_get_mode(struct snd_kcontrol *kcontrol,
50 struct snd_ctl_elem_value *ucontrol) 50 struct snd_ctl_elem_value *ucontrol)
51{ 51{
52 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 52 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
53 struct lm4857 *lm4857 = snd_soc_codec_get_drvdata(codec); 53 struct lm4857 *lm4857 = snd_soc_codec_get_drvdata(codec);
54 54
55 ucontrol->value.integer.value[0] = lm4857->mode; 55 ucontrol->value.integer.value[0] = lm4857->mode;
@@ -60,7 +60,7 @@ static int lm4857_get_mode(struct snd_kcontrol *kcontrol,
60static int lm4857_set_mode(struct snd_kcontrol *kcontrol, 60static int lm4857_set_mode(struct snd_kcontrol *kcontrol,
61 struct snd_ctl_elem_value *ucontrol) 61 struct snd_ctl_elem_value *ucontrol)
62{ 62{
63 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 63 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
64 struct lm4857 *lm4857 = snd_soc_codec_get_drvdata(codec); 64 struct lm4857 *lm4857 = snd_soc_codec_get_drvdata(codec);
65 uint8_t value = ucontrol->value.integer.value[0]; 65 uint8_t value = ucontrol->value.integer.value[0];
66 66
diff --git a/sound/soc/codecs/max9768.c b/sound/soc/codecs/max9768.c
index ec481fc428c7..e1c196a41930 100644
--- a/sound/soc/codecs/max9768.c
+++ b/sound/soc/codecs/max9768.c
@@ -43,7 +43,7 @@ static struct reg_default max9768_default_regs[] = {
43static int max9768_get_gpio(struct snd_kcontrol *kcontrol, 43static int max9768_get_gpio(struct snd_kcontrol *kcontrol,
44 struct snd_ctl_elem_value *ucontrol) 44 struct snd_ctl_elem_value *ucontrol)
45{ 45{
46 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 46 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
47 struct max9768 *max9768 = snd_soc_codec_get_drvdata(codec); 47 struct max9768 *max9768 = snd_soc_codec_get_drvdata(codec);
48 int val = gpio_get_value_cansleep(max9768->mute_gpio); 48 int val = gpio_get_value_cansleep(max9768->mute_gpio);
49 49
@@ -55,7 +55,7 @@ static int max9768_get_gpio(struct snd_kcontrol *kcontrol,
55static int max9768_set_gpio(struct snd_kcontrol *kcontrol, 55static int max9768_set_gpio(struct snd_kcontrol *kcontrol,
56 struct snd_ctl_elem_value *ucontrol) 56 struct snd_ctl_elem_value *ucontrol)
57{ 57{
58 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 58 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
59 struct max9768 *max9768 = snd_soc_codec_get_drvdata(codec); 59 struct max9768 *max9768 = snd_soc_codec_get_drvdata(codec);
60 60
61 gpio_set_value_cansleep(max9768->mute_gpio, !ucontrol->value.integer.value[0]); 61 gpio_set_value_cansleep(max9768->mute_gpio, !ucontrol->value.integer.value[0]);
diff --git a/sound/soc/codecs/max98088.c b/sound/soc/codecs/max98088.c
index ef7cf89f5623..9134982807b5 100644
--- a/sound/soc/codecs/max98088.c
+++ b/sound/soc/codecs/max98088.c
@@ -635,7 +635,7 @@ static SOC_ENUM_SINGLE_DECL(max98088_dai1_adc_filter_enum,
635static int max98088_mic1pre_set(struct snd_kcontrol *kcontrol, 635static int max98088_mic1pre_set(struct snd_kcontrol *kcontrol,
636 struct snd_ctl_elem_value *ucontrol) 636 struct snd_ctl_elem_value *ucontrol)
637{ 637{
638 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 638 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
639 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 639 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
640 unsigned int sel = ucontrol->value.integer.value[0]; 640 unsigned int sel = ucontrol->value.integer.value[0];
641 641
@@ -649,7 +649,7 @@ static int max98088_mic1pre_set(struct snd_kcontrol *kcontrol,
649static int max98088_mic1pre_get(struct snd_kcontrol *kcontrol, 649static int max98088_mic1pre_get(struct snd_kcontrol *kcontrol,
650 struct snd_ctl_elem_value *ucontrol) 650 struct snd_ctl_elem_value *ucontrol)
651{ 651{
652 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 652 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
653 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 653 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
654 654
655 ucontrol->value.integer.value[0] = max98088->mic1pre; 655 ucontrol->value.integer.value[0] = max98088->mic1pre;
@@ -659,7 +659,7 @@ static int max98088_mic1pre_get(struct snd_kcontrol *kcontrol,
659static int max98088_mic2pre_set(struct snd_kcontrol *kcontrol, 659static int max98088_mic2pre_set(struct snd_kcontrol *kcontrol,
660 struct snd_ctl_elem_value *ucontrol) 660 struct snd_ctl_elem_value *ucontrol)
661{ 661{
662 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 662 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
663 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 663 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
664 unsigned int sel = ucontrol->value.integer.value[0]; 664 unsigned int sel = ucontrol->value.integer.value[0];
665 665
@@ -673,7 +673,7 @@ static int max98088_mic2pre_set(struct snd_kcontrol *kcontrol,
673static int max98088_mic2pre_get(struct snd_kcontrol *kcontrol, 673static int max98088_mic2pre_get(struct snd_kcontrol *kcontrol,
674 struct snd_ctl_elem_value *ucontrol) 674 struct snd_ctl_elem_value *ucontrol)
675{ 675{
676 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 676 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
677 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 677 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
678 678
679 ucontrol->value.integer.value[0] = max98088->mic2pre; 679 ucontrol->value.integer.value[0] = max98088->mic2pre;
@@ -1750,7 +1750,7 @@ static void max98088_setup_eq2(struct snd_soc_codec *codec)
1750static int max98088_put_eq_enum(struct snd_kcontrol *kcontrol, 1750static int max98088_put_eq_enum(struct snd_kcontrol *kcontrol,
1751 struct snd_ctl_elem_value *ucontrol) 1751 struct snd_ctl_elem_value *ucontrol)
1752{ 1752{
1753 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1753 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1754 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1754 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1755 struct max98088_pdata *pdata = max98088->pdata; 1755 struct max98088_pdata *pdata = max98088->pdata;
1756 int channel = max98088_get_channel(codec, kcontrol->id.name); 1756 int channel = max98088_get_channel(codec, kcontrol->id.name);
@@ -1782,7 +1782,7 @@ static int max98088_put_eq_enum(struct snd_kcontrol *kcontrol,
1782static int max98088_get_eq_enum(struct snd_kcontrol *kcontrol, 1782static int max98088_get_eq_enum(struct snd_kcontrol *kcontrol,
1783 struct snd_ctl_elem_value *ucontrol) 1783 struct snd_ctl_elem_value *ucontrol)
1784{ 1784{
1785 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1785 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1786 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1786 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1787 int channel = max98088_get_channel(codec, kcontrol->id.name); 1787 int channel = max98088_get_channel(codec, kcontrol->id.name);
1788 struct max98088_cdata *cdata; 1788 struct max98088_cdata *cdata;
diff --git a/sound/soc/codecs/max98090.c b/sound/soc/codecs/max98090.c
index f7b0b37aa858..f5fccc7a8e89 100644
--- a/sound/soc/codecs/max98090.c
+++ b/sound/soc/codecs/max98090.c
@@ -11,10 +11,13 @@
11#include <linux/delay.h> 11#include <linux/delay.h>
12#include <linux/i2c.h> 12#include <linux/i2c.h>
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/of.h>
14#include <linux/pm.h> 15#include <linux/pm.h>
15#include <linux/pm_runtime.h> 16#include <linux/pm_runtime.h>
16#include <linux/regmap.h> 17#include <linux/regmap.h>
17#include <linux/slab.h> 18#include <linux/slab.h>
19#include <linux/acpi.h>
20#include <linux/clk.h>
18#include <sound/jack.h> 21#include <sound/jack.h>
19#include <sound/pcm.h> 22#include <sound/pcm.h>
20#include <sound/pcm_params.h> 23#include <sound/pcm_params.h>
@@ -255,6 +258,7 @@ static struct reg_default max98090_reg[] = {
255static bool max98090_volatile_register(struct device *dev, unsigned int reg) 258static bool max98090_volatile_register(struct device *dev, unsigned int reg)
256{ 259{
257 switch (reg) { 260 switch (reg) {
261 case M98090_REG_SOFTWARE_RESET:
258 case M98090_REG_DEVICE_STATUS: 262 case M98090_REG_DEVICE_STATUS:
259 case M98090_REG_JACK_STATUS: 263 case M98090_REG_JACK_STATUS:
260 case M98090_REG_REVISION_ID: 264 case M98090_REG_REVISION_ID:
@@ -389,6 +393,7 @@ static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv, -1500, 100, 0);
389static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0); 393static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
390static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0); 394static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
391static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0); 395static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
396static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0);
392 397
393static const unsigned int max98090_mixout_tlv[] = { 398static const unsigned int max98090_mixout_tlv[] = {
394 TLV_DB_RANGE_HEAD(2), 399 TLV_DB_RANGE_HEAD(2),
@@ -426,7 +431,7 @@ static const unsigned int max98090_rcv_lout_tlv[] = {
426static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol, 431static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
427 struct snd_ctl_elem_value *ucontrol) 432 struct snd_ctl_elem_value *ucontrol)
428{ 433{
429 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 434 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
430 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 435 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
431 struct soc_mixer_control *mc = 436 struct soc_mixer_control *mc =
432 (struct soc_mixer_control *)kcontrol->private_value; 437 (struct soc_mixer_control *)kcontrol->private_value;
@@ -466,7 +471,7 @@ static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
466static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol, 471static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
467 struct snd_ctl_elem_value *ucontrol) 472 struct snd_ctl_elem_value *ucontrol)
468{ 473{
469 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 474 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
470 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 475 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
471 struct soc_mixer_control *mc = 476 struct soc_mixer_control *mc =
472 (struct soc_mixer_control *)kcontrol->private_value; 477 (struct soc_mixer_control *)kcontrol->private_value;
@@ -665,7 +670,7 @@ static const struct snd_kcontrol_new max98090_snd_controls[] = {
665 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume", 670 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
666 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT, 671 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
667 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv, 672 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
668 max98090_put_enab_tlv, max98090_micboost_tlv), 673 max98090_put_enab_tlv, max98090_sdg_tlv),
669 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL, 674 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
670 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0, 675 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
671 max98090_dvg_tlv), 676 max98090_dvg_tlv),
@@ -875,7 +880,7 @@ static const char *dmic_mux_text[] = { "ADC", "DMIC" };
875static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text); 880static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text);
876 881
877static const struct snd_kcontrol_new max98090_dmic_mux = 882static const struct snd_kcontrol_new max98090_dmic_mux =
878 SOC_DAPM_ENUM_VIRT("DMIC Mux", dmic_mux_enum); 883 SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum);
879 884
880static const char *max98090_micpre_text[] = { "Off", "On" }; 885static const char *max98090_micpre_text[] = { "Off", "On" };
881 886
@@ -1175,8 +1180,7 @@ static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = {
1175 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM, 1180 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM,
1176 0, 0, &max98090_mic2_mux), 1181 0, 0, &max98090_mic2_mux),
1177 1182
1178 SND_SOC_DAPM_VIRT_MUX("DMIC Mux", SND_SOC_NOPM, 1183 SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM, 0, 0, &max98090_dmic_mux),
1179 0, 0, &max98090_dmic_mux),
1180 1184
1181 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL, 1185 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
1182 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event, 1186 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
@@ -1544,19 +1548,19 @@ static const int lrclk_rates[] = {
1544}; 1548};
1545 1549
1546static const int user_pclk_rates[] = { 1550static const int user_pclk_rates[] = {
1547 13000000, 13000000 1551 13000000, 13000000, 19200000, 19200000,
1548}; 1552};
1549 1553
1550static const int user_lrclk_rates[] = { 1554static const int user_lrclk_rates[] = {
1551 44100, 48000 1555 44100, 48000, 44100, 48000,
1552}; 1556};
1553 1557
1554static const unsigned long long ni_value[] = { 1558static const unsigned long long ni_value[] = {
1555 3528, 768 1559 3528, 768, 441, 8
1556}; 1560};
1557 1561
1558static const unsigned long long mi_value[] = { 1562static const unsigned long long mi_value[] = {
1559 8125, 1625 1563 8125, 1625, 1500, 25
1560}; 1564};
1561 1565
1562static void max98090_configure_bclk(struct snd_soc_codec *codec) 1566static void max98090_configure_bclk(struct snd_soc_codec *codec)
@@ -1673,6 +1677,7 @@ static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
1673 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00); 1677 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
1674 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1678 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1675 M98090_USE_M1_MASK, 0); 1679 M98090_USE_M1_MASK, 0);
1680 max98090->master = false;
1676 break; 1681 break;
1677 case SND_SOC_DAIFMT_CBM_CFM: 1682 case SND_SOC_DAIFMT_CBM_CFM:
1678 /* Set to master mode */ 1683 /* Set to master mode */
@@ -1689,6 +1694,7 @@ static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
1689 regval |= M98090_MAS_MASK | 1694 regval |= M98090_MAS_MASK |
1690 M98090_BSEL_32; 1695 M98090_BSEL_32;
1691 } 1696 }
1697 max98090->master = true;
1692 break; 1698 break;
1693 case SND_SOC_DAIFMT_CBS_CFM: 1699 case SND_SOC_DAIFMT_CBS_CFM:
1694 case SND_SOC_DAIFMT_CBM_CFS: 1700 case SND_SOC_DAIFMT_CBM_CFS:
@@ -1792,16 +1798,22 @@ static int max98090_set_bias_level(struct snd_soc_codec *codec,
1792 1798
1793 switch (level) { 1799 switch (level) {
1794 case SND_SOC_BIAS_ON: 1800 case SND_SOC_BIAS_ON:
1795 if (max98090->jack_state == M98090_JACK_STATE_HEADSET) {
1796 /*
1797 * Set to normal bias level.
1798 */
1799 snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE,
1800 M98090_MBVSEL_MASK, M98090_MBVSEL_2V8);
1801 }
1802 break; 1801 break;
1803 1802
1804 case SND_SOC_BIAS_PREPARE: 1803 case SND_SOC_BIAS_PREPARE:
1804 /*
1805 * SND_SOC_BIAS_PREPARE is called while preparing for a
1806 * transition to ON or away from ON. If current bias_level
1807 * is SND_SOC_BIAS_ON, then it is preparing for a transition
1808 * away from ON. Disable the clock in that case, otherwise
1809 * enable it.
1810 */
1811 if (!IS_ERR(max98090->mclk)) {
1812 if (codec->dapm.bias_level == SND_SOC_BIAS_ON)
1813 clk_disable_unprepare(max98090->mclk);
1814 else
1815 clk_prepare_enable(max98090->mclk);
1816 }
1805 break; 1817 break;
1806 1818
1807 case SND_SOC_BIAS_STANDBY: 1819 case SND_SOC_BIAS_STANDBY:
@@ -1872,7 +1884,8 @@ static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
1872 return -EINVAL; 1884 return -EINVAL;
1873 } 1885 }
1874 1886
1875 max98090_configure_bclk(codec); 1887 if (max98090->master)
1888 max98090_configure_bclk(codec);
1876 1889
1877 cdata->rate = max98090->lrclk; 1890 cdata->rate = max98090->lrclk;
1878 1891
@@ -1930,6 +1943,11 @@ static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
1930 if (freq == max98090->sysclk) 1943 if (freq == max98090->sysclk)
1931 return 0; 1944 return 0;
1932 1945
1946 if (!IS_ERR(max98090->mclk)) {
1947 freq = clk_round_rate(max98090->mclk, freq);
1948 clk_set_rate(max98090->mclk, freq);
1949 }
1950
1933 /* Setup clocks for slave mode, and using the PLL 1951 /* Setup clocks for slave mode, and using the PLL
1934 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 1952 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1935 * 0x02 (when master clk is 20MHz to 40MHz).. 1953 * 0x02 (when master clk is 20MHz to 40MHz)..
@@ -1951,8 +1969,6 @@ static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
1951 1969
1952 max98090->sysclk = freq; 1970 max98090->sysclk = freq;
1953 1971
1954 max98090_configure_bclk(codec);
1955
1956 return 0; 1972 return 0;
1957} 1973}
1958 1974
@@ -2216,6 +2232,10 @@ static int max98090_probe(struct snd_soc_codec *codec)
2216 2232
2217 dev_dbg(codec->dev, "max98090_probe\n"); 2233 dev_dbg(codec->dev, "max98090_probe\n");
2218 2234
2235 max98090->mclk = devm_clk_get(codec->dev, "mclk");
2236 if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER)
2237 return -EPROBE_DEFER;
2238
2219 max98090->codec = codec; 2239 max98090->codec = codec;
2220 2240
2221 /* Reset the codec, the DSP core, and disable all interrupts */ 2241 /* Reset the codec, the DSP core, and disable all interrupts */
@@ -2224,6 +2244,7 @@ static int max98090_probe(struct snd_soc_codec *codec)
2224 /* Initialize private data */ 2244 /* Initialize private data */
2225 2245
2226 max98090->sysclk = (unsigned)-1; 2246 max98090->sysclk = (unsigned)-1;
2247 max98090->master = false;
2227 2248
2228 cdata = &max98090->dai[0]; 2249 cdata = &max98090->dai[0];
2229 cdata->rate = (unsigned)-1; 2250 cdata->rate = (unsigned)-1;
@@ -2293,6 +2314,9 @@ static int max98090_probe(struct snd_soc_codec *codec)
2293 snd_soc_write(codec, M98090_REG_BIAS_CONTROL, 2314 snd_soc_write(codec, M98090_REG_BIAS_CONTROL,
2294 M98090_VCM_MODE_MASK); 2315 M98090_VCM_MODE_MASK);
2295 2316
2317 snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE,
2318 M98090_MBVSEL_MASK, M98090_MBVSEL_2V8);
2319
2296 max98090_handle_pdata(codec); 2320 max98090_handle_pdata(codec);
2297 2321
2298 max98090_add_widgets(codec); 2322 max98090_add_widgets(codec);
@@ -2329,9 +2353,11 @@ static const struct regmap_config max98090_regmap = {
2329}; 2353};
2330 2354
2331static int max98090_i2c_probe(struct i2c_client *i2c, 2355static int max98090_i2c_probe(struct i2c_client *i2c,
2332 const struct i2c_device_id *id) 2356 const struct i2c_device_id *i2c_id)
2333{ 2357{
2334 struct max98090_priv *max98090; 2358 struct max98090_priv *max98090;
2359 const struct acpi_device_id *acpi_id;
2360 kernel_ulong_t driver_data = 0;
2335 int ret; 2361 int ret;
2336 2362
2337 pr_debug("max98090_i2c_probe\n"); 2363 pr_debug("max98090_i2c_probe\n");
@@ -2341,7 +2367,19 @@ static int max98090_i2c_probe(struct i2c_client *i2c,
2341 if (max98090 == NULL) 2367 if (max98090 == NULL)
2342 return -ENOMEM; 2368 return -ENOMEM;
2343 2369
2344 max98090->devtype = id->driver_data; 2370 if (ACPI_HANDLE(&i2c->dev)) {
2371 acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table,
2372 &i2c->dev);
2373 if (!acpi_id) {
2374 dev_err(&i2c->dev, "No driver data\n");
2375 return -EINVAL;
2376 }
2377 driver_data = acpi_id->driver_data;
2378 } else if (i2c_id) {
2379 driver_data = i2c_id->driver_data;
2380 }
2381
2382 max98090->devtype = driver_data;
2345 i2c_set_clientdata(i2c, max98090); 2383 i2c_set_clientdata(i2c, max98090);
2346 max98090->pdata = i2c->dev.platform_data; 2384 max98090->pdata = i2c->dev.platform_data;
2347 max98090->irq = i2c->irq; 2385 max98090->irq = i2c->irq;
@@ -2373,6 +2411,8 @@ static int max98090_runtime_resume(struct device *dev)
2373 2411
2374 regcache_cache_only(max98090->regmap, false); 2412 regcache_cache_only(max98090->regmap, false);
2375 2413
2414 max98090_reset(max98090);
2415
2376 regcache_sync(max98090->regmap); 2416 regcache_sync(max98090->regmap);
2377 2417
2378 return 0; 2418 return 0;
@@ -2388,9 +2428,34 @@ static int max98090_runtime_suspend(struct device *dev)
2388} 2428}
2389#endif 2429#endif
2390 2430
2431#ifdef CONFIG_PM
2432static int max98090_resume(struct device *dev)
2433{
2434 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2435 unsigned int status;
2436
2437 regcache_mark_dirty(max98090->regmap);
2438
2439 max98090_reset(max98090);
2440
2441 /* clear IRQ status */
2442 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2443
2444 regcache_sync(max98090->regmap);
2445
2446 return 0;
2447}
2448
2449static int max98090_suspend(struct device *dev)
2450{
2451 return 0;
2452}
2453#endif
2454
2391static const struct dev_pm_ops max98090_pm = { 2455static const struct dev_pm_ops max98090_pm = {
2392 SET_RUNTIME_PM_OPS(max98090_runtime_suspend, 2456 SET_RUNTIME_PM_OPS(max98090_runtime_suspend,
2393 max98090_runtime_resume, NULL) 2457 max98090_runtime_resume, NULL)
2458 SET_SYSTEM_SLEEP_PM_OPS(max98090_suspend, max98090_resume)
2394}; 2459};
2395 2460
2396static const struct i2c_device_id max98090_i2c_id[] = { 2461static const struct i2c_device_id max98090_i2c_id[] = {
@@ -2405,12 +2470,21 @@ static const struct of_device_id max98090_of_match[] = {
2405}; 2470};
2406MODULE_DEVICE_TABLE(of, max98090_of_match); 2471MODULE_DEVICE_TABLE(of, max98090_of_match);
2407 2472
2473#ifdef CONFIG_ACPI
2474static struct acpi_device_id max98090_acpi_match[] = {
2475 { "193C9890", MAX98090 },
2476 { }
2477};
2478MODULE_DEVICE_TABLE(acpi, max98090_acpi_match);
2479#endif
2480
2408static struct i2c_driver max98090_i2c_driver = { 2481static struct i2c_driver max98090_i2c_driver = {
2409 .driver = { 2482 .driver = {
2410 .name = "max98090", 2483 .name = "max98090",
2411 .owner = THIS_MODULE, 2484 .owner = THIS_MODULE,
2412 .pm = &max98090_pm, 2485 .pm = &max98090_pm,
2413 .of_match_table = of_match_ptr(max98090_of_match), 2486 .of_match_table = of_match_ptr(max98090_of_match),
2487 .acpi_match_table = ACPI_PTR(max98090_acpi_match),
2414 }, 2488 },
2415 .probe = max98090_i2c_probe, 2489 .probe = max98090_i2c_probe,
2416 .remove = max98090_i2c_remove, 2490 .remove = max98090_i2c_remove,
diff --git a/sound/soc/codecs/max98090.h b/sound/soc/codecs/max98090.h
index 1a4e2334a7b2..cf1b6062ba8c 100644
--- a/sound/soc/codecs/max98090.h
+++ b/sound/soc/codecs/max98090.h
@@ -1524,6 +1524,7 @@ struct max98090_priv {
1524 struct snd_soc_codec *codec; 1524 struct snd_soc_codec *codec;
1525 enum max98090_type devtype; 1525 enum max98090_type devtype;
1526 struct max98090_pdata *pdata; 1526 struct max98090_pdata *pdata;
1527 struct clk *mclk;
1527 unsigned int sysclk; 1528 unsigned int sysclk;
1528 unsigned int bclk; 1529 unsigned int bclk;
1529 unsigned int lrclk; 1530 unsigned int lrclk;
@@ -1540,6 +1541,7 @@ struct max98090_priv {
1540 unsigned int pa2en; 1541 unsigned int pa2en;
1541 unsigned int extmic_mux; 1542 unsigned int extmic_mux;
1542 unsigned int sidetone; 1543 unsigned int sidetone;
1544 bool master;
1543}; 1545};
1544 1546
1545int max98090_mic_detect(struct snd_soc_codec *codec, 1547int max98090_mic_detect(struct snd_soc_codec *codec,
diff --git a/sound/soc/codecs/max98095.c b/sound/soc/codecs/max98095.c
index 03f0536e6f61..89ec00424880 100644
--- a/sound/soc/codecs/max98095.c
+++ b/sound/soc/codecs/max98095.c
@@ -15,6 +15,7 @@
15#include <linux/delay.h> 15#include <linux/delay.h>
16#include <linux/pm.h> 16#include <linux/pm.h>
17#include <linux/i2c.h> 17#include <linux/i2c.h>
18#include <linux/clk.h>
18#include <sound/core.h> 19#include <sound/core.h>
19#include <sound/pcm.h> 20#include <sound/pcm.h>
20#include <sound/pcm_params.h> 21#include <sound/pcm_params.h>
@@ -42,6 +43,7 @@ struct max98095_priv {
42 struct regmap *regmap; 43 struct regmap *regmap;
43 enum max98095_type devtype; 44 enum max98095_type devtype;
44 struct max98095_pdata *pdata; 45 struct max98095_pdata *pdata;
46 struct clk *mclk;
45 unsigned int sysclk; 47 unsigned int sysclk;
46 struct max98095_cdata dai[3]; 48 struct max98095_cdata dai[3];
47 const char **eq_texts; 49 const char **eq_texts;
@@ -612,7 +614,7 @@ static SOC_ENUM_SINGLE_DECL(max98095_dai3_dac_filter_enum,
612static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol, 614static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol,
613 struct snd_ctl_elem_value *ucontrol) 615 struct snd_ctl_elem_value *ucontrol)
614{ 616{
615 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 617 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
616 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 618 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
617 unsigned int sel = ucontrol->value.integer.value[0]; 619 unsigned int sel = ucontrol->value.integer.value[0];
618 620
@@ -626,7 +628,7 @@ static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol,
626static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol, 628static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol,
627 struct snd_ctl_elem_value *ucontrol) 629 struct snd_ctl_elem_value *ucontrol)
628{ 630{
629 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 631 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
630 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 632 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
631 633
632 ucontrol->value.integer.value[0] = max98095->mic1pre; 634 ucontrol->value.integer.value[0] = max98095->mic1pre;
@@ -636,7 +638,7 @@ static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol,
636static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol, 638static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol,
637 struct snd_ctl_elem_value *ucontrol) 639 struct snd_ctl_elem_value *ucontrol)
638{ 640{
639 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 641 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
640 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 642 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
641 unsigned int sel = ucontrol->value.integer.value[0]; 643 unsigned int sel = ucontrol->value.integer.value[0];
642 644
@@ -650,7 +652,7 @@ static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol,
650static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol, 652static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol,
651 struct snd_ctl_elem_value *ucontrol) 653 struct snd_ctl_elem_value *ucontrol)
652{ 654{
653 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 655 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
654 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 656 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
655 657
656 ucontrol->value.integer.value[0] = max98095->mic2pre; 658 ucontrol->value.integer.value[0] = max98095->mic2pre;
@@ -1395,6 +1397,11 @@ static int max98095_dai_set_sysclk(struct snd_soc_dai *dai,
1395 if (freq == max98095->sysclk) 1397 if (freq == max98095->sysclk)
1396 return 0; 1398 return 0;
1397 1399
1400 if (!IS_ERR(max98095->mclk)) {
1401 freq = clk_round_rate(max98095->mclk, freq);
1402 clk_set_rate(max98095->mclk, freq);
1403 }
1404
1398 /* Setup clocks for slave mode, and using the PLL 1405 /* Setup clocks for slave mode, and using the PLL
1399 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 1406 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1400 * 0x02 (when master clk is 20MHz to 40MHz).. 1407 * 0x02 (when master clk is 20MHz to 40MHz)..
@@ -1634,6 +1641,19 @@ static int max98095_set_bias_level(struct snd_soc_codec *codec,
1634 break; 1641 break;
1635 1642
1636 case SND_SOC_BIAS_PREPARE: 1643 case SND_SOC_BIAS_PREPARE:
1644 /*
1645 * SND_SOC_BIAS_PREPARE is called while preparing for a
1646 * transition to ON or away from ON. If current bias_level
1647 * is SND_SOC_BIAS_ON, then it is preparing for a transition
1648 * away from ON. Disable the clock in that case, otherwise
1649 * enable it.
1650 */
1651 if (!IS_ERR(max98095->mclk)) {
1652 if (codec->dapm.bias_level == SND_SOC_BIAS_ON)
1653 clk_disable_unprepare(max98095->mclk);
1654 else
1655 clk_prepare_enable(max98095->mclk);
1656 }
1637 break; 1657 break;
1638 1658
1639 case SND_SOC_BIAS_STANDBY: 1659 case SND_SOC_BIAS_STANDBY:
@@ -1737,7 +1757,7 @@ static int max98095_get_eq_channel(const char *name)
1737static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol, 1757static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol,
1738 struct snd_ctl_elem_value *ucontrol) 1758 struct snd_ctl_elem_value *ucontrol)
1739{ 1759{
1740 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1760 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1741 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1761 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1742 struct max98095_pdata *pdata = max98095->pdata; 1762 struct max98095_pdata *pdata = max98095->pdata;
1743 int channel = max98095_get_eq_channel(kcontrol->id.name); 1763 int channel = max98095_get_eq_channel(kcontrol->id.name);
@@ -1801,7 +1821,7 @@ static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol,
1801static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol, 1821static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol,
1802 struct snd_ctl_elem_value *ucontrol) 1822 struct snd_ctl_elem_value *ucontrol)
1803{ 1823{
1804 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1824 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1805 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1825 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1806 int channel = max98095_get_eq_channel(kcontrol->id.name); 1826 int channel = max98095_get_eq_channel(kcontrol->id.name);
1807 struct max98095_cdata *cdata; 1827 struct max98095_cdata *cdata;
@@ -1891,7 +1911,7 @@ static int max98095_get_bq_channel(struct snd_soc_codec *codec,
1891static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol, 1911static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol,
1892 struct snd_ctl_elem_value *ucontrol) 1912 struct snd_ctl_elem_value *ucontrol)
1893{ 1913{
1894 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1914 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1895 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1915 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1896 struct max98095_pdata *pdata = max98095->pdata; 1916 struct max98095_pdata *pdata = max98095->pdata;
1897 int channel = max98095_get_bq_channel(codec, kcontrol->id.name); 1917 int channel = max98095_get_bq_channel(codec, kcontrol->id.name);
@@ -1952,7 +1972,7 @@ static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol,
1952static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol, 1972static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol,
1953 struct snd_ctl_elem_value *ucontrol) 1973 struct snd_ctl_elem_value *ucontrol)
1954{ 1974{
1955 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1975 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1956 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1976 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1957 int channel = max98095_get_bq_channel(codec, kcontrol->id.name); 1977 int channel = max98095_get_bq_channel(codec, kcontrol->id.name);
1958 struct max98095_cdata *cdata; 1978 struct max98095_cdata *cdata;
@@ -2238,6 +2258,10 @@ static int max98095_probe(struct snd_soc_codec *codec)
2238 struct i2c_client *client; 2258 struct i2c_client *client;
2239 int ret = 0; 2259 int ret = 0;
2240 2260
2261 max98095->mclk = devm_clk_get(codec->dev, "mclk");
2262 if (PTR_ERR(max98095->mclk) == -EPROBE_DEFER)
2263 return -EPROBE_DEFER;
2264
2241 /* reset the codec, the DSP core, and disable all interrupts */ 2265 /* reset the codec, the DSP core, and disable all interrupts */
2242 max98095_reset(codec); 2266 max98095_reset(codec);
2243 2267
@@ -2399,10 +2423,17 @@ static const struct i2c_device_id max98095_i2c_id[] = {
2399}; 2423};
2400MODULE_DEVICE_TABLE(i2c, max98095_i2c_id); 2424MODULE_DEVICE_TABLE(i2c, max98095_i2c_id);
2401 2425
2426static const struct of_device_id max98095_of_match[] = {
2427 { .compatible = "maxim,max98095", },
2428 { }
2429};
2430MODULE_DEVICE_TABLE(of, max98095_of_match);
2431
2402static struct i2c_driver max98095_i2c_driver = { 2432static struct i2c_driver max98095_i2c_driver = {
2403 .driver = { 2433 .driver = {
2404 .name = "max98095", 2434 .name = "max98095",
2405 .owner = THIS_MODULE, 2435 .owner = THIS_MODULE,
2436 .of_match_table = of_match_ptr(max98095_of_match),
2406 }, 2437 },
2407 .probe = max98095_i2c_probe, 2438 .probe = max98095_i2c_probe,
2408 .remove = max98095_i2c_remove, 2439 .remove = max98095_i2c_remove,
diff --git a/sound/soc/codecs/mc13783.c b/sound/soc/codecs/mc13783.c
index 2c59b1fb69dc..9965277b595a 100644
--- a/sound/soc/codecs/mc13783.c
+++ b/sound/soc/codecs/mc13783.c
@@ -22,6 +22,7 @@
22 */ 22 */
23#include <linux/module.h> 23#include <linux/module.h>
24#include <linux/device.h> 24#include <linux/device.h>
25#include <linux/of.h>
25#include <linux/mfd/mc13xxx.h> 26#include <linux/mfd/mc13xxx.h>
26#include <linux/slab.h> 27#include <linux/slab.h>
27#include <sound/core.h> 28#include <sound/core.h>
@@ -409,7 +410,7 @@ static const char * const adcl_enum_text[] = {
409static SOC_ENUM_SINGLE_VIRT_DECL(adcl_enum, adcl_enum_text); 410static SOC_ENUM_SINGLE_VIRT_DECL(adcl_enum, adcl_enum_text);
410 411
411static const struct snd_kcontrol_new left_input_mux = 412static const struct snd_kcontrol_new left_input_mux =
412 SOC_DAPM_ENUM_VIRT("Route", adcl_enum); 413 SOC_DAPM_ENUM("Route", adcl_enum);
413 414
414static const char * const adcr_enum_text[] = { 415static const char * const adcr_enum_text[] = {
415 "MC1R", "MC2", "RXINR", "TXIN", 416 "MC1R", "MC2", "RXINR", "TXIN",
@@ -418,7 +419,7 @@ static const char * const adcr_enum_text[] = {
418static SOC_ENUM_SINGLE_VIRT_DECL(adcr_enum, adcr_enum_text); 419static SOC_ENUM_SINGLE_VIRT_DECL(adcr_enum, adcr_enum_text);
419 420
420static const struct snd_kcontrol_new right_input_mux = 421static const struct snd_kcontrol_new right_input_mux =
421 SOC_DAPM_ENUM_VIRT("Route", adcr_enum); 422 SOC_DAPM_ENUM("Route", adcr_enum);
422 423
423static const struct snd_kcontrol_new samp_ctl = 424static const struct snd_kcontrol_new samp_ctl =
424 SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_RX0, 3, 1, 0); 425 SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_RX0, 3, 1, 0);
@@ -478,9 +479,9 @@ static const struct snd_soc_dapm_widget mc13783_dapm_widgets[] = {
478 SND_SOC_DAPM_SWITCH("MC2 Amp", MC13783_AUDIO_TX, 9, 0, &mc2_amp_ctl), 479 SND_SOC_DAPM_SWITCH("MC2 Amp", MC13783_AUDIO_TX, 9, 0, &mc2_amp_ctl),
479 SND_SOC_DAPM_SWITCH("TXIN Amp", MC13783_AUDIO_TX, 11, 0, &atx_amp_ctl), 480 SND_SOC_DAPM_SWITCH("TXIN Amp", MC13783_AUDIO_TX, 11, 0, &atx_amp_ctl),
480 481
481 SND_SOC_DAPM_VIRT_MUX("PGA Left Input Mux", SND_SOC_NOPM, 0, 0, 482 SND_SOC_DAPM_MUX("PGA Left Input Mux", SND_SOC_NOPM, 0, 0,
482 &left_input_mux), 483 &left_input_mux),
483 SND_SOC_DAPM_VIRT_MUX("PGA Right Input Mux", SND_SOC_NOPM, 0, 0, 484 SND_SOC_DAPM_MUX("PGA Right Input Mux", SND_SOC_NOPM, 0, 0,
484 &right_input_mux), 485 &right_input_mux),
485 486
486 SND_SOC_DAPM_MUX("Speaker Amp Source MUX", SND_SOC_NOPM, 0, 0, 487 SND_SOC_DAPM_MUX("Speaker Amp Source MUX", SND_SOC_NOPM, 0, 0,
@@ -608,14 +609,6 @@ static struct snd_kcontrol_new mc13783_control_list[] = {
608static int mc13783_probe(struct snd_soc_codec *codec) 609static int mc13783_probe(struct snd_soc_codec *codec)
609{ 610{
610 struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec); 611 struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
611 int ret;
612
613 ret = snd_soc_codec_set_cache_io(codec,
614 dev_get_regmap(codec->dev->parent, NULL));
615 if (ret != 0) {
616 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
617 return ret;
618 }
619 612
620 /* these are the reset values */ 613 /* these are the reset values */
621 mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX0, 0x25893); 614 mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX0, 0x25893);
@@ -735,9 +728,15 @@ static struct snd_soc_dai_driver mc13783_dai_sync[] = {
735 } 728 }
736}; 729};
737 730
731static struct regmap *mc13783_get_regmap(struct device *dev)
732{
733 return dev_get_regmap(dev->parent, NULL);
734}
735
738static struct snd_soc_codec_driver soc_codec_dev_mc13783 = { 736static struct snd_soc_codec_driver soc_codec_dev_mc13783 = {
739 .probe = mc13783_probe, 737 .probe = mc13783_probe,
740 .remove = mc13783_remove, 738 .remove = mc13783_remove,
739 .get_regmap = mc13783_get_regmap,
741 .controls = mc13783_control_list, 740 .controls = mc13783_control_list,
742 .num_controls = ARRAY_SIZE(mc13783_control_list), 741 .num_controls = ARRAY_SIZE(mc13783_control_list),
743 .dapm_widgets = mc13783_dapm_widgets, 742 .dapm_widgets = mc13783_dapm_widgets,
@@ -750,6 +749,7 @@ static int __init mc13783_codec_probe(struct platform_device *pdev)
750{ 749{
751 struct mc13783_priv *priv; 750 struct mc13783_priv *priv;
752 struct mc13xxx_codec_platform_data *pdata = pdev->dev.platform_data; 751 struct mc13xxx_codec_platform_data *pdata = pdev->dev.platform_data;
752 struct device_node *np;
753 int ret; 753 int ret;
754 754
755 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 755 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
@@ -760,7 +760,17 @@ static int __init mc13783_codec_probe(struct platform_device *pdev)
760 priv->adc_ssi_port = pdata->adc_ssi_port; 760 priv->adc_ssi_port = pdata->adc_ssi_port;
761 priv->dac_ssi_port = pdata->dac_ssi_port; 761 priv->dac_ssi_port = pdata->dac_ssi_port;
762 } else { 762 } else {
763 return -ENOSYS; 763 np = of_get_child_by_name(pdev->dev.parent->of_node, "codec");
764 if (!np)
765 return -ENOSYS;
766
767 ret = of_property_read_u32(np, "adc-port", &priv->adc_ssi_port);
768 if (ret)
769 return ret;
770
771 ret = of_property_read_u32(np, "dac-port", &priv->dac_ssi_port);
772 if (ret)
773 return ret;
764 } 774 }
765 775
766 dev_set_drvdata(&pdev->dev, priv); 776 dev_set_drvdata(&pdev->dev, priv);
diff --git a/sound/soc/codecs/pcm1681.c b/sound/soc/codecs/pcm1681.c
index e427544183d7..a722a023c262 100644
--- a/sound/soc/codecs/pcm1681.c
+++ b/sound/soc/codecs/pcm1681.c
@@ -115,7 +115,7 @@ static int pcm1681_set_deemph(struct snd_soc_codec *codec)
115static int pcm1681_get_deemph(struct snd_kcontrol *kcontrol, 115static int pcm1681_get_deemph(struct snd_kcontrol *kcontrol,
116 struct snd_ctl_elem_value *ucontrol) 116 struct snd_ctl_elem_value *ucontrol)
117{ 117{
118 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 118 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
119 struct pcm1681_private *priv = snd_soc_codec_get_drvdata(codec); 119 struct pcm1681_private *priv = snd_soc_codec_get_drvdata(codec);
120 120
121 ucontrol->value.enumerated.item[0] = priv->deemph; 121 ucontrol->value.enumerated.item[0] = priv->deemph;
@@ -126,7 +126,7 @@ static int pcm1681_get_deemph(struct snd_kcontrol *kcontrol,
126static int pcm1681_put_deemph(struct snd_kcontrol *kcontrol, 126static int pcm1681_put_deemph(struct snd_kcontrol *kcontrol,
127 struct snd_ctl_elem_value *ucontrol) 127 struct snd_ctl_elem_value *ucontrol)
128{ 128{
129 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 129 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
130 struct pcm1681_private *priv = snd_soc_codec_get_drvdata(codec); 130 struct pcm1681_private *priv = snd_soc_codec_get_drvdata(codec);
131 131
132 priv->deemph = ucontrol->value.enumerated.item[0]; 132 priv->deemph = ucontrol->value.enumerated.item[0];
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c
index 4b4c0c7bb918..163ec3855fd4 100644
--- a/sound/soc/codecs/pcm512x.c
+++ b/sound/soc/codecs/pcm512x.c
@@ -269,7 +269,7 @@ SOC_DOUBLE("Playback Digital Switch", PCM512x_MUTE, PCM512x_RQML_SHIFT,
269 PCM512x_RQMR_SHIFT, 1, 1), 269 PCM512x_RQMR_SHIFT, 1, 1),
270 270
271SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1), 271SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1),
272SOC_VALUE_ENUM("DSP Program", pcm512x_dsp_program), 272SOC_ENUM("DSP Program", pcm512x_dsp_program),
273 273
274SOC_ENUM("Clock Missing Period", pcm512x_clk_missing), 274SOC_ENUM("Clock Missing Period", pcm512x_clk_missing),
275SOC_ENUM("Auto Mute Time Left", pcm512x_autom_l), 275SOC_ENUM("Auto Mute Time Left", pcm512x_autom_l),
@@ -517,6 +517,7 @@ void pcm512x_remove(struct device *dev)
517} 517}
518EXPORT_SYMBOL_GPL(pcm512x_remove); 518EXPORT_SYMBOL_GPL(pcm512x_remove);
519 519
520#ifdef CONFIG_PM_RUNTIME
520static int pcm512x_suspend(struct device *dev) 521static int pcm512x_suspend(struct device *dev)
521{ 522{
522 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); 523 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
@@ -578,6 +579,7 @@ static int pcm512x_resume(struct device *dev)
578 579
579 return 0; 580 return 0;
580} 581}
582#endif
581 583
582const struct dev_pm_ops pcm512x_pm_ops = { 584const struct dev_pm_ops pcm512x_pm_ops = {
583 SET_RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL) 585 SET_RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL)
diff --git a/sound/soc/codecs/rl6231.c b/sound/soc/codecs/rl6231.c
new file mode 100644
index 000000000000..7b82fbe0d14c
--- /dev/null
+++ b/sound/soc/codecs/rl6231.c
@@ -0,0 +1,152 @@
1/*
2 * rl6231.c - RL6231 class device shared support
3 *
4 * Copyright 2014 Realtek Semiconductor Corp.
5 *
6 * Author: Oder Chiou <oder_chiou@realtek.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/gpio.h>
19#include <linux/i2c.h>
20#include <linux/regmap.h>
21#include <linux/of.h>
22#include <linux/of_gpio.h>
23#include <linux/platform_device.h>
24#include <linux/spi/spi.h>
25#include <linux/acpi.h>
26#include <sound/core.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33
34#include "rl6231.h"
35
36/**
37 * rl6231_calc_dmic_clk - Calculate the parameter of dmic.
38 *
39 * @rate: base clock rate.
40 *
41 * Choose dmic clock between 1MHz and 3MHz.
42 * It is better for clock to approximate 3MHz.
43 */
44int rl6231_calc_dmic_clk(int rate)
45{
46 int div[] = {2, 3, 4, 6, 8, 12}, idx = -EINVAL;
47 int i, red, bound, temp;
48
49 red = 3000000 * 12;
50 for (i = 0; i < ARRAY_SIZE(div); i++) {
51 bound = div[i] * 3000000;
52 if (rate > bound)
53 continue;
54 temp = bound - rate;
55 if (temp < red) {
56 red = temp;
57 idx = i;
58 }
59 }
60
61 return idx;
62}
63EXPORT_SYMBOL_GPL(rl6231_calc_dmic_clk);
64
65/**
66 * rl6231_pll_calc - Calcualte PLL M/N/K code.
67 * @freq_in: external clock provided to codec.
68 * @freq_out: target clock which codec works on.
69 * @pll_code: Pointer to structure with M, N, K and bypass flag.
70 *
71 * Calcualte M/N/K code to configure PLL for codec.
72 *
73 * Returns 0 for success or negative error code.
74 */
75int rl6231_pll_calc(const unsigned int freq_in,
76 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
77{
78 int max_n = RL6231_PLL_N_MAX, max_m = RL6231_PLL_M_MAX;
79 int k, red, n_t, pll_out, in_t, out_t;
80 int n = 0, m = 0, m_t = 0;
81 int red_t = abs(freq_out - freq_in);
82 bool bypass = false;
83
84 if (RL6231_PLL_INP_MAX < freq_in || RL6231_PLL_INP_MIN > freq_in)
85 return -EINVAL;
86
87 k = 100000000 / freq_out - 2;
88 if (k > RL6231_PLL_K_MAX)
89 k = RL6231_PLL_K_MAX;
90 for (n_t = 0; n_t <= max_n; n_t++) {
91 in_t = freq_in / (k + 2);
92 pll_out = freq_out / (n_t + 2);
93 if (in_t < 0)
94 continue;
95 if (in_t == pll_out) {
96 bypass = true;
97 n = n_t;
98 goto code_find;
99 }
100 red = abs(in_t - pll_out);
101 if (red < red_t) {
102 bypass = true;
103 n = n_t;
104 m = m_t;
105 if (red == 0)
106 goto code_find;
107 red_t = red;
108 }
109 for (m_t = 0; m_t <= max_m; m_t++) {
110 out_t = in_t / (m_t + 2);
111 red = abs(out_t - pll_out);
112 if (red < red_t) {
113 bypass = false;
114 n = n_t;
115 m = m_t;
116 if (red == 0)
117 goto code_find;
118 red_t = red;
119 }
120 }
121 }
122 pr_debug("Only get approximation about PLL\n");
123
124code_find:
125
126 pll_code->m_bp = bypass;
127 pll_code->m_code = m;
128 pll_code->n_code = n;
129 pll_code->k_code = k;
130 return 0;
131}
132EXPORT_SYMBOL_GPL(rl6231_pll_calc);
133
134int rl6231_get_clk_info(int sclk, int rate)
135{
136 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
137
138 if (sclk <= 0 || rate <= 0)
139 return -EINVAL;
140
141 rate = rate << 8;
142 for (i = 0; i < ARRAY_SIZE(pd); i++)
143 if (sclk == rate * pd[i])
144 return i;
145
146 return -EINVAL;
147}
148EXPORT_SYMBOL_GPL(rl6231_get_clk_info);
149
150MODULE_DESCRIPTION("RL6231 class device shared support");
151MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
152MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/rl6231.h b/sound/soc/codecs/rl6231.h
new file mode 100644
index 000000000000..0f7b057ed736
--- /dev/null
+++ b/sound/soc/codecs/rl6231.h
@@ -0,0 +1,34 @@
1/*
2 * rl6231.h - RL6231 class device shared support
3 *
4 * Copyright 2014 Realtek Semiconductor Corp.
5 *
6 * Author: Oder Chiou <oder_chiou@realtek.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __RL6231_H__
14#define __RL6231_H__
15
16#define RL6231_PLL_INP_MAX 40000000
17#define RL6231_PLL_INP_MIN 256000
18#define RL6231_PLL_N_MAX 0x1ff
19#define RL6231_PLL_K_MAX 0x1f
20#define RL6231_PLL_M_MAX 0xf
21
22struct rl6231_pll_code {
23 bool m_bp; /* Indicates bypass m code or not. */
24 int m_code;
25 int n_code;
26 int k_code;
27};
28
29int rl6231_calc_dmic_clk(int rate);
30int rl6231_pll_calc(const unsigned int freq_in,
31 const unsigned int freq_out, struct rl6231_pll_code *pll_code);
32int rl6231_get_clk_info(int sclk, int rate);
33
34#endif /* __RL6231_H__ */
diff --git a/sound/soc/codecs/rt5631.c b/sound/soc/codecs/rt5631.c
index d4c229f0233f..30e234708579 100644
--- a/sound/soc/codecs/rt5631.c
+++ b/sound/soc/codecs/rt5631.c
@@ -188,7 +188,7 @@ static unsigned int mic_bst_tlv[] = {
188static int rt5631_dmic_get(struct snd_kcontrol *kcontrol, 188static int rt5631_dmic_get(struct snd_kcontrol *kcontrol,
189 struct snd_ctl_elem_value *ucontrol) 189 struct snd_ctl_elem_value *ucontrol)
190{ 190{
191 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 191 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
192 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec); 192 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
193 193
194 ucontrol->value.integer.value[0] = rt5631->dmic_used_flag; 194 ucontrol->value.integer.value[0] = rt5631->dmic_used_flag;
@@ -199,7 +199,7 @@ static int rt5631_dmic_get(struct snd_kcontrol *kcontrol,
199static int rt5631_dmic_put(struct snd_kcontrol *kcontrol, 199static int rt5631_dmic_put(struct snd_kcontrol *kcontrol,
200 struct snd_ctl_elem_value *ucontrol) 200 struct snd_ctl_elem_value *ucontrol)
201{ 201{
202 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 202 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
203 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec); 203 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
204 204
205 rt5631->dmic_used_flag = ucontrol->value.integer.value[0]; 205 rt5631->dmic_used_flag = ucontrol->value.integer.value[0];
diff --git a/sound/soc/codecs/rt5640.c b/sound/soc/codecs/rt5640.c
index 68b4dd622b87..de80e89b5fd8 100644
--- a/sound/soc/codecs/rt5640.c
+++ b/sound/soc/codecs/rt5640.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * rt5640.c -- RT5640 ALSA SoC audio codec driver 2 * rt5640.c -- RT5640/RT5639 ALSA SoC audio codec driver
3 * 3 *
4 * Copyright 2011 Realtek Semiconductor Corp. 4 * Copyright 2011 Realtek Semiconductor Corp.
5 * Author: Johnny Hsu <johnnyhsu@realtek.com> 5 * Author: Johnny Hsu <johnnyhsu@realtek.com>
@@ -18,6 +18,7 @@
18#include <linux/gpio.h> 18#include <linux/gpio.h>
19#include <linux/i2c.h> 19#include <linux/i2c.h>
20#include <linux/regmap.h> 20#include <linux/regmap.h>
21#include <linux/of.h>
21#include <linux/of_gpio.h> 22#include <linux/of_gpio.h>
22#include <linux/platform_device.h> 23#include <linux/platform_device.h>
23#include <linux/spi/spi.h> 24#include <linux/spi/spi.h>
@@ -30,6 +31,7 @@
30#include <sound/initval.h> 31#include <sound/initval.h>
31#include <sound/tlv.h> 32#include <sound/tlv.h>
32 33
34#include "rl6231.h"
33#include "rt5640.h" 35#include "rt5640.h"
34 36
35#define RT5640_DEVICE_ID 0x6231 37#define RT5640_DEVICE_ID 0x6231
@@ -59,7 +61,7 @@ static struct reg_default init_list[] = {
59}; 61};
60#define RT5640_INIT_REG_LEN ARRAY_SIZE(init_list) 62#define RT5640_INIT_REG_LEN ARRAY_SIZE(init_list)
61 63
62static const struct reg_default rt5640_reg[RT5640_VENDOR_ID2 + 1] = { 64static const struct reg_default rt5640_reg[] = {
63 { 0x00, 0x000e }, 65 { 0x00, 0x000e },
64 { 0x01, 0xc8c8 }, 66 { 0x01, 0xc8c8 },
65 { 0x02, 0xc8c8 }, 67 { 0x02, 0xc8c8 },
@@ -398,18 +400,13 @@ static const struct snd_kcontrol_new rt5640_snd_controls[] = {
398 RT5640_VOL_L_SFT, RT5640_VOL_R_SFT, 1, 1), 400 RT5640_VOL_L_SFT, RT5640_VOL_R_SFT, 1, 1),
399 SOC_DOUBLE_TLV("OUT Playback Volume", RT5640_OUTPUT, 401 SOC_DOUBLE_TLV("OUT Playback Volume", RT5640_OUTPUT,
400 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, 39, 1, out_vol_tlv), 402 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, 39, 1, out_vol_tlv),
401 /* MONO Output Control */ 403
402 SOC_SINGLE("Mono Playback Switch", RT5640_MONO_OUT,
403 RT5640_L_MUTE_SFT, 1, 1),
404 /* DAC Digital Volume */ 404 /* DAC Digital Volume */
405 SOC_DOUBLE("DAC2 Playback Switch", RT5640_DAC2_CTRL, 405 SOC_DOUBLE("DAC2 Playback Switch", RT5640_DAC2_CTRL,
406 RT5640_M_DAC_L2_VOL_SFT, RT5640_M_DAC_R2_VOL_SFT, 1, 1), 406 RT5640_M_DAC_L2_VOL_SFT, RT5640_M_DAC_R2_VOL_SFT, 1, 1),
407 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5640_DAC1_DIG_VOL, 407 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5640_DAC1_DIG_VOL,
408 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, 408 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
409 175, 0, dac_vol_tlv), 409 175, 0, dac_vol_tlv),
410 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5640_DAC2_DIG_VOL,
411 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
412 175, 0, dac_vol_tlv),
413 /* IN1/IN2 Control */ 410 /* IN1/IN2 Control */
414 SOC_SINGLE_TLV("IN1 Boost", RT5640_IN1_IN2, 411 SOC_SINGLE_TLV("IN1 Boost", RT5640_IN1_IN2,
415 RT5640_BST_SFT1, 8, 0, bst_tlv), 412 RT5640_BST_SFT1, 8, 0, bst_tlv),
@@ -441,6 +438,15 @@ static const struct snd_kcontrol_new rt5640_snd_controls[] = {
441 SOC_ENUM("DAC IF2 Data Switch", rt5640_if2_dac_enum), 438 SOC_ENUM("DAC IF2 Data Switch", rt5640_if2_dac_enum),
442}; 439};
443 440
441static const struct snd_kcontrol_new rt5640_specific_snd_controls[] = {
442 /* MONO Output Control */
443 SOC_SINGLE("Mono Playback Switch", RT5640_MONO_OUT, RT5640_L_MUTE_SFT,
444 1, 1),
445
446 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5640_DAC2_DIG_VOL,
447 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, 175, 0, dac_vol_tlv),
448};
449
444/** 450/**
445 * set_dmic_clk - Set parameter of dmic. 451 * set_dmic_clk - Set parameter of dmic.
446 * 452 *
@@ -448,30 +454,16 @@ static const struct snd_kcontrol_new rt5640_snd_controls[] = {
448 * @kcontrol: The kcontrol of this widget. 454 * @kcontrol: The kcontrol of this widget.
449 * @event: Event id. 455 * @event: Event id.
450 * 456 *
451 * Choose dmic clock between 1MHz and 3MHz.
452 * It is better for clock to approximate 3MHz.
453 */ 457 */
454static int set_dmic_clk(struct snd_soc_dapm_widget *w, 458static int set_dmic_clk(struct snd_soc_dapm_widget *w,
455 struct snd_kcontrol *kcontrol, int event) 459 struct snd_kcontrol *kcontrol, int event)
456{ 460{
457 struct snd_soc_codec *codec = w->codec; 461 struct snd_soc_codec *codec = w->codec;
458 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec); 462 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
459 int div[] = {2, 3, 4, 6, 8, 12}; 463 int idx = -EINVAL;
460 int idx = -EINVAL, i; 464
461 int rate, red, bound, temp; 465 idx = rl6231_calc_dmic_clk(rt5640->sysclk);
462 466
463 rate = rt5640->sysclk;
464 red = 3000000 * 12;
465 for (i = 0; i < ARRAY_SIZE(div); i++) {
466 bound = div[i] * 3000000;
467 if (rate > bound)
468 continue;
469 temp = bound - rate;
470 if (temp < red) {
471 red = temp;
472 idx = i;
473 }
474 }
475 if (idx < 0) 467 if (idx < 0)
476 dev_err(codec->dev, "Failed to set DMIC clock\n"); 468 dev_err(codec->dev, "Failed to set DMIC clock\n");
477 else 469 else
@@ -480,14 +472,14 @@ static int set_dmic_clk(struct snd_soc_dapm_widget *w,
480 return idx; 472 return idx;
481} 473}
482 474
483static int check_sysclk1_source(struct snd_soc_dapm_widget *source, 475static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
484 struct snd_soc_dapm_widget *sink) 476 struct snd_soc_dapm_widget *sink)
485{ 477{
486 unsigned int val; 478 unsigned int val;
487 479
488 val = snd_soc_read(source->codec, RT5640_GLB_CLK); 480 val = snd_soc_read(source->codec, RT5640_GLB_CLK);
489 val &= RT5640_SCLK_SRC_MASK; 481 val &= RT5640_SCLK_SRC_MASK;
490 if (val == RT5640_SCLK_SRC_PLL1 || val == RT5640_SCLK_SRC_PLL1T) 482 if (val == RT5640_SCLK_SRC_PLL1)
491 return 1; 483 return 1;
492 else 484 else
493 return 0; 485 return 0;
@@ -554,6 +546,20 @@ static const struct snd_kcontrol_new rt5640_sto_dac_r_mix[] = {
554 RT5640_M_ANC_DAC_R_SFT, 1, 1), 546 RT5640_M_ANC_DAC_R_SFT, 1, 1),
555}; 547};
556 548
549static const struct snd_kcontrol_new rt5639_sto_dac_l_mix[] = {
550 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_STO_DAC_MIXER,
551 RT5640_M_DAC_L1_SFT, 1, 1),
552 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_STO_DAC_MIXER,
553 RT5640_M_DAC_L2_SFT, 1, 1),
554};
555
556static const struct snd_kcontrol_new rt5639_sto_dac_r_mix[] = {
557 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_STO_DAC_MIXER,
558 RT5640_M_DAC_R1_SFT, 1, 1),
559 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_STO_DAC_MIXER,
560 RT5640_M_DAC_R2_SFT, 1, 1),
561};
562
557static const struct snd_kcontrol_new rt5640_mono_dac_l_mix[] = { 563static const struct snd_kcontrol_new rt5640_mono_dac_l_mix[] = {
558 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_MONO_DAC_MIXER, 564 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_MONO_DAC_MIXER,
559 RT5640_M_DAC_L1_MONO_L_SFT, 1, 1), 565 RT5640_M_DAC_L1_MONO_L_SFT, 1, 1),
@@ -676,6 +682,30 @@ static const struct snd_kcontrol_new rt5640_out_r_mix[] = {
676 RT5640_M_DAC_R1_OM_R_SFT, 1, 1), 682 RT5640_M_DAC_R1_OM_R_SFT, 1, 1),
677}; 683};
678 684
685static const struct snd_kcontrol_new rt5639_out_l_mix[] = {
686 SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_L3_MIXER,
687 RT5640_M_BST1_OM_L_SFT, 1, 1),
688 SOC_DAPM_SINGLE("INL Switch", RT5640_OUT_L3_MIXER,
689 RT5640_M_IN_L_OM_L_SFT, 1, 1),
690 SOC_DAPM_SINGLE("REC MIXL Switch", RT5640_OUT_L3_MIXER,
691 RT5640_M_RM_L_OM_L_SFT, 1, 1),
692 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_OUT_L3_MIXER,
693 RT5640_M_DAC_L1_OM_L_SFT, 1, 1),
694};
695
696static const struct snd_kcontrol_new rt5639_out_r_mix[] = {
697 SOC_DAPM_SINGLE("BST2 Switch", RT5640_OUT_R3_MIXER,
698 RT5640_M_BST4_OM_R_SFT, 1, 1),
699 SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_R3_MIXER,
700 RT5640_M_BST1_OM_R_SFT, 1, 1),
701 SOC_DAPM_SINGLE("INR Switch", RT5640_OUT_R3_MIXER,
702 RT5640_M_IN_R_OM_R_SFT, 1, 1),
703 SOC_DAPM_SINGLE("REC MIXR Switch", RT5640_OUT_R3_MIXER,
704 RT5640_M_RM_R_OM_R_SFT, 1, 1),
705 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_OUT_R3_MIXER,
706 RT5640_M_DAC_R1_OM_R_SFT, 1, 1),
707};
708
679static const struct snd_kcontrol_new rt5640_spo_l_mix[] = { 709static const struct snd_kcontrol_new rt5640_spo_l_mix[] = {
680 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPO_L_MIXER, 710 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPO_L_MIXER,
681 RT5640_M_DAC_R1_SPM_L_SFT, 1, 1), 711 RT5640_M_DAC_R1_SPM_L_SFT, 1, 1),
@@ -707,6 +737,13 @@ static const struct snd_kcontrol_new rt5640_hpo_mix[] = {
707 RT5640_M_HPVOL_HM_SFT, 1, 1), 737 RT5640_M_HPVOL_HM_SFT, 1, 1),
708}; 738};
709 739
740static const struct snd_kcontrol_new rt5639_hpo_mix[] = {
741 SOC_DAPM_SINGLE("HPO MIX DAC1 Switch", RT5640_HPO_MIXER,
742 RT5640_M_DAC1_HM_SFT, 1, 1),
743 SOC_DAPM_SINGLE("HPO MIX HPVOL Switch", RT5640_HPO_MIXER,
744 RT5640_M_HPVOL_HM_SFT, 1, 1),
745};
746
710static const struct snd_kcontrol_new rt5640_lout_mix[] = { 747static const struct snd_kcontrol_new rt5640_lout_mix[] = {
711 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_LOUT_MIXER, 748 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_LOUT_MIXER,
712 RT5640_M_DAC_L1_LM_SFT, 1, 1), 749 RT5640_M_DAC_L1_LM_SFT, 1, 1),
@@ -824,7 +861,7 @@ static SOC_VALUE_ENUM_SINGLE_DECL(rt5640_dac_l2_enum,
824 0x3, rt5640_dac_l2_src, rt5640_dac_l2_values); 861 0x3, rt5640_dac_l2_src, rt5640_dac_l2_values);
825 862
826static const struct snd_kcontrol_new rt5640_dac_l2_mux = 863static const struct snd_kcontrol_new rt5640_dac_l2_mux =
827 SOC_DAPM_VALUE_ENUM("DAC2 left channel source", rt5640_dac_l2_enum); 864 SOC_DAPM_ENUM("DAC2 left channel source", rt5640_dac_l2_enum);
828 865
829static const char * const rt5640_dac_r2_src[] = { 866static const char * const rt5640_dac_r2_src[] = {
830 "IF2", 867 "IF2",
@@ -859,7 +896,7 @@ static SOC_VALUE_ENUM_SINGLE_DECL(rt5640_dai_iis_map_enum,
859 rt5640_dai_iis_map_values); 896 rt5640_dai_iis_map_values);
860 897
861static const struct snd_kcontrol_new rt5640_dai_mux = 898static const struct snd_kcontrol_new rt5640_dai_mux =
862 SOC_DAPM_VALUE_ENUM("DAI select", rt5640_dai_iis_map_enum); 899 SOC_DAPM_ENUM("DAI select", rt5640_dai_iis_map_enum);
863 900
864/* SDI select */ 901/* SDI select */
865static const char * const rt5640_sdi_sel[] = { 902static const char * const rt5640_sdi_sel[] = {
@@ -872,54 +909,6 @@ static SOC_ENUM_SINGLE_DECL(rt5640_sdi_sel_enum, RT5640_I2S2_SDP,
872static const struct snd_kcontrol_new rt5640_sdi_mux = 909static const struct snd_kcontrol_new rt5640_sdi_mux =
873 SOC_DAPM_ENUM("SDI select", rt5640_sdi_sel_enum); 910 SOC_DAPM_ENUM("SDI select", rt5640_sdi_sel_enum);
874 911
875static int rt5640_set_dmic1_event(struct snd_soc_dapm_widget *w,
876 struct snd_kcontrol *kcontrol, int event)
877{
878 struct snd_soc_codec *codec = w->codec;
879
880 switch (event) {
881 case SND_SOC_DAPM_PRE_PMU:
882 snd_soc_update_bits(codec, RT5640_GPIO_CTRL1,
883 RT5640_GP2_PIN_MASK | RT5640_GP3_PIN_MASK,
884 RT5640_GP2_PIN_DMIC1_SCL | RT5640_GP3_PIN_DMIC1_SDA);
885 snd_soc_update_bits(codec, RT5640_DMIC,
886 RT5640_DMIC_1L_LH_MASK | RT5640_DMIC_1R_LH_MASK |
887 RT5640_DMIC_1_DP_MASK,
888 RT5640_DMIC_1L_LH_FALLING | RT5640_DMIC_1R_LH_RISING |
889 RT5640_DMIC_1_DP_IN1P);
890 break;
891
892 default:
893 return 0;
894 }
895
896 return 0;
897}
898
899static int rt5640_set_dmic2_event(struct snd_soc_dapm_widget *w,
900 struct snd_kcontrol *kcontrol, int event)
901{
902 struct snd_soc_codec *codec = w->codec;
903
904 switch (event) {
905 case SND_SOC_DAPM_PRE_PMU:
906 snd_soc_update_bits(codec, RT5640_GPIO_CTRL1,
907 RT5640_GP2_PIN_MASK | RT5640_GP4_PIN_MASK,
908 RT5640_GP2_PIN_DMIC1_SCL | RT5640_GP4_PIN_DMIC2_SDA);
909 snd_soc_update_bits(codec, RT5640_DMIC,
910 RT5640_DMIC_2L_LH_MASK | RT5640_DMIC_2R_LH_MASK |
911 RT5640_DMIC_2_DP_MASK,
912 RT5640_DMIC_2L_LH_FALLING | RT5640_DMIC_2R_LH_RISING |
913 RT5640_DMIC_2_DP_IN1N);
914 break;
915
916 default:
917 return 0;
918 }
919
920 return 0;
921}
922
923static void hp_amp_power_on(struct snd_soc_codec *codec) 912static void hp_amp_power_on(struct snd_soc_codec *codec)
924{ 913{
925 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec); 914 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
@@ -1054,12 +1043,10 @@ static const struct snd_soc_dapm_widget rt5640_dapm_widgets[] = {
1054 1043
1055 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, 1044 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1056 set_dmic_clk, SND_SOC_DAPM_PRE_PMU), 1045 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1057 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5640_DMIC, 1046 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5640_DMIC, RT5640_DMIC_1_EN_SFT, 0,
1058 RT5640_DMIC_1_EN_SFT, 0, rt5640_set_dmic1_event, 1047 NULL, 0),
1059 SND_SOC_DAPM_PRE_PMU), 1048 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5640_DMIC, RT5640_DMIC_2_EN_SFT, 0,
1060 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5640_DMIC, 1049 NULL, 0),
1061 RT5640_DMIC_2_EN_SFT, 0, rt5640_set_dmic2_event,
1062 SND_SOC_DAPM_PRE_PMU),
1063 /* Boost */ 1050 /* Boost */
1064 SND_SOC_DAPM_PGA("BST1", RT5640_PWR_ANLG2, 1051 SND_SOC_DAPM_PGA("BST1", RT5640_PWR_ANLG2,
1065 RT5640_PWR_BST1_BIT, 0, NULL, 0), 1052 RT5640_PWR_BST1_BIT, 0, NULL, 0),
@@ -1146,26 +1133,15 @@ static const struct snd_soc_dapm_widget rt5640_dapm_widgets[] = {
1146 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), 1133 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1147 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 1134 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1148 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), 1135 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1149 /* Audio DSP */ 1136
1150 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
1151 /* ANC */
1152 SND_SOC_DAPM_PGA("ANC", SND_SOC_NOPM, 0, 0, NULL, 0),
1153 /* Output Side */ 1137 /* Output Side */
1154 /* DAC mixer before sound effect */ 1138 /* DAC mixer before sound effect */
1155 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0, 1139 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1156 rt5640_dac_l_mix, ARRAY_SIZE(rt5640_dac_l_mix)), 1140 rt5640_dac_l_mix, ARRAY_SIZE(rt5640_dac_l_mix)),
1157 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0, 1141 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1158 rt5640_dac_r_mix, ARRAY_SIZE(rt5640_dac_r_mix)), 1142 rt5640_dac_r_mix, ARRAY_SIZE(rt5640_dac_r_mix)),
1159 /* DAC2 channel Mux */ 1143
1160 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0,
1161 &rt5640_dac_l2_mux),
1162 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0,
1163 &rt5640_dac_r2_mux),
1164 /* DAC Mixer */ 1144 /* DAC Mixer */
1165 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1166 rt5640_sto_dac_l_mix, ARRAY_SIZE(rt5640_sto_dac_l_mix)),
1167 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1168 rt5640_sto_dac_r_mix, ARRAY_SIZE(rt5640_sto_dac_r_mix)),
1169 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, 1145 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1170 rt5640_mono_dac_l_mix, ARRAY_SIZE(rt5640_mono_dac_l_mix)), 1146 rt5640_mono_dac_l_mix, ARRAY_SIZE(rt5640_mono_dac_l_mix)),
1171 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, 1147 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
@@ -1177,21 +1153,14 @@ static const struct snd_soc_dapm_widget rt5640_dapm_widgets[] = {
1177 /* DACs */ 1153 /* DACs */
1178 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5640_PWR_DIG1, 1154 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5640_PWR_DIG1,
1179 RT5640_PWR_DAC_L1_BIT, 0), 1155 RT5640_PWR_DAC_L1_BIT, 0),
1180 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5640_PWR_DIG1,
1181 RT5640_PWR_DAC_L2_BIT, 0),
1182 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5640_PWR_DIG1, 1156 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5640_PWR_DIG1,
1183 RT5640_PWR_DAC_R1_BIT, 0), 1157 RT5640_PWR_DAC_R1_BIT, 0),
1184 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5640_PWR_DIG1, 1158
1185 RT5640_PWR_DAC_R2_BIT, 0),
1186 /* SPK/OUT Mixer */ 1159 /* SPK/OUT Mixer */
1187 SND_SOC_DAPM_MIXER("SPK MIXL", RT5640_PWR_MIXER, RT5640_PWR_SM_L_BIT, 1160 SND_SOC_DAPM_MIXER("SPK MIXL", RT5640_PWR_MIXER, RT5640_PWR_SM_L_BIT,
1188 0, rt5640_spk_l_mix, ARRAY_SIZE(rt5640_spk_l_mix)), 1161 0, rt5640_spk_l_mix, ARRAY_SIZE(rt5640_spk_l_mix)),
1189 SND_SOC_DAPM_MIXER("SPK MIXR", RT5640_PWR_MIXER, RT5640_PWR_SM_R_BIT, 1162 SND_SOC_DAPM_MIXER("SPK MIXR", RT5640_PWR_MIXER, RT5640_PWR_SM_R_BIT,
1190 0, rt5640_spk_r_mix, ARRAY_SIZE(rt5640_spk_r_mix)), 1163 0, rt5640_spk_r_mix, ARRAY_SIZE(rt5640_spk_r_mix)),
1191 SND_SOC_DAPM_MIXER("OUT MIXL", RT5640_PWR_MIXER, RT5640_PWR_OM_L_BIT,
1192 0, rt5640_out_l_mix, ARRAY_SIZE(rt5640_out_l_mix)),
1193 SND_SOC_DAPM_MIXER("OUT MIXR", RT5640_PWR_MIXER, RT5640_PWR_OM_R_BIT,
1194 0, rt5640_out_r_mix, ARRAY_SIZE(rt5640_out_r_mix)),
1195 /* Ouput Volume */ 1164 /* Ouput Volume */
1196 SND_SOC_DAPM_PGA("SPKVOL L", RT5640_PWR_VOL, 1165 SND_SOC_DAPM_PGA("SPKVOL L", RT5640_PWR_VOL,
1197 RT5640_PWR_SV_L_BIT, 0, NULL, 0), 1166 RT5640_PWR_SV_L_BIT, 0, NULL, 0),
@@ -1210,16 +1179,8 @@ static const struct snd_soc_dapm_widget rt5640_dapm_widgets[] = {
1210 0, rt5640_spo_l_mix, ARRAY_SIZE(rt5640_spo_l_mix)), 1179 0, rt5640_spo_l_mix, ARRAY_SIZE(rt5640_spo_l_mix)),
1211 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 1180 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0,
1212 0, rt5640_spo_r_mix, ARRAY_SIZE(rt5640_spo_r_mix)), 1181 0, rt5640_spo_r_mix, ARRAY_SIZE(rt5640_spo_r_mix)),
1213 SND_SOC_DAPM_MIXER("HPO MIX L", SND_SOC_NOPM, 0, 0,
1214 rt5640_hpo_mix, ARRAY_SIZE(rt5640_hpo_mix)),
1215 SND_SOC_DAPM_MIXER("HPO MIX R", SND_SOC_NOPM, 0, 0,
1216 rt5640_hpo_mix, ARRAY_SIZE(rt5640_hpo_mix)),
1217 SND_SOC_DAPM_MIXER("LOUT MIX", RT5640_PWR_ANLG1, RT5640_PWR_LM_BIT, 0, 1182 SND_SOC_DAPM_MIXER("LOUT MIX", RT5640_PWR_ANLG1, RT5640_PWR_LM_BIT, 0,
1218 rt5640_lout_mix, ARRAY_SIZE(rt5640_lout_mix)), 1183 rt5640_lout_mix, ARRAY_SIZE(rt5640_lout_mix)),
1219 SND_SOC_DAPM_MIXER("Mono MIX", RT5640_PWR_ANLG1, RT5640_PWR_MM_BIT, 0,
1220 rt5640_mono_mix, ARRAY_SIZE(rt5640_mono_mix)),
1221 SND_SOC_DAPM_SUPPLY("Improve MONO Amp Drv", RT5640_PWR_ANLG1,
1222 RT5640_PWR_MA_BIT, 0, NULL, 0),
1223 SND_SOC_DAPM_SUPPLY_S("Improve HP Amp Drv", 1, SND_SOC_NOPM, 1184 SND_SOC_DAPM_SUPPLY_S("Improve HP Amp Drv", 1, SND_SOC_NOPM,
1224 0, 0, rt5640_hp_power_event, SND_SOC_DAPM_POST_PMU), 1185 0, 0, rt5640_hp_power_event, SND_SOC_DAPM_POST_PMU),
1225 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, 1186 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0,
@@ -1251,10 +1212,69 @@ static const struct snd_soc_dapm_widget rt5640_dapm_widgets[] = {
1251 SND_SOC_DAPM_OUTPUT("HPOR"), 1212 SND_SOC_DAPM_OUTPUT("HPOR"),
1252 SND_SOC_DAPM_OUTPUT("LOUTL"), 1213 SND_SOC_DAPM_OUTPUT("LOUTL"),
1253 SND_SOC_DAPM_OUTPUT("LOUTR"), 1214 SND_SOC_DAPM_OUTPUT("LOUTR"),
1215};
1216
1217static const struct snd_soc_dapm_widget rt5640_specific_dapm_widgets[] = {
1218 /* Audio DSP */
1219 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
1220 /* ANC */
1221 SND_SOC_DAPM_PGA("ANC", SND_SOC_NOPM, 0, 0, NULL, 0),
1222
1223 /* DAC2 channel Mux */
1224 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dac_l2_mux),
1225 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dac_r2_mux),
1226
1227 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1228 rt5640_sto_dac_l_mix, ARRAY_SIZE(rt5640_sto_dac_l_mix)),
1229 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1230 rt5640_sto_dac_r_mix, ARRAY_SIZE(rt5640_sto_dac_r_mix)),
1231
1232 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5640_PWR_DIG1, RT5640_PWR_DAC_R2_BIT,
1233 0),
1234 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5640_PWR_DIG1, RT5640_PWR_DAC_L2_BIT,
1235 0),
1236
1237 SND_SOC_DAPM_MIXER("OUT MIXL", RT5640_PWR_MIXER, RT5640_PWR_OM_L_BIT,
1238 0, rt5640_out_l_mix, ARRAY_SIZE(rt5640_out_l_mix)),
1239 SND_SOC_DAPM_MIXER("OUT MIXR", RT5640_PWR_MIXER, RT5640_PWR_OM_R_BIT,
1240 0, rt5640_out_r_mix, ARRAY_SIZE(rt5640_out_r_mix)),
1241
1242 SND_SOC_DAPM_MIXER("HPO MIX L", SND_SOC_NOPM, 0, 0,
1243 rt5640_hpo_mix, ARRAY_SIZE(rt5640_hpo_mix)),
1244 SND_SOC_DAPM_MIXER("HPO MIX R", SND_SOC_NOPM, 0, 0,
1245 rt5640_hpo_mix, ARRAY_SIZE(rt5640_hpo_mix)),
1246
1247 SND_SOC_DAPM_MIXER("Mono MIX", RT5640_PWR_ANLG1, RT5640_PWR_MM_BIT, 0,
1248 rt5640_mono_mix, ARRAY_SIZE(rt5640_mono_mix)),
1249 SND_SOC_DAPM_SUPPLY("Improve MONO Amp Drv", RT5640_PWR_ANLG1,
1250 RT5640_PWR_MA_BIT, 0, NULL, 0),
1251
1254 SND_SOC_DAPM_OUTPUT("MONOP"), 1252 SND_SOC_DAPM_OUTPUT("MONOP"),
1255 SND_SOC_DAPM_OUTPUT("MONON"), 1253 SND_SOC_DAPM_OUTPUT("MONON"),
1256}; 1254};
1257 1255
1256static const struct snd_soc_dapm_widget rt5639_specific_dapm_widgets[] = {
1257 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1258 rt5639_sto_dac_l_mix, ARRAY_SIZE(rt5639_sto_dac_l_mix)),
1259 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1260 rt5639_sto_dac_r_mix, ARRAY_SIZE(rt5639_sto_dac_r_mix)),
1261
1262 SND_SOC_DAPM_SUPPLY("DAC L2 Filter", RT5640_PWR_DIG1,
1263 RT5640_PWR_DAC_L2_BIT, 0, NULL, 0),
1264 SND_SOC_DAPM_SUPPLY("DAC R2 Filter", RT5640_PWR_DIG1,
1265 RT5640_PWR_DAC_R2_BIT, 0, NULL, 0),
1266
1267 SND_SOC_DAPM_MIXER("OUT MIXL", RT5640_PWR_MIXER, RT5640_PWR_OM_L_BIT,
1268 0, rt5639_out_l_mix, ARRAY_SIZE(rt5639_out_l_mix)),
1269 SND_SOC_DAPM_MIXER("OUT MIXR", RT5640_PWR_MIXER, RT5640_PWR_OM_R_BIT,
1270 0, rt5639_out_r_mix, ARRAY_SIZE(rt5639_out_r_mix)),
1271
1272 SND_SOC_DAPM_MIXER("HPO MIX L", SND_SOC_NOPM, 0, 0,
1273 rt5639_hpo_mix, ARRAY_SIZE(rt5639_hpo_mix)),
1274 SND_SOC_DAPM_MIXER("HPO MIX R", SND_SOC_NOPM, 0, 0,
1275 rt5639_hpo_mix, ARRAY_SIZE(rt5639_hpo_mix)),
1276};
1277
1258static const struct snd_soc_dapm_route rt5640_dapm_routes[] = { 1278static const struct snd_soc_dapm_route rt5640_dapm_routes[] = {
1259 {"IN1P", NULL, "LDO2"}, 1279 {"IN1P", NULL, "LDO2"},
1260 {"IN2P", NULL, "LDO2"}, 1280 {"IN2P", NULL, "LDO2"},
@@ -1323,22 +1343,22 @@ static const struct snd_soc_dapm_route rt5640_dapm_routes[] = {
1323 {"Stereo ADC MIXL", "ADC1 Switch", "Stereo ADC L1 Mux"}, 1343 {"Stereo ADC MIXL", "ADC1 Switch", "Stereo ADC L1 Mux"},
1324 {"Stereo ADC MIXL", "ADC2 Switch", "Stereo ADC L2 Mux"}, 1344 {"Stereo ADC MIXL", "ADC2 Switch", "Stereo ADC L2 Mux"},
1325 {"Stereo ADC MIXL", NULL, "Stereo Filter"}, 1345 {"Stereo ADC MIXL", NULL, "Stereo Filter"},
1326 {"Stereo Filter", NULL, "PLL1", check_sysclk1_source}, 1346 {"Stereo Filter", NULL, "PLL1", is_sys_clk_from_pll},
1327 1347
1328 {"Stereo ADC MIXR", "ADC1 Switch", "Stereo ADC R1 Mux"}, 1348 {"Stereo ADC MIXR", "ADC1 Switch", "Stereo ADC R1 Mux"},
1329 {"Stereo ADC MIXR", "ADC2 Switch", "Stereo ADC R2 Mux"}, 1349 {"Stereo ADC MIXR", "ADC2 Switch", "Stereo ADC R2 Mux"},
1330 {"Stereo ADC MIXR", NULL, "Stereo Filter"}, 1350 {"Stereo ADC MIXR", NULL, "Stereo Filter"},
1331 {"Stereo Filter", NULL, "PLL1", check_sysclk1_source}, 1351 {"Stereo Filter", NULL, "PLL1", is_sys_clk_from_pll},
1332 1352
1333 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"}, 1353 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
1334 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"}, 1354 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
1335 {"Mono ADC MIXL", NULL, "Mono Left Filter"}, 1355 {"Mono ADC MIXL", NULL, "Mono Left Filter"},
1336 {"Mono Left Filter", NULL, "PLL1", check_sysclk1_source}, 1356 {"Mono Left Filter", NULL, "PLL1", is_sys_clk_from_pll},
1337 1357
1338 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"}, 1358 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
1339 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"}, 1359 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
1340 {"Mono ADC MIXR", NULL, "Mono Right Filter"}, 1360 {"Mono ADC MIXR", NULL, "Mono Right Filter"},
1341 {"Mono Right Filter", NULL, "PLL1", check_sysclk1_source}, 1361 {"Mono Right Filter", NULL, "PLL1", is_sys_clk_from_pll},
1342 1362
1343 {"IF2 ADC L", NULL, "Mono ADC MIXL"}, 1363 {"IF2 ADC L", NULL, "Mono ADC MIXL"},
1344 {"IF2 ADC R", NULL, "Mono ADC MIXR"}, 1364 {"IF2 ADC R", NULL, "Mono ADC MIXR"},
@@ -1396,71 +1416,38 @@ static const struct snd_soc_dapm_route rt5640_dapm_routes[] = {
1396 {"DAC MIXR", "Stereo ADC Switch", "Stereo ADC MIXR"}, 1416 {"DAC MIXR", "Stereo ADC Switch", "Stereo ADC MIXR"},
1397 {"DAC MIXR", "INF1 Switch", "IF1 DAC R"}, 1417 {"DAC MIXR", "INF1 Switch", "IF1 DAC R"},
1398 1418
1399 {"ANC", NULL, "Stereo ADC MIXL"},
1400 {"ANC", NULL, "Stereo ADC MIXR"},
1401
1402 {"Audio DSP", NULL, "DAC MIXL"},
1403 {"Audio DSP", NULL, "DAC MIXR"},
1404
1405 {"DAC L2 Mux", "IF2", "IF2 DAC L"},
1406 {"DAC L2 Mux", "Base L/R", "Audio DSP"},
1407
1408 {"DAC R2 Mux", "IF2", "IF2 DAC R"},
1409
1410 {"Stereo DAC MIXL", "DAC L1 Switch", "DAC MIXL"}, 1419 {"Stereo DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
1411 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1412 {"Stereo DAC MIXL", "ANC Switch", "ANC"},
1413 {"Stereo DAC MIXR", "DAC R1 Switch", "DAC MIXR"}, 1420 {"Stereo DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
1414 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1415 {"Stereo DAC MIXR", "ANC Switch", "ANC"},
1416 1421
1417 {"Mono DAC MIXL", "DAC L1 Switch", "DAC MIXL"}, 1422 {"Mono DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
1418 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1419 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
1420 {"Mono DAC MIXR", "DAC R1 Switch", "DAC MIXR"}, 1423 {"Mono DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
1421 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1422 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
1423 1424
1424 {"DIG MIXL", "DAC L1 Switch", "DAC MIXL"}, 1425 {"DIG MIXL", "DAC L1 Switch", "DAC MIXL"},
1425 {"DIG MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1426 {"DIG MIXR", "DAC R1 Switch", "DAC MIXR"}, 1426 {"DIG MIXR", "DAC R1 Switch", "DAC MIXR"},
1427 {"DIG MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1428 1427
1429 {"DAC L1", NULL, "Stereo DAC MIXL"}, 1428 {"DAC L1", NULL, "Stereo DAC MIXL"},
1430 {"DAC L1", NULL, "PLL1", check_sysclk1_source}, 1429 {"DAC L1", NULL, "PLL1", is_sys_clk_from_pll},
1431 {"DAC R1", NULL, "Stereo DAC MIXR"}, 1430 {"DAC R1", NULL, "Stereo DAC MIXR"},
1432 {"DAC R1", NULL, "PLL1", check_sysclk1_source}, 1431 {"DAC R1", NULL, "PLL1", is_sys_clk_from_pll},
1433 {"DAC L2", NULL, "Mono DAC MIXL"},
1434 {"DAC L2", NULL, "PLL1", check_sysclk1_source},
1435 {"DAC R2", NULL, "Mono DAC MIXR"},
1436 {"DAC R2", NULL, "PLL1", check_sysclk1_source},
1437 1432
1438 {"SPK MIXL", "REC MIXL Switch", "RECMIXL"}, 1433 {"SPK MIXL", "REC MIXL Switch", "RECMIXL"},
1439 {"SPK MIXL", "INL Switch", "INL VOL"}, 1434 {"SPK MIXL", "INL Switch", "INL VOL"},
1440 {"SPK MIXL", "DAC L1 Switch", "DAC L1"}, 1435 {"SPK MIXL", "DAC L1 Switch", "DAC L1"},
1441 {"SPK MIXL", "DAC L2 Switch", "DAC L2"},
1442 {"SPK MIXL", "OUT MIXL Switch", "OUT MIXL"}, 1436 {"SPK MIXL", "OUT MIXL Switch", "OUT MIXL"},
1443 {"SPK MIXR", "REC MIXR Switch", "RECMIXR"}, 1437 {"SPK MIXR", "REC MIXR Switch", "RECMIXR"},
1444 {"SPK MIXR", "INR Switch", "INR VOL"}, 1438 {"SPK MIXR", "INR Switch", "INR VOL"},
1445 {"SPK MIXR", "DAC R1 Switch", "DAC R1"}, 1439 {"SPK MIXR", "DAC R1 Switch", "DAC R1"},
1446 {"SPK MIXR", "DAC R2 Switch", "DAC R2"},
1447 {"SPK MIXR", "OUT MIXR Switch", "OUT MIXR"}, 1440 {"SPK MIXR", "OUT MIXR Switch", "OUT MIXR"},
1448 1441
1449 {"OUT MIXL", "SPK MIXL Switch", "SPK MIXL"},
1450 {"OUT MIXL", "BST1 Switch", "BST1"}, 1442 {"OUT MIXL", "BST1 Switch", "BST1"},
1451 {"OUT MIXL", "INL Switch", "INL VOL"}, 1443 {"OUT MIXL", "INL Switch", "INL VOL"},
1452 {"OUT MIXL", "REC MIXL Switch", "RECMIXL"}, 1444 {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
1453 {"OUT MIXL", "DAC R2 Switch", "DAC R2"},
1454 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
1455 {"OUT MIXL", "DAC L1 Switch", "DAC L1"}, 1445 {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
1456 1446
1457 {"OUT MIXR", "SPK MIXR Switch", "SPK MIXR"},
1458 {"OUT MIXR", "BST2 Switch", "BST2"}, 1447 {"OUT MIXR", "BST2 Switch", "BST2"},
1459 {"OUT MIXR", "BST1 Switch", "BST1"}, 1448 {"OUT MIXR", "BST1 Switch", "BST1"},
1460 {"OUT MIXR", "INR Switch", "INR VOL"}, 1449 {"OUT MIXR", "INR Switch", "INR VOL"},
1461 {"OUT MIXR", "REC MIXR Switch", "RECMIXR"}, 1450 {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
1462 {"OUT MIXR", "DAC L2 Switch", "DAC L2"},
1463 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
1464 {"OUT MIXR", "DAC R1 Switch", "DAC R1"}, 1451 {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
1465 1452
1466 {"SPKVOL L", NULL, "SPK MIXL"}, 1453 {"SPKVOL L", NULL, "SPK MIXL"},
@@ -1479,11 +1466,9 @@ static const struct snd_soc_dapm_route rt5640_dapm_routes[] = {
1479 {"SPOR MIX", "SPKVOL R Switch", "SPKVOL R"}, 1466 {"SPOR MIX", "SPKVOL R Switch", "SPKVOL R"},
1480 {"SPOR MIX", "BST1 Switch", "BST1"}, 1467 {"SPOR MIX", "BST1 Switch", "BST1"},
1481 1468
1482 {"HPO MIX L", "HPO MIX DAC2 Switch", "DAC L2"},
1483 {"HPO MIX L", "HPO MIX DAC1 Switch", "DAC L1"}, 1469 {"HPO MIX L", "HPO MIX DAC1 Switch", "DAC L1"},
1484 {"HPO MIX L", "HPO MIX HPVOL Switch", "HPOVOL L"}, 1470 {"HPO MIX L", "HPO MIX HPVOL Switch", "HPOVOL L"},
1485 {"HPO MIX L", NULL, "HP L Amp"}, 1471 {"HPO MIX L", NULL, "HP L Amp"},
1486 {"HPO MIX R", "HPO MIX DAC2 Switch", "DAC R2"},
1487 {"HPO MIX R", "HPO MIX DAC1 Switch", "DAC R1"}, 1472 {"HPO MIX R", "HPO MIX DAC1 Switch", "DAC R1"},
1488 {"HPO MIX R", "HPO MIX HPVOL Switch", "HPOVOL R"}, 1473 {"HPO MIX R", "HPO MIX HPVOL Switch", "HPOVOL R"},
1489 {"HPO MIX R", NULL, "HP R Amp"}, 1474 {"HPO MIX R", NULL, "HP R Amp"},
@@ -1493,12 +1478,6 @@ static const struct snd_soc_dapm_route rt5640_dapm_routes[] = {
1493 {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"}, 1478 {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
1494 {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"}, 1479 {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
1495 1480
1496 {"Mono MIX", "DAC R2 Switch", "DAC R2"},
1497 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
1498 {"Mono MIX", "OUTVOL R Switch", "OUTVOL R"},
1499 {"Mono MIX", "OUTVOL L Switch", "OUTVOL L"},
1500 {"Mono MIX", "BST1 Switch", "BST1"},
1501
1502 {"HP Amp", NULL, "HPO MIX L"}, 1481 {"HP Amp", NULL, "HPO MIX L"},
1503 {"HP Amp", NULL, "HPO MIX R"}, 1482 {"HP Amp", NULL, "HPO MIX R"},
1504 1483
@@ -1523,11 +1502,82 @@ static const struct snd_soc_dapm_route rt5640_dapm_routes[] = {
1523 {"HPOR", NULL, "HP R Playback"}, 1502 {"HPOR", NULL, "HP R Playback"},
1524 {"LOUTL", NULL, "LOUT MIX"}, 1503 {"LOUTL", NULL, "LOUT MIX"},
1525 {"LOUTR", NULL, "LOUT MIX"}, 1504 {"LOUTR", NULL, "LOUT MIX"},
1505};
1506
1507static const struct snd_soc_dapm_route rt5640_specific_dapm_routes[] = {
1508 {"ANC", NULL, "Stereo ADC MIXL"},
1509 {"ANC", NULL, "Stereo ADC MIXR"},
1510
1511 {"Audio DSP", NULL, "DAC MIXL"},
1512 {"Audio DSP", NULL, "DAC MIXR"},
1513
1514 {"DAC L2 Mux", "IF2", "IF2 DAC L"},
1515 {"DAC L2 Mux", "Base L/R", "Audio DSP"},
1516
1517 {"DAC R2 Mux", "IF2", "IF2 DAC R"},
1518
1519 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1520 {"Stereo DAC MIXL", "ANC Switch", "ANC"},
1521 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1522 {"Stereo DAC MIXR", "ANC Switch", "ANC"},
1523
1524 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1525 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
1526
1527 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1528 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
1529
1530 {"DIG MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1531 {"DIG MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1532
1533 {"DAC L2", NULL, "Mono DAC MIXL"},
1534 {"DAC L2", NULL, "PLL1", is_sys_clk_from_pll},
1535 {"DAC R2", NULL, "Mono DAC MIXR"},
1536 {"DAC R2", NULL, "PLL1", is_sys_clk_from_pll},
1537
1538 {"SPK MIXL", "DAC L2 Switch", "DAC L2"},
1539 {"SPK MIXR", "DAC R2 Switch", "DAC R2"},
1540
1541 {"OUT MIXL", "SPK MIXL Switch", "SPK MIXL"},
1542 {"OUT MIXR", "SPK MIXR Switch", "SPK MIXR"},
1543
1544 {"OUT MIXL", "DAC R2 Switch", "DAC R2"},
1545 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
1546
1547 {"OUT MIXR", "DAC L2 Switch", "DAC L2"},
1548 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
1549
1550 {"HPO MIX L", "HPO MIX DAC2 Switch", "DAC L2"},
1551 {"HPO MIX R", "HPO MIX DAC2 Switch", "DAC R2"},
1552
1553 {"Mono MIX", "DAC R2 Switch", "DAC R2"},
1554 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
1555 {"Mono MIX", "OUTVOL R Switch", "OUTVOL R"},
1556 {"Mono MIX", "OUTVOL L Switch", "OUTVOL L"},
1557 {"Mono MIX", "BST1 Switch", "BST1"},
1558
1526 {"MONOP", NULL, "Mono MIX"}, 1559 {"MONOP", NULL, "Mono MIX"},
1527 {"MONON", NULL, "Mono MIX"}, 1560 {"MONON", NULL, "Mono MIX"},
1528 {"MONOP", NULL, "Improve MONO Amp Drv"}, 1561 {"MONOP", NULL, "Improve MONO Amp Drv"},
1529}; 1562};
1530 1563
1564static const struct snd_soc_dapm_route rt5639_specific_dapm_routes[] = {
1565 {"Stereo DAC MIXL", "DAC L2 Switch", "IF2 DAC L"},
1566 {"Stereo DAC MIXR", "DAC R2 Switch", "IF2 DAC R"},
1567
1568 {"Mono DAC MIXL", "DAC L2 Switch", "IF2 DAC L"},
1569 {"Mono DAC MIXL", "DAC R2 Switch", "IF2 DAC R"},
1570
1571 {"Mono DAC MIXR", "DAC R2 Switch", "IF2 DAC R"},
1572 {"Mono DAC MIXR", "DAC L2 Switch", "IF2 DAC L"},
1573
1574 {"DIG MIXL", "DAC L2 Switch", "IF2 DAC L"},
1575 {"DIG MIXR", "DAC R2 Switch", "IF2 DAC R"},
1576
1577 {"IF2 DAC L", NULL, "DAC L2 Filter"},
1578 {"IF2 DAC R", NULL, "DAC R2 Filter"},
1579};
1580
1531static int get_sdp_info(struct snd_soc_codec *codec, int dai_id) 1581static int get_sdp_info(struct snd_soc_codec *codec, int dai_id)
1532{ 1582{
1533 int ret = 0, val; 1583 int ret = 0, val;
@@ -1576,21 +1626,6 @@ static int get_sdp_info(struct snd_soc_codec *codec, int dai_id)
1576 return ret; 1626 return ret;
1577} 1627}
1578 1628
1579static int get_clk_info(int sclk, int rate)
1580{
1581 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
1582
1583 if (sclk <= 0 || rate <= 0)
1584 return -EINVAL;
1585
1586 rate = rate << 8;
1587 for (i = 0; i < ARRAY_SIZE(pd); i++)
1588 if (sclk == rate * pd[i])
1589 return i;
1590
1591 return -EINVAL;
1592}
1593
1594static int rt5640_hw_params(struct snd_pcm_substream *substream, 1629static int rt5640_hw_params(struct snd_pcm_substream *substream,
1595 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1630 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1596{ 1631{
@@ -1600,7 +1635,7 @@ static int rt5640_hw_params(struct snd_pcm_substream *substream,
1600 int dai_sel, pre_div, bclk_ms, frame_size; 1635 int dai_sel, pre_div, bclk_ms, frame_size;
1601 1636
1602 rt5640->lrck[dai->id] = params_rate(params); 1637 rt5640->lrck[dai->id] = params_rate(params);
1603 pre_div = get_clk_info(rt5640->sysclk, rt5640->lrck[dai->id]); 1638 pre_div = rl6231_get_clk_info(rt5640->sysclk, rt5640->lrck[dai->id]);
1604 if (pre_div < 0) { 1639 if (pre_div < 0) {
1605 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n", 1640 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
1606 rt5640->lrck[dai->id], dai->id); 1641 rt5640->lrck[dai->id], dai->id);
@@ -1622,16 +1657,16 @@ static int rt5640_hw_params(struct snd_pcm_substream *substream,
1622 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", 1657 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1623 bclk_ms, pre_div, dai->id); 1658 bclk_ms, pre_div, dai->id);
1624 1659
1625 switch (params_format(params)) { 1660 switch (params_width(params)) {
1626 case SNDRV_PCM_FORMAT_S16_LE: 1661 case 16:
1627 break; 1662 break;
1628 case SNDRV_PCM_FORMAT_S20_3LE: 1663 case 20:
1629 val_len |= RT5640_I2S_DL_20; 1664 val_len |= RT5640_I2S_DL_20;
1630 break; 1665 break;
1631 case SNDRV_PCM_FORMAT_S24_LE: 1666 case 24:
1632 val_len |= RT5640_I2S_DL_24; 1667 val_len |= RT5640_I2S_DL_24;
1633 break; 1668 break;
1634 case SNDRV_PCM_FORMAT_S8: 1669 case 8:
1635 val_len |= RT5640_I2S_DL_8; 1670 val_len |= RT5640_I2S_DL_8;
1636 break; 1671 break;
1637 default: 1672 default:
@@ -1744,12 +1779,6 @@ static int rt5640_set_dai_sysclk(struct snd_soc_dai *dai,
1744 case RT5640_SCLK_S_PLL1: 1779 case RT5640_SCLK_S_PLL1:
1745 reg_val |= RT5640_SCLK_SRC_PLL1; 1780 reg_val |= RT5640_SCLK_SRC_PLL1;
1746 break; 1781 break;
1747 case RT5640_SCLK_S_PLL1_TK:
1748 reg_val |= RT5640_SCLK_SRC_PLL1T;
1749 break;
1750 case RT5640_SCLK_S_RCCLK:
1751 reg_val |= RT5640_SCLK_SRC_RCCLK;
1752 break;
1753 default: 1782 default:
1754 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); 1783 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
1755 return -EINVAL; 1784 return -EINVAL;
@@ -1763,65 +1792,12 @@ static int rt5640_set_dai_sysclk(struct snd_soc_dai *dai,
1763 return 0; 1792 return 0;
1764} 1793}
1765 1794
1766/**
1767 * rt5640_pll_calc - Calculate PLL M/N/K code.
1768 * @freq_in: external clock provided to codec.
1769 * @freq_out: target clock which codec works on.
1770 * @pll_code: Pointer to structure with M, N, K and bypass flag.
1771 *
1772 * Calculate M/N/K code to configure PLL for codec. And K is assigned to 2
1773 * which make calculation more efficiently.
1774 *
1775 * Returns 0 for success or negative error code.
1776 */
1777static int rt5640_pll_calc(const unsigned int freq_in,
1778 const unsigned int freq_out, struct rt5640_pll_code *pll_code)
1779{
1780 int max_n = RT5640_PLL_N_MAX, max_m = RT5640_PLL_M_MAX;
1781 int n = 0, m = 0, red, n_t, m_t, in_t, out_t;
1782 int red_t = abs(freq_out - freq_in);
1783 bool bypass = false;
1784
1785 if (RT5640_PLL_INP_MAX < freq_in || RT5640_PLL_INP_MIN > freq_in)
1786 return -EINVAL;
1787
1788 for (n_t = 0; n_t <= max_n; n_t++) {
1789 in_t = (freq_in >> 1) + (freq_in >> 2) * n_t;
1790 if (in_t < 0)
1791 continue;
1792 if (in_t == freq_out) {
1793 bypass = true;
1794 n = n_t;
1795 goto code_find;
1796 }
1797 for (m_t = 0; m_t <= max_m; m_t++) {
1798 out_t = in_t / (m_t + 2);
1799 red = abs(out_t - freq_out);
1800 if (red < red_t) {
1801 n = n_t;
1802 m = m_t;
1803 if (red == 0)
1804 goto code_find;
1805 red_t = red;
1806 }
1807 }
1808 }
1809 pr_debug("Only get approximation about PLL\n");
1810
1811code_find:
1812 pll_code->m_bp = bypass;
1813 pll_code->m_code = m;
1814 pll_code->n_code = n;
1815 pll_code->k_code = 2;
1816 return 0;
1817}
1818
1819static int rt5640_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 1795static int rt5640_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
1820 unsigned int freq_in, unsigned int freq_out) 1796 unsigned int freq_in, unsigned int freq_out)
1821{ 1797{
1822 struct snd_soc_codec *codec = dai->codec; 1798 struct snd_soc_codec *codec = dai->codec;
1823 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec); 1799 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
1824 struct rt5640_pll_code *pll_code = &rt5640->pll_code; 1800 struct rl6231_pll_code pll_code;
1825 int ret, dai_sel; 1801 int ret, dai_sel;
1826 1802
1827 if (source == rt5640->pll_src && freq_in == rt5640->pll_in && 1803 if (source == rt5640->pll_src && freq_in == rt5640->pll_in &&
@@ -1865,20 +1841,21 @@ static int rt5640_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
1865 return -EINVAL; 1841 return -EINVAL;
1866 } 1842 }
1867 1843
1868 ret = rt5640_pll_calc(freq_in, freq_out, pll_code); 1844 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1869 if (ret < 0) { 1845 if (ret < 0) {
1870 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in); 1846 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
1871 return ret; 1847 return ret;
1872 } 1848 }
1873 1849
1874 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=2\n", pll_code->m_bp, 1850 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
1875 (pll_code->m_bp ? 0 : pll_code->m_code), pll_code->n_code); 1851 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
1852 pll_code.n_code, pll_code.k_code);
1876 1853
1877 snd_soc_write(codec, RT5640_PLL_CTRL1, 1854 snd_soc_write(codec, RT5640_PLL_CTRL1,
1878 pll_code->n_code << RT5640_PLL_N_SFT | pll_code->k_code); 1855 pll_code.n_code << RT5640_PLL_N_SFT | pll_code.k_code);
1879 snd_soc_write(codec, RT5640_PLL_CTRL2, 1856 snd_soc_write(codec, RT5640_PLL_CTRL2,
1880 (pll_code->m_bp ? 0 : pll_code->m_code) << RT5640_PLL_M_SFT | 1857 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5640_PLL_M_SFT |
1881 pll_code->m_bp << RT5640_PLL_M_BP_SFT); 1858 pll_code.m_bp << RT5640_PLL_M_BP_SFT);
1882 1859
1883 rt5640->pll_in = freq_in; 1860 rt5640->pll_in = freq_in;
1884 rt5640->pll_out = freq_out; 1861 rt5640->pll_out = freq_out;
@@ -1890,11 +1867,9 @@ static int rt5640_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
1890static int rt5640_set_bias_level(struct snd_soc_codec *codec, 1867static int rt5640_set_bias_level(struct snd_soc_codec *codec,
1891 enum snd_soc_bias_level level) 1868 enum snd_soc_bias_level level)
1892{ 1869{
1893 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
1894 switch (level) { 1870 switch (level) {
1895 case SND_SOC_BIAS_STANDBY: 1871 case SND_SOC_BIAS_STANDBY:
1896 if (SND_SOC_BIAS_OFF == codec->dapm.bias_level) { 1872 if (SND_SOC_BIAS_OFF == codec->dapm.bias_level) {
1897 regcache_cache_only(rt5640->regmap, false);
1898 snd_soc_update_bits(codec, RT5640_PWR_ANLG1, 1873 snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
1899 RT5640_PWR_VREF1 | RT5640_PWR_MB | 1874 RT5640_PWR_VREF1 | RT5640_PWR_MB |
1900 RT5640_PWR_BG | RT5640_PWR_VREF2, 1875 RT5640_PWR_BG | RT5640_PWR_VREF2,
@@ -1904,7 +1879,6 @@ static int rt5640_set_bias_level(struct snd_soc_codec *codec,
1904 snd_soc_update_bits(codec, RT5640_PWR_ANLG1, 1879 snd_soc_update_bits(codec, RT5640_PWR_ANLG1,
1905 RT5640_PWR_FV1 | RT5640_PWR_FV2, 1880 RT5640_PWR_FV1 | RT5640_PWR_FV2,
1906 RT5640_PWR_FV1 | RT5640_PWR_FV2); 1881 RT5640_PWR_FV1 | RT5640_PWR_FV2);
1907 regcache_sync(rt5640->regmap);
1908 snd_soc_update_bits(codec, RT5640_DUMMY1, 1882 snd_soc_update_bits(codec, RT5640_DUMMY1,
1909 0x0301, 0x0301); 1883 0x0301, 0x0301);
1910 snd_soc_update_bits(codec, RT5640_MICBIAS, 1884 snd_soc_update_bits(codec, RT5640_MICBIAS,
@@ -1938,13 +1912,39 @@ static int rt5640_probe(struct snd_soc_codec *codec)
1938 1912
1939 rt5640->codec = codec; 1913 rt5640->codec = codec;
1940 1914
1941 codec->dapm.idle_bias_off = 1;
1942 rt5640_set_bias_level(codec, SND_SOC_BIAS_OFF); 1915 rt5640_set_bias_level(codec, SND_SOC_BIAS_OFF);
1943 1916
1944 snd_soc_update_bits(codec, RT5640_DUMMY1, 0x0301, 0x0301); 1917 snd_soc_update_bits(codec, RT5640_DUMMY1, 0x0301, 0x0301);
1945 snd_soc_update_bits(codec, RT5640_MICBIAS, 0x0030, 0x0030); 1918 snd_soc_update_bits(codec, RT5640_MICBIAS, 0x0030, 0x0030);
1946 snd_soc_update_bits(codec, RT5640_DSP_PATH2, 0xfc00, 0x0c00); 1919 snd_soc_update_bits(codec, RT5640_DSP_PATH2, 0xfc00, 0x0c00);
1947 1920
1921 switch (snd_soc_read(codec, RT5640_RESET) & RT5640_ID_MASK) {
1922 case RT5640_ID_5640:
1923 case RT5640_ID_5642:
1924 snd_soc_add_codec_controls(codec,
1925 rt5640_specific_snd_controls,
1926 ARRAY_SIZE(rt5640_specific_snd_controls));
1927 snd_soc_dapm_new_controls(&codec->dapm,
1928 rt5640_specific_dapm_widgets,
1929 ARRAY_SIZE(rt5640_specific_dapm_widgets));
1930 snd_soc_dapm_add_routes(&codec->dapm,
1931 rt5640_specific_dapm_routes,
1932 ARRAY_SIZE(rt5640_specific_dapm_routes));
1933 break;
1934 case RT5640_ID_5639:
1935 snd_soc_dapm_new_controls(&codec->dapm,
1936 rt5639_specific_dapm_widgets,
1937 ARRAY_SIZE(rt5639_specific_dapm_widgets));
1938 snd_soc_dapm_add_routes(&codec->dapm,
1939 rt5639_specific_dapm_routes,
1940 ARRAY_SIZE(rt5639_specific_dapm_routes));
1941 break;
1942 default:
1943 dev_err(codec->dev,
1944 "The driver is for RT5639 RT5640 or RT5642 only\n");
1945 return -ENODEV;
1946 }
1947
1948 return 0; 1948 return 0;
1949} 1949}
1950 1950
@@ -1979,6 +1979,9 @@ static int rt5640_resume(struct snd_soc_codec *codec)
1979 msleep(400); 1979 msleep(400);
1980 } 1980 }
1981 1981
1982 regcache_cache_only(rt5640->regmap, false);
1983 regcache_sync(rt5640->regmap);
1984
1982 return 0; 1985 return 0;
1983} 1986}
1984#else 1987#else
@@ -2044,6 +2047,7 @@ static struct snd_soc_codec_driver soc_codec_dev_rt5640 = {
2044 .suspend = rt5640_suspend, 2047 .suspend = rt5640_suspend,
2045 .resume = rt5640_resume, 2048 .resume = rt5640_resume,
2046 .set_bias_level = rt5640_set_bias_level, 2049 .set_bias_level = rt5640_set_bias_level,
2050 .idle_bias_off = true,
2047 .controls = rt5640_snd_controls, 2051 .controls = rt5640_snd_controls,
2048 .num_controls = ARRAY_SIZE(rt5640_snd_controls), 2052 .num_controls = ARRAY_SIZE(rt5640_snd_controls),
2049 .dapm_widgets = rt5640_dapm_widgets, 2053 .dapm_widgets = rt5640_dapm_widgets,
@@ -2070,12 +2074,15 @@ static const struct regmap_config rt5640_regmap = {
2070 2074
2071static const struct i2c_device_id rt5640_i2c_id[] = { 2075static const struct i2c_device_id rt5640_i2c_id[] = {
2072 { "rt5640", 0 }, 2076 { "rt5640", 0 },
2077 { "rt5639", 0 },
2078 { "rt5642", 0 },
2073 { } 2079 { }
2074}; 2080};
2075MODULE_DEVICE_TABLE(i2c, rt5640_i2c_id); 2081MODULE_DEVICE_TABLE(i2c, rt5640_i2c_id);
2076 2082
2077#if defined(CONFIG_OF) 2083#if defined(CONFIG_OF)
2078static const struct of_device_id rt5640_of_match[] = { 2084static const struct of_device_id rt5640_of_match[] = {
2085 { .compatible = "realtek,rt5639", },
2079 { .compatible = "realtek,rt5640", }, 2086 { .compatible = "realtek,rt5640", },
2080 {}, 2087 {},
2081}; 2088};
@@ -2166,7 +2173,7 @@ static int rt5640_i2c_probe(struct i2c_client *i2c,
2166 } 2173 }
2167 2174
2168 regmap_read(rt5640->regmap, RT5640_VENDOR_ID2, &val); 2175 regmap_read(rt5640->regmap, RT5640_VENDOR_ID2, &val);
2169 if ((val != RT5640_DEVICE_ID)) { 2176 if (val != RT5640_DEVICE_ID) {
2170 dev_err(&i2c->dev, 2177 dev_err(&i2c->dev,
2171 "Device with ID register %x is not rt5640/39\n", val); 2178 "Device with ID register %x is not rt5640/39\n", val);
2172 return -ENODEV; 2179 return -ENODEV;
@@ -2187,6 +2194,25 @@ static int rt5640_i2c_probe(struct i2c_client *i2c,
2187 regmap_update_bits(rt5640->regmap, RT5640_IN3_IN4, 2194 regmap_update_bits(rt5640->regmap, RT5640_IN3_IN4,
2188 RT5640_IN_DF2, RT5640_IN_DF2); 2195 RT5640_IN_DF2, RT5640_IN_DF2);
2189 2196
2197 if (rt5640->pdata.dmic_en) {
2198 regmap_update_bits(rt5640->regmap, RT5640_GPIO_CTRL1,
2199 RT5640_GP2_PIN_MASK, RT5640_GP2_PIN_DMIC1_SCL);
2200
2201 if (rt5640->pdata.dmic1_data_pin) {
2202 regmap_update_bits(rt5640->regmap, RT5640_DMIC,
2203 RT5640_DMIC_1_DP_MASK, RT5640_DMIC_1_DP_GPIO3);
2204 regmap_update_bits(rt5640->regmap, RT5640_GPIO_CTRL1,
2205 RT5640_GP3_PIN_MASK, RT5640_GP3_PIN_DMIC1_SDA);
2206 }
2207
2208 if (rt5640->pdata.dmic2_data_pin) {
2209 regmap_update_bits(rt5640->regmap, RT5640_DMIC,
2210 RT5640_DMIC_2_DP_MASK, RT5640_DMIC_2_DP_GPIO4);
2211 regmap_update_bits(rt5640->regmap, RT5640_GPIO_CTRL1,
2212 RT5640_GP4_PIN_MASK, RT5640_GP4_PIN_DMIC2_SDA);
2213 }
2214 }
2215
2190 rt5640->hp_mute = 1; 2216 rt5640->hp_mute = 1;
2191 2217
2192 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5640, 2218 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5640,
@@ -2219,6 +2245,6 @@ static struct i2c_driver rt5640_i2c_driver = {
2219}; 2245};
2220module_i2c_driver(rt5640_i2c_driver); 2246module_i2c_driver(rt5640_i2c_driver);
2221 2247
2222MODULE_DESCRIPTION("ASoC RT5640 driver"); 2248MODULE_DESCRIPTION("ASoC RT5640/RT5639 driver");
2223MODULE_AUTHOR("Johnny Hsu <johnnyhsu@realtek.com>"); 2249MODULE_AUTHOR("Johnny Hsu <johnnyhsu@realtek.com>");
2224MODULE_LICENSE("GPL v2"); 2250MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/rt5640.h b/sound/soc/codecs/rt5640.h
index 5e8df25a13f3..58ebe96b86da 100644
--- a/sound/soc/codecs/rt5640.h
+++ b/sound/soc/codecs/rt5640.h
@@ -192,6 +192,13 @@
192#define RT5640_R_VOL_MASK (0x3f) 192#define RT5640_R_VOL_MASK (0x3f)
193#define RT5640_R_VOL_SFT 0 193#define RT5640_R_VOL_SFT 0
194 194
195/* SW Reset & Device ID (0x00) */
196#define RT5640_ID_MASK (0x3 << 1)
197#define RT5640_ID_5639 (0x0 << 1)
198#define RT5640_ID_5640 (0x2 << 1)
199#define RT5640_ID_5642 (0x3 << 1)
200
201
195/* IN1 and IN2 Control (0x0d) */ 202/* IN1 and IN2 Control (0x0d) */
196/* IN3 and IN4 Control (0x0e) */ 203/* IN3 and IN4 Control (0x0e) */
197#define RT5640_BST_SFT1 12 204#define RT5640_BST_SFT1 12
@@ -976,8 +983,6 @@
976#define RT5640_SCLK_SRC_SFT 14 983#define RT5640_SCLK_SRC_SFT 14
977#define RT5640_SCLK_SRC_MCLK (0x0 << 14) 984#define RT5640_SCLK_SRC_MCLK (0x0 << 14)
978#define RT5640_SCLK_SRC_PLL1 (0x1 << 14) 985#define RT5640_SCLK_SRC_PLL1 (0x1 << 14)
979#define RT5640_SCLK_SRC_PLL1T (0x2 << 14)
980#define RT5640_SCLK_SRC_RCCLK (0x3 << 14) /* 15MHz */
981#define RT5640_PLL1_SRC_MASK (0x3 << 12) 986#define RT5640_PLL1_SRC_MASK (0x3 << 12)
982#define RT5640_PLL1_SRC_SFT 12 987#define RT5640_PLL1_SRC_SFT 12
983#define RT5640_PLL1_SRC_MCLK (0x0 << 12) 988#define RT5640_PLL1_SRC_MCLK (0x0 << 12)
@@ -2074,13 +2079,6 @@ enum {
2074 RT5640_DMIC2, 2079 RT5640_DMIC2,
2075}; 2080};
2076 2081
2077struct rt5640_pll_code {
2078 bool m_bp; /* Indicates bypass m code or not. */
2079 int m_code;
2080 int n_code;
2081 int k_code;
2082};
2083
2084struct rt5640_priv { 2082struct rt5640_priv {
2085 struct snd_soc_codec *codec; 2083 struct snd_soc_codec *codec;
2086 struct rt5640_platform_data pdata; 2084 struct rt5640_platform_data pdata;
@@ -2092,12 +2090,10 @@ struct rt5640_priv {
2092 int bclk[RT5640_AIFS]; 2090 int bclk[RT5640_AIFS];
2093 int master[RT5640_AIFS]; 2091 int master[RT5640_AIFS];
2094 2092
2095 struct rt5640_pll_code pll_code;
2096 int pll_src; 2093 int pll_src;
2097 int pll_in; 2094 int pll_in;
2098 int pll_out; 2095 int pll_out;
2099 2096
2100 int dmic_en;
2101 bool hp_mute; 2097 bool hp_mute;
2102}; 2098};
2103 2099
diff --git a/sound/soc/codecs/rt5645.c b/sound/soc/codecs/rt5645.c
new file mode 100644
index 000000000000..02147be2b302
--- /dev/null
+++ b/sound/soc/codecs/rt5645.c
@@ -0,0 +1,2378 @@
1/*
2 * rt5645.c -- RT5645 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
20#include <sound/core.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/jack.h>
24#include <sound/soc.h>
25#include <sound/soc-dapm.h>
26#include <sound/initval.h>
27#include <sound/tlv.h>
28
29#include "rl6231.h"
30#include "rt5645.h"
31
32#define RT5645_DEVICE_ID 0x6308
33
34#define RT5645_PR_RANGE_BASE (0xff + 1)
35#define RT5645_PR_SPACING 0x100
36
37#define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
38
39static const struct regmap_range_cfg rt5645_ranges[] = {
40 {
41 .name = "PR",
42 .range_min = RT5645_PR_BASE,
43 .range_max = RT5645_PR_BASE + 0xf8,
44 .selector_reg = RT5645_PRIV_INDEX,
45 .selector_mask = 0xff,
46 .selector_shift = 0x0,
47 .window_start = RT5645_PRIV_DATA,
48 .window_len = 0x1,
49 },
50};
51
52static const struct reg_default init_list[] = {
53 {RT5645_PR_BASE + 0x3d, 0x3600},
54 {RT5645_PR_BASE + 0x1c, 0xfd20},
55 {RT5645_PR_BASE + 0x20, 0x611f},
56 {RT5645_PR_BASE + 0x21, 0x4040},
57 {RT5645_PR_BASE + 0x23, 0x0004},
58};
59#define RT5645_INIT_REG_LEN ARRAY_SIZE(init_list)
60
61static const struct reg_default rt5645_reg[] = {
62 { 0x00, 0x0000 },
63 { 0x01, 0xc8c8 },
64 { 0x02, 0xc8c8 },
65 { 0x03, 0xc8c8 },
66 { 0x0a, 0x0002 },
67 { 0x0b, 0x2827 },
68 { 0x0c, 0xe000 },
69 { 0x0d, 0x0000 },
70 { 0x0e, 0x0000 },
71 { 0x0f, 0x0808 },
72 { 0x14, 0x3333 },
73 { 0x16, 0x4b00 },
74 { 0x18, 0x018b },
75 { 0x19, 0xafaf },
76 { 0x1a, 0xafaf },
77 { 0x1b, 0x0001 },
78 { 0x1c, 0x2f2f },
79 { 0x1d, 0x2f2f },
80 { 0x1e, 0x0000 },
81 { 0x20, 0x0000 },
82 { 0x27, 0x7060 },
83 { 0x28, 0x7070 },
84 { 0x29, 0x8080 },
85 { 0x2a, 0x5656 },
86 { 0x2b, 0x5454 },
87 { 0x2c, 0xaaa0 },
88 { 0x2f, 0x1002 },
89 { 0x31, 0x5000 },
90 { 0x32, 0x0000 },
91 { 0x33, 0x0000 },
92 { 0x34, 0x0000 },
93 { 0x35, 0x0000 },
94 { 0x3b, 0x0000 },
95 { 0x3c, 0x007f },
96 { 0x3d, 0x0000 },
97 { 0x3e, 0x007f },
98 { 0x3f, 0x0000 },
99 { 0x40, 0x001f },
100 { 0x41, 0x0000 },
101 { 0x42, 0x001f },
102 { 0x45, 0x6000 },
103 { 0x46, 0x003e },
104 { 0x47, 0x003e },
105 { 0x48, 0xf807 },
106 { 0x4a, 0x0004 },
107 { 0x4d, 0x0000 },
108 { 0x4e, 0x0000 },
109 { 0x4f, 0x01ff },
110 { 0x50, 0x0000 },
111 { 0x51, 0x0000 },
112 { 0x52, 0x01ff },
113 { 0x53, 0xf000 },
114 { 0x56, 0x0111 },
115 { 0x57, 0x0064 },
116 { 0x58, 0xef0e },
117 { 0x59, 0xf0f0 },
118 { 0x5a, 0xef0e },
119 { 0x5b, 0xf0f0 },
120 { 0x5c, 0xef0e },
121 { 0x5d, 0xf0f0 },
122 { 0x5e, 0xf000 },
123 { 0x5f, 0x0000 },
124 { 0x61, 0x0300 },
125 { 0x62, 0x0000 },
126 { 0x63, 0x00c2 },
127 { 0x64, 0x0000 },
128 { 0x65, 0x0000 },
129 { 0x66, 0x0000 },
130 { 0x6a, 0x0000 },
131 { 0x6c, 0x0aaa },
132 { 0x70, 0x8000 },
133 { 0x71, 0x8000 },
134 { 0x72, 0x8000 },
135 { 0x73, 0x7770 },
136 { 0x74, 0x3e00 },
137 { 0x75, 0x2409 },
138 { 0x76, 0x000a },
139 { 0x77, 0x0c00 },
140 { 0x78, 0x0000 },
141 { 0x80, 0x0000 },
142 { 0x81, 0x0000 },
143 { 0x82, 0x0000 },
144 { 0x83, 0x0000 },
145 { 0x84, 0x0000 },
146 { 0x85, 0x0000 },
147 { 0x8a, 0x0000 },
148 { 0x8e, 0x0004 },
149 { 0x8f, 0x1100 },
150 { 0x90, 0x0646 },
151 { 0x91, 0x0c06 },
152 { 0x93, 0x0000 },
153 { 0x94, 0x0200 },
154 { 0x95, 0x0000 },
155 { 0x9a, 0x2184 },
156 { 0x9b, 0x010a },
157 { 0x9c, 0x0aea },
158 { 0x9d, 0x000c },
159 { 0x9e, 0x0400 },
160 { 0xa0, 0xa0a8 },
161 { 0xa1, 0x0059 },
162 { 0xa2, 0x0001 },
163 { 0xae, 0x6000 },
164 { 0xaf, 0x0000 },
165 { 0xb0, 0x6000 },
166 { 0xb1, 0x0000 },
167 { 0xb2, 0x0000 },
168 { 0xb3, 0x001f },
169 { 0xb4, 0x020c },
170 { 0xb5, 0x1f00 },
171 { 0xb6, 0x0000 },
172 { 0xbb, 0x0000 },
173 { 0xbc, 0x0000 },
174 { 0xbd, 0x0000 },
175 { 0xbe, 0x0000 },
176 { 0xbf, 0x3100 },
177 { 0xc0, 0x0000 },
178 { 0xc1, 0x0000 },
179 { 0xc2, 0x0000 },
180 { 0xc3, 0x2000 },
181 { 0xcd, 0x0000 },
182 { 0xce, 0x0000 },
183 { 0xcf, 0x1813 },
184 { 0xd0, 0x0690 },
185 { 0xd1, 0x1c17 },
186 { 0xd3, 0xb320 },
187 { 0xd4, 0x0000 },
188 { 0xd6, 0x0400 },
189 { 0xd9, 0x0809 },
190 { 0xda, 0x0000 },
191 { 0xdb, 0x0003 },
192 { 0xdc, 0x0049 },
193 { 0xdd, 0x001b },
194 { 0xe6, 0x8000 },
195 { 0xe7, 0x0200 },
196 { 0xec, 0xb300 },
197 { 0xed, 0x0000 },
198 { 0xf0, 0x001f },
199 { 0xf1, 0x020c },
200 { 0xf2, 0x1f00 },
201 { 0xf3, 0x0000 },
202 { 0xf4, 0x4000 },
203 { 0xf8, 0x0000 },
204 { 0xf9, 0x0000 },
205 { 0xfa, 0x2060 },
206 { 0xfb, 0x4040 },
207 { 0xfc, 0x0000 },
208 { 0xfd, 0x0002 },
209 { 0xfe, 0x10ec },
210 { 0xff, 0x6308 },
211};
212
213static int rt5645_reset(struct snd_soc_codec *codec)
214{
215 return snd_soc_write(codec, RT5645_RESET, 0);
216}
217
218static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
219{
220 int i;
221
222 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
223 if (reg >= rt5645_ranges[i].range_min &&
224 reg <= rt5645_ranges[i].range_max) {
225 return true;
226 }
227 }
228
229 switch (reg) {
230 case RT5645_RESET:
231 case RT5645_PRIV_DATA:
232 case RT5645_IN1_CTRL1:
233 case RT5645_IN1_CTRL2:
234 case RT5645_IN1_CTRL3:
235 case RT5645_A_JD_CTRL1:
236 case RT5645_ADC_EQ_CTRL1:
237 case RT5645_EQ_CTRL1:
238 case RT5645_ALC_CTRL_1:
239 case RT5645_IRQ_CTRL2:
240 case RT5645_IRQ_CTRL3:
241 case RT5645_INT_IRQ_ST:
242 case RT5645_IL_CMD:
243 case RT5645_VENDOR_ID:
244 case RT5645_VENDOR_ID1:
245 case RT5645_VENDOR_ID2:
246 return true;
247 default:
248 return false;
249 }
250}
251
252static bool rt5645_readable_register(struct device *dev, unsigned int reg)
253{
254 int i;
255
256 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
257 if (reg >= rt5645_ranges[i].range_min &&
258 reg <= rt5645_ranges[i].range_max) {
259 return true;
260 }
261 }
262
263 switch (reg) {
264 case RT5645_RESET:
265 case RT5645_SPK_VOL:
266 case RT5645_HP_VOL:
267 case RT5645_LOUT1:
268 case RT5645_IN1_CTRL1:
269 case RT5645_IN1_CTRL2:
270 case RT5645_IN1_CTRL3:
271 case RT5645_IN2_CTRL:
272 case RT5645_INL1_INR1_VOL:
273 case RT5645_SPK_FUNC_LIM:
274 case RT5645_ADJ_HPF_CTRL:
275 case RT5645_DAC1_DIG_VOL:
276 case RT5645_DAC2_DIG_VOL:
277 case RT5645_DAC_CTRL:
278 case RT5645_STO1_ADC_DIG_VOL:
279 case RT5645_MONO_ADC_DIG_VOL:
280 case RT5645_ADC_BST_VOL1:
281 case RT5645_ADC_BST_VOL2:
282 case RT5645_STO1_ADC_MIXER:
283 case RT5645_MONO_ADC_MIXER:
284 case RT5645_AD_DA_MIXER:
285 case RT5645_STO_DAC_MIXER:
286 case RT5645_MONO_DAC_MIXER:
287 case RT5645_DIG_MIXER:
288 case RT5645_DIG_INF1_DATA:
289 case RT5645_PDM_OUT_CTRL:
290 case RT5645_REC_L1_MIXER:
291 case RT5645_REC_L2_MIXER:
292 case RT5645_REC_R1_MIXER:
293 case RT5645_REC_R2_MIXER:
294 case RT5645_HPMIXL_CTRL:
295 case RT5645_HPOMIXL_CTRL:
296 case RT5645_HPMIXR_CTRL:
297 case RT5645_HPOMIXR_CTRL:
298 case RT5645_HPO_MIXER:
299 case RT5645_SPK_L_MIXER:
300 case RT5645_SPK_R_MIXER:
301 case RT5645_SPO_MIXER:
302 case RT5645_SPO_CLSD_RATIO:
303 case RT5645_OUT_L1_MIXER:
304 case RT5645_OUT_R1_MIXER:
305 case RT5645_OUT_L_GAIN1:
306 case RT5645_OUT_L_GAIN2:
307 case RT5645_OUT_R_GAIN1:
308 case RT5645_OUT_R_GAIN2:
309 case RT5645_LOUT_MIXER:
310 case RT5645_HAPTIC_CTRL1:
311 case RT5645_HAPTIC_CTRL2:
312 case RT5645_HAPTIC_CTRL3:
313 case RT5645_HAPTIC_CTRL4:
314 case RT5645_HAPTIC_CTRL5:
315 case RT5645_HAPTIC_CTRL6:
316 case RT5645_HAPTIC_CTRL7:
317 case RT5645_HAPTIC_CTRL8:
318 case RT5645_HAPTIC_CTRL9:
319 case RT5645_HAPTIC_CTRL10:
320 case RT5645_PWR_DIG1:
321 case RT5645_PWR_DIG2:
322 case RT5645_PWR_ANLG1:
323 case RT5645_PWR_ANLG2:
324 case RT5645_PWR_MIXER:
325 case RT5645_PWR_VOL:
326 case RT5645_PRIV_INDEX:
327 case RT5645_PRIV_DATA:
328 case RT5645_I2S1_SDP:
329 case RT5645_I2S2_SDP:
330 case RT5645_ADDA_CLK1:
331 case RT5645_ADDA_CLK2:
332 case RT5645_DMIC_CTRL1:
333 case RT5645_DMIC_CTRL2:
334 case RT5645_TDM_CTRL_1:
335 case RT5645_TDM_CTRL_2:
336 case RT5645_GLB_CLK:
337 case RT5645_PLL_CTRL1:
338 case RT5645_PLL_CTRL2:
339 case RT5645_ASRC_1:
340 case RT5645_ASRC_2:
341 case RT5645_ASRC_3:
342 case RT5645_ASRC_4:
343 case RT5645_DEPOP_M1:
344 case RT5645_DEPOP_M2:
345 case RT5645_DEPOP_M3:
346 case RT5645_MICBIAS:
347 case RT5645_A_JD_CTRL1:
348 case RT5645_VAD_CTRL4:
349 case RT5645_CLSD_OUT_CTRL:
350 case RT5645_ADC_EQ_CTRL1:
351 case RT5645_ADC_EQ_CTRL2:
352 case RT5645_EQ_CTRL1:
353 case RT5645_EQ_CTRL2:
354 case RT5645_ALC_CTRL_1:
355 case RT5645_ALC_CTRL_2:
356 case RT5645_ALC_CTRL_3:
357 case RT5645_ALC_CTRL_4:
358 case RT5645_ALC_CTRL_5:
359 case RT5645_JD_CTRL:
360 case RT5645_IRQ_CTRL1:
361 case RT5645_IRQ_CTRL2:
362 case RT5645_IRQ_CTRL3:
363 case RT5645_INT_IRQ_ST:
364 case RT5645_GPIO_CTRL1:
365 case RT5645_GPIO_CTRL2:
366 case RT5645_GPIO_CTRL3:
367 case RT5645_BASS_BACK:
368 case RT5645_MP3_PLUS1:
369 case RT5645_MP3_PLUS2:
370 case RT5645_ADJ_HPF1:
371 case RT5645_ADJ_HPF2:
372 case RT5645_HP_CALIB_AMP_DET:
373 case RT5645_SV_ZCD1:
374 case RT5645_SV_ZCD2:
375 case RT5645_IL_CMD:
376 case RT5645_IL_CMD2:
377 case RT5645_IL_CMD3:
378 case RT5645_DRC1_HL_CTRL1:
379 case RT5645_DRC2_HL_CTRL1:
380 case RT5645_ADC_MONO_HP_CTRL1:
381 case RT5645_ADC_MONO_HP_CTRL2:
382 case RT5645_DRC2_CTRL1:
383 case RT5645_DRC2_CTRL2:
384 case RT5645_DRC2_CTRL3:
385 case RT5645_DRC2_CTRL4:
386 case RT5645_DRC2_CTRL5:
387 case RT5645_JD_CTRL3:
388 case RT5645_JD_CTRL4:
389 case RT5645_GEN_CTRL1:
390 case RT5645_GEN_CTRL2:
391 case RT5645_GEN_CTRL3:
392 case RT5645_VENDOR_ID:
393 case RT5645_VENDOR_ID1:
394 case RT5645_VENDOR_ID2:
395 return true;
396 default:
397 return false;
398 }
399}
400
401static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
402static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
403static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
404static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
405static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
406
407/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
408static unsigned int bst_tlv[] = {
409 TLV_DB_RANGE_HEAD(7),
410 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
411 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
412 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
413 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
414 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
415 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
416 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
417};
418
419static const char * const rt5645_tdm_data_swap_select[] = {
420 "L/R", "R/L", "L/L", "R/R"
421};
422
423static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
424 RT5645_TDM_CTRL_1, 6, rt5645_tdm_data_swap_select);
425
426static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
427 RT5645_TDM_CTRL_1, 4, rt5645_tdm_data_swap_select);
428
429static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
430 RT5645_TDM_CTRL_1, 2, rt5645_tdm_data_swap_select);
431
432static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot6_7_enum,
433 RT5645_TDM_CTRL_1, 0, rt5645_tdm_data_swap_select);
434
435static const char * const rt5645_tdm_adc_data_select[] = {
436 "1/2/R", "2/1/R", "R/1/2", "R/2/1"
437};
438
439static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_sel_enum,
440 RT5645_TDM_CTRL_1, 8,
441 rt5645_tdm_adc_data_select);
442
443static const struct snd_kcontrol_new rt5645_snd_controls[] = {
444 /* Speaker Output Volume */
445 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
446 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
447 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
448 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
449
450 /* Headphone Output Volume */
451 SOC_DOUBLE("HP Channel Switch", RT5645_HP_VOL,
452 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
453 SOC_DOUBLE_TLV("HP Playback Volume", RT5645_HP_VOL,
454 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
455
456 /* OUTPUT Control */
457 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
458 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
459 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
460 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
461 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
462 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
463
464 /* DAC Digital Volume */
465 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
466 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
467 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
468 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 175, 0, dac_vol_tlv),
469 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
470 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 175, 0, dac_vol_tlv),
471
472 /* IN1/IN2 Control */
473 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
474 RT5645_BST_SFT1, 8, 0, bst_tlv),
475 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
476 RT5645_BST_SFT2, 8, 0, bst_tlv),
477
478 /* INL/INR Volume Control */
479 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
480 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
481
482 /* ADC Digital Volume Control */
483 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
484 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
485 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
486 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 127, 0, adc_vol_tlv),
487 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
488 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
489 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
490 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 127, 0, adc_vol_tlv),
491
492 /* ADC Boost Volume Control */
493 SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5645_ADC_BST_VOL1,
494 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
495 adc_bst_tlv),
496 SOC_DOUBLE_TLV("STO2 ADC Boost Gain", RT5645_ADC_BST_VOL1,
497 RT5645_STO2_ADC_L_BST_SFT, RT5645_STO2_ADC_R_BST_SFT, 3, 0,
498 adc_bst_tlv),
499
500 /* I2S2 function select */
501 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
502 1, 1),
503
504 /* TDM */
505 SOC_ENUM("TDM Adc Slot0 1 Data", rt5645_tdm_adc_slot0_1_enum),
506 SOC_ENUM("TDM Adc Slot2 3 Data", rt5645_tdm_adc_slot2_3_enum),
507 SOC_ENUM("TDM Adc Slot4 5 Data", rt5645_tdm_adc_slot4_5_enum),
508 SOC_ENUM("TDM Adc Slot6 7 Data", rt5645_tdm_adc_slot6_7_enum),
509 SOC_ENUM("TDM IF1 ADC DATA Sel", rt5645_tdm_adc_sel_enum),
510 SOC_SINGLE("TDM IF1_DAC1_L Sel", RT5645_TDM_CTRL_3, 12, 7, 0),
511 SOC_SINGLE("TDM IF1_DAC1_R Sel", RT5645_TDM_CTRL_3, 8, 7, 0),
512 SOC_SINGLE("TDM IF1_DAC2_L Sel", RT5645_TDM_CTRL_3, 4, 7, 0),
513 SOC_SINGLE("TDM IF1_DAC2_R Sel", RT5645_TDM_CTRL_3, 0, 7, 0),
514};
515
516/**
517 * set_dmic_clk - Set parameter of dmic.
518 *
519 * @w: DAPM widget.
520 * @kcontrol: The kcontrol of this widget.
521 * @event: Event id.
522 *
523 */
524static int set_dmic_clk(struct snd_soc_dapm_widget *w,
525 struct snd_kcontrol *kcontrol, int event)
526{
527 struct snd_soc_codec *codec = w->codec;
528 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
529 int idx = -EINVAL;
530
531 idx = rl6231_calc_dmic_clk(rt5645->sysclk);
532
533 if (idx < 0)
534 dev_err(codec->dev, "Failed to set DMIC clock\n");
535 else
536 snd_soc_update_bits(codec, RT5645_DMIC_CTRL1,
537 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
538 return idx;
539}
540
541static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
542 struct snd_soc_dapm_widget *sink)
543{
544 unsigned int val;
545
546 val = snd_soc_read(source->codec, RT5645_GLB_CLK);
547 val &= RT5645_SCLK_SRC_MASK;
548 if (val == RT5645_SCLK_SRC_PLL1)
549 return 1;
550 else
551 return 0;
552}
553
554/* Digital Mixer */
555static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
556 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
557 RT5645_M_ADC_L1_SFT, 1, 1),
558 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
559 RT5645_M_ADC_L2_SFT, 1, 1),
560};
561
562static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
563 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
564 RT5645_M_ADC_R1_SFT, 1, 1),
565 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
566 RT5645_M_ADC_R2_SFT, 1, 1),
567};
568
569static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
570 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
571 RT5645_M_MONO_ADC_L1_SFT, 1, 1),
572 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
573 RT5645_M_MONO_ADC_L2_SFT, 1, 1),
574};
575
576static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
577 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
578 RT5645_M_MONO_ADC_R1_SFT, 1, 1),
579 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
580 RT5645_M_MONO_ADC_R2_SFT, 1, 1),
581};
582
583static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
584 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
585 RT5645_M_ADCMIX_L_SFT, 1, 1),
586 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
587 RT5645_M_DAC1_L_SFT, 1, 1),
588};
589
590static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
591 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
592 RT5645_M_ADCMIX_R_SFT, 1, 1),
593 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
594 RT5645_M_DAC1_R_SFT, 1, 1),
595};
596
597static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
598 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
599 RT5645_M_DAC_L1_SFT, 1, 1),
600 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
601 RT5645_M_DAC_L2_SFT, 1, 1),
602 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
603 RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
604};
605
606static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
607 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
608 RT5645_M_DAC_R1_SFT, 1, 1),
609 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
610 RT5645_M_DAC_R2_SFT, 1, 1),
611 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
612 RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
613};
614
615static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
616 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
617 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
618 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
619 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
620 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
621 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
622};
623
624static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
625 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
626 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
627 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
628 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
629 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
630 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
631};
632
633static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
634 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
635 RT5645_M_STO_L_DAC_L_SFT, 1, 1),
636 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
637 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
638 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
639 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
640};
641
642static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
643 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
644 RT5645_M_STO_R_DAC_R_SFT, 1, 1),
645 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
646 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
647 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
648 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
649};
650
651/* Analog Input Mixer */
652static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
653 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
654 RT5645_M_HP_L_RM_L_SFT, 1, 1),
655 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
656 RT5645_M_IN_L_RM_L_SFT, 1, 1),
657 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
658 RT5645_M_BST2_RM_L_SFT, 1, 1),
659 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
660 RT5645_M_BST1_RM_L_SFT, 1, 1),
661 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
662 RT5645_M_OM_L_RM_L_SFT, 1, 1),
663};
664
665static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
666 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
667 RT5645_M_HP_R_RM_R_SFT, 1, 1),
668 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
669 RT5645_M_IN_R_RM_R_SFT, 1, 1),
670 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
671 RT5645_M_BST2_RM_R_SFT, 1, 1),
672 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
673 RT5645_M_BST1_RM_R_SFT, 1, 1),
674 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
675 RT5645_M_OM_R_RM_R_SFT, 1, 1),
676};
677
678static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
679 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
680 RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
681 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
682 RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
683 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
684 RT5645_M_IN_L_SM_L_SFT, 1, 1),
685 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
686 RT5645_M_BST1_L_SM_L_SFT, 1, 1),
687};
688
689static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
690 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
691 RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
692 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
693 RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
694 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
695 RT5645_M_IN_R_SM_R_SFT, 1, 1),
696 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
697 RT5645_M_BST2_R_SM_R_SFT, 1, 1),
698};
699
700static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
701 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
702 RT5645_M_BST1_OM_L_SFT, 1, 1),
703 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
704 RT5645_M_IN_L_OM_L_SFT, 1, 1),
705 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
706 RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
707 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
708 RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
709};
710
711static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
712 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
713 RT5645_M_BST2_OM_R_SFT, 1, 1),
714 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
715 RT5645_M_IN_R_OM_R_SFT, 1, 1),
716 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
717 RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
718 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
719 RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
720};
721
722static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
723 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
724 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
725 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
726 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
727 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
728 RT5645_M_SV_R_SPM_L_SFT, 1, 1),
729 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
730 RT5645_M_SV_L_SPM_L_SFT, 1, 1),
731};
732
733static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
734 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
735 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
736 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
737 RT5645_M_SV_R_SPM_R_SFT, 1, 1),
738};
739
740static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
741 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
742 RT5645_M_DAC1_HM_SFT, 1, 1),
743 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
744 RT5645_M_HPVOL_HM_SFT, 1, 1),
745};
746
747static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
748 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
749 RT5645_M_DAC1_HV_SFT, 1, 1),
750 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
751 RT5645_M_DAC2_HV_SFT, 1, 1),
752 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
753 RT5645_M_IN_HV_SFT, 1, 1),
754 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
755 RT5645_M_BST1_HV_SFT, 1, 1),
756};
757
758static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
759 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
760 RT5645_M_DAC1_HV_SFT, 1, 1),
761 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
762 RT5645_M_DAC2_HV_SFT, 1, 1),
763 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
764 RT5645_M_IN_HV_SFT, 1, 1),
765 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
766 RT5645_M_BST2_HV_SFT, 1, 1),
767};
768
769static const struct snd_kcontrol_new rt5645_lout_mix[] = {
770 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
771 RT5645_M_DAC_L1_LM_SFT, 1, 1),
772 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
773 RT5645_M_DAC_R1_LM_SFT, 1, 1),
774 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
775 RT5645_M_OV_L_LM_SFT, 1, 1),
776 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
777 RT5645_M_OV_R_LM_SFT, 1, 1),
778};
779
780/*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
781static const char * const rt5645_dac1_src[] = {
782 "IF1 DAC", "IF2 DAC", "IF3 DAC"
783};
784
785static SOC_ENUM_SINGLE_DECL(
786 rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
787 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
788
789static const struct snd_kcontrol_new rt5645_dac1l_mux =
790 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
791
792static SOC_ENUM_SINGLE_DECL(
793 rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
794 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
795
796static const struct snd_kcontrol_new rt5645_dac1r_mux =
797 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
798
799/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
800static const char * const rt5645_dac12_src[] = {
801 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
802};
803
804static SOC_ENUM_SINGLE_DECL(
805 rt5645_dac2l_enum, RT5645_DAC_CTRL,
806 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
807
808static const struct snd_kcontrol_new rt5645_dac_l2_mux =
809 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
810
811static const char * const rt5645_dacr2_src[] = {
812 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
813};
814
815static SOC_ENUM_SINGLE_DECL(
816 rt5645_dac2r_enum, RT5645_DAC_CTRL,
817 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
818
819static const struct snd_kcontrol_new rt5645_dac_r2_mux =
820 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
821
822
823/* INL/R source */
824static const char * const rt5645_inl_src[] = {
825 "IN2P", "MonoP"
826};
827
828static SOC_ENUM_SINGLE_DECL(
829 rt5645_inl_enum, RT5645_INL1_INR1_VOL,
830 RT5645_INL_SEL_SFT, rt5645_inl_src);
831
832static const struct snd_kcontrol_new rt5645_inl_mux =
833 SOC_DAPM_ENUM("INL source", rt5645_inl_enum);
834
835static const char * const rt5645_inr_src[] = {
836 "IN2N", "MonoN"
837};
838
839static SOC_ENUM_SINGLE_DECL(
840 rt5645_inr_enum, RT5645_INL1_INR1_VOL,
841 RT5645_INR_SEL_SFT, rt5645_inr_src);
842
843static const struct snd_kcontrol_new rt5645_inr_mux =
844 SOC_DAPM_ENUM("INR source", rt5645_inr_enum);
845
846/* Stereo1 ADC source */
847/* MX-27 [12] */
848static const char * const rt5645_stereo_adc1_src[] = {
849 "DAC MIX", "ADC"
850};
851
852static SOC_ENUM_SINGLE_DECL(
853 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
854 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
855
856static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
857 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
858
859/* MX-27 [11] */
860static const char * const rt5645_stereo_adc2_src[] = {
861 "DAC MIX", "DMIC"
862};
863
864static SOC_ENUM_SINGLE_DECL(
865 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
866 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
867
868static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
869 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
870
871/* MX-27 [8] */
872static const char * const rt5645_stereo_dmic_src[] = {
873 "DMIC1", "DMIC2"
874};
875
876static SOC_ENUM_SINGLE_DECL(
877 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
878 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
879
880static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
881 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
882
883/* Mono ADC source */
884/* MX-28 [12] */
885static const char * const rt5645_mono_adc_l1_src[] = {
886 "Mono DAC MIXL", "ADC"
887};
888
889static SOC_ENUM_SINGLE_DECL(
890 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
891 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
892
893static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
894 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
895/* MX-28 [11] */
896static const char * const rt5645_mono_adc_l2_src[] = {
897 "Mono DAC MIXL", "DMIC"
898};
899
900static SOC_ENUM_SINGLE_DECL(
901 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
902 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
903
904static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
905 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
906
907/* MX-28 [8] */
908static const char * const rt5645_mono_dmic_src[] = {
909 "DMIC1", "DMIC2"
910};
911
912static SOC_ENUM_SINGLE_DECL(
913 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
914 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
915
916static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
917 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
918/* MX-28 [1:0] */
919static SOC_ENUM_SINGLE_DECL(
920 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
921 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
922
923static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
924 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
925/* MX-28 [4] */
926static const char * const rt5645_mono_adc_r1_src[] = {
927 "Mono DAC MIXR", "ADC"
928};
929
930static SOC_ENUM_SINGLE_DECL(
931 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
932 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
933
934static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
935 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
936/* MX-28 [3] */
937static const char * const rt5645_mono_adc_r2_src[] = {
938 "Mono DAC MIXR", "DMIC"
939};
940
941static SOC_ENUM_SINGLE_DECL(
942 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
943 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
944
945static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
946 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
947
948/* MX-77 [9:8] */
949static const char * const rt5645_if1_adc_in_src[] = {
950 "IF_ADC1", "IF_ADC2", "VAD_ADC"
951};
952
953static SOC_ENUM_SINGLE_DECL(
954 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
955 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
956
957static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
958 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
959
960/* MX-2F [13:12] */
961static const char * const rt5645_if2_adc_in_src[] = {
962 "IF_ADC1", "IF_ADC2", "VAD_ADC"
963};
964
965static SOC_ENUM_SINGLE_DECL(
966 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
967 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
968
969static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
970 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
971
972/* MX-2F [1:0] */
973static const char * const rt5645_if3_adc_in_src[] = {
974 "IF_ADC1", "IF_ADC2", "VAD_ADC"
975};
976
977static SOC_ENUM_SINGLE_DECL(
978 rt5645_if3_adc_in_enum, RT5645_DIG_INF1_DATA,
979 RT5645_IF3_ADC_IN_SFT, rt5645_if3_adc_in_src);
980
981static const struct snd_kcontrol_new rt5645_if3_adc_in_mux =
982 SOC_DAPM_ENUM("IF3 ADC IN source", rt5645_if3_adc_in_enum);
983
984/* MX-31 [15] [13] [11] [9] */
985static const char * const rt5645_pdm_src[] = {
986 "Mono DAC", "Stereo DAC"
987};
988
989static SOC_ENUM_SINGLE_DECL(
990 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
991 RT5645_PDM1_L_SFT, rt5645_pdm_src);
992
993static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
994 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
995
996static SOC_ENUM_SINGLE_DECL(
997 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
998 RT5645_PDM1_R_SFT, rt5645_pdm_src);
999
1000static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1001 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1002
1003/* MX-9D [9:8] */
1004static const char * const rt5645_vad_adc_src[] = {
1005 "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1006};
1007
1008static SOC_ENUM_SINGLE_DECL(
1009 rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1010 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1011
1012static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1013 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1014
1015static const struct snd_kcontrol_new spk_l_vol_control =
1016 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1017 RT5645_L_MUTE_SFT, 1, 1);
1018
1019static const struct snd_kcontrol_new spk_r_vol_control =
1020 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1021 RT5645_R_MUTE_SFT, 1, 1);
1022
1023static const struct snd_kcontrol_new hp_l_vol_control =
1024 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1025 RT5645_L_MUTE_SFT, 1, 1);
1026
1027static const struct snd_kcontrol_new hp_r_vol_control =
1028 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1029 RT5645_R_MUTE_SFT, 1, 1);
1030
1031static const struct snd_kcontrol_new pdm1_l_vol_control =
1032 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1033 RT5645_M_PDM1_L, 1, 1);
1034
1035static const struct snd_kcontrol_new pdm1_r_vol_control =
1036 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1037 RT5645_M_PDM1_R, 1, 1);
1038
1039static void hp_amp_power(struct snd_soc_codec *codec, int on)
1040{
1041 static int hp_amp_power_count;
1042 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1043
1044 if (on) {
1045 if (hp_amp_power_count <= 0) {
1046 /* depop parameters */
1047 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1048 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1049 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1050 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1051 RT5645_HP_DCC_INT1, 0x9f01);
1052 mdelay(150);
1053 /* headphone amp power on */
1054 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1055 RT5645_PWR_FV1 | RT5645_PWR_FV2 , 0);
1056 snd_soc_update_bits(codec, RT5645_PWR_VOL,
1057 RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1058 RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1059 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1060 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1061 RT5645_PWR_HA,
1062 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1063 RT5645_PWR_HA);
1064 mdelay(5);
1065 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1066 RT5645_PWR_FV1 | RT5645_PWR_FV2,
1067 RT5645_PWR_FV1 | RT5645_PWR_FV2);
1068
1069 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1070 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1071 RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1072 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1073 0x14, 0x1aaa);
1074 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1075 0x24, 0x0430);
1076 }
1077 hp_amp_power_count++;
1078 } else {
1079 hp_amp_power_count--;
1080 if (hp_amp_power_count <= 0) {
1081 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1082 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1083 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1084 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1085 /* headphone amp power down */
1086 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000);
1087 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1088 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1089 RT5645_PWR_HA, 0);
1090 }
1091 }
1092}
1093
1094static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1095 struct snd_kcontrol *kcontrol, int event)
1096{
1097 struct snd_soc_codec *codec = w->codec;
1098 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1099
1100 switch (event) {
1101 case SND_SOC_DAPM_POST_PMU:
1102 hp_amp_power(codec, 1);
1103 /* headphone unmute sequence */
1104 snd_soc_update_bits(codec, RT5645_DEPOP_M3, RT5645_CP_FQ1_MASK |
1105 RT5645_CP_FQ2_MASK | RT5645_CP_FQ3_MASK,
1106 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1107 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1108 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
1109 regmap_write(rt5645->regmap,
1110 RT5645_PR_BASE + RT5645_MAMP_INT_REG2, 0xfc00);
1111 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1112 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1113 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1114 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1115 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1116 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1117 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1118 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1119 msleep(40);
1120 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1121 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1122 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1123 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1124 break;
1125
1126 case SND_SOC_DAPM_PRE_PMD:
1127 /* headphone mute sequence */
1128 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1129 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1130 RT5645_CP_FQ3_MASK,
1131 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1132 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1133 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
1134 regmap_write(rt5645->regmap,
1135 RT5645_PR_BASE + RT5645_MAMP_INT_REG2, 0xfc00);
1136 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1137 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1138 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1139 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1140 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1141 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1142 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1143 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1144 msleep(30);
1145 hp_amp_power(codec, 0);
1146 break;
1147
1148 default:
1149 return 0;
1150 }
1151
1152 return 0;
1153}
1154
1155static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1156 struct snd_kcontrol *kcontrol, int event)
1157{
1158 struct snd_soc_codec *codec = w->codec;
1159
1160 switch (event) {
1161 case SND_SOC_DAPM_POST_PMU:
1162 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1163 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1164 RT5645_PWR_CLS_D_L,
1165 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1166 RT5645_PWR_CLS_D_L);
1167 break;
1168
1169 case SND_SOC_DAPM_PRE_PMD:
1170 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1171 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1172 RT5645_PWR_CLS_D_L, 0);
1173 break;
1174
1175 default:
1176 return 0;
1177 }
1178
1179 return 0;
1180}
1181
1182static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1183 struct snd_kcontrol *kcontrol, int event)
1184{
1185 struct snd_soc_codec *codec = w->codec;
1186
1187 switch (event) {
1188 case SND_SOC_DAPM_POST_PMU:
1189 hp_amp_power(codec, 1);
1190 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1191 RT5645_PWR_LM, RT5645_PWR_LM);
1192 snd_soc_update_bits(codec, RT5645_LOUT1,
1193 RT5645_L_MUTE | RT5645_R_MUTE, 0);
1194 break;
1195
1196 case SND_SOC_DAPM_PRE_PMD:
1197 snd_soc_update_bits(codec, RT5645_LOUT1,
1198 RT5645_L_MUTE | RT5645_R_MUTE,
1199 RT5645_L_MUTE | RT5645_R_MUTE);
1200 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1201 RT5645_PWR_LM, 0);
1202 hp_amp_power(codec, 0);
1203 break;
1204
1205 default:
1206 return 0;
1207 }
1208
1209 return 0;
1210}
1211
1212static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1213 struct snd_kcontrol *kcontrol, int event)
1214{
1215 struct snd_soc_codec *codec = w->codec;
1216
1217 switch (event) {
1218 case SND_SOC_DAPM_POST_PMU:
1219 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1220 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1221 break;
1222
1223 case SND_SOC_DAPM_PRE_PMD:
1224 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1225 RT5645_PWR_BST2_P, 0);
1226 break;
1227
1228 default:
1229 return 0;
1230 }
1231
1232 return 0;
1233}
1234
1235static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1236 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1237 RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1238 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1239 RT5645_PWR_PLL_BIT, 0, NULL, 0),
1240
1241 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1242 RT5645_PWR_JD1_BIT, 0, NULL, 0),
1243 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1244 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1245
1246 /* Input Side */
1247 /* micbias */
1248 SND_SOC_DAPM_MICBIAS("micbias1", RT5645_PWR_ANLG2,
1249 RT5645_PWR_MB1_BIT, 0),
1250 SND_SOC_DAPM_MICBIAS("micbias2", RT5645_PWR_ANLG2,
1251 RT5645_PWR_MB2_BIT, 0),
1252 /* Input Lines */
1253 SND_SOC_DAPM_INPUT("DMIC L1"),
1254 SND_SOC_DAPM_INPUT("DMIC R1"),
1255 SND_SOC_DAPM_INPUT("DMIC L2"),
1256 SND_SOC_DAPM_INPUT("DMIC R2"),
1257
1258 SND_SOC_DAPM_INPUT("IN1P"),
1259 SND_SOC_DAPM_INPUT("IN1N"),
1260 SND_SOC_DAPM_INPUT("IN2P"),
1261 SND_SOC_DAPM_INPUT("IN2N"),
1262
1263 SND_SOC_DAPM_INPUT("Haptic Generator"),
1264
1265 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1266 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1267 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1268 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1269 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
1270 RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
1271 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
1272 RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
1273 /* Boost */
1274 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
1275 RT5645_PWR_BST1_BIT, 0, NULL, 0),
1276 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
1277 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
1278 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1279 /* Input Volume */
1280 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
1281 RT5645_PWR_IN_L_BIT, 0, NULL, 0),
1282 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
1283 RT5645_PWR_IN_R_BIT, 0, NULL, 0),
1284 /* REC Mixer */
1285 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
1286 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
1287 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
1288 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
1289 /* ADCs */
1290 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
1291 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
1292
1293 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
1294 RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
1295 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
1296 RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
1297
1298 /* ADC Mux */
1299 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1300 &rt5645_sto1_dmic_mux),
1301 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1302 &rt5645_sto_adc2_mux),
1303 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1304 &rt5645_sto_adc2_mux),
1305 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1306 &rt5645_sto_adc1_mux),
1307 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1308 &rt5645_sto_adc1_mux),
1309 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1310 &rt5645_mono_dmic_l_mux),
1311 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1312 &rt5645_mono_dmic_r_mux),
1313 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1314 &rt5645_mono_adc_l2_mux),
1315 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1316 &rt5645_mono_adc_l1_mux),
1317 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1318 &rt5645_mono_adc_r1_mux),
1319 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1320 &rt5645_mono_adc_r2_mux),
1321 /* ADC Mixer */
1322
1323 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
1324 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
1325 SND_SOC_DAPM_SUPPLY_S("adc stereo2 filter", 1, RT5645_PWR_DIG2,
1326 RT5645_PWR_ADC_S2F_BIT, 0, NULL, 0),
1327 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1328 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
1329 NULL, 0),
1330 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1331 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
1332 NULL, 0),
1333 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
1334 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1335 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1336 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
1337 NULL, 0),
1338 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
1339 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1340 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1341 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
1342 NULL, 0),
1343
1344 /* ADC PGA */
1345 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1346 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1347 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1348 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1349 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1350 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1351 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1352 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1353 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1354 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1355
1356 /* IF1 2 Mux */
1357 SND_SOC_DAPM_MUX("IF1 ADC Mux", SND_SOC_NOPM,
1358 0, 0, &rt5645_if1_adc_in_mux),
1359 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
1360 0, 0, &rt5645_if2_adc_in_mux),
1361
1362 /* Digital Interface */
1363 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
1364 RT5645_PWR_I2S1_BIT, 0, NULL, 0),
1365 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1366 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1367 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1368 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1369 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1370 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1371 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1372 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1373 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1374 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
1375 RT5645_PWR_I2S2_BIT, 0, NULL, 0),
1376 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1377 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1378 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1379 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1380
1381 /* Digital Interface Select */
1382 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
1383 0, 0, &rt5645_vad_adc_mux),
1384
1385 /* Audio Interface */
1386 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1387 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1388 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1389 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1390
1391 /* Output Side */
1392 /* DAC mixer before sound effect */
1393 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1394 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
1395 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1396 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
1397
1398 /* DAC2 channel Mux */
1399 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
1400 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
1401 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
1402 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
1403 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
1404 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
1405
1406 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
1407 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
1408
1409 /* DAC Mixer */
1410 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
1411 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
1412 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
1413 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
1414 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
1415 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
1416 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1417 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
1418 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1419 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
1420 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1421 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
1422 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1423 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
1424 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1425 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
1426 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1427 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
1428
1429 /* DACs */
1430 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
1431 0),
1432 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
1433 0),
1434 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
1435 0),
1436 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
1437 0),
1438 /* OUT Mixer */
1439 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
1440 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
1441 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
1442 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
1443 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
1444 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
1445 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
1446 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
1447 /* Ouput Volume */
1448 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
1449 &spk_l_vol_control),
1450 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
1451 &spk_r_vol_control),
1452 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
1453 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
1454 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
1455 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
1456 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
1457 RT5645_PWR_HM_L_BIT, 0, NULL, 0),
1458 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
1459 RT5645_PWR_HM_R_BIT, 0, NULL, 0),
1460 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1461 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1462 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
1463 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
1464 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
1465
1466 /* HPO/LOUT/Mono Mixer */
1467 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
1468 ARRAY_SIZE(rt5645_spo_l_mix)),
1469 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
1470 ARRAY_SIZE(rt5645_spo_r_mix)),
1471 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
1472 ARRAY_SIZE(rt5645_hpo_mix)),
1473 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
1474 ARRAY_SIZE(rt5645_lout_mix)),
1475
1476 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
1477 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1478 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
1479 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1480 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
1481 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1482
1483 /* PDM */
1484 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
1485 0, NULL, 0),
1486 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
1487 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
1488
1489 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
1490 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
1491
1492 /* Output Lines */
1493 SND_SOC_DAPM_OUTPUT("HPOL"),
1494 SND_SOC_DAPM_OUTPUT("HPOR"),
1495 SND_SOC_DAPM_OUTPUT("LOUTL"),
1496 SND_SOC_DAPM_OUTPUT("LOUTR"),
1497 SND_SOC_DAPM_OUTPUT("PDM1L"),
1498 SND_SOC_DAPM_OUTPUT("PDM1R"),
1499 SND_SOC_DAPM_OUTPUT("SPOL"),
1500 SND_SOC_DAPM_OUTPUT("SPOR"),
1501};
1502
1503static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
1504 { "IN1P", NULL, "LDO2" },
1505 { "IN2P", NULL, "LDO2" },
1506
1507 { "DMIC1", NULL, "DMIC L1" },
1508 { "DMIC1", NULL, "DMIC R1" },
1509 { "DMIC2", NULL, "DMIC L2" },
1510 { "DMIC2", NULL, "DMIC R2" },
1511
1512 { "BST1", NULL, "IN1P" },
1513 { "BST1", NULL, "IN1N" },
1514 { "BST1", NULL, "JD Power" },
1515 { "BST1", NULL, "Mic Det Power" },
1516 { "BST2", NULL, "IN2P" },
1517 { "BST2", NULL, "IN2N" },
1518
1519 { "INL VOL", NULL, "IN2P" },
1520 { "INR VOL", NULL, "IN2N" },
1521
1522 { "RECMIXL", "HPOL Switch", "HPOL" },
1523 { "RECMIXL", "INL Switch", "INL VOL" },
1524 { "RECMIXL", "BST2 Switch", "BST2" },
1525 { "RECMIXL", "BST1 Switch", "BST1" },
1526 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
1527
1528 { "RECMIXR", "HPOR Switch", "HPOR" },
1529 { "RECMIXR", "INR Switch", "INR VOL" },
1530 { "RECMIXR", "BST2 Switch", "BST2" },
1531 { "RECMIXR", "BST1 Switch", "BST1" },
1532 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
1533
1534 { "ADC L", NULL, "RECMIXL" },
1535 { "ADC L", NULL, "ADC L power" },
1536 { "ADC R", NULL, "RECMIXR" },
1537 { "ADC R", NULL, "ADC R power" },
1538
1539 {"DMIC L1", NULL, "DMIC CLK"},
1540 {"DMIC L1", NULL, "DMIC1 Power"},
1541 {"DMIC R1", NULL, "DMIC CLK"},
1542 {"DMIC R1", NULL, "DMIC1 Power"},
1543 {"DMIC L2", NULL, "DMIC CLK"},
1544 {"DMIC L2", NULL, "DMIC2 Power"},
1545 {"DMIC R2", NULL, "DMIC CLK"},
1546 {"DMIC R2", NULL, "DMIC2 Power"},
1547
1548 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
1549 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
1550
1551 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
1552 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
1553
1554 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
1555 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
1556
1557 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1558 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
1559 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
1560 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
1561
1562 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
1563 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
1564 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1565 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
1566
1567 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
1568 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1569 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1570 { "Mono ADC L1 Mux", "ADC", "ADC L" },
1571
1572 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1573 { "Mono ADC R1 Mux", "ADC", "ADC R" },
1574 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
1575 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1576
1577 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
1578 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
1579 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
1580 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
1581
1582 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
1583 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
1584 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1585
1586 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
1587 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
1588 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1589
1590 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
1591 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
1592 { "Mono ADC MIXL", NULL, "adc mono left filter" },
1593 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
1594
1595 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
1596 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
1597 { "Mono ADC MIXR", NULL, "adc mono right filter" },
1598 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
1599
1600 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
1601 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
1602 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
1603
1604 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
1605 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
1606 { "IF_ADC2", NULL, "Mono ADC MIXL" },
1607 { "IF_ADC2", NULL, "Mono ADC MIXR" },
1608 { "VAD_ADC", NULL, "VAD ADC Mux" },
1609
1610 { "IF1 ADC Mux", "IF_ADC1", "IF_ADC1" },
1611 { "IF1 ADC Mux", "IF_ADC2", "IF_ADC2" },
1612 { "IF1 ADC Mux", "VAD_ADC", "VAD_ADC" },
1613
1614 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
1615 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
1616 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
1617
1618 { "IF1 ADC", NULL, "I2S1" },
1619 { "IF1 ADC", NULL, "IF1 ADC Mux" },
1620 { "IF2 ADC", NULL, "I2S2" },
1621 { "IF2 ADC", NULL, "IF2 ADC Mux" },
1622
1623 { "AIF1TX", NULL, "IF1 ADC" },
1624 { "AIF1TX", NULL, "IF2 ADC" },
1625 { "AIF2TX", NULL, "IF2 ADC" },
1626
1627 { "IF1 DAC1", NULL, "AIF1RX" },
1628 { "IF1 DAC2", NULL, "AIF1RX" },
1629 { "IF2 DAC", NULL, "AIF2RX" },
1630
1631 { "IF1 DAC1", NULL, "I2S1" },
1632 { "IF1 DAC2", NULL, "I2S1" },
1633 { "IF2 DAC", NULL, "I2S2" },
1634
1635 { "IF1 DAC2 L", NULL, "IF1 DAC2" },
1636 { "IF1 DAC2 R", NULL, "IF1 DAC2" },
1637 { "IF1 DAC1 L", NULL, "IF1 DAC1" },
1638 { "IF1 DAC1 R", NULL, "IF1 DAC1" },
1639 { "IF2 DAC L", NULL, "IF2 DAC" },
1640 { "IF2 DAC R", NULL, "IF2 DAC" },
1641
1642 { "DAC1 L Mux", "IF1 DAC", "IF1 DAC1 L" },
1643 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
1644
1645 { "DAC1 R Mux", "IF1 DAC", "IF1 DAC1 R" },
1646 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
1647
1648 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
1649 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
1650 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
1651 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
1652 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
1653 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
1654
1655 { "DAC L2 Mux", "IF1 DAC", "IF1 DAC2 L" },
1656 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
1657 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
1658 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
1659 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
1660 { "DAC L2 Volume", NULL, "dac mono left filter" },
1661
1662 { "DAC R2 Mux", "IF1 DAC", "IF1 DAC2 R" },
1663 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
1664 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
1665 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
1666 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
1667 { "DAC R2 Volume", NULL, "dac mono right filter" },
1668
1669 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
1670 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
1671 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1672 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
1673 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
1674 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
1675 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1676 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
1677
1678 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
1679 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1680 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
1681 { "Mono DAC MIXL", NULL, "dac mono left filter" },
1682 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
1683 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1684 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
1685 { "Mono DAC MIXR", NULL, "dac mono right filter" },
1686
1687 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
1688 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1689 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
1690 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
1691 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1692 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
1693
1694 { "DAC L1", NULL, "Stereo DAC MIXL" },
1695 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
1696 { "DAC R1", NULL, "Stereo DAC MIXR" },
1697 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
1698 { "DAC L2", NULL, "Mono DAC MIXL" },
1699 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
1700 { "DAC R2", NULL, "Mono DAC MIXR" },
1701 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
1702
1703 { "SPK MIXL", "BST1 Switch", "BST1" },
1704 { "SPK MIXL", "INL Switch", "INL VOL" },
1705 { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
1706 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
1707 { "SPK MIXR", "BST2 Switch", "BST2" },
1708 { "SPK MIXR", "INR Switch", "INR VOL" },
1709 { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
1710 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
1711
1712 { "OUT MIXL", "BST1 Switch", "BST1" },
1713 { "OUT MIXL", "INL Switch", "INL VOL" },
1714 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
1715 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
1716
1717 { "OUT MIXR", "BST2 Switch", "BST2" },
1718 { "OUT MIXR", "INR Switch", "INR VOL" },
1719 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
1720 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
1721
1722 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
1723 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
1724 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
1725 { "HPOVOL MIXL", "BST1 Switch", "BST1" },
1726 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
1727 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
1728 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
1729 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
1730 { "HPOVOL MIXR", "BST2 Switch", "BST2" },
1731 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
1732
1733 { "DAC 2", NULL, "DAC L2" },
1734 { "DAC 2", NULL, "DAC R2" },
1735 { "DAC 1", NULL, "DAC L1" },
1736 { "DAC 1", NULL, "DAC R1" },
1737 { "HPOVOL L", "Switch", "HPOVOL MIXL" },
1738 { "HPOVOL R", "Switch", "HPOVOL MIXR" },
1739 { "HPOVOL", NULL, "HPOVOL L" },
1740 { "HPOVOL", NULL, "HPOVOL R" },
1741 { "HPO MIX", "DAC1 Switch", "DAC 1" },
1742 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
1743
1744 { "SPKVOL L", "Switch", "SPK MIXL" },
1745 { "SPKVOL R", "Switch", "SPK MIXR" },
1746
1747 { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
1748 { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
1749 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
1750 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
1751 { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
1752 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
1753
1754 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
1755 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
1756 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
1757 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
1758
1759 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
1760 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
1761 { "PDM1 L Mux", NULL, "PDM1 Power" },
1762 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
1763 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
1764 { "PDM1 R Mux", NULL, "PDM1 Power" },
1765
1766 { "HP amp", NULL, "HPO MIX" },
1767 { "HP amp", NULL, "JD Power" },
1768 { "HP amp", NULL, "Mic Det Power" },
1769 { "HP amp", NULL, "LDO2" },
1770 { "HPOL", NULL, "HP amp" },
1771 { "HPOR", NULL, "HP amp" },
1772
1773 { "LOUT amp", NULL, "LOUT MIX" },
1774 { "LOUTL", NULL, "LOUT amp" },
1775 { "LOUTR", NULL, "LOUT amp" },
1776
1777 { "PDM1 L", "Switch", "PDM1 L Mux" },
1778 { "PDM1 R", "Switch", "PDM1 R Mux" },
1779
1780 { "PDM1L", NULL, "PDM1 L" },
1781 { "PDM1R", NULL, "PDM1 R" },
1782
1783 { "SPK amp", NULL, "SPOL MIX" },
1784 { "SPK amp", NULL, "SPOR MIX" },
1785 { "SPOL", NULL, "SPK amp" },
1786 { "SPOR", NULL, "SPK amp" },
1787};
1788
1789static int rt5645_hw_params(struct snd_pcm_substream *substream,
1790 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1791{
1792 struct snd_soc_codec *codec = dai->codec;
1793 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1794 unsigned int val_len = 0, val_clk, mask_clk;
1795 int pre_div, bclk_ms, frame_size;
1796
1797 rt5645->lrck[dai->id] = params_rate(params);
1798 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
1799 if (pre_div < 0) {
1800 dev_err(codec->dev, "Unsupported clock setting\n");
1801 return -EINVAL;
1802 }
1803 frame_size = snd_soc_params_to_frame_size(params);
1804 if (frame_size < 0) {
1805 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
1806 return -EINVAL;
1807 }
1808 bclk_ms = frame_size > 32;
1809 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
1810
1811 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
1812 rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
1813 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1814 bclk_ms, pre_div, dai->id);
1815
1816 switch (params_width(params)) {
1817 case 16:
1818 break;
1819 case 20:
1820 val_len |= RT5645_I2S_DL_20;
1821 break;
1822 case 24:
1823 val_len |= RT5645_I2S_DL_24;
1824 break;
1825 case 8:
1826 val_len |= RT5645_I2S_DL_8;
1827 break;
1828 default:
1829 return -EINVAL;
1830 }
1831
1832 switch (dai->id) {
1833 case RT5645_AIF1:
1834 mask_clk = RT5645_I2S_BCLK_MS1_MASK | RT5645_I2S_PD1_MASK;
1835 val_clk = bclk_ms << RT5645_I2S_BCLK_MS1_SFT |
1836 pre_div << RT5645_I2S_PD1_SFT;
1837 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
1838 RT5645_I2S_DL_MASK, val_len);
1839 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
1840 break;
1841 case RT5645_AIF2:
1842 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
1843 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
1844 pre_div << RT5645_I2S_PD2_SFT;
1845 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
1846 RT5645_I2S_DL_MASK, val_len);
1847 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
1848 break;
1849 default:
1850 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
1851 return -EINVAL;
1852 }
1853
1854 return 0;
1855}
1856
1857static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1858{
1859 struct snd_soc_codec *codec = dai->codec;
1860 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1861 unsigned int reg_val = 0;
1862
1863 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1864 case SND_SOC_DAIFMT_CBM_CFM:
1865 rt5645->master[dai->id] = 1;
1866 break;
1867 case SND_SOC_DAIFMT_CBS_CFS:
1868 reg_val |= RT5645_I2S_MS_S;
1869 rt5645->master[dai->id] = 0;
1870 break;
1871 default:
1872 return -EINVAL;
1873 }
1874
1875 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1876 case SND_SOC_DAIFMT_NB_NF:
1877 break;
1878 case SND_SOC_DAIFMT_IB_NF:
1879 reg_val |= RT5645_I2S_BP_INV;
1880 break;
1881 default:
1882 return -EINVAL;
1883 }
1884
1885 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1886 case SND_SOC_DAIFMT_I2S:
1887 break;
1888 case SND_SOC_DAIFMT_LEFT_J:
1889 reg_val |= RT5645_I2S_DF_LEFT;
1890 break;
1891 case SND_SOC_DAIFMT_DSP_A:
1892 reg_val |= RT5645_I2S_DF_PCM_A;
1893 break;
1894 case SND_SOC_DAIFMT_DSP_B:
1895 reg_val |= RT5645_I2S_DF_PCM_B;
1896 break;
1897 default:
1898 return -EINVAL;
1899 }
1900 switch (dai->id) {
1901 case RT5645_AIF1:
1902 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
1903 RT5645_I2S_MS_MASK | RT5645_I2S_BP_MASK |
1904 RT5645_I2S_DF_MASK, reg_val);
1905 break;
1906 case RT5645_AIF2:
1907 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
1908 RT5645_I2S_MS_MASK | RT5645_I2S_BP_MASK |
1909 RT5645_I2S_DF_MASK, reg_val);
1910 break;
1911 default:
1912 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
1913 return -EINVAL;
1914 }
1915 return 0;
1916}
1917
1918static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
1919 int clk_id, unsigned int freq, int dir)
1920{
1921 struct snd_soc_codec *codec = dai->codec;
1922 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1923 unsigned int reg_val = 0;
1924
1925 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
1926 return 0;
1927
1928 switch (clk_id) {
1929 case RT5645_SCLK_S_MCLK:
1930 reg_val |= RT5645_SCLK_SRC_MCLK;
1931 break;
1932 case RT5645_SCLK_S_PLL1:
1933 reg_val |= RT5645_SCLK_SRC_PLL1;
1934 break;
1935 case RT5645_SCLK_S_RCCLK:
1936 reg_val |= RT5645_SCLK_SRC_RCCLK;
1937 break;
1938 default:
1939 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
1940 return -EINVAL;
1941 }
1942 snd_soc_update_bits(codec, RT5645_GLB_CLK,
1943 RT5645_SCLK_SRC_MASK, reg_val);
1944 rt5645->sysclk = freq;
1945 rt5645->sysclk_src = clk_id;
1946
1947 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
1948
1949 return 0;
1950}
1951
1952static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
1953 unsigned int freq_in, unsigned int freq_out)
1954{
1955 struct snd_soc_codec *codec = dai->codec;
1956 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1957 struct rl6231_pll_code pll_code;
1958 int ret;
1959
1960 if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
1961 freq_out == rt5645->pll_out)
1962 return 0;
1963
1964 if (!freq_in || !freq_out) {
1965 dev_dbg(codec->dev, "PLL disabled\n");
1966
1967 rt5645->pll_in = 0;
1968 rt5645->pll_out = 0;
1969 snd_soc_update_bits(codec, RT5645_GLB_CLK,
1970 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
1971 return 0;
1972 }
1973
1974 switch (source) {
1975 case RT5645_PLL1_S_MCLK:
1976 snd_soc_update_bits(codec, RT5645_GLB_CLK,
1977 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
1978 break;
1979 case RT5645_PLL1_S_BCLK1:
1980 case RT5645_PLL1_S_BCLK2:
1981 switch (dai->id) {
1982 case RT5645_AIF1:
1983 snd_soc_update_bits(codec, RT5645_GLB_CLK,
1984 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
1985 break;
1986 case RT5645_AIF2:
1987 snd_soc_update_bits(codec, RT5645_GLB_CLK,
1988 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
1989 break;
1990 default:
1991 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
1992 return -EINVAL;
1993 }
1994 break;
1995 default:
1996 dev_err(codec->dev, "Unknown PLL source %d\n", source);
1997 return -EINVAL;
1998 }
1999
2000 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2001 if (ret < 0) {
2002 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2003 return ret;
2004 }
2005
2006 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
2007 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2008 pll_code.n_code, pll_code.k_code);
2009
2010 snd_soc_write(codec, RT5645_PLL_CTRL1,
2011 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2012 snd_soc_write(codec, RT5645_PLL_CTRL2,
2013 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT |
2014 pll_code.m_bp << RT5645_PLL_M_BP_SFT);
2015
2016 rt5645->pll_in = freq_in;
2017 rt5645->pll_out = freq_out;
2018 rt5645->pll_src = source;
2019
2020 return 0;
2021}
2022
2023static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2024 unsigned int rx_mask, int slots, int slot_width)
2025{
2026 struct snd_soc_codec *codec = dai->codec;
2027 unsigned int val = 0;
2028
2029 if (rx_mask || tx_mask)
2030 val |= (1 << 14);
2031
2032 switch (slots) {
2033 case 4:
2034 val |= (1 << 12);
2035 break;
2036 case 6:
2037 val |= (2 << 12);
2038 break;
2039 case 8:
2040 val |= (3 << 12);
2041 break;
2042 case 2:
2043 default:
2044 break;
2045 }
2046
2047 switch (slot_width) {
2048 case 20:
2049 val |= (1 << 10);
2050 break;
2051 case 24:
2052 val |= (2 << 10);
2053 break;
2054 case 32:
2055 val |= (3 << 10);
2056 break;
2057 case 16:
2058 default:
2059 break;
2060 }
2061
2062 snd_soc_update_bits(codec, RT5645_TDM_CTRL_1, 0x7c00, val);
2063
2064 return 0;
2065}
2066
2067static int rt5645_set_bias_level(struct snd_soc_codec *codec,
2068 enum snd_soc_bias_level level)
2069{
2070 switch (level) {
2071 case SND_SOC_BIAS_STANDBY:
2072 if (SND_SOC_BIAS_OFF == codec->dapm.bias_level) {
2073 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2074 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2075 RT5645_PWR_BG | RT5645_PWR_VREF2,
2076 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2077 RT5645_PWR_BG | RT5645_PWR_VREF2);
2078 mdelay(10);
2079 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2080 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2081 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2082 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2083 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
2084 }
2085 break;
2086
2087 case SND_SOC_BIAS_OFF:
2088 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100);
2089 snd_soc_write(codec, RT5645_GEN_CTRL1, 0x0128);
2090 snd_soc_write(codec, RT5645_PWR_DIG1, 0x0000);
2091 snd_soc_write(codec, RT5645_PWR_DIG2, 0x0000);
2092 snd_soc_write(codec, RT5645_PWR_VOL, 0x0000);
2093 snd_soc_write(codec, RT5645_PWR_MIXER, 0x0000);
2094 snd_soc_write(codec, RT5645_PWR_ANLG1, 0x0000);
2095 snd_soc_write(codec, RT5645_PWR_ANLG2, 0x0000);
2096 break;
2097
2098 default:
2099 break;
2100 }
2101 codec->dapm.bias_level = level;
2102
2103 return 0;
2104}
2105
2106static int rt5645_probe(struct snd_soc_codec *codec)
2107{
2108 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2109
2110 rt5645->codec = codec;
2111
2112 rt5645_set_bias_level(codec, SND_SOC_BIAS_OFF);
2113
2114 snd_soc_update_bits(codec, RT5645_CHARGE_PUMP, 0x0300, 0x0200);
2115
2116 return 0;
2117}
2118
2119static int rt5645_remove(struct snd_soc_codec *codec)
2120{
2121 rt5645_reset(codec);
2122 return 0;
2123}
2124
2125#ifdef CONFIG_PM
2126static int rt5645_suspend(struct snd_soc_codec *codec)
2127{
2128 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2129
2130 regcache_cache_only(rt5645->regmap, true);
2131 regcache_mark_dirty(rt5645->regmap);
2132
2133 return 0;
2134}
2135
2136static int rt5645_resume(struct snd_soc_codec *codec)
2137{
2138 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2139
2140 regcache_cache_only(rt5645->regmap, false);
2141 regcache_sync(rt5645->regmap);
2142
2143 return 0;
2144}
2145#else
2146#define rt5645_suspend NULL
2147#define rt5645_resume NULL
2148#endif
2149
2150#define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
2151#define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2152 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2153
2154static struct snd_soc_dai_ops rt5645_aif_dai_ops = {
2155 .hw_params = rt5645_hw_params,
2156 .set_fmt = rt5645_set_dai_fmt,
2157 .set_sysclk = rt5645_set_dai_sysclk,
2158 .set_tdm_slot = rt5645_set_tdm_slot,
2159 .set_pll = rt5645_set_dai_pll,
2160};
2161
2162static struct snd_soc_dai_driver rt5645_dai[] = {
2163 {
2164 .name = "rt5645-aif1",
2165 .id = RT5645_AIF1,
2166 .playback = {
2167 .stream_name = "AIF1 Playback",
2168 .channels_min = 1,
2169 .channels_max = 2,
2170 .rates = RT5645_STEREO_RATES,
2171 .formats = RT5645_FORMATS,
2172 },
2173 .capture = {
2174 .stream_name = "AIF1 Capture",
2175 .channels_min = 1,
2176 .channels_max = 2,
2177 .rates = RT5645_STEREO_RATES,
2178 .formats = RT5645_FORMATS,
2179 },
2180 .ops = &rt5645_aif_dai_ops,
2181 },
2182 {
2183 .name = "rt5645-aif2",
2184 .id = RT5645_AIF2,
2185 .playback = {
2186 .stream_name = "AIF2 Playback",
2187 .channels_min = 1,
2188 .channels_max = 2,
2189 .rates = RT5645_STEREO_RATES,
2190 .formats = RT5645_FORMATS,
2191 },
2192 .capture = {
2193 .stream_name = "AIF2 Capture",
2194 .channels_min = 1,
2195 .channels_max = 2,
2196 .rates = RT5645_STEREO_RATES,
2197 .formats = RT5645_FORMATS,
2198 },
2199 .ops = &rt5645_aif_dai_ops,
2200 },
2201};
2202
2203static struct snd_soc_codec_driver soc_codec_dev_rt5645 = {
2204 .probe = rt5645_probe,
2205 .remove = rt5645_remove,
2206 .suspend = rt5645_suspend,
2207 .resume = rt5645_resume,
2208 .set_bias_level = rt5645_set_bias_level,
2209 .idle_bias_off = true,
2210 .controls = rt5645_snd_controls,
2211 .num_controls = ARRAY_SIZE(rt5645_snd_controls),
2212 .dapm_widgets = rt5645_dapm_widgets,
2213 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
2214 .dapm_routes = rt5645_dapm_routes,
2215 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
2216};
2217
2218static const struct regmap_config rt5645_regmap = {
2219 .reg_bits = 8,
2220 .val_bits = 16,
2221
2222 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
2223 RT5645_PR_SPACING),
2224 .volatile_reg = rt5645_volatile_register,
2225 .readable_reg = rt5645_readable_register,
2226
2227 .cache_type = REGCACHE_RBTREE,
2228 .reg_defaults = rt5645_reg,
2229 .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
2230 .ranges = rt5645_ranges,
2231 .num_ranges = ARRAY_SIZE(rt5645_ranges),
2232};
2233
2234static const struct i2c_device_id rt5645_i2c_id[] = {
2235 { "rt5645", 0 },
2236 { }
2237};
2238MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
2239
2240static int rt5645_i2c_probe(struct i2c_client *i2c,
2241 const struct i2c_device_id *id)
2242{
2243 struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev);
2244 struct rt5645_priv *rt5645;
2245 int ret;
2246 unsigned int val;
2247
2248 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
2249 GFP_KERNEL);
2250 if (rt5645 == NULL)
2251 return -ENOMEM;
2252
2253 i2c_set_clientdata(i2c, rt5645);
2254
2255 if (pdata)
2256 rt5645->pdata = *pdata;
2257
2258 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
2259 if (IS_ERR(rt5645->regmap)) {
2260 ret = PTR_ERR(rt5645->regmap);
2261 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2262 ret);
2263 return ret;
2264 }
2265
2266 regmap_read(rt5645->regmap, RT5645_VENDOR_ID2, &val);
2267 if (val != RT5645_DEVICE_ID) {
2268 dev_err(&i2c->dev,
2269 "Device with ID register %x is not rt5645\n", val);
2270 return -ENODEV;
2271 }
2272
2273 regmap_write(rt5645->regmap, RT5645_RESET, 0);
2274
2275 ret = regmap_register_patch(rt5645->regmap, init_list,
2276 ARRAY_SIZE(init_list));
2277 if (ret != 0)
2278 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2279
2280 if (rt5645->pdata.in2_diff)
2281 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
2282 RT5645_IN_DF2, RT5645_IN_DF2);
2283
2284 if (rt5645->pdata.dmic_en) {
2285 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2286 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
2287
2288 switch (rt5645->pdata.dmic1_data_pin) {
2289 case RT5645_DMIC_DATA_IN2N:
2290 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2291 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
2292 break;
2293
2294 case RT5645_DMIC_DATA_GPIO5:
2295 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2296 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
2297 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2298 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
2299 break;
2300
2301 case RT5645_DMIC_DATA_GPIO11:
2302 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2303 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
2304 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2305 RT5645_GP11_PIN_MASK,
2306 RT5645_GP11_PIN_DMIC1_SDA);
2307 break;
2308
2309 default:
2310 break;
2311 }
2312
2313 switch (rt5645->pdata.dmic2_data_pin) {
2314 case RT5645_DMIC_DATA_IN2P:
2315 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2316 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
2317 break;
2318
2319 case RT5645_DMIC_DATA_GPIO6:
2320 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2321 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
2322 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2323 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
2324 break;
2325
2326 case RT5645_DMIC_DATA_GPIO10:
2327 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2328 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
2329 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2330 RT5645_GP10_PIN_MASK,
2331 RT5645_GP10_PIN_DMIC2_SDA);
2332 break;
2333
2334 case RT5645_DMIC_DATA_GPIO12:
2335 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2336 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
2337 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2338 RT5645_GP12_PIN_MASK,
2339 RT5645_GP12_PIN_DMIC2_SDA);
2340 break;
2341
2342 default:
2343 break;
2344 }
2345
2346 }
2347
2348 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645,
2349 rt5645_dai, ARRAY_SIZE(rt5645_dai));
2350 if (ret < 0)
2351 goto err;
2352
2353 return 0;
2354err:
2355 return ret;
2356}
2357
2358static int rt5645_i2c_remove(struct i2c_client *i2c)
2359{
2360 snd_soc_unregister_codec(&i2c->dev);
2361
2362 return 0;
2363}
2364
2365static struct i2c_driver rt5645_i2c_driver = {
2366 .driver = {
2367 .name = "rt5645",
2368 .owner = THIS_MODULE,
2369 },
2370 .probe = rt5645_i2c_probe,
2371 .remove = rt5645_i2c_remove,
2372 .id_table = rt5645_i2c_id,
2373};
2374module_i2c_driver(rt5645_i2c_driver);
2375
2376MODULE_DESCRIPTION("ASoC RT5645 driver");
2377MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2378MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/rt5645.h b/sound/soc/codecs/rt5645.h
new file mode 100644
index 000000000000..355b7e9eefab
--- /dev/null
+++ b/sound/soc/codecs/rt5645.h
@@ -0,0 +1,2181 @@
1/*
2 * rt5645.h -- RT5645 ALSA SoC audio driver
3 *
4 * Copyright 2013 Realtek Microelectronics
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __RT5645_H__
13#define __RT5645_H__
14
15#include <sound/rt5645.h>
16
17/* Info */
18#define RT5645_RESET 0x00
19#define RT5645_VENDOR_ID 0xfd
20#define RT5645_VENDOR_ID1 0xfe
21#define RT5645_VENDOR_ID2 0xff
22/* I/O - Output */
23#define RT5645_SPK_VOL 0x01
24#define RT5645_HP_VOL 0x02
25#define RT5645_LOUT1 0x03
26#define RT5645_LOUT_CTRL 0x05
27/* I/O - Input */
28#define RT5645_IN1_CTRL1 0x0a
29#define RT5645_IN1_CTRL2 0x0b
30#define RT5645_IN1_CTRL3 0x0c
31#define RT5645_IN2_CTRL 0x0d
32#define RT5645_INL1_INR1_VOL 0x0f
33#define RT5645_SPK_FUNC_LIM 0x14
34#define RT5645_ADJ_HPF_CTRL 0x16
35/* I/O - ADC/DAC/DMIC */
36#define RT5645_DAC1_DIG_VOL 0x19
37#define RT5645_DAC2_DIG_VOL 0x1a
38#define RT5645_DAC_CTRL 0x1b
39#define RT5645_STO1_ADC_DIG_VOL 0x1c
40#define RT5645_MONO_ADC_DIG_VOL 0x1d
41#define RT5645_ADC_BST_VOL1 0x1e
42/* Mixer - D-D */
43#define RT5645_ADC_BST_VOL2 0x20
44#define RT5645_STO1_ADC_MIXER 0x27
45#define RT5645_MONO_ADC_MIXER 0x28
46#define RT5645_AD_DA_MIXER 0x29
47#define RT5645_STO_DAC_MIXER 0x2a
48#define RT5645_MONO_DAC_MIXER 0x2b
49#define RT5645_DIG_MIXER 0x2c
50#define RT5645_DIG_INF1_DATA 0x2f
51/* Mixer - PDM */
52#define RT5645_PDM_OUT_CTRL 0x31
53/* Mixer - ADC */
54#define RT5645_REC_L1_MIXER 0x3b
55#define RT5645_REC_L2_MIXER 0x3c
56#define RT5645_REC_R1_MIXER 0x3d
57#define RT5645_REC_R2_MIXER 0x3e
58/* Mixer - DAC */
59#define RT5645_HPMIXL_CTRL 0x3f
60#define RT5645_HPOMIXL_CTRL 0x40
61#define RT5645_HPMIXR_CTRL 0x41
62#define RT5645_HPOMIXR_CTRL 0x42
63#define RT5645_HPO_MIXER 0x45
64#define RT5645_SPK_L_MIXER 0x46
65#define RT5645_SPK_R_MIXER 0x47
66#define RT5645_SPO_MIXER 0x48
67#define RT5645_SPO_CLSD_RATIO 0x4a
68#define RT5645_OUT_L_GAIN1 0x4d
69#define RT5645_OUT_L_GAIN2 0x4e
70#define RT5645_OUT_L1_MIXER 0x4f
71#define RT5645_OUT_R_GAIN1 0x50
72#define RT5645_OUT_R_GAIN2 0x51
73#define RT5645_OUT_R1_MIXER 0x52
74#define RT5645_LOUT_MIXER 0x53
75/* Haptic */
76#define RT5645_HAPTIC_CTRL1 0x56
77#define RT5645_HAPTIC_CTRL2 0x57
78#define RT5645_HAPTIC_CTRL3 0x58
79#define RT5645_HAPTIC_CTRL4 0x59
80#define RT5645_HAPTIC_CTRL5 0x5a
81#define RT5645_HAPTIC_CTRL6 0x5b
82#define RT5645_HAPTIC_CTRL7 0x5c
83#define RT5645_HAPTIC_CTRL8 0x5d
84#define RT5645_HAPTIC_CTRL9 0x5e
85#define RT5645_HAPTIC_CTRL10 0x5f
86/* Power */
87#define RT5645_PWR_DIG1 0x61
88#define RT5645_PWR_DIG2 0x62
89#define RT5645_PWR_ANLG1 0x63
90#define RT5645_PWR_ANLG2 0x64
91#define RT5645_PWR_MIXER 0x65
92#define RT5645_PWR_VOL 0x66
93/* Private Register Control */
94#define RT5645_PRIV_INDEX 0x6a
95#define RT5645_PRIV_DATA 0x6c
96/* Format - ADC/DAC */
97#define RT5645_I2S1_SDP 0x70
98#define RT5645_I2S2_SDP 0x71
99#define RT5645_ADDA_CLK1 0x73
100#define RT5645_ADDA_CLK2 0x74
101#define RT5645_DMIC_CTRL1 0x75
102#define RT5645_DMIC_CTRL2 0x76
103/* Format - TDM Control */
104#define RT5645_TDM_CTRL_1 0x77
105#define RT5645_TDM_CTRL_2 0x78
106#define RT5645_TDM_CTRL_3 0x79
107
108/* Function - Analog */
109#define RT5645_GLB_CLK 0x80
110#define RT5645_PLL_CTRL1 0x81
111#define RT5645_PLL_CTRL2 0x82
112#define RT5645_ASRC_1 0x83
113#define RT5645_ASRC_2 0x84
114#define RT5645_ASRC_3 0x85
115#define RT5645_ASRC_4 0x8a
116#define RT5645_DEPOP_M1 0x8e
117#define RT5645_DEPOP_M2 0x8f
118#define RT5645_DEPOP_M3 0x90
119#define RT5645_CHARGE_PUMP 0x91
120#define RT5645_MICBIAS 0x93
121#define RT5645_A_JD_CTRL1 0x94
122#define RT5645_VAD_CTRL4 0x9d
123#define RT5645_CLSD_OUT_CTRL 0xa0
124/* Function - Digital */
125#define RT5645_ADC_EQ_CTRL1 0xae
126#define RT5645_ADC_EQ_CTRL2 0xaf
127#define RT5645_EQ_CTRL1 0xb0
128#define RT5645_EQ_CTRL2 0xb1
129#define RT5645_ALC_CTRL_1 0xb3
130#define RT5645_ALC_CTRL_2 0xb4
131#define RT5645_ALC_CTRL_3 0xb5
132#define RT5645_ALC_CTRL_4 0xb6
133#define RT5645_ALC_CTRL_5 0xb7
134#define RT5645_JD_CTRL 0xbb
135#define RT5645_IRQ_CTRL1 0xbc
136#define RT5645_IRQ_CTRL2 0xbd
137#define RT5645_IRQ_CTRL3 0xbe
138#define RT5645_INT_IRQ_ST 0xbf
139#define RT5645_GPIO_CTRL1 0xc0
140#define RT5645_GPIO_CTRL2 0xc1
141#define RT5645_GPIO_CTRL3 0xc2
142#define RT5645_BASS_BACK 0xcf
143#define RT5645_MP3_PLUS1 0xd0
144#define RT5645_MP3_PLUS2 0xd1
145#define RT5645_ADJ_HPF1 0xd3
146#define RT5645_ADJ_HPF2 0xd4
147#define RT5645_HP_CALIB_AMP_DET 0xd6
148#define RT5645_SV_ZCD1 0xd9
149#define RT5645_SV_ZCD2 0xda
150#define RT5645_IL_CMD 0xdb
151#define RT5645_IL_CMD2 0xdc
152#define RT5645_IL_CMD3 0xdd
153#define RT5645_DRC1_HL_CTRL1 0xe7
154#define RT5645_DRC2_HL_CTRL1 0xe9
155#define RT5645_MUTI_DRC_CTRL1 0xea
156#define RT5645_ADC_MONO_HP_CTRL1 0xec
157#define RT5645_ADC_MONO_HP_CTRL2 0xed
158#define RT5645_DRC2_CTRL1 0xf0
159#define RT5645_DRC2_CTRL2 0xf1
160#define RT5645_DRC2_CTRL3 0xf2
161#define RT5645_DRC2_CTRL4 0xf3
162#define RT5645_DRC2_CTRL5 0xf4
163#define RT5645_JD_CTRL3 0xf8
164#define RT5645_JD_CTRL4 0xf9
165/* General Control */
166#define RT5645_GEN_CTRL1 0xfa
167#define RT5645_GEN_CTRL2 0xfb
168#define RT5645_GEN_CTRL3 0xfc
169
170
171/* Index of Codec Private Register definition */
172#define RT5645_DIG_VOL 0x00
173#define RT5645_PR_ALC_CTRL_1 0x01
174#define RT5645_PR_ALC_CTRL_2 0x02
175#define RT5645_PR_ALC_CTRL_3 0x03
176#define RT5645_PR_ALC_CTRL_4 0x04
177#define RT5645_PR_ALC_CTRL_5 0x05
178#define RT5645_PR_ALC_CTRL_6 0x06
179#define RT5645_BIAS_CUR1 0x12
180#define RT5645_BIAS_CUR3 0x14
181#define RT5645_CLSD_INT_REG1 0x1c
182#define RT5645_MAMP_INT_REG2 0x37
183#define RT5645_CHOP_DAC_ADC 0x3d
184#define RT5645_MIXER_INT_REG 0x3f
185#define RT5645_3D_SPK 0x63
186#define RT5645_WND_1 0x6c
187#define RT5645_WND_2 0x6d
188#define RT5645_WND_3 0x6e
189#define RT5645_WND_4 0x6f
190#define RT5645_WND_5 0x70
191#define RT5645_WND_8 0x73
192#define RT5645_DIP_SPK_INF 0x75
193#define RT5645_HP_DCC_INT1 0x77
194#define RT5645_EQ_BW_LOP 0xa0
195#define RT5645_EQ_GN_LOP 0xa1
196#define RT5645_EQ_FC_BP1 0xa2
197#define RT5645_EQ_BW_BP1 0xa3
198#define RT5645_EQ_GN_BP1 0xa4
199#define RT5645_EQ_FC_BP2 0xa5
200#define RT5645_EQ_BW_BP2 0xa6
201#define RT5645_EQ_GN_BP2 0xa7
202#define RT5645_EQ_FC_BP3 0xa8
203#define RT5645_EQ_BW_BP3 0xa9
204#define RT5645_EQ_GN_BP3 0xaa
205#define RT5645_EQ_FC_BP4 0xab
206#define RT5645_EQ_BW_BP4 0xac
207#define RT5645_EQ_GN_BP4 0xad
208#define RT5645_EQ_FC_HIP1 0xae
209#define RT5645_EQ_GN_HIP1 0xaf
210#define RT5645_EQ_FC_HIP2 0xb0
211#define RT5645_EQ_BW_HIP2 0xb1
212#define RT5645_EQ_GN_HIP2 0xb2
213#define RT5645_EQ_PRE_VOL 0xb3
214#define RT5645_EQ_PST_VOL 0xb4
215
216
217/* global definition */
218#define RT5645_L_MUTE (0x1 << 15)
219#define RT5645_L_MUTE_SFT 15
220#define RT5645_VOL_L_MUTE (0x1 << 14)
221#define RT5645_VOL_L_SFT 14
222#define RT5645_R_MUTE (0x1 << 7)
223#define RT5645_R_MUTE_SFT 7
224#define RT5645_VOL_R_MUTE (0x1 << 6)
225#define RT5645_VOL_R_SFT 6
226#define RT5645_L_VOL_MASK (0x3f << 8)
227#define RT5645_L_VOL_SFT 8
228#define RT5645_R_VOL_MASK (0x3f)
229#define RT5645_R_VOL_SFT 0
230
231/* IN1 Control 1 (0x0a) */
232#define RT5645_CBJ_BST1_MASK (0xf << 12)
233#define RT5645_CBJ_BST1_SFT (12)
234#define RT5645_CBJ_JD_HP_EN (0x1 << 9)
235#define RT5645_CBJ_JD_MIC_EN (0x1 << 8)
236#define RT5645_CBJ_JD_MIC_SW_EN (0x1 << 7)
237#define RT5645_CBJ_MIC_SEL_R (0x1 << 6)
238#define RT5645_CBJ_MIC_SEL_L (0x1 << 5)
239#define RT5645_CBJ_MIC_SW (0x1 << 4)
240#define RT5645_CBJ_BST1_EN (0x1 << 2)
241
242/* IN1 Control 2 (0x0b) */
243#define RT5645_CBJ_MN_JD (0x1 << 12)
244#define RT5645_CAPLESS_EN (0x1 << 11)
245#define RT5645_CBJ_DET_MODE (0x1 << 7)
246
247/* IN1 Control 3 (0x0c) */
248#define RT5645_CBJ_TIE_G_L (0x1 << 15)
249#define RT5645_CBJ_TIE_G_R (0x1 << 14)
250
251/* IN2 Control (0x0d) */
252#define RT5645_BST_MASK1 (0xf<<12)
253#define RT5645_BST_SFT1 12
254#define RT5645_BST_MASK2 (0xf<<8)
255#define RT5645_BST_SFT2 8
256#define RT5645_IN_DF2 (0x1 << 6)
257#define RT5645_IN_SFT2 6
258
259/* INL and INR Volume Control (0x0f) */
260#define RT5645_INL_SEL_MASK (0x1 << 15)
261#define RT5645_INL_SEL_SFT 15
262#define RT5645_INL_SEL_IN4P (0x0 << 15)
263#define RT5645_INL_SEL_MONOP (0x1 << 15)
264#define RT5645_INL_VOL_MASK (0x1f << 8)
265#define RT5645_INL_VOL_SFT 8
266#define RT5645_INR_SEL_MASK (0x1 << 7)
267#define RT5645_INR_SEL_SFT 7
268#define RT5645_INR_SEL_IN4N (0x0 << 7)
269#define RT5645_INR_SEL_MONON (0x1 << 7)
270#define RT5645_INR_VOL_MASK (0x1f)
271#define RT5645_INR_VOL_SFT 0
272
273/* DAC1 Digital Volume (0x19) */
274#define RT5645_DAC_L1_VOL_MASK (0xff << 8)
275#define RT5645_DAC_L1_VOL_SFT 8
276#define RT5645_DAC_R1_VOL_MASK (0xff)
277#define RT5645_DAC_R1_VOL_SFT 0
278
279/* DAC2 Digital Volume (0x1a) */
280#define RT5645_DAC_L2_VOL_MASK (0xff << 8)
281#define RT5645_DAC_L2_VOL_SFT 8
282#define RT5645_DAC_R2_VOL_MASK (0xff)
283#define RT5645_DAC_R2_VOL_SFT 0
284
285/* DAC2 Control (0x1b) */
286#define RT5645_M_DAC_L2_VOL (0x1 << 13)
287#define RT5645_M_DAC_L2_VOL_SFT 13
288#define RT5645_M_DAC_R2_VOL (0x1 << 12)
289#define RT5645_M_DAC_R2_VOL_SFT 12
290#define RT5645_DAC2_L_SEL_MASK (0x7 << 4)
291#define RT5645_DAC2_L_SEL_SFT 4
292#define RT5645_DAC2_R_SEL_MASK (0x7 << 0)
293#define RT5645_DAC2_R_SEL_SFT 0
294
295/* ADC Digital Volume Control (0x1c) */
296#define RT5645_ADC_L_VOL_MASK (0x7f << 8)
297#define RT5645_ADC_L_VOL_SFT 8
298#define RT5645_ADC_R_VOL_MASK (0x7f)
299#define RT5645_ADC_R_VOL_SFT 0
300
301/* Mono ADC Digital Volume Control (0x1d) */
302#define RT5645_MONO_ADC_L_VOL_MASK (0x7f << 8)
303#define RT5645_MONO_ADC_L_VOL_SFT 8
304#define RT5645_MONO_ADC_R_VOL_MASK (0x7f)
305#define RT5645_MONO_ADC_R_VOL_SFT 0
306
307/* ADC Boost Volume Control (0x1e) */
308#define RT5645_STO1_ADC_L_BST_MASK (0x3 << 14)
309#define RT5645_STO1_ADC_L_BST_SFT 14
310#define RT5645_STO1_ADC_R_BST_MASK (0x3 << 12)
311#define RT5645_STO1_ADC_R_BST_SFT 12
312#define RT5645_STO1_ADC_COMP_MASK (0x3 << 10)
313#define RT5645_STO1_ADC_COMP_SFT 10
314#define RT5645_STO2_ADC_L_BST_MASK (0x3 << 8)
315#define RT5645_STO2_ADC_L_BST_SFT 8
316#define RT5645_STO2_ADC_R_BST_MASK (0x3 << 6)
317#define RT5645_STO2_ADC_R_BST_SFT 6
318#define RT5645_STO2_ADC_COMP_MASK (0x3 << 4)
319#define RT5645_STO2_ADC_COMP_SFT 4
320
321/* Stereo2 ADC Mixer Control (0x26) */
322#define RT5645_STO2_ADC_SRC_MASK (0x1 << 15)
323#define RT5645_STO2_ADC_SRC_SFT 15
324
325/* Stereo ADC Mixer Control (0x27) */
326#define RT5645_M_ADC_L1 (0x1 << 14)
327#define RT5645_M_ADC_L1_SFT 14
328#define RT5645_M_ADC_L2 (0x1 << 13)
329#define RT5645_M_ADC_L2_SFT 13
330#define RT5645_ADC_1_SRC_MASK (0x1 << 12)
331#define RT5645_ADC_1_SRC_SFT 12
332#define RT5645_ADC_1_SRC_ADC (0x1 << 12)
333#define RT5645_ADC_1_SRC_DACMIX (0x0 << 12)
334#define RT5645_ADC_2_SRC_MASK (0x1 << 11)
335#define RT5645_ADC_2_SRC_SFT 11
336#define RT5645_DMIC_SRC_MASK (0x1 << 8)
337#define RT5645_DMIC_SRC_SFT 8
338#define RT5645_M_ADC_R1 (0x1 << 6)
339#define RT5645_M_ADC_R1_SFT 6
340#define RT5645_M_ADC_R2 (0x1 << 5)
341#define RT5645_M_ADC_R2_SFT 5
342#define RT5645_DMIC3_SRC_MASK (0x1 << 1)
343#define RT5645_DMIC3_SRC_SFT 0
344
345/* Mono ADC Mixer Control (0x28) */
346#define RT5645_M_MONO_ADC_L1 (0x1 << 14)
347#define RT5645_M_MONO_ADC_L1_SFT 14
348#define RT5645_M_MONO_ADC_L2 (0x1 << 13)
349#define RT5645_M_MONO_ADC_L2_SFT 13
350#define RT5645_MONO_ADC_L1_SRC_MASK (0x1 << 12)
351#define RT5645_MONO_ADC_L1_SRC_SFT 12
352#define RT5645_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
353#define RT5645_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
354#define RT5645_MONO_ADC_L2_SRC_MASK (0x1 << 11)
355#define RT5645_MONO_ADC_L2_SRC_SFT 11
356#define RT5645_MONO_DMIC_L_SRC_MASK (0x1 << 8)
357#define RT5645_MONO_DMIC_L_SRC_SFT 8
358#define RT5645_M_MONO_ADC_R1 (0x1 << 6)
359#define RT5645_M_MONO_ADC_R1_SFT 6
360#define RT5645_M_MONO_ADC_R2 (0x1 << 5)
361#define RT5645_M_MONO_ADC_R2_SFT 5
362#define RT5645_MONO_ADC_R1_SRC_MASK (0x1 << 4)
363#define RT5645_MONO_ADC_R1_SRC_SFT 4
364#define RT5645_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
365#define RT5645_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
366#define RT5645_MONO_ADC_R2_SRC_MASK (0x1 << 3)
367#define RT5645_MONO_ADC_R2_SRC_SFT 3
368#define RT5645_MONO_DMIC_R_SRC_MASK (0x3)
369#define RT5645_MONO_DMIC_R_SRC_SFT 0
370
371/* ADC Mixer to DAC Mixer Control (0x29) */
372#define RT5645_M_ADCMIX_L (0x1 << 15)
373#define RT5645_M_ADCMIX_L_SFT 15
374#define RT5645_M_DAC1_L (0x1 << 14)
375#define RT5645_M_DAC1_L_SFT 14
376#define RT5645_DAC1_R_SEL_MASK (0x3 << 10)
377#define RT5645_DAC1_R_SEL_SFT 10
378#define RT5645_DAC1_R_SEL_IF1 (0x0 << 10)
379#define RT5645_DAC1_R_SEL_IF2 (0x1 << 10)
380#define RT5645_DAC1_R_SEL_IF3 (0x2 << 10)
381#define RT5645_DAC1_R_SEL_IF4 (0x3 << 10)
382#define RT5645_DAC1_L_SEL_MASK (0x3 << 8)
383#define RT5645_DAC1_L_SEL_SFT 8
384#define RT5645_DAC1_L_SEL_IF1 (0x0 << 8)
385#define RT5645_DAC1_L_SEL_IF2 (0x1 << 8)
386#define RT5645_DAC1_L_SEL_IF3 (0x2 << 8)
387#define RT5645_DAC1_L_SEL_IF4 (0x3 << 8)
388#define RT5645_M_ADCMIX_R (0x1 << 7)
389#define RT5645_M_ADCMIX_R_SFT 7
390#define RT5645_M_DAC1_R (0x1 << 6)
391#define RT5645_M_DAC1_R_SFT 6
392
393/* Stereo DAC Mixer Control (0x2a) */
394#define RT5645_M_DAC_L1 (0x1 << 14)
395#define RT5645_M_DAC_L1_SFT 14
396#define RT5645_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
397#define RT5645_DAC_L1_STO_L_VOL_SFT 13
398#define RT5645_M_DAC_L2 (0x1 << 12)
399#define RT5645_M_DAC_L2_SFT 12
400#define RT5645_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
401#define RT5645_DAC_L2_STO_L_VOL_SFT 11
402#define RT5645_M_ANC_DAC_L (0x1 << 10)
403#define RT5645_M_ANC_DAC_L_SFT 10
404#define RT5645_M_DAC_R1_STO_L (0x1 << 9)
405#define RT5645_M_DAC_R1_STO_L_SFT 9
406#define RT5645_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
407#define RT5645_DAC_R1_STO_L_VOL_SFT 8
408#define RT5645_M_DAC_R1 (0x1 << 6)
409#define RT5645_M_DAC_R1_SFT 6
410#define RT5645_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
411#define RT5645_DAC_R1_STO_R_VOL_SFT 5
412#define RT5645_M_DAC_R2 (0x1 << 4)
413#define RT5645_M_DAC_R2_SFT 4
414#define RT5645_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
415#define RT5645_DAC_R2_STO_R_VOL_SFT 3
416#define RT5645_M_ANC_DAC_R (0x1 << 2)
417#define RT5645_M_ANC_DAC_R_SFT 2
418#define RT5645_M_DAC_L1_STO_R (0x1 << 1)
419#define RT5645_M_DAC_L1_STO_R_SFT 1
420#define RT5645_DAC_L1_STO_R_VOL_MASK (0x1)
421#define RT5645_DAC_L1_STO_R_VOL_SFT 0
422
423/* Mono DAC Mixer Control (0x2b) */
424#define RT5645_M_DAC_L1_MONO_L (0x1 << 14)
425#define RT5645_M_DAC_L1_MONO_L_SFT 14
426#define RT5645_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
427#define RT5645_DAC_L1_MONO_L_VOL_SFT 13
428#define RT5645_M_DAC_L2_MONO_L (0x1 << 12)
429#define RT5645_M_DAC_L2_MONO_L_SFT 12
430#define RT5645_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
431#define RT5645_DAC_L2_MONO_L_VOL_SFT 11
432#define RT5645_M_DAC_R2_MONO_L (0x1 << 10)
433#define RT5645_M_DAC_R2_MONO_L_SFT 10
434#define RT5645_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
435#define RT5645_DAC_R2_MONO_L_VOL_SFT 9
436#define RT5645_M_DAC_R1_MONO_R (0x1 << 6)
437#define RT5645_M_DAC_R1_MONO_R_SFT 6
438#define RT5645_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
439#define RT5645_DAC_R1_MONO_R_VOL_SFT 5
440#define RT5645_M_DAC_R2_MONO_R (0x1 << 4)
441#define RT5645_M_DAC_R2_MONO_R_SFT 4
442#define RT5645_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
443#define RT5645_DAC_R2_MONO_R_VOL_SFT 3
444#define RT5645_M_DAC_L2_MONO_R (0x1 << 2)
445#define RT5645_M_DAC_L2_MONO_R_SFT 2
446#define RT5645_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
447#define RT5645_DAC_L2_MONO_R_VOL_SFT 1
448
449/* Digital Mixer Control (0x2c) */
450#define RT5645_M_STO_L_DAC_L (0x1 << 15)
451#define RT5645_M_STO_L_DAC_L_SFT 15
452#define RT5645_STO_L_DAC_L_VOL_MASK (0x1 << 14)
453#define RT5645_STO_L_DAC_L_VOL_SFT 14
454#define RT5645_M_DAC_L2_DAC_L (0x1 << 13)
455#define RT5645_M_DAC_L2_DAC_L_SFT 13
456#define RT5645_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
457#define RT5645_DAC_L2_DAC_L_VOL_SFT 12
458#define RT5645_M_STO_R_DAC_R (0x1 << 11)
459#define RT5645_M_STO_R_DAC_R_SFT 11
460#define RT5645_STO_R_DAC_R_VOL_MASK (0x1 << 10)
461#define RT5645_STO_R_DAC_R_VOL_SFT 10
462#define RT5645_M_DAC_R2_DAC_R (0x1 << 9)
463#define RT5645_M_DAC_R2_DAC_R_SFT 9
464#define RT5645_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
465#define RT5645_DAC_R2_DAC_R_VOL_SFT 8
466#define RT5645_M_DAC_R2_DAC_L (0x1 << 7)
467#define RT5645_M_DAC_R2_DAC_L_SFT 7
468#define RT5645_DAC_R2_DAC_L_VOL_MASK (0x1 << 6)
469#define RT5645_DAC_R2_DAC_L_VOL_SFT 6
470#define RT5645_M_DAC_L2_DAC_R (0x1 << 5)
471#define RT5645_M_DAC_L2_DAC_R_SFT 5
472#define RT5645_DAC_L2_DAC_R_VOL_MASK (0x1 << 4)
473#define RT5645_DAC_L2_DAC_R_VOL_SFT 4
474
475/* Digital Interface Data Control (0x2f) */
476#define RT5645_IF1_ADC2_IN_SEL (0x1 << 15)
477#define RT5645_IF1_ADC2_IN_SFT 15
478#define RT5645_IF2_ADC_IN_MASK (0x7 << 12)
479#define RT5645_IF2_ADC_IN_SFT 12
480#define RT5645_IF2_DAC_SEL_MASK (0x3 << 10)
481#define RT5645_IF2_DAC_SEL_SFT 10
482#define RT5645_IF2_ADC_SEL_MASK (0x3 << 8)
483#define RT5645_IF2_ADC_SEL_SFT 8
484#define RT5645_IF3_DAC_SEL_MASK (0x3 << 6)
485#define RT5645_IF3_DAC_SEL_SFT 6
486#define RT5645_IF3_ADC_SEL_MASK (0x3 << 4)
487#define RT5645_IF3_ADC_SEL_SFT 4
488#define RT5645_IF3_ADC_IN_MASK (0x7)
489#define RT5645_IF3_ADC_IN_SFT 0
490
491/* PDM Output Control (0x31) */
492#define RT5645_PDM1_L_MASK (0x1 << 15)
493#define RT5645_PDM1_L_SFT 15
494#define RT5645_M_PDM1_L (0x1 << 14)
495#define RT5645_M_PDM1_L_SFT 14
496#define RT5645_PDM1_R_MASK (0x1 << 13)
497#define RT5645_PDM1_R_SFT 13
498#define RT5645_M_PDM1_R (0x1 << 12)
499#define RT5645_M_PDM1_R_SFT 12
500#define RT5645_PDM2_L_MASK (0x1 << 11)
501#define RT5645_PDM2_L_SFT 11
502#define RT5645_M_PDM2_L (0x1 << 10)
503#define RT5645_M_PDM2_L_SFT 10
504#define RT5645_PDM2_R_MASK (0x1 << 9)
505#define RT5645_PDM2_R_SFT 9
506#define RT5645_M_PDM2_R (0x1 << 8)
507#define RT5645_M_PDM2_R_SFT 8
508#define RT5645_PDM2_BUSY (0x1 << 7)
509#define RT5645_PDM1_BUSY (0x1 << 6)
510#define RT5645_PDM_PATTERN (0x1 << 5)
511#define RT5645_PDM_GAIN (0x1 << 4)
512#define RT5645_PDM_DIV_MASK (0x3)
513
514/* REC Left Mixer Control 1 (0x3b) */
515#define RT5645_G_HP_L_RM_L_MASK (0x7 << 13)
516#define RT5645_G_HP_L_RM_L_SFT 13
517#define RT5645_G_IN_L_RM_L_MASK (0x7 << 10)
518#define RT5645_G_IN_L_RM_L_SFT 10
519#define RT5645_G_BST4_RM_L_MASK (0x7 << 7)
520#define RT5645_G_BST4_RM_L_SFT 7
521#define RT5645_G_BST3_RM_L_MASK (0x7 << 4)
522#define RT5645_G_BST3_RM_L_SFT 4
523#define RT5645_G_BST2_RM_L_MASK (0x7 << 1)
524#define RT5645_G_BST2_RM_L_SFT 1
525
526/* REC Left Mixer Control 2 (0x3c) */
527#define RT5645_G_BST1_RM_L_MASK (0x7 << 13)
528#define RT5645_G_BST1_RM_L_SFT 13
529#define RT5645_G_OM_L_RM_L_MASK (0x7 << 10)
530#define RT5645_G_OM_L_RM_L_SFT 10
531#define RT5645_M_MM_L_RM_L (0x1 << 6)
532#define RT5645_M_MM_L_RM_L_SFT 6
533#define RT5645_M_IN_L_RM_L (0x1 << 5)
534#define RT5645_M_IN_L_RM_L_SFT 5
535#define RT5645_M_HP_L_RM_L (0x1 << 4)
536#define RT5645_M_HP_L_RM_L_SFT 4
537#define RT5645_M_BST3_RM_L (0x1 << 3)
538#define RT5645_M_BST3_RM_L_SFT 3
539#define RT5645_M_BST2_RM_L (0x1 << 2)
540#define RT5645_M_BST2_RM_L_SFT 2
541#define RT5645_M_BST1_RM_L (0x1 << 1)
542#define RT5645_M_BST1_RM_L_SFT 1
543#define RT5645_M_OM_L_RM_L (0x1)
544#define RT5645_M_OM_L_RM_L_SFT 0
545
546/* REC Right Mixer Control 1 (0x3d) */
547#define RT5645_G_HP_R_RM_R_MASK (0x7 << 13)
548#define RT5645_G_HP_R_RM_R_SFT 13
549#define RT5645_G_IN_R_RM_R_MASK (0x7 << 10)
550#define RT5645_G_IN_R_RM_R_SFT 10
551#define RT5645_G_BST4_RM_R_MASK (0x7 << 7)
552#define RT5645_G_BST4_RM_R_SFT 7
553#define RT5645_G_BST3_RM_R_MASK (0x7 << 4)
554#define RT5645_G_BST3_RM_R_SFT 4
555#define RT5645_G_BST2_RM_R_MASK (0x7 << 1)
556#define RT5645_G_BST2_RM_R_SFT 1
557
558/* REC Right Mixer Control 2 (0x3e) */
559#define RT5645_G_BST1_RM_R_MASK (0x7 << 13)
560#define RT5645_G_BST1_RM_R_SFT 13
561#define RT5645_G_OM_R_RM_R_MASK (0x7 << 10)
562#define RT5645_G_OM_R_RM_R_SFT 10
563#define RT5645_M_MM_R_RM_R (0x1 << 6)
564#define RT5645_M_MM_R_RM_R_SFT 6
565#define RT5645_M_IN_R_RM_R (0x1 << 5)
566#define RT5645_M_IN_R_RM_R_SFT 5
567#define RT5645_M_HP_R_RM_R (0x1 << 4)
568#define RT5645_M_HP_R_RM_R_SFT 4
569#define RT5645_M_BST3_RM_R (0x1 << 3)
570#define RT5645_M_BST3_RM_R_SFT 3
571#define RT5645_M_BST2_RM_R (0x1 << 2)
572#define RT5645_M_BST2_RM_R_SFT 2
573#define RT5645_M_BST1_RM_R (0x1 << 1)
574#define RT5645_M_BST1_RM_R_SFT 1
575#define RT5645_M_OM_R_RM_R (0x1)
576#define RT5645_M_OM_R_RM_R_SFT 0
577
578/* HPOMIX Control (0x40) (0x42) */
579#define RT5645_M_BST1_HV (0x1 << 4)
580#define RT5645_M_BST1_HV_SFT 4
581#define RT5645_M_BST2_HV (0x1 << 4)
582#define RT5645_M_BST2_HV_SFT 4
583#define RT5645_M_BST3_HV (0x1 << 3)
584#define RT5645_M_BST3_HV_SFT 3
585#define RT5645_M_IN_HV (0x1 << 2)
586#define RT5645_M_IN_HV_SFT 2
587#define RT5645_M_DAC2_HV (0x1 << 1)
588#define RT5645_M_DAC2_HV_SFT 1
589#define RT5645_M_DAC1_HV (0x1 << 0)
590#define RT5645_M_DAC1_HV_SFT 0
591
592/* HPMIX Control (0x45) */
593#define RT5645_M_DAC1_HM (0x1 << 14)
594#define RT5645_M_DAC1_HM_SFT 14
595#define RT5645_M_HPVOL_HM (0x1 << 13)
596#define RT5645_M_HPVOL_HM_SFT 13
597
598/* SPK Left Mixer Control (0x46) */
599#define RT5645_G_RM_L_SM_L_MASK (0x3 << 14)
600#define RT5645_G_RM_L_SM_L_SFT 14
601#define RT5645_G_IN_L_SM_L_MASK (0x3 << 12)
602#define RT5645_G_IN_L_SM_L_SFT 12
603#define RT5645_G_DAC_L1_SM_L_MASK (0x3 << 10)
604#define RT5645_G_DAC_L1_SM_L_SFT 10
605#define RT5645_G_DAC_L2_SM_L_MASK (0x3 << 8)
606#define RT5645_G_DAC_L2_SM_L_SFT 8
607#define RT5645_G_OM_L_SM_L_MASK (0x3 << 6)
608#define RT5645_G_OM_L_SM_L_SFT 6
609#define RT5645_M_BST1_L_SM_L (0x1 << 5)
610#define RT5645_M_BST1_L_SM_L_SFT 5
611#define RT5645_M_IN_L_SM_L (0x1 << 3)
612#define RT5645_M_IN_L_SM_L_SFT 3
613#define RT5645_M_DAC_L1_SM_L (0x1 << 1)
614#define RT5645_M_DAC_L1_SM_L_SFT 1
615#define RT5645_M_DAC_L2_SM_L (0x1 << 2)
616#define RT5645_M_DAC_L2_SM_L_SFT 2
617#define RT5645_M_BST3_L_SM_L (0x1 << 4)
618#define RT5645_M_BST3_L_SM_L_SFT 4
619
620/* SPK Right Mixer Control (0x47) */
621#define RT5645_G_RM_R_SM_R_MASK (0x3 << 14)
622#define RT5645_G_RM_R_SM_R_SFT 14
623#define RT5645_G_IN_R_SM_R_MASK (0x3 << 12)
624#define RT5645_G_IN_R_SM_R_SFT 12
625#define RT5645_G_DAC_R1_SM_R_MASK (0x3 << 10)
626#define RT5645_G_DAC_R1_SM_R_SFT 10
627#define RT5645_G_DAC_R2_SM_R_MASK (0x3 << 8)
628#define RT5645_G_DAC_R2_SM_R_SFT 8
629#define RT5645_G_OM_R_SM_R_MASK (0x3 << 6)
630#define RT5645_G_OM_R_SM_R_SFT 6
631#define RT5645_M_BST2_R_SM_R (0x1 << 5)
632#define RT5645_M_BST2_R_SM_R_SFT 5
633#define RT5645_M_IN_R_SM_R (0x1 << 3)
634#define RT5645_M_IN_R_SM_R_SFT 3
635#define RT5645_M_DAC_R1_SM_R (0x1 << 1)
636#define RT5645_M_DAC_R1_SM_R_SFT 1
637#define RT5645_M_DAC_R2_SM_R (0x1 << 2)
638#define RT5645_M_DAC_R2_SM_R_SFT 2
639#define RT5645_M_BST3_R_SM_R (0x1 << 4)
640#define RT5645_M_BST3_R_SM_R_SFT 4
641
642/* SPOLMIX Control (0x48) */
643#define RT5645_M_DAC_L1_SPM_L (0x1 << 15)
644#define RT5645_M_DAC_L1_SPM_L_SFT 15
645#define RT5645_M_DAC_R1_SPM_L (0x1 << 14)
646#define RT5645_M_DAC_R1_SPM_L_SFT 14
647#define RT5645_M_SV_L_SPM_L (0x1 << 13)
648#define RT5645_M_SV_L_SPM_L_SFT 13
649#define RT5645_M_SV_R_SPM_L (0x1 << 12)
650#define RT5645_M_SV_R_SPM_L_SFT 12
651#define RT5645_M_BST3_SPM_L (0x1 << 11)
652#define RT5645_M_BST3_SPM_L_SFT 11
653#define RT5645_M_DAC_R1_SPM_R (0x1 << 2)
654#define RT5645_M_DAC_R1_SPM_R_SFT 2
655#define RT5645_M_BST3_SPM_R (0x1 << 1)
656#define RT5645_M_BST3_SPM_R_SFT 1
657#define RT5645_M_SV_R_SPM_R (0x1 << 0)
658#define RT5645_M_SV_R_SPM_R_SFT 0
659
660/* Mono Output Mixer Control (0x4c) */
661#define RT5645_M_OV_L_MM (0x1 << 9)
662#define RT5645_M_OV_L_MM_SFT 9
663#define RT5645_M_DAC_L2_MA (0x1 << 8)
664#define RT5645_M_DAC_L2_MA_SFT 8
665#define RT5645_G_MONOMIX_MASK (0x1 << 10)
666#define RT5645_G_MONOMIX_SFT 10
667#define RT5645_M_BST2_MM (0x1 << 4)
668#define RT5645_M_BST2_MM_SFT 4
669#define RT5645_M_DAC_R1_MM (0x1 << 3)
670#define RT5645_M_DAC_R1_MM_SFT 3
671#define RT5645_M_DAC_R2_MM (0x1 << 2)
672#define RT5645_M_DAC_R2_MM_SFT 2
673#define RT5645_M_DAC_L2_MM (0x1 << 1)
674#define RT5645_M_DAC_L2_MM_SFT 1
675#define RT5645_M_BST3_MM (0x1 << 0)
676#define RT5645_M_BST3_MM_SFT 0
677
678/* Output Left Mixer Control 1 (0x4d) */
679#define RT5645_G_BST3_OM_L_MASK (0x7 << 13)
680#define RT5645_G_BST3_OM_L_SFT 13
681#define RT5645_G_BST2_OM_L_MASK (0x7 << 10)
682#define RT5645_G_BST2_OM_L_SFT 10
683#define RT5645_G_BST1_OM_L_MASK (0x7 << 7)
684#define RT5645_G_BST1_OM_L_SFT 7
685#define RT5645_G_IN_L_OM_L_MASK (0x7 << 4)
686#define RT5645_G_IN_L_OM_L_SFT 4
687#define RT5645_G_RM_L_OM_L_MASK (0x7 << 1)
688#define RT5645_G_RM_L_OM_L_SFT 1
689
690/* Output Left Mixer Control 2 (0x4e) */
691#define RT5645_G_DAC_R2_OM_L_MASK (0x7 << 13)
692#define RT5645_G_DAC_R2_OM_L_SFT 13
693#define RT5645_G_DAC_L2_OM_L_MASK (0x7 << 10)
694#define RT5645_G_DAC_L2_OM_L_SFT 10
695#define RT5645_G_DAC_L1_OM_L_MASK (0x7 << 7)
696#define RT5645_G_DAC_L1_OM_L_SFT 7
697
698/* Output Left Mixer Control 3 (0x4f) */
699#define RT5645_M_BST3_OM_L (0x1 << 4)
700#define RT5645_M_BST3_OM_L_SFT 4
701#define RT5645_M_BST1_OM_L (0x1 << 3)
702#define RT5645_M_BST1_OM_L_SFT 3
703#define RT5645_M_IN_L_OM_L (0x1 << 2)
704#define RT5645_M_IN_L_OM_L_SFT 2
705#define RT5645_M_DAC_L2_OM_L (0x1 << 1)
706#define RT5645_M_DAC_L2_OM_L_SFT 1
707#define RT5645_M_DAC_L1_OM_L (0x1)
708#define RT5645_M_DAC_L1_OM_L_SFT 0
709
710/* Output Right Mixer Control 1 (0x50) */
711#define RT5645_G_BST4_OM_R_MASK (0x7 << 13)
712#define RT5645_G_BST4_OM_R_SFT 13
713#define RT5645_G_BST2_OM_R_MASK (0x7 << 10)
714#define RT5645_G_BST2_OM_R_SFT 10
715#define RT5645_G_BST1_OM_R_MASK (0x7 << 7)
716#define RT5645_G_BST1_OM_R_SFT 7
717#define RT5645_G_IN_R_OM_R_MASK (0x7 << 4)
718#define RT5645_G_IN_R_OM_R_SFT 4
719#define RT5645_G_RM_R_OM_R_MASK (0x7 << 1)
720#define RT5645_G_RM_R_OM_R_SFT 1
721
722/* Output Right Mixer Control 2 (0x51) */
723#define RT5645_G_DAC_L2_OM_R_MASK (0x7 << 13)
724#define RT5645_G_DAC_L2_OM_R_SFT 13
725#define RT5645_G_DAC_R2_OM_R_MASK (0x7 << 10)
726#define RT5645_G_DAC_R2_OM_R_SFT 10
727#define RT5645_G_DAC_R1_OM_R_MASK (0x7 << 7)
728#define RT5645_G_DAC_R1_OM_R_SFT 7
729
730/* Output Right Mixer Control 3 (0x52) */
731#define RT5645_M_BST3_OM_R (0x1 << 4)
732#define RT5645_M_BST3_OM_R_SFT 4
733#define RT5645_M_BST2_OM_R (0x1 << 3)
734#define RT5645_M_BST2_OM_R_SFT 3
735#define RT5645_M_IN_R_OM_R (0x1 << 2)
736#define RT5645_M_IN_R_OM_R_SFT 2
737#define RT5645_M_DAC_R2_OM_R (0x1 << 1)
738#define RT5645_M_DAC_R2_OM_R_SFT 1
739#define RT5645_M_DAC_R1_OM_R (0x1)
740#define RT5645_M_DAC_R1_OM_R_SFT 0
741
742/* LOUT Mixer Control (0x53) */
743#define RT5645_M_DAC_L1_LM (0x1 << 15)
744#define RT5645_M_DAC_L1_LM_SFT 15
745#define RT5645_M_DAC_R1_LM (0x1 << 14)
746#define RT5645_M_DAC_R1_LM_SFT 14
747#define RT5645_M_OV_L_LM (0x1 << 13)
748#define RT5645_M_OV_L_LM_SFT 13
749#define RT5645_M_OV_R_LM (0x1 << 12)
750#define RT5645_M_OV_R_LM_SFT 12
751#define RT5645_G_LOUTMIX_MASK (0x1 << 11)
752#define RT5645_G_LOUTMIX_SFT 11
753
754/* Power Management for Digital 1 (0x61) */
755#define RT5645_PWR_I2S1 (0x1 << 15)
756#define RT5645_PWR_I2S1_BIT 15
757#define RT5645_PWR_I2S2 (0x1 << 14)
758#define RT5645_PWR_I2S2_BIT 14
759#define RT5645_PWR_I2S3 (0x1 << 13)
760#define RT5645_PWR_I2S3_BIT 13
761#define RT5645_PWR_DAC_L1 (0x1 << 12)
762#define RT5645_PWR_DAC_L1_BIT 12
763#define RT5645_PWR_DAC_R1 (0x1 << 11)
764#define RT5645_PWR_DAC_R1_BIT 11
765#define RT5645_PWR_CLS_D_R (0x1 << 9)
766#define RT5645_PWR_CLS_D_R_BIT 9
767#define RT5645_PWR_CLS_D_L (0x1 << 8)
768#define RT5645_PWR_CLS_D_L_BIT 8
769#define RT5645_PWR_ADC_R (0x1 << 1)
770#define RT5645_PWR_ADC_R_BIT 1
771#define RT5645_PWR_DAC_L2 (0x1 << 7)
772#define RT5645_PWR_DAC_L2_BIT 7
773#define RT5645_PWR_DAC_R2 (0x1 << 6)
774#define RT5645_PWR_DAC_R2_BIT 6
775#define RT5645_PWR_ADC_L (0x1 << 2)
776#define RT5645_PWR_ADC_L_BIT 2
777#define RT5645_PWR_ADC_R (0x1 << 1)
778#define RT5645_PWR_ADC_R_BIT 1
779#define RT5645_PWR_CLS_D (0x1)
780#define RT5645_PWR_CLS_D_BIT 0
781
782/* Power Management for Digital 2 (0x62) */
783#define RT5645_PWR_ADC_S1F (0x1 << 15)
784#define RT5645_PWR_ADC_S1F_BIT 15
785#define RT5645_PWR_ADC_MF_L (0x1 << 14)
786#define RT5645_PWR_ADC_MF_L_BIT 14
787#define RT5645_PWR_ADC_MF_R (0x1 << 13)
788#define RT5645_PWR_ADC_MF_R_BIT 13
789#define RT5645_PWR_I2S_DSP (0x1 << 12)
790#define RT5645_PWR_I2S_DSP_BIT 12
791#define RT5645_PWR_DAC_S1F (0x1 << 11)
792#define RT5645_PWR_DAC_S1F_BIT 11
793#define RT5645_PWR_DAC_MF_L (0x1 << 10)
794#define RT5645_PWR_DAC_MF_L_BIT 10
795#define RT5645_PWR_DAC_MF_R (0x1 << 9)
796#define RT5645_PWR_DAC_MF_R_BIT 9
797#define RT5645_PWR_ADC_S2F (0x1 << 8)
798#define RT5645_PWR_ADC_S2F_BIT 8
799#define RT5645_PWR_PDM1 (0x1 << 7)
800#define RT5645_PWR_PDM1_BIT 7
801#define RT5645_PWR_PDM2 (0x1 << 6)
802#define RT5645_PWR_PDM2_BIT 6
803#define RT5645_PWR_IPTV (0x1 << 1)
804#define RT5645_PWR_IPTV_BIT 1
805#define RT5645_PWR_PAD (0x1)
806#define RT5645_PWR_PAD_BIT 0
807
808/* Power Management for Analog 1 (0x63) */
809#define RT5645_PWR_VREF1 (0x1 << 15)
810#define RT5645_PWR_VREF1_BIT 15
811#define RT5645_PWR_FV1 (0x1 << 14)
812#define RT5645_PWR_FV1_BIT 14
813#define RT5645_PWR_MB (0x1 << 13)
814#define RT5645_PWR_MB_BIT 13
815#define RT5645_PWR_LM (0x1 << 12)
816#define RT5645_PWR_LM_BIT 12
817#define RT5645_PWR_BG (0x1 << 11)
818#define RT5645_PWR_BG_BIT 11
819#define RT5645_PWR_MA (0x1 << 10)
820#define RT5645_PWR_MA_BIT 10
821#define RT5645_PWR_HP_L (0x1 << 7)
822#define RT5645_PWR_HP_L_BIT 7
823#define RT5645_PWR_HP_R (0x1 << 6)
824#define RT5645_PWR_HP_R_BIT 6
825#define RT5645_PWR_HA (0x1 << 5)
826#define RT5645_PWR_HA_BIT 5
827#define RT5645_PWR_VREF2 (0x1 << 4)
828#define RT5645_PWR_VREF2_BIT 4
829#define RT5645_PWR_FV2 (0x1 << 3)
830#define RT5645_PWR_FV2_BIT 3
831#define RT5645_LDO_SEL_MASK (0x3)
832#define RT5645_LDO_SEL_SFT 0
833
834/* Power Management for Analog 2 (0x64) */
835#define RT5645_PWR_BST1 (0x1 << 15)
836#define RT5645_PWR_BST1_BIT 15
837#define RT5645_PWR_BST2 (0x1 << 14)
838#define RT5645_PWR_BST2_BIT 14
839#define RT5645_PWR_BST3 (0x1 << 13)
840#define RT5645_PWR_BST3_BIT 13
841#define RT5645_PWR_BST4 (0x1 << 12)
842#define RT5645_PWR_BST4_BIT 12
843#define RT5645_PWR_MB1 (0x1 << 11)
844#define RT5645_PWR_MB1_BIT 11
845#define RT5645_PWR_MB2 (0x1 << 10)
846#define RT5645_PWR_MB2_BIT 10
847#define RT5645_PWR_PLL (0x1 << 9)
848#define RT5645_PWR_PLL_BIT 9
849#define RT5645_PWR_BST2_P (0x1 << 5)
850#define RT5645_PWR_BST2_P_BIT 5
851#define RT5645_PWR_BST3_P (0x1 << 4)
852#define RT5645_PWR_BST3_P_BIT 4
853#define RT5645_PWR_BST4_P (0x1 << 3)
854#define RT5645_PWR_BST4_P_BIT 3
855#define RT5645_PWR_JD1 (0x1 << 2)
856#define RT5645_PWR_JD1_BIT 2
857#define RT5645_PWR_JD (0x1 << 1)
858#define RT5645_PWR_JD_BIT 1
859
860/* Power Management for Mixer (0x65) */
861#define RT5645_PWR_OM_L (0x1 << 15)
862#define RT5645_PWR_OM_L_BIT 15
863#define RT5645_PWR_OM_R (0x1 << 14)
864#define RT5645_PWR_OM_R_BIT 14
865#define RT5645_PWR_SM_L (0x1 << 13)
866#define RT5645_PWR_SM_L_BIT 13
867#define RT5645_PWR_SM_R (0x1 << 12)
868#define RT5645_PWR_SM_R_BIT 12
869#define RT5645_PWR_RM_L (0x1 << 11)
870#define RT5645_PWR_RM_L_BIT 11
871#define RT5645_PWR_RM_R (0x1 << 10)
872#define RT5645_PWR_RM_R_BIT 10
873#define RT5645_PWR_MM (0x1 << 8)
874#define RT5645_PWR_MM_BIT 8
875#define RT5645_PWR_HM_L (0x1 << 7)
876#define RT5645_PWR_HM_L_BIT 7
877#define RT5645_PWR_HM_R (0x1 << 6)
878#define RT5645_PWR_HM_R_BIT 6
879#define RT5645_PWR_LDO2 (0x1 << 1)
880#define RT5645_PWR_LDO2_BIT 1
881
882/* Power Management for Volume (0x66) */
883#define RT5645_PWR_SV_L (0x1 << 15)
884#define RT5645_PWR_SV_L_BIT 15
885#define RT5645_PWR_SV_R (0x1 << 14)
886#define RT5645_PWR_SV_R_BIT 14
887#define RT5645_PWR_HV_L (0x1 << 11)
888#define RT5645_PWR_HV_L_BIT 11
889#define RT5645_PWR_HV_R (0x1 << 10)
890#define RT5645_PWR_HV_R_BIT 10
891#define RT5645_PWR_IN_L (0x1 << 9)
892#define RT5645_PWR_IN_L_BIT 9
893#define RT5645_PWR_IN_R (0x1 << 8)
894#define RT5645_PWR_IN_R_BIT 8
895#define RT5645_PWR_MIC_DET (0x1 << 5)
896#define RT5645_PWR_MIC_DET_BIT 5
897
898/* I2S1/2 Audio Serial Data Port Control (0x70 0x71) */
899#define RT5645_I2S_MS_MASK (0x1 << 15)
900#define RT5645_I2S_MS_SFT 15
901#define RT5645_I2S_MS_M (0x0 << 15)
902#define RT5645_I2S_MS_S (0x1 << 15)
903#define RT5645_I2S_O_CP_MASK (0x3 << 10)
904#define RT5645_I2S_O_CP_SFT 10
905#define RT5645_I2S_O_CP_OFF (0x0 << 10)
906#define RT5645_I2S_O_CP_U_LAW (0x1 << 10)
907#define RT5645_I2S_O_CP_A_LAW (0x2 << 10)
908#define RT5645_I2S_I_CP_MASK (0x3 << 8)
909#define RT5645_I2S_I_CP_SFT 8
910#define RT5645_I2S_I_CP_OFF (0x0 << 8)
911#define RT5645_I2S_I_CP_U_LAW (0x1 << 8)
912#define RT5645_I2S_I_CP_A_LAW (0x2 << 8)
913#define RT5645_I2S_BP_MASK (0x1 << 7)
914#define RT5645_I2S_BP_SFT 7
915#define RT5645_I2S_BP_NOR (0x0 << 7)
916#define RT5645_I2S_BP_INV (0x1 << 7)
917#define RT5645_I2S_DL_MASK (0x3 << 2)
918#define RT5645_I2S_DL_SFT 2
919#define RT5645_I2S_DL_16 (0x0 << 2)
920#define RT5645_I2S_DL_20 (0x1 << 2)
921#define RT5645_I2S_DL_24 (0x2 << 2)
922#define RT5645_I2S_DL_8 (0x3 << 2)
923#define RT5645_I2S_DF_MASK (0x3)
924#define RT5645_I2S_DF_SFT 0
925#define RT5645_I2S_DF_I2S (0x0)
926#define RT5645_I2S_DF_LEFT (0x1)
927#define RT5645_I2S_DF_PCM_A (0x2)
928#define RT5645_I2S_DF_PCM_B (0x3)
929
930/* I2S2 Audio Serial Data Port Control (0x71) */
931#define RT5645_I2S2_SDI_MASK (0x1 << 6)
932#define RT5645_I2S2_SDI_SFT 6
933#define RT5645_I2S2_SDI_I2S1 (0x0 << 6)
934#define RT5645_I2S2_SDI_I2S2 (0x1 << 6)
935
936/* ADC/DAC Clock Control 1 (0x73) */
937#define RT5645_I2S_BCLK_MS1_MASK (0x1 << 15)
938#define RT5645_I2S_BCLK_MS1_SFT 15
939#define RT5645_I2S_BCLK_MS1_32 (0x0 << 15)
940#define RT5645_I2S_BCLK_MS1_64 (0x1 << 15)
941#define RT5645_I2S_PD1_MASK (0x7 << 12)
942#define RT5645_I2S_PD1_SFT 12
943#define RT5645_I2S_PD1_1 (0x0 << 12)
944#define RT5645_I2S_PD1_2 (0x1 << 12)
945#define RT5645_I2S_PD1_3 (0x2 << 12)
946#define RT5645_I2S_PD1_4 (0x3 << 12)
947#define RT5645_I2S_PD1_6 (0x4 << 12)
948#define RT5645_I2S_PD1_8 (0x5 << 12)
949#define RT5645_I2S_PD1_12 (0x6 << 12)
950#define RT5645_I2S_PD1_16 (0x7 << 12)
951#define RT5645_I2S_BCLK_MS2_MASK (0x1 << 11)
952#define RT5645_I2S_BCLK_MS2_SFT 11
953#define RT5645_I2S_BCLK_MS2_32 (0x0 << 11)
954#define RT5645_I2S_BCLK_MS2_64 (0x1 << 11)
955#define RT5645_I2S_PD2_MASK (0x7 << 8)
956#define RT5645_I2S_PD2_SFT 8
957#define RT5645_I2S_PD2_1 (0x0 << 8)
958#define RT5645_I2S_PD2_2 (0x1 << 8)
959#define RT5645_I2S_PD2_3 (0x2 << 8)
960#define RT5645_I2S_PD2_4 (0x3 << 8)
961#define RT5645_I2S_PD2_6 (0x4 << 8)
962#define RT5645_I2S_PD2_8 (0x5 << 8)
963#define RT5645_I2S_PD2_12 (0x6 << 8)
964#define RT5645_I2S_PD2_16 (0x7 << 8)
965#define RT5645_I2S_BCLK_MS3_MASK (0x1 << 7)
966#define RT5645_I2S_BCLK_MS3_SFT 7
967#define RT5645_I2S_BCLK_MS3_32 (0x0 << 7)
968#define RT5645_I2S_BCLK_MS3_64 (0x1 << 7)
969#define RT5645_I2S_PD3_MASK (0x7 << 4)
970#define RT5645_I2S_PD3_SFT 4
971#define RT5645_I2S_PD3_1 (0x0 << 4)
972#define RT5645_I2S_PD3_2 (0x1 << 4)
973#define RT5645_I2S_PD3_3 (0x2 << 4)
974#define RT5645_I2S_PD3_4 (0x3 << 4)
975#define RT5645_I2S_PD3_6 (0x4 << 4)
976#define RT5645_I2S_PD3_8 (0x5 << 4)
977#define RT5645_I2S_PD3_12 (0x6 << 4)
978#define RT5645_I2S_PD3_16 (0x7 << 4)
979#define RT5645_DAC_OSR_MASK (0x3 << 2)
980#define RT5645_DAC_OSR_SFT 2
981#define RT5645_DAC_OSR_128 (0x0 << 2)
982#define RT5645_DAC_OSR_64 (0x1 << 2)
983#define RT5645_DAC_OSR_32 (0x2 << 2)
984#define RT5645_DAC_OSR_16 (0x3 << 2)
985#define RT5645_ADC_OSR_MASK (0x3)
986#define RT5645_ADC_OSR_SFT 0
987#define RT5645_ADC_OSR_128 (0x0)
988#define RT5645_ADC_OSR_64 (0x1)
989#define RT5645_ADC_OSR_32 (0x2)
990#define RT5645_ADC_OSR_16 (0x3)
991
992/* ADC/DAC Clock Control 2 (0x74) */
993#define RT5645_DAC_L_OSR_MASK (0x3 << 14)
994#define RT5645_DAC_L_OSR_SFT 14
995#define RT5645_DAC_L_OSR_128 (0x0 << 14)
996#define RT5645_DAC_L_OSR_64 (0x1 << 14)
997#define RT5645_DAC_L_OSR_32 (0x2 << 14)
998#define RT5645_DAC_L_OSR_16 (0x3 << 14)
999#define RT5645_ADC_R_OSR_MASK (0x3 << 12)
1000#define RT5645_ADC_R_OSR_SFT 12
1001#define RT5645_ADC_R_OSR_128 (0x0 << 12)
1002#define RT5645_ADC_R_OSR_64 (0x1 << 12)
1003#define RT5645_ADC_R_OSR_32 (0x2 << 12)
1004#define RT5645_ADC_R_OSR_16 (0x3 << 12)
1005#define RT5645_DAHPF_EN (0x1 << 11)
1006#define RT5645_DAHPF_EN_SFT 11
1007#define RT5645_ADHPF_EN (0x1 << 10)
1008#define RT5645_ADHPF_EN_SFT 10
1009
1010/* Digital Microphone Control (0x75) */
1011#define RT5645_DMIC_1_EN_MASK (0x1 << 15)
1012#define RT5645_DMIC_1_EN_SFT 15
1013#define RT5645_DMIC_1_DIS (0x0 << 15)
1014#define RT5645_DMIC_1_EN (0x1 << 15)
1015#define RT5645_DMIC_2_EN_MASK (0x1 << 14)
1016#define RT5645_DMIC_2_EN_SFT 14
1017#define RT5645_DMIC_2_DIS (0x0 << 14)
1018#define RT5645_DMIC_2_EN (0x1 << 14)
1019#define RT5645_DMIC_1L_LH_MASK (0x1 << 13)
1020#define RT5645_DMIC_1L_LH_SFT 13
1021#define RT5645_DMIC_1L_LH_FALLING (0x0 << 13)
1022#define RT5645_DMIC_1L_LH_RISING (0x1 << 13)
1023#define RT5645_DMIC_1R_LH_MASK (0x1 << 12)
1024#define RT5645_DMIC_1R_LH_SFT 12
1025#define RT5645_DMIC_1R_LH_FALLING (0x0 << 12)
1026#define RT5645_DMIC_1R_LH_RISING (0x1 << 12)
1027#define RT5645_DMIC_2_DP_MASK (0x3 << 10)
1028#define RT5645_DMIC_2_DP_SFT 10
1029#define RT5645_DMIC_2_DP_GPIO6 (0x0 << 10)
1030#define RT5645_DMIC_2_DP_GPIO10 (0x1 << 10)
1031#define RT5645_DMIC_2_DP_GPIO12 (0x2 << 10)
1032#define RT5645_DMIC_2_DP_IN2P (0x3 << 10)
1033#define RT5645_DMIC_2L_LH_MASK (0x1 << 9)
1034#define RT5645_DMIC_2L_LH_SFT 9
1035#define RT5645_DMIC_2L_LH_FALLING (0x0 << 9)
1036#define RT5645_DMIC_2L_LH_RISING (0x1 << 9)
1037#define RT5645_DMIC_2R_LH_MASK (0x1 << 8)
1038#define RT5645_DMIC_2R_LH_SFT 8
1039#define RT5645_DMIC_2R_LH_FALLING (0x0 << 8)
1040#define RT5645_DMIC_2R_LH_RISING (0x1 << 8)
1041#define RT5645_DMIC_CLK_MASK (0x7 << 5)
1042#define RT5645_DMIC_CLK_SFT 5
1043#define RT5645_DMIC_3_EN_MASK (0x1 << 4)
1044#define RT5645_DMIC_3_EN_SFT 4
1045#define RT5645_DMIC_3_DIS (0x0 << 4)
1046#define RT5645_DMIC_3_EN (0x1 << 4)
1047#define RT5645_DMIC_1_DP_MASK (0x3 << 0)
1048#define RT5645_DMIC_1_DP_SFT 0
1049#define RT5645_DMIC_1_DP_GPIO5 (0x0 << 0)
1050#define RT5645_DMIC_1_DP_IN2N (0x1 << 0)
1051#define RT5645_DMIC_1_DP_GPIO11 (0x2 << 0)
1052
1053/* TDM Control 1 (0x77) */
1054#define RT5645_IF1_ADC_IN_MASK (0x3 << 8)
1055#define RT5645_IF1_ADC_IN_SFT 8
1056
1057/* Global Clock Control (0x80) */
1058#define RT5645_SCLK_SRC_MASK (0x3 << 14)
1059#define RT5645_SCLK_SRC_SFT 14
1060#define RT5645_SCLK_SRC_MCLK (0x0 << 14)
1061#define RT5645_SCLK_SRC_PLL1 (0x1 << 14)
1062#define RT5645_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */
1063#define RT5645_PLL1_SRC_MASK (0x3 << 12)
1064#define RT5645_PLL1_SRC_SFT 12
1065#define RT5645_PLL1_SRC_MCLK (0x0 << 12)
1066#define RT5645_PLL1_SRC_BCLK1 (0x1 << 12)
1067#define RT5645_PLL1_SRC_BCLK2 (0x2 << 12)
1068#define RT5645_PLL1_SRC_BCLK3 (0x3 << 12)
1069#define RT5645_PLL1_PD_MASK (0x1 << 3)
1070#define RT5645_PLL1_PD_SFT 3
1071#define RT5645_PLL1_PD_1 (0x0 << 3)
1072#define RT5645_PLL1_PD_2 (0x1 << 3)
1073
1074#define RT5645_PLL_INP_MAX 40000000
1075#define RT5645_PLL_INP_MIN 256000
1076/* PLL M/N/K Code Control 1 (0x81) */
1077#define RT5645_PLL_N_MAX 0x1ff
1078#define RT5645_PLL_N_MASK (RT5645_PLL_N_MAX << 7)
1079#define RT5645_PLL_N_SFT 7
1080#define RT5645_PLL_K_MAX 0x1f
1081#define RT5645_PLL_K_MASK (RT5645_PLL_K_MAX)
1082#define RT5645_PLL_K_SFT 0
1083
1084/* PLL M/N/K Code Control 2 (0x82) */
1085#define RT5645_PLL_M_MAX 0xf
1086#define RT5645_PLL_M_MASK (RT5645_PLL_M_MAX << 12)
1087#define RT5645_PLL_M_SFT 12
1088#define RT5645_PLL_M_BP (0x1 << 11)
1089#define RT5645_PLL_M_BP_SFT 11
1090
1091/* ASRC Control 1 (0x83) */
1092#define RT5645_STO_T_MASK (0x1 << 15)
1093#define RT5645_STO_T_SFT 15
1094#define RT5645_STO_T_SCLK (0x0 << 15)
1095#define RT5645_STO_T_LRCK1 (0x1 << 15)
1096#define RT5645_M1_T_MASK (0x1 << 14)
1097#define RT5645_M1_T_SFT 14
1098#define RT5645_M1_T_I2S2 (0x0 << 14)
1099#define RT5645_M1_T_I2S2_D3 (0x1 << 14)
1100#define RT5645_I2S2_F_MASK (0x1 << 12)
1101#define RT5645_I2S2_F_SFT 12
1102#define RT5645_I2S2_F_I2S2_D2 (0x0 << 12)
1103#define RT5645_I2S2_F_I2S1_TCLK (0x1 << 12)
1104#define RT5645_DMIC_1_M_MASK (0x1 << 9)
1105#define RT5645_DMIC_1_M_SFT 9
1106#define RT5645_DMIC_1_M_NOR (0x0 << 9)
1107#define RT5645_DMIC_1_M_ASYN (0x1 << 9)
1108#define RT5645_DMIC_2_M_MASK (0x1 << 8)
1109#define RT5645_DMIC_2_M_SFT 8
1110#define RT5645_DMIC_2_M_NOR (0x0 << 8)
1111#define RT5645_DMIC_2_M_ASYN (0x1 << 8)
1112
1113/* ASRC Control 2 (0x84) */
1114#define RT5645_MDA_L_M_MASK (0x1 << 15)
1115#define RT5645_MDA_L_M_SFT 15
1116#define RT5645_MDA_L_M_NOR (0x0 << 15)
1117#define RT5645_MDA_L_M_ASYN (0x1 << 15)
1118#define RT5645_MDA_R_M_MASK (0x1 << 14)
1119#define RT5645_MDA_R_M_SFT 14
1120#define RT5645_MDA_R_M_NOR (0x0 << 14)
1121#define RT5645_MDA_R_M_ASYN (0x1 << 14)
1122#define RT5645_MAD_L_M_MASK (0x1 << 13)
1123#define RT5645_MAD_L_M_SFT 13
1124#define RT5645_MAD_L_M_NOR (0x0 << 13)
1125#define RT5645_MAD_L_M_ASYN (0x1 << 13)
1126#define RT5645_MAD_R_M_MASK (0x1 << 12)
1127#define RT5645_MAD_R_M_SFT 12
1128#define RT5645_MAD_R_M_NOR (0x0 << 12)
1129#define RT5645_MAD_R_M_ASYN (0x1 << 12)
1130#define RT5645_ADC_M_MASK (0x1 << 11)
1131#define RT5645_ADC_M_SFT 11
1132#define RT5645_ADC_M_NOR (0x0 << 11)
1133#define RT5645_ADC_M_ASYN (0x1 << 11)
1134#define RT5645_STO_DAC_M_MASK (0x1 << 5)
1135#define RT5645_STO_DAC_M_SFT 5
1136#define RT5645_STO_DAC_M_NOR (0x0 << 5)
1137#define RT5645_STO_DAC_M_ASYN (0x1 << 5)
1138#define RT5645_I2S1_R_D_MASK (0x1 << 4)
1139#define RT5645_I2S1_R_D_SFT 4
1140#define RT5645_I2S1_R_D_DIS (0x0 << 4)
1141#define RT5645_I2S1_R_D_EN (0x1 << 4)
1142#define RT5645_I2S2_R_D_MASK (0x1 << 3)
1143#define RT5645_I2S2_R_D_SFT 3
1144#define RT5645_I2S2_R_D_DIS (0x0 << 3)
1145#define RT5645_I2S2_R_D_EN (0x1 << 3)
1146#define RT5645_PRE_SCLK_MASK (0x3)
1147#define RT5645_PRE_SCLK_SFT 0
1148#define RT5645_PRE_SCLK_512 (0x0)
1149#define RT5645_PRE_SCLK_1024 (0x1)
1150#define RT5645_PRE_SCLK_2048 (0x2)
1151
1152/* ASRC Control 3 (0x85) */
1153#define RT5645_I2S1_RATE_MASK (0xf << 12)
1154#define RT5645_I2S1_RATE_SFT 12
1155#define RT5645_I2S2_RATE_MASK (0xf << 8)
1156#define RT5645_I2S2_RATE_SFT 8
1157
1158/* ASRC Control 4 (0x89) */
1159#define RT5645_I2S1_PD_MASK (0x7 << 12)
1160#define RT5645_I2S1_PD_SFT 12
1161#define RT5645_I2S2_PD_MASK (0x7 << 8)
1162#define RT5645_I2S2_PD_SFT 8
1163
1164/* HPOUT Over Current Detection (0x8b) */
1165#define RT5645_HP_OVCD_MASK (0x1 << 10)
1166#define RT5645_HP_OVCD_SFT 10
1167#define RT5645_HP_OVCD_DIS (0x0 << 10)
1168#define RT5645_HP_OVCD_EN (0x1 << 10)
1169#define RT5645_HP_OC_TH_MASK (0x3 << 8)
1170#define RT5645_HP_OC_TH_SFT 8
1171#define RT5645_HP_OC_TH_90 (0x0 << 8)
1172#define RT5645_HP_OC_TH_105 (0x1 << 8)
1173#define RT5645_HP_OC_TH_120 (0x2 << 8)
1174#define RT5645_HP_OC_TH_135 (0x3 << 8)
1175
1176/* Class D Over Current Control (0x8c) */
1177#define RT5645_CLSD_OC_MASK (0x1 << 9)
1178#define RT5645_CLSD_OC_SFT 9
1179#define RT5645_CLSD_OC_PU (0x0 << 9)
1180#define RT5645_CLSD_OC_PD (0x1 << 9)
1181#define RT5645_AUTO_PD_MASK (0x1 << 8)
1182#define RT5645_AUTO_PD_SFT 8
1183#define RT5645_AUTO_PD_DIS (0x0 << 8)
1184#define RT5645_AUTO_PD_EN (0x1 << 8)
1185#define RT5645_CLSD_OC_TH_MASK (0x3f)
1186#define RT5645_CLSD_OC_TH_SFT 0
1187
1188/* Class D Output Control (0x8d) */
1189#define RT5645_CLSD_RATIO_MASK (0xf << 12)
1190#define RT5645_CLSD_RATIO_SFT 12
1191#define RT5645_CLSD_OM_MASK (0x1 << 11)
1192#define RT5645_CLSD_OM_SFT 11
1193#define RT5645_CLSD_OM_MONO (0x0 << 11)
1194#define RT5645_CLSD_OM_STO (0x1 << 11)
1195#define RT5645_CLSD_SCH_MASK (0x1 << 10)
1196#define RT5645_CLSD_SCH_SFT 10
1197#define RT5645_CLSD_SCH_L (0x0 << 10)
1198#define RT5645_CLSD_SCH_S (0x1 << 10)
1199
1200/* Depop Mode Control 1 (0x8e) */
1201#define RT5645_SMT_TRIG_MASK (0x1 << 15)
1202#define RT5645_SMT_TRIG_SFT 15
1203#define RT5645_SMT_TRIG_DIS (0x0 << 15)
1204#define RT5645_SMT_TRIG_EN (0x1 << 15)
1205#define RT5645_HP_L_SMT_MASK (0x1 << 9)
1206#define RT5645_HP_L_SMT_SFT 9
1207#define RT5645_HP_L_SMT_DIS (0x0 << 9)
1208#define RT5645_HP_L_SMT_EN (0x1 << 9)
1209#define RT5645_HP_R_SMT_MASK (0x1 << 8)
1210#define RT5645_HP_R_SMT_SFT 8
1211#define RT5645_HP_R_SMT_DIS (0x0 << 8)
1212#define RT5645_HP_R_SMT_EN (0x1 << 8)
1213#define RT5645_HP_CD_PD_MASK (0x1 << 7)
1214#define RT5645_HP_CD_PD_SFT 7
1215#define RT5645_HP_CD_PD_DIS (0x0 << 7)
1216#define RT5645_HP_CD_PD_EN (0x1 << 7)
1217#define RT5645_RSTN_MASK (0x1 << 6)
1218#define RT5645_RSTN_SFT 6
1219#define RT5645_RSTN_DIS (0x0 << 6)
1220#define RT5645_RSTN_EN (0x1 << 6)
1221#define RT5645_RSTP_MASK (0x1 << 5)
1222#define RT5645_RSTP_SFT 5
1223#define RT5645_RSTP_DIS (0x0 << 5)
1224#define RT5645_RSTP_EN (0x1 << 5)
1225#define RT5645_HP_CO_MASK (0x1 << 4)
1226#define RT5645_HP_CO_SFT 4
1227#define RT5645_HP_CO_DIS (0x0 << 4)
1228#define RT5645_HP_CO_EN (0x1 << 4)
1229#define RT5645_HP_CP_MASK (0x1 << 3)
1230#define RT5645_HP_CP_SFT 3
1231#define RT5645_HP_CP_PD (0x0 << 3)
1232#define RT5645_HP_CP_PU (0x1 << 3)
1233#define RT5645_HP_SG_MASK (0x1 << 2)
1234#define RT5645_HP_SG_SFT 2
1235#define RT5645_HP_SG_DIS (0x0 << 2)
1236#define RT5645_HP_SG_EN (0x1 << 2)
1237#define RT5645_HP_DP_MASK (0x1 << 1)
1238#define RT5645_HP_DP_SFT 1
1239#define RT5645_HP_DP_PD (0x0 << 1)
1240#define RT5645_HP_DP_PU (0x1 << 1)
1241#define RT5645_HP_CB_MASK (0x1)
1242#define RT5645_HP_CB_SFT 0
1243#define RT5645_HP_CB_PD (0x0)
1244#define RT5645_HP_CB_PU (0x1)
1245
1246/* Depop Mode Control 2 (0x8f) */
1247#define RT5645_DEPOP_MASK (0x1 << 13)
1248#define RT5645_DEPOP_SFT 13
1249#define RT5645_DEPOP_AUTO (0x0 << 13)
1250#define RT5645_DEPOP_MAN (0x1 << 13)
1251#define RT5645_RAMP_MASK (0x1 << 12)
1252#define RT5645_RAMP_SFT 12
1253#define RT5645_RAMP_DIS (0x0 << 12)
1254#define RT5645_RAMP_EN (0x1 << 12)
1255#define RT5645_BPS_MASK (0x1 << 11)
1256#define RT5645_BPS_SFT 11
1257#define RT5645_BPS_DIS (0x0 << 11)
1258#define RT5645_BPS_EN (0x1 << 11)
1259#define RT5645_FAST_UPDN_MASK (0x1 << 10)
1260#define RT5645_FAST_UPDN_SFT 10
1261#define RT5645_FAST_UPDN_DIS (0x0 << 10)
1262#define RT5645_FAST_UPDN_EN (0x1 << 10)
1263#define RT5645_MRES_MASK (0x3 << 8)
1264#define RT5645_MRES_SFT 8
1265#define RT5645_MRES_15MO (0x0 << 8)
1266#define RT5645_MRES_25MO (0x1 << 8)
1267#define RT5645_MRES_35MO (0x2 << 8)
1268#define RT5645_MRES_45MO (0x3 << 8)
1269#define RT5645_VLO_MASK (0x1 << 7)
1270#define RT5645_VLO_SFT 7
1271#define RT5645_VLO_3V (0x0 << 7)
1272#define RT5645_VLO_32V (0x1 << 7)
1273#define RT5645_DIG_DP_MASK (0x1 << 6)
1274#define RT5645_DIG_DP_SFT 6
1275#define RT5645_DIG_DP_DIS (0x0 << 6)
1276#define RT5645_DIG_DP_EN (0x1 << 6)
1277#define RT5645_DP_TH_MASK (0x3 << 4)
1278#define RT5645_DP_TH_SFT 4
1279
1280/* Depop Mode Control 3 (0x90) */
1281#define RT5645_CP_SYS_MASK (0x7 << 12)
1282#define RT5645_CP_SYS_SFT 12
1283#define RT5645_CP_FQ1_MASK (0x7 << 8)
1284#define RT5645_CP_FQ1_SFT 8
1285#define RT5645_CP_FQ2_MASK (0x7 << 4)
1286#define RT5645_CP_FQ2_SFT 4
1287#define RT5645_CP_FQ3_MASK (0x7)
1288#define RT5645_CP_FQ3_SFT 0
1289#define RT5645_CP_FQ_1_5_KHZ 0
1290#define RT5645_CP_FQ_3_KHZ 1
1291#define RT5645_CP_FQ_6_KHZ 2
1292#define RT5645_CP_FQ_12_KHZ 3
1293#define RT5645_CP_FQ_24_KHZ 4
1294#define RT5645_CP_FQ_48_KHZ 5
1295#define RT5645_CP_FQ_96_KHZ 6
1296#define RT5645_CP_FQ_192_KHZ 7
1297
1298/* PV detection and SPK gain control (0x92) */
1299#define RT5645_PVDD_DET_MASK (0x1 << 15)
1300#define RT5645_PVDD_DET_SFT 15
1301#define RT5645_PVDD_DET_DIS (0x0 << 15)
1302#define RT5645_PVDD_DET_EN (0x1 << 15)
1303#define RT5645_SPK_AG_MASK (0x1 << 14)
1304#define RT5645_SPK_AG_SFT 14
1305#define RT5645_SPK_AG_DIS (0x0 << 14)
1306#define RT5645_SPK_AG_EN (0x1 << 14)
1307
1308/* Micbias Control (0x93) */
1309#define RT5645_MIC1_BS_MASK (0x1 << 15)
1310#define RT5645_MIC1_BS_SFT 15
1311#define RT5645_MIC1_BS_9AV (0x0 << 15)
1312#define RT5645_MIC1_BS_75AV (0x1 << 15)
1313#define RT5645_MIC2_BS_MASK (0x1 << 14)
1314#define RT5645_MIC2_BS_SFT 14
1315#define RT5645_MIC2_BS_9AV (0x0 << 14)
1316#define RT5645_MIC2_BS_75AV (0x1 << 14)
1317#define RT5645_MIC1_CLK_MASK (0x1 << 13)
1318#define RT5645_MIC1_CLK_SFT 13
1319#define RT5645_MIC1_CLK_DIS (0x0 << 13)
1320#define RT5645_MIC1_CLK_EN (0x1 << 13)
1321#define RT5645_MIC2_CLK_MASK (0x1 << 12)
1322#define RT5645_MIC2_CLK_SFT 12
1323#define RT5645_MIC2_CLK_DIS (0x0 << 12)
1324#define RT5645_MIC2_CLK_EN (0x1 << 12)
1325#define RT5645_MIC1_OVCD_MASK (0x1 << 11)
1326#define RT5645_MIC1_OVCD_SFT 11
1327#define RT5645_MIC1_OVCD_DIS (0x0 << 11)
1328#define RT5645_MIC1_OVCD_EN (0x1 << 11)
1329#define RT5645_MIC1_OVTH_MASK (0x3 << 9)
1330#define RT5645_MIC1_OVTH_SFT 9
1331#define RT5645_MIC1_OVTH_600UA (0x0 << 9)
1332#define RT5645_MIC1_OVTH_1500UA (0x1 << 9)
1333#define RT5645_MIC1_OVTH_2000UA (0x2 << 9)
1334#define RT5645_MIC2_OVCD_MASK (0x1 << 8)
1335#define RT5645_MIC2_OVCD_SFT 8
1336#define RT5645_MIC2_OVCD_DIS (0x0 << 8)
1337#define RT5645_MIC2_OVCD_EN (0x1 << 8)
1338#define RT5645_MIC2_OVTH_MASK (0x3 << 6)
1339#define RT5645_MIC2_OVTH_SFT 6
1340#define RT5645_MIC2_OVTH_600UA (0x0 << 6)
1341#define RT5645_MIC2_OVTH_1500UA (0x1 << 6)
1342#define RT5645_MIC2_OVTH_2000UA (0x2 << 6)
1343#define RT5645_PWR_MB_MASK (0x1 << 5)
1344#define RT5645_PWR_MB_SFT 5
1345#define RT5645_PWR_MB_PD (0x0 << 5)
1346#define RT5645_PWR_MB_PU (0x1 << 5)
1347#define RT5645_PWR_CLK25M_MASK (0x1 << 4)
1348#define RT5645_PWR_CLK25M_SFT 4
1349#define RT5645_PWR_CLK25M_PD (0x0 << 4)
1350#define RT5645_PWR_CLK25M_PU (0x1 << 4)
1351
1352/* VAD Control 4 (0x9d) */
1353#define RT5645_VAD_SEL_MASK (0x3 << 8)
1354#define RT5645_VAD_SEL_SFT 8
1355
1356/* EQ Control 1 (0xb0) */
1357#define RT5645_EQ_SRC_MASK (0x1 << 15)
1358#define RT5645_EQ_SRC_SFT 15
1359#define RT5645_EQ_SRC_DAC (0x0 << 15)
1360#define RT5645_EQ_SRC_ADC (0x1 << 15)
1361#define RT5645_EQ_UPD (0x1 << 14)
1362#define RT5645_EQ_UPD_BIT 14
1363#define RT5645_EQ_CD_MASK (0x1 << 13)
1364#define RT5645_EQ_CD_SFT 13
1365#define RT5645_EQ_CD_DIS (0x0 << 13)
1366#define RT5645_EQ_CD_EN (0x1 << 13)
1367#define RT5645_EQ_DITH_MASK (0x3 << 8)
1368#define RT5645_EQ_DITH_SFT 8
1369#define RT5645_EQ_DITH_NOR (0x0 << 8)
1370#define RT5645_EQ_DITH_LSB (0x1 << 8)
1371#define RT5645_EQ_DITH_LSB_1 (0x2 << 8)
1372#define RT5645_EQ_DITH_LSB_2 (0x3 << 8)
1373
1374/* EQ Control 2 (0xb1) */
1375#define RT5645_EQ_HPF1_M_MASK (0x1 << 8)
1376#define RT5645_EQ_HPF1_M_SFT 8
1377#define RT5645_EQ_HPF1_M_HI (0x0 << 8)
1378#define RT5645_EQ_HPF1_M_1ST (0x1 << 8)
1379#define RT5645_EQ_LPF1_M_MASK (0x1 << 7)
1380#define RT5645_EQ_LPF1_M_SFT 7
1381#define RT5645_EQ_LPF1_M_LO (0x0 << 7)
1382#define RT5645_EQ_LPF1_M_1ST (0x1 << 7)
1383#define RT5645_EQ_HPF2_MASK (0x1 << 6)
1384#define RT5645_EQ_HPF2_SFT 6
1385#define RT5645_EQ_HPF2_DIS (0x0 << 6)
1386#define RT5645_EQ_HPF2_EN (0x1 << 6)
1387#define RT5645_EQ_HPF1_MASK (0x1 << 5)
1388#define RT5645_EQ_HPF1_SFT 5
1389#define RT5645_EQ_HPF1_DIS (0x0 << 5)
1390#define RT5645_EQ_HPF1_EN (0x1 << 5)
1391#define RT5645_EQ_BPF4_MASK (0x1 << 4)
1392#define RT5645_EQ_BPF4_SFT 4
1393#define RT5645_EQ_BPF4_DIS (0x0 << 4)
1394#define RT5645_EQ_BPF4_EN (0x1 << 4)
1395#define RT5645_EQ_BPF3_MASK (0x1 << 3)
1396#define RT5645_EQ_BPF3_SFT 3
1397#define RT5645_EQ_BPF3_DIS (0x0 << 3)
1398#define RT5645_EQ_BPF3_EN (0x1 << 3)
1399#define RT5645_EQ_BPF2_MASK (0x1 << 2)
1400#define RT5645_EQ_BPF2_SFT 2
1401#define RT5645_EQ_BPF2_DIS (0x0 << 2)
1402#define RT5645_EQ_BPF2_EN (0x1 << 2)
1403#define RT5645_EQ_BPF1_MASK (0x1 << 1)
1404#define RT5645_EQ_BPF1_SFT 1
1405#define RT5645_EQ_BPF1_DIS (0x0 << 1)
1406#define RT5645_EQ_BPF1_EN (0x1 << 1)
1407#define RT5645_EQ_LPF_MASK (0x1)
1408#define RT5645_EQ_LPF_SFT 0
1409#define RT5645_EQ_LPF_DIS (0x0)
1410#define RT5645_EQ_LPF_EN (0x1)
1411#define RT5645_EQ_CTRL_MASK (0x7f)
1412
1413/* Memory Test (0xb2) */
1414#define RT5645_MT_MASK (0x1 << 15)
1415#define RT5645_MT_SFT 15
1416#define RT5645_MT_DIS (0x0 << 15)
1417#define RT5645_MT_EN (0x1 << 15)
1418
1419/* DRC/AGC Control 1 (0xb4) */
1420#define RT5645_DRC_AGC_P_MASK (0x1 << 15)
1421#define RT5645_DRC_AGC_P_SFT 15
1422#define RT5645_DRC_AGC_P_DAC (0x0 << 15)
1423#define RT5645_DRC_AGC_P_ADC (0x1 << 15)
1424#define RT5645_DRC_AGC_MASK (0x1 << 14)
1425#define RT5645_DRC_AGC_SFT 14
1426#define RT5645_DRC_AGC_DIS (0x0 << 14)
1427#define RT5645_DRC_AGC_EN (0x1 << 14)
1428#define RT5645_DRC_AGC_UPD (0x1 << 13)
1429#define RT5645_DRC_AGC_UPD_BIT 13
1430#define RT5645_DRC_AGC_AR_MASK (0x1f << 8)
1431#define RT5645_DRC_AGC_AR_SFT 8
1432#define RT5645_DRC_AGC_R_MASK (0x7 << 5)
1433#define RT5645_DRC_AGC_R_SFT 5
1434#define RT5645_DRC_AGC_R_48K (0x1 << 5)
1435#define RT5645_DRC_AGC_R_96K (0x2 << 5)
1436#define RT5645_DRC_AGC_R_192K (0x3 << 5)
1437#define RT5645_DRC_AGC_R_441K (0x5 << 5)
1438#define RT5645_DRC_AGC_R_882K (0x6 << 5)
1439#define RT5645_DRC_AGC_R_1764K (0x7 << 5)
1440#define RT5645_DRC_AGC_RC_MASK (0x1f)
1441#define RT5645_DRC_AGC_RC_SFT 0
1442
1443/* DRC/AGC Control 2 (0xb5) */
1444#define RT5645_DRC_AGC_POB_MASK (0x3f << 8)
1445#define RT5645_DRC_AGC_POB_SFT 8
1446#define RT5645_DRC_AGC_CP_MASK (0x1 << 7)
1447#define RT5645_DRC_AGC_CP_SFT 7
1448#define RT5645_DRC_AGC_CP_DIS (0x0 << 7)
1449#define RT5645_DRC_AGC_CP_EN (0x1 << 7)
1450#define RT5645_DRC_AGC_CPR_MASK (0x3 << 5)
1451#define RT5645_DRC_AGC_CPR_SFT 5
1452#define RT5645_DRC_AGC_CPR_1_1 (0x0 << 5)
1453#define RT5645_DRC_AGC_CPR_1_2 (0x1 << 5)
1454#define RT5645_DRC_AGC_CPR_1_3 (0x2 << 5)
1455#define RT5645_DRC_AGC_CPR_1_4 (0x3 << 5)
1456#define RT5645_DRC_AGC_PRB_MASK (0x1f)
1457#define RT5645_DRC_AGC_PRB_SFT 0
1458
1459/* DRC/AGC Control 3 (0xb6) */
1460#define RT5645_DRC_AGC_NGB_MASK (0xf << 12)
1461#define RT5645_DRC_AGC_NGB_SFT 12
1462#define RT5645_DRC_AGC_TAR_MASK (0x1f << 7)
1463#define RT5645_DRC_AGC_TAR_SFT 7
1464#define RT5645_DRC_AGC_NG_MASK (0x1 << 6)
1465#define RT5645_DRC_AGC_NG_SFT 6
1466#define RT5645_DRC_AGC_NG_DIS (0x0 << 6)
1467#define RT5645_DRC_AGC_NG_EN (0x1 << 6)
1468#define RT5645_DRC_AGC_NGH_MASK (0x1 << 5)
1469#define RT5645_DRC_AGC_NGH_SFT 5
1470#define RT5645_DRC_AGC_NGH_DIS (0x0 << 5)
1471#define RT5645_DRC_AGC_NGH_EN (0x1 << 5)
1472#define RT5645_DRC_AGC_NGT_MASK (0x1f)
1473#define RT5645_DRC_AGC_NGT_SFT 0
1474
1475/* ANC Control 1 (0xb8) */
1476#define RT5645_ANC_M_MASK (0x1 << 15)
1477#define RT5645_ANC_M_SFT 15
1478#define RT5645_ANC_M_NOR (0x0 << 15)
1479#define RT5645_ANC_M_REV (0x1 << 15)
1480#define RT5645_ANC_MASK (0x1 << 14)
1481#define RT5645_ANC_SFT 14
1482#define RT5645_ANC_DIS (0x0 << 14)
1483#define RT5645_ANC_EN (0x1 << 14)
1484#define RT5645_ANC_MD_MASK (0x3 << 12)
1485#define RT5645_ANC_MD_SFT 12
1486#define RT5645_ANC_MD_DIS (0x0 << 12)
1487#define RT5645_ANC_MD_67MS (0x1 << 12)
1488#define RT5645_ANC_MD_267MS (0x2 << 12)
1489#define RT5645_ANC_MD_1067MS (0x3 << 12)
1490#define RT5645_ANC_SN_MASK (0x1 << 11)
1491#define RT5645_ANC_SN_SFT 11
1492#define RT5645_ANC_SN_DIS (0x0 << 11)
1493#define RT5645_ANC_SN_EN (0x1 << 11)
1494#define RT5645_ANC_CLK_MASK (0x1 << 10)
1495#define RT5645_ANC_CLK_SFT 10
1496#define RT5645_ANC_CLK_ANC (0x0 << 10)
1497#define RT5645_ANC_CLK_REG (0x1 << 10)
1498#define RT5645_ANC_ZCD_MASK (0x3 << 8)
1499#define RT5645_ANC_ZCD_SFT 8
1500#define RT5645_ANC_ZCD_DIS (0x0 << 8)
1501#define RT5645_ANC_ZCD_T1 (0x1 << 8)
1502#define RT5645_ANC_ZCD_T2 (0x2 << 8)
1503#define RT5645_ANC_ZCD_WT (0x3 << 8)
1504#define RT5645_ANC_CS_MASK (0x1 << 7)
1505#define RT5645_ANC_CS_SFT 7
1506#define RT5645_ANC_CS_DIS (0x0 << 7)
1507#define RT5645_ANC_CS_EN (0x1 << 7)
1508#define RT5645_ANC_SW_MASK (0x1 << 6)
1509#define RT5645_ANC_SW_SFT 6
1510#define RT5645_ANC_SW_NOR (0x0 << 6)
1511#define RT5645_ANC_SW_AUTO (0x1 << 6)
1512#define RT5645_ANC_CO_L_MASK (0x3f)
1513#define RT5645_ANC_CO_L_SFT 0
1514
1515/* ANC Control 2 (0xb6) */
1516#define RT5645_ANC_FG_R_MASK (0xf << 12)
1517#define RT5645_ANC_FG_R_SFT 12
1518#define RT5645_ANC_FG_L_MASK (0xf << 8)
1519#define RT5645_ANC_FG_L_SFT 8
1520#define RT5645_ANC_CG_R_MASK (0xf << 4)
1521#define RT5645_ANC_CG_R_SFT 4
1522#define RT5645_ANC_CG_L_MASK (0xf)
1523#define RT5645_ANC_CG_L_SFT 0
1524
1525/* ANC Control 3 (0xb6) */
1526#define RT5645_ANC_CD_MASK (0x1 << 6)
1527#define RT5645_ANC_CD_SFT 6
1528#define RT5645_ANC_CD_BOTH (0x0 << 6)
1529#define RT5645_ANC_CD_IND (0x1 << 6)
1530#define RT5645_ANC_CO_R_MASK (0x3f)
1531#define RT5645_ANC_CO_R_SFT 0
1532
1533/* Jack Detect Control (0xbb) */
1534#define RT5645_JD_MASK (0x7 << 13)
1535#define RT5645_JD_SFT 13
1536#define RT5645_JD_DIS (0x0 << 13)
1537#define RT5645_JD_GPIO1 (0x1 << 13)
1538#define RT5645_JD_JD1_IN4P (0x2 << 13)
1539#define RT5645_JD_JD2_IN4N (0x3 << 13)
1540#define RT5645_JD_GPIO2 (0x4 << 13)
1541#define RT5645_JD_GPIO3 (0x5 << 13)
1542#define RT5645_JD_GPIO4 (0x6 << 13)
1543#define RT5645_JD_HP_MASK (0x1 << 11)
1544#define RT5645_JD_HP_SFT 11
1545#define RT5645_JD_HP_DIS (0x0 << 11)
1546#define RT5645_JD_HP_EN (0x1 << 11)
1547#define RT5645_JD_HP_TRG_MASK (0x1 << 10)
1548#define RT5645_JD_HP_TRG_SFT 10
1549#define RT5645_JD_HP_TRG_LO (0x0 << 10)
1550#define RT5645_JD_HP_TRG_HI (0x1 << 10)
1551#define RT5645_JD_SPL_MASK (0x1 << 9)
1552#define RT5645_JD_SPL_SFT 9
1553#define RT5645_JD_SPL_DIS (0x0 << 9)
1554#define RT5645_JD_SPL_EN (0x1 << 9)
1555#define RT5645_JD_SPL_TRG_MASK (0x1 << 8)
1556#define RT5645_JD_SPL_TRG_SFT 8
1557#define RT5645_JD_SPL_TRG_LO (0x0 << 8)
1558#define RT5645_JD_SPL_TRG_HI (0x1 << 8)
1559#define RT5645_JD_SPR_MASK (0x1 << 7)
1560#define RT5645_JD_SPR_SFT 7
1561#define RT5645_JD_SPR_DIS (0x0 << 7)
1562#define RT5645_JD_SPR_EN (0x1 << 7)
1563#define RT5645_JD_SPR_TRG_MASK (0x1 << 6)
1564#define RT5645_JD_SPR_TRG_SFT 6
1565#define RT5645_JD_SPR_TRG_LO (0x0 << 6)
1566#define RT5645_JD_SPR_TRG_HI (0x1 << 6)
1567#define RT5645_JD_MO_MASK (0x1 << 5)
1568#define RT5645_JD_MO_SFT 5
1569#define RT5645_JD_MO_DIS (0x0 << 5)
1570#define RT5645_JD_MO_EN (0x1 << 5)
1571#define RT5645_JD_MO_TRG_MASK (0x1 << 4)
1572#define RT5645_JD_MO_TRG_SFT 4
1573#define RT5645_JD_MO_TRG_LO (0x0 << 4)
1574#define RT5645_JD_MO_TRG_HI (0x1 << 4)
1575#define RT5645_JD_LO_MASK (0x1 << 3)
1576#define RT5645_JD_LO_SFT 3
1577#define RT5645_JD_LO_DIS (0x0 << 3)
1578#define RT5645_JD_LO_EN (0x1 << 3)
1579#define RT5645_JD_LO_TRG_MASK (0x1 << 2)
1580#define RT5645_JD_LO_TRG_SFT 2
1581#define RT5645_JD_LO_TRG_LO (0x0 << 2)
1582#define RT5645_JD_LO_TRG_HI (0x1 << 2)
1583#define RT5645_JD1_IN4P_MASK (0x1 << 1)
1584#define RT5645_JD1_IN4P_SFT 1
1585#define RT5645_JD1_IN4P_DIS (0x0 << 1)
1586#define RT5645_JD1_IN4P_EN (0x1 << 1)
1587#define RT5645_JD2_IN4N_MASK (0x1)
1588#define RT5645_JD2_IN4N_SFT 0
1589#define RT5645_JD2_IN4N_DIS (0x0)
1590#define RT5645_JD2_IN4N_EN (0x1)
1591
1592/* Jack detect for ANC (0xbc) */
1593#define RT5645_ANC_DET_MASK (0x3 << 4)
1594#define RT5645_ANC_DET_SFT 4
1595#define RT5645_ANC_DET_DIS (0x0 << 4)
1596#define RT5645_ANC_DET_MB1 (0x1 << 4)
1597#define RT5645_ANC_DET_MB2 (0x2 << 4)
1598#define RT5645_ANC_DET_JD (0x3 << 4)
1599#define RT5645_AD_TRG_MASK (0x1 << 3)
1600#define RT5645_AD_TRG_SFT 3
1601#define RT5645_AD_TRG_LO (0x0 << 3)
1602#define RT5645_AD_TRG_HI (0x1 << 3)
1603#define RT5645_ANCM_DET_MASK (0x3 << 4)
1604#define RT5645_ANCM_DET_SFT 4
1605#define RT5645_ANCM_DET_DIS (0x0 << 4)
1606#define RT5645_ANCM_DET_MB1 (0x1 << 4)
1607#define RT5645_ANCM_DET_MB2 (0x2 << 4)
1608#define RT5645_ANCM_DET_JD (0x3 << 4)
1609#define RT5645_AMD_TRG_MASK (0x1 << 3)
1610#define RT5645_AMD_TRG_SFT 3
1611#define RT5645_AMD_TRG_LO (0x0 << 3)
1612#define RT5645_AMD_TRG_HI (0x1 << 3)
1613
1614/* IRQ Control 1 (0xbd) */
1615#define RT5645_IRQ_JD_MASK (0x1 << 15)
1616#define RT5645_IRQ_JD_SFT 15
1617#define RT5645_IRQ_JD_BP (0x0 << 15)
1618#define RT5645_IRQ_JD_NOR (0x1 << 15)
1619#define RT5645_IRQ_OT_MASK (0x1 << 14)
1620#define RT5645_IRQ_OT_SFT 14
1621#define RT5645_IRQ_OT_BP (0x0 << 14)
1622#define RT5645_IRQ_OT_NOR (0x1 << 14)
1623#define RT5645_JD_STKY_MASK (0x1 << 13)
1624#define RT5645_JD_STKY_SFT 13
1625#define RT5645_JD_STKY_DIS (0x0 << 13)
1626#define RT5645_JD_STKY_EN (0x1 << 13)
1627#define RT5645_OT_STKY_MASK (0x1 << 12)
1628#define RT5645_OT_STKY_SFT 12
1629#define RT5645_OT_STKY_DIS (0x0 << 12)
1630#define RT5645_OT_STKY_EN (0x1 << 12)
1631#define RT5645_JD_P_MASK (0x1 << 11)
1632#define RT5645_JD_P_SFT 11
1633#define RT5645_JD_P_NOR (0x0 << 11)
1634#define RT5645_JD_P_INV (0x1 << 11)
1635#define RT5645_OT_P_MASK (0x1 << 10)
1636#define RT5645_OT_P_SFT 10
1637#define RT5645_OT_P_NOR (0x0 << 10)
1638#define RT5645_OT_P_INV (0x1 << 10)
1639
1640/* IRQ Control 2 (0xbe) */
1641#define RT5645_IRQ_MB1_OC_MASK (0x1 << 15)
1642#define RT5645_IRQ_MB1_OC_SFT 15
1643#define RT5645_IRQ_MB1_OC_BP (0x0 << 15)
1644#define RT5645_IRQ_MB1_OC_NOR (0x1 << 15)
1645#define RT5645_IRQ_MB2_OC_MASK (0x1 << 14)
1646#define RT5645_IRQ_MB2_OC_SFT 14
1647#define RT5645_IRQ_MB2_OC_BP (0x0 << 14)
1648#define RT5645_IRQ_MB2_OC_NOR (0x1 << 14)
1649#define RT5645_MB1_OC_STKY_MASK (0x1 << 13)
1650#define RT5645_MB1_OC_STKY_SFT 13
1651#define RT5645_MB1_OC_STKY_DIS (0x0 << 13)
1652#define RT5645_MB1_OC_STKY_EN (0x1 << 13)
1653#define RT5645_MB2_OC_STKY_MASK (0x1 << 12)
1654#define RT5645_MB2_OC_STKY_SFT 12
1655#define RT5645_MB2_OC_STKY_DIS (0x0 << 12)
1656#define RT5645_MB2_OC_STKY_EN (0x1 << 12)
1657#define RT5645_MB1_OC_P_MASK (0x1 << 7)
1658#define RT5645_MB1_OC_P_SFT 7
1659#define RT5645_MB1_OC_P_NOR (0x0 << 7)
1660#define RT5645_MB1_OC_P_INV (0x1 << 7)
1661#define RT5645_MB2_OC_P_MASK (0x1 << 6)
1662#define RT5645_MB2_OC_P_SFT 6
1663#define RT5645_MB2_OC_P_NOR (0x0 << 6)
1664#define RT5645_MB2_OC_P_INV (0x1 << 6)
1665#define RT5645_MB1_OC_CLR (0x1 << 3)
1666#define RT5645_MB1_OC_CLR_SFT 3
1667#define RT5645_MB2_OC_CLR (0x1 << 2)
1668#define RT5645_MB2_OC_CLR_SFT 2
1669
1670/* GPIO Control 1 (0xc0) */
1671#define RT5645_GP1_PIN_MASK (0x1 << 15)
1672#define RT5645_GP1_PIN_SFT 15
1673#define RT5645_GP1_PIN_GPIO1 (0x0 << 15)
1674#define RT5645_GP1_PIN_IRQ (0x1 << 15)
1675#define RT5645_GP2_PIN_MASK (0x1 << 14)
1676#define RT5645_GP2_PIN_SFT 14
1677#define RT5645_GP2_PIN_GPIO2 (0x0 << 14)
1678#define RT5645_GP2_PIN_DMIC1_SCL (0x1 << 14)
1679#define RT5645_GP3_PIN_MASK (0x3 << 12)
1680#define RT5645_GP3_PIN_SFT 12
1681#define RT5645_GP3_PIN_GPIO3 (0x0 << 12)
1682#define RT5645_GP3_PIN_DMIC1_SDA (0x1 << 12)
1683#define RT5645_GP3_PIN_IRQ (0x2 << 12)
1684#define RT5645_GP4_PIN_MASK (0x1 << 11)
1685#define RT5645_GP4_PIN_SFT 11
1686#define RT5645_GP4_PIN_GPIO4 (0x0 << 11)
1687#define RT5645_GP4_PIN_DMIC2_SDA (0x1 << 11)
1688#define RT5645_DP_SIG_MASK (0x1 << 10)
1689#define RT5645_DP_SIG_SFT 10
1690#define RT5645_DP_SIG_TEST (0x0 << 10)
1691#define RT5645_DP_SIG_AP (0x1 << 10)
1692#define RT5645_GPIO_M_MASK (0x1 << 9)
1693#define RT5645_GPIO_M_SFT 9
1694#define RT5645_GPIO_M_FLT (0x0 << 9)
1695#define RT5645_GPIO_M_PH (0x1 << 9)
1696#define RT5645_I2S2_SEL (0x1 << 8)
1697#define RT5645_I2S2_SEL_SFT 8
1698#define RT5645_GP5_PIN_MASK (0x1 << 7)
1699#define RT5645_GP5_PIN_SFT 7
1700#define RT5645_GP5_PIN_GPIO5 (0x0 << 7)
1701#define RT5645_GP5_PIN_DMIC1_SDA (0x1 << 7)
1702#define RT5645_GP6_PIN_MASK (0x1 << 6)
1703#define RT5645_GP6_PIN_SFT 6
1704#define RT5645_GP6_PIN_GPIO6 (0x0 << 6)
1705#define RT5645_GP6_PIN_DMIC2_SDA (0x1 << 6)
1706#define RT5645_GP8_PIN_MASK (0x1 << 3)
1707#define RT5645_GP8_PIN_SFT 3
1708#define RT5645_GP8_PIN_GPIO8 (0x0 << 3)
1709#define RT5645_GP8_PIN_DMIC2_SDA (0x1 << 3)
1710#define RT5645_GP12_PIN_MASK (0x1 << 2)
1711#define RT5645_GP12_PIN_SFT 2
1712#define RT5645_GP12_PIN_GPIO12 (0x0 << 2)
1713#define RT5645_GP12_PIN_DMIC2_SDA (0x1 << 2)
1714#define RT5645_GP11_PIN_MASK (0x1 << 1)
1715#define RT5645_GP11_PIN_SFT 1
1716#define RT5645_GP11_PIN_GPIO11 (0x0 << 1)
1717#define RT5645_GP11_PIN_DMIC1_SDA (0x1 << 1)
1718#define RT5645_GP10_PIN_MASK (0x1)
1719#define RT5645_GP10_PIN_SFT 0
1720#define RT5645_GP10_PIN_GPIO10 (0x0)
1721#define RT5645_GP10_PIN_DMIC2_SDA (0x1)
1722
1723/* GPIO Control 3 (0xc2) */
1724#define RT5645_GP4_PF_MASK (0x1 << 11)
1725#define RT5645_GP4_PF_SFT 11
1726#define RT5645_GP4_PF_IN (0x0 << 11)
1727#define RT5645_GP4_PF_OUT (0x1 << 11)
1728#define RT5645_GP4_OUT_MASK (0x1 << 10)
1729#define RT5645_GP4_OUT_SFT 10
1730#define RT5645_GP4_OUT_LO (0x0 << 10)
1731#define RT5645_GP4_OUT_HI (0x1 << 10)
1732#define RT5645_GP4_P_MASK (0x1 << 9)
1733#define RT5645_GP4_P_SFT 9
1734#define RT5645_GP4_P_NOR (0x0 << 9)
1735#define RT5645_GP4_P_INV (0x1 << 9)
1736#define RT5645_GP3_PF_MASK (0x1 << 8)
1737#define RT5645_GP3_PF_SFT 8
1738#define RT5645_GP3_PF_IN (0x0 << 8)
1739#define RT5645_GP3_PF_OUT (0x1 << 8)
1740#define RT5645_GP3_OUT_MASK (0x1 << 7)
1741#define RT5645_GP3_OUT_SFT 7
1742#define RT5645_GP3_OUT_LO (0x0 << 7)
1743#define RT5645_GP3_OUT_HI (0x1 << 7)
1744#define RT5645_GP3_P_MASK (0x1 << 6)
1745#define RT5645_GP3_P_SFT 6
1746#define RT5645_GP3_P_NOR (0x0 << 6)
1747#define RT5645_GP3_P_INV (0x1 << 6)
1748#define RT5645_GP2_PF_MASK (0x1 << 5)
1749#define RT5645_GP2_PF_SFT 5
1750#define RT5645_GP2_PF_IN (0x0 << 5)
1751#define RT5645_GP2_PF_OUT (0x1 << 5)
1752#define RT5645_GP2_OUT_MASK (0x1 << 4)
1753#define RT5645_GP2_OUT_SFT 4
1754#define RT5645_GP2_OUT_LO (0x0 << 4)
1755#define RT5645_GP2_OUT_HI (0x1 << 4)
1756#define RT5645_GP2_P_MASK (0x1 << 3)
1757#define RT5645_GP2_P_SFT 3
1758#define RT5645_GP2_P_NOR (0x0 << 3)
1759#define RT5645_GP2_P_INV (0x1 << 3)
1760#define RT5645_GP1_PF_MASK (0x1 << 2)
1761#define RT5645_GP1_PF_SFT 2
1762#define RT5645_GP1_PF_IN (0x0 << 2)
1763#define RT5645_GP1_PF_OUT (0x1 << 2)
1764#define RT5645_GP1_OUT_MASK (0x1 << 1)
1765#define RT5645_GP1_OUT_SFT 1
1766#define RT5645_GP1_OUT_LO (0x0 << 1)
1767#define RT5645_GP1_OUT_HI (0x1 << 1)
1768#define RT5645_GP1_P_MASK (0x1)
1769#define RT5645_GP1_P_SFT 0
1770#define RT5645_GP1_P_NOR (0x0)
1771#define RT5645_GP1_P_INV (0x1)
1772
1773/* Programmable Register Array Control 1 (0xc8) */
1774#define RT5645_REG_SEQ_MASK (0xf << 12)
1775#define RT5645_REG_SEQ_SFT 12
1776#define RT5645_SEQ1_ST_MASK (0x1 << 11) /*RO*/
1777#define RT5645_SEQ1_ST_SFT 11
1778#define RT5645_SEQ1_ST_RUN (0x0 << 11)
1779#define RT5645_SEQ1_ST_FIN (0x1 << 11)
1780#define RT5645_SEQ2_ST_MASK (0x1 << 10) /*RO*/
1781#define RT5645_SEQ2_ST_SFT 10
1782#define RT5645_SEQ2_ST_RUN (0x0 << 10)
1783#define RT5645_SEQ2_ST_FIN (0x1 << 10)
1784#define RT5645_REG_LV_MASK (0x1 << 9)
1785#define RT5645_REG_LV_SFT 9
1786#define RT5645_REG_LV_MX (0x0 << 9)
1787#define RT5645_REG_LV_PR (0x1 << 9)
1788#define RT5645_SEQ_2_PT_MASK (0x1 << 8)
1789#define RT5645_SEQ_2_PT_BIT 8
1790#define RT5645_REG_IDX_MASK (0xff)
1791#define RT5645_REG_IDX_SFT 0
1792
1793/* Programmable Register Array Control 2 (0xc9) */
1794#define RT5645_REG_DAT_MASK (0xffff)
1795#define RT5645_REG_DAT_SFT 0
1796
1797/* Programmable Register Array Control 3 (0xca) */
1798#define RT5645_SEQ_DLY_MASK (0xff << 8)
1799#define RT5645_SEQ_DLY_SFT 8
1800#define RT5645_PROG_MASK (0x1 << 7)
1801#define RT5645_PROG_SFT 7
1802#define RT5645_PROG_DIS (0x0 << 7)
1803#define RT5645_PROG_EN (0x1 << 7)
1804#define RT5645_SEQ1_PT_RUN (0x1 << 6)
1805#define RT5645_SEQ1_PT_RUN_BIT 6
1806#define RT5645_SEQ2_PT_RUN (0x1 << 5)
1807#define RT5645_SEQ2_PT_RUN_BIT 5
1808
1809/* Programmable Register Array Control 4 (0xcb) */
1810#define RT5645_SEQ1_START_MASK (0xf << 8)
1811#define RT5645_SEQ1_START_SFT 8
1812#define RT5645_SEQ1_END_MASK (0xf)
1813#define RT5645_SEQ1_END_SFT 0
1814
1815/* Programmable Register Array Control 5 (0xcc) */
1816#define RT5645_SEQ2_START_MASK (0xf << 8)
1817#define RT5645_SEQ2_START_SFT 8
1818#define RT5645_SEQ2_END_MASK (0xf)
1819#define RT5645_SEQ2_END_SFT 0
1820
1821/* Scramble Function (0xcd) */
1822#define RT5645_SCB_KEY_MASK (0xff)
1823#define RT5645_SCB_KEY_SFT 0
1824
1825/* Scramble Control (0xce) */
1826#define RT5645_SCB_SWAP_MASK (0x1 << 15)
1827#define RT5645_SCB_SWAP_SFT 15
1828#define RT5645_SCB_SWAP_DIS (0x0 << 15)
1829#define RT5645_SCB_SWAP_EN (0x1 << 15)
1830#define RT5645_SCB_MASK (0x1 << 14)
1831#define RT5645_SCB_SFT 14
1832#define RT5645_SCB_DIS (0x0 << 14)
1833#define RT5645_SCB_EN (0x1 << 14)
1834
1835/* Baseback Control (0xcf) */
1836#define RT5645_BB_MASK (0x1 << 15)
1837#define RT5645_BB_SFT 15
1838#define RT5645_BB_DIS (0x0 << 15)
1839#define RT5645_BB_EN (0x1 << 15)
1840#define RT5645_BB_CT_MASK (0x7 << 12)
1841#define RT5645_BB_CT_SFT 12
1842#define RT5645_BB_CT_A (0x0 << 12)
1843#define RT5645_BB_CT_B (0x1 << 12)
1844#define RT5645_BB_CT_C (0x2 << 12)
1845#define RT5645_BB_CT_D (0x3 << 12)
1846#define RT5645_M_BB_L_MASK (0x1 << 9)
1847#define RT5645_M_BB_L_SFT 9
1848#define RT5645_M_BB_R_MASK (0x1 << 8)
1849#define RT5645_M_BB_R_SFT 8
1850#define RT5645_M_BB_HPF_L_MASK (0x1 << 7)
1851#define RT5645_M_BB_HPF_L_SFT 7
1852#define RT5645_M_BB_HPF_R_MASK (0x1 << 6)
1853#define RT5645_M_BB_HPF_R_SFT 6
1854#define RT5645_G_BB_BST_MASK (0x3f)
1855#define RT5645_G_BB_BST_SFT 0
1856
1857/* MP3 Plus Control 1 (0xd0) */
1858#define RT5645_M_MP3_L_MASK (0x1 << 15)
1859#define RT5645_M_MP3_L_SFT 15
1860#define RT5645_M_MP3_R_MASK (0x1 << 14)
1861#define RT5645_M_MP3_R_SFT 14
1862#define RT5645_M_MP3_MASK (0x1 << 13)
1863#define RT5645_M_MP3_SFT 13
1864#define RT5645_M_MP3_DIS (0x0 << 13)
1865#define RT5645_M_MP3_EN (0x1 << 13)
1866#define RT5645_EG_MP3_MASK (0x1f << 8)
1867#define RT5645_EG_MP3_SFT 8
1868#define RT5645_MP3_HLP_MASK (0x1 << 7)
1869#define RT5645_MP3_HLP_SFT 7
1870#define RT5645_MP3_HLP_DIS (0x0 << 7)
1871#define RT5645_MP3_HLP_EN (0x1 << 7)
1872#define RT5645_M_MP3_ORG_L_MASK (0x1 << 6)
1873#define RT5645_M_MP3_ORG_L_SFT 6
1874#define RT5645_M_MP3_ORG_R_MASK (0x1 << 5)
1875#define RT5645_M_MP3_ORG_R_SFT 5
1876
1877/* MP3 Plus Control 2 (0xd1) */
1878#define RT5645_MP3_WT_MASK (0x1 << 13)
1879#define RT5645_MP3_WT_SFT 13
1880#define RT5645_MP3_WT_1_4 (0x0 << 13)
1881#define RT5645_MP3_WT_1_2 (0x1 << 13)
1882#define RT5645_OG_MP3_MASK (0x1f << 8)
1883#define RT5645_OG_MP3_SFT 8
1884#define RT5645_HG_MP3_MASK (0x3f)
1885#define RT5645_HG_MP3_SFT 0
1886
1887/* 3D HP Control 1 (0xd2) */
1888#define RT5645_3D_CF_MASK (0x1 << 15)
1889#define RT5645_3D_CF_SFT 15
1890#define RT5645_3D_CF_DIS (0x0 << 15)
1891#define RT5645_3D_CF_EN (0x1 << 15)
1892#define RT5645_3D_HP_MASK (0x1 << 14)
1893#define RT5645_3D_HP_SFT 14
1894#define RT5645_3D_HP_DIS (0x0 << 14)
1895#define RT5645_3D_HP_EN (0x1 << 14)
1896#define RT5645_3D_BT_MASK (0x1 << 13)
1897#define RT5645_3D_BT_SFT 13
1898#define RT5645_3D_BT_DIS (0x0 << 13)
1899#define RT5645_3D_BT_EN (0x1 << 13)
1900#define RT5645_3D_1F_MIX_MASK (0x3 << 11)
1901#define RT5645_3D_1F_MIX_SFT 11
1902#define RT5645_3D_HP_M_MASK (0x1 << 10)
1903#define RT5645_3D_HP_M_SFT 10
1904#define RT5645_3D_HP_M_SUR (0x0 << 10)
1905#define RT5645_3D_HP_M_FRO (0x1 << 10)
1906#define RT5645_M_3D_HRTF_MASK (0x1 << 9)
1907#define RT5645_M_3D_HRTF_SFT 9
1908#define RT5645_M_3D_D2H_MASK (0x1 << 8)
1909#define RT5645_M_3D_D2H_SFT 8
1910#define RT5645_M_3D_D2R_MASK (0x1 << 7)
1911#define RT5645_M_3D_D2R_SFT 7
1912#define RT5645_M_3D_REVB_MASK (0x1 << 6)
1913#define RT5645_M_3D_REVB_SFT 6
1914
1915/* Adjustable high pass filter control 1 (0xd3) */
1916#define RT5645_2ND_HPF_MASK (0x1 << 15)
1917#define RT5645_2ND_HPF_SFT 15
1918#define RT5645_2ND_HPF_DIS (0x0 << 15)
1919#define RT5645_2ND_HPF_EN (0x1 << 15)
1920#define RT5645_HPF_CF_L_MASK (0x7 << 12)
1921#define RT5645_HPF_CF_L_SFT 12
1922#define RT5645_1ST_HPF_MASK (0x1 << 11)
1923#define RT5645_1ST_HPF_SFT 11
1924#define RT5645_1ST_HPF_DIS (0x0 << 11)
1925#define RT5645_1ST_HPF_EN (0x1 << 11)
1926#define RT5645_HPF_CF_R_MASK (0x7 << 8)
1927#define RT5645_HPF_CF_R_SFT 8
1928#define RT5645_ZD_T_MASK (0x3 << 6)
1929#define RT5645_ZD_T_SFT 6
1930#define RT5645_ZD_F_MASK (0x3 << 4)
1931#define RT5645_ZD_F_SFT 4
1932#define RT5645_ZD_F_IM (0x0 << 4)
1933#define RT5645_ZD_F_ZC_IM (0x1 << 4)
1934#define RT5645_ZD_F_ZC_IOD (0x2 << 4)
1935#define RT5645_ZD_F_UN (0x3 << 4)
1936
1937/* HP calibration control and Amp detection (0xd6) */
1938#define RT5645_SI_DAC_MASK (0x1 << 11)
1939#define RT5645_SI_DAC_SFT 11
1940#define RT5645_SI_DAC_AUTO (0x0 << 11)
1941#define RT5645_SI_DAC_TEST (0x1 << 11)
1942#define RT5645_DC_CAL_M_MASK (0x1 << 10)
1943#define RT5645_DC_CAL_M_SFT 10
1944#define RT5645_DC_CAL_M_CAL (0x0 << 10)
1945#define RT5645_DC_CAL_M_NOR (0x1 << 10)
1946#define RT5645_DC_CAL_MASK (0x1 << 9)
1947#define RT5645_DC_CAL_SFT 9
1948#define RT5645_DC_CAL_DIS (0x0 << 9)
1949#define RT5645_DC_CAL_EN (0x1 << 9)
1950#define RT5645_HPD_RCV_MASK (0x7 << 6)
1951#define RT5645_HPD_RCV_SFT 6
1952#define RT5645_HPD_PS_MASK (0x1 << 5)
1953#define RT5645_HPD_PS_SFT 5
1954#define RT5645_HPD_PS_DIS (0x0 << 5)
1955#define RT5645_HPD_PS_EN (0x1 << 5)
1956#define RT5645_CAL_M_MASK (0x1 << 4)
1957#define RT5645_CAL_M_SFT 4
1958#define RT5645_CAL_M_DEP (0x0 << 4)
1959#define RT5645_CAL_M_CAL (0x1 << 4)
1960#define RT5645_CAL_MASK (0x1 << 3)
1961#define RT5645_CAL_SFT 3
1962#define RT5645_CAL_DIS (0x0 << 3)
1963#define RT5645_CAL_EN (0x1 << 3)
1964#define RT5645_CAL_TEST_MASK (0x1 << 2)
1965#define RT5645_CAL_TEST_SFT 2
1966#define RT5645_CAL_TEST_DIS (0x0 << 2)
1967#define RT5645_CAL_TEST_EN (0x1 << 2)
1968#define RT5645_CAL_P_MASK (0x3)
1969#define RT5645_CAL_P_SFT 0
1970#define RT5645_CAL_P_NONE (0x0)
1971#define RT5645_CAL_P_CAL (0x1)
1972#define RT5645_CAL_P_DAC_CAL (0x2)
1973
1974/* Soft volume and zero cross control 1 (0xd9) */
1975#define RT5645_SV_MASK (0x1 << 15)
1976#define RT5645_SV_SFT 15
1977#define RT5645_SV_DIS (0x0 << 15)
1978#define RT5645_SV_EN (0x1 << 15)
1979#define RT5645_SPO_SV_MASK (0x1 << 14)
1980#define RT5645_SPO_SV_SFT 14
1981#define RT5645_SPO_SV_DIS (0x0 << 14)
1982#define RT5645_SPO_SV_EN (0x1 << 14)
1983#define RT5645_OUT_SV_MASK (0x1 << 13)
1984#define RT5645_OUT_SV_SFT 13
1985#define RT5645_OUT_SV_DIS (0x0 << 13)
1986#define RT5645_OUT_SV_EN (0x1 << 13)
1987#define RT5645_HP_SV_MASK (0x1 << 12)
1988#define RT5645_HP_SV_SFT 12
1989#define RT5645_HP_SV_DIS (0x0 << 12)
1990#define RT5645_HP_SV_EN (0x1 << 12)
1991#define RT5645_ZCD_DIG_MASK (0x1 << 11)
1992#define RT5645_ZCD_DIG_SFT 11
1993#define RT5645_ZCD_DIG_DIS (0x0 << 11)
1994#define RT5645_ZCD_DIG_EN (0x1 << 11)
1995#define RT5645_ZCD_MASK (0x1 << 10)
1996#define RT5645_ZCD_SFT 10
1997#define RT5645_ZCD_PD (0x0 << 10)
1998#define RT5645_ZCD_PU (0x1 << 10)
1999#define RT5645_M_ZCD_MASK (0x3f << 4)
2000#define RT5645_M_ZCD_SFT 4
2001#define RT5645_M_ZCD_RM_L (0x1 << 9)
2002#define RT5645_M_ZCD_RM_R (0x1 << 8)
2003#define RT5645_M_ZCD_SM_L (0x1 << 7)
2004#define RT5645_M_ZCD_SM_R (0x1 << 6)
2005#define RT5645_M_ZCD_OM_L (0x1 << 5)
2006#define RT5645_M_ZCD_OM_R (0x1 << 4)
2007#define RT5645_SV_DLY_MASK (0xf)
2008#define RT5645_SV_DLY_SFT 0
2009
2010/* Soft volume and zero cross control 2 (0xda) */
2011#define RT5645_ZCD_HP_MASK (0x1 << 15)
2012#define RT5645_ZCD_HP_SFT 15
2013#define RT5645_ZCD_HP_DIS (0x0 << 15)
2014#define RT5645_ZCD_HP_EN (0x1 << 15)
2015
2016
2017/* Codec Private Register definition */
2018/* 3D Speaker Control (0x63) */
2019#define RT5645_3D_SPK_MASK (0x1 << 15)
2020#define RT5645_3D_SPK_SFT 15
2021#define RT5645_3D_SPK_DIS (0x0 << 15)
2022#define RT5645_3D_SPK_EN (0x1 << 15)
2023#define RT5645_3D_SPK_M_MASK (0x3 << 13)
2024#define RT5645_3D_SPK_M_SFT 13
2025#define RT5645_3D_SPK_CG_MASK (0x1f << 8)
2026#define RT5645_3D_SPK_CG_SFT 8
2027#define RT5645_3D_SPK_SG_MASK (0x1f)
2028#define RT5645_3D_SPK_SG_SFT 0
2029
2030/* Wind Noise Detection Control 1 (0x6c) */
2031#define RT5645_WND_MASK (0x1 << 15)
2032#define RT5645_WND_SFT 15
2033#define RT5645_WND_DIS (0x0 << 15)
2034#define RT5645_WND_EN (0x1 << 15)
2035
2036/* Wind Noise Detection Control 2 (0x6d) */
2037#define RT5645_WND_FC_NW_MASK (0x3f << 10)
2038#define RT5645_WND_FC_NW_SFT 10
2039#define RT5645_WND_FC_WK_MASK (0x3f << 4)
2040#define RT5645_WND_FC_WK_SFT 4
2041
2042/* Wind Noise Detection Control 3 (0x6e) */
2043#define RT5645_HPF_FC_MASK (0x3f << 6)
2044#define RT5645_HPF_FC_SFT 6
2045#define RT5645_WND_FC_ST_MASK (0x3f)
2046#define RT5645_WND_FC_ST_SFT 0
2047
2048/* Wind Noise Detection Control 4 (0x6f) */
2049#define RT5645_WND_TH_LO_MASK (0x3ff)
2050#define RT5645_WND_TH_LO_SFT 0
2051
2052/* Wind Noise Detection Control 5 (0x70) */
2053#define RT5645_WND_TH_HI_MASK (0x3ff)
2054#define RT5645_WND_TH_HI_SFT 0
2055
2056/* Wind Noise Detection Control 8 (0x73) */
2057#define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2058#define RT5645_WND_WIND_SFT 13
2059#define RT5645_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2060#define RT5645_WND_STRONG_SFT 12
2061enum {
2062 RT5645_NO_WIND,
2063 RT5645_BREEZE,
2064 RT5645_STORM,
2065};
2066
2067/* Dipole Speaker Interface (0x75) */
2068#define RT5645_DP_ATT_MASK (0x3 << 14)
2069#define RT5645_DP_ATT_SFT 14
2070#define RT5645_DP_SPK_MASK (0x1 << 10)
2071#define RT5645_DP_SPK_SFT 10
2072#define RT5645_DP_SPK_DIS (0x0 << 10)
2073#define RT5645_DP_SPK_EN (0x1 << 10)
2074
2075/* EQ Pre Volume Control (0xb3) */
2076#define RT5645_EQ_PRE_VOL_MASK (0xffff)
2077#define RT5645_EQ_PRE_VOL_SFT 0
2078
2079/* EQ Post Volume Control (0xb4) */
2080#define RT5645_EQ_PST_VOL_MASK (0xffff)
2081#define RT5645_EQ_PST_VOL_SFT 0
2082
2083/* Jack Detect Control 3 (0xf8) */
2084#define RT5645_CMP_MIC_IN_DET_MASK (0x7 << 12)
2085#define RT5645_JD_CBJ_EN (0x1 << 7)
2086#define RT5645_JD_CBJ_POL (0x1 << 6)
2087#define RT5645_JD_TRI_CBJ_SEL_MASK (0x7 << 3)
2088#define RT5645_JD_TRI_CBJ_SEL_SFT (3)
2089#define RT5645_JD_TRI_HPO_SEL_MASK (0x7)
2090#define RT5645_JD_TRI_HPO_SEL_SFT (0)
2091#define RT5645_JD_F_GPIO_JD1 (0x0)
2092#define RT5645_JD_F_JD1_1 (0x1)
2093#define RT5645_JD_F_JD1_2 (0x2)
2094#define RT5645_JD_F_JD2 (0x3)
2095#define RT5645_JD_F_JD3 (0x4)
2096#define RT5645_JD_F_GPIO_JD2 (0x5)
2097#define RT5645_JD_F_MX0B_12 (0x6)
2098
2099/* Digital Misc Control (0xfa) */
2100#define RT5645_RST_DSP (0x1 << 13)
2101#define RT5645_IF1_ADC1_IN1_SEL (0x1 << 12)
2102#define RT5645_IF1_ADC1_IN1_SFT 12
2103#define RT5645_IF1_ADC1_IN2_SEL (0x1 << 11)
2104#define RT5645_IF1_ADC1_IN2_SFT 11
2105#define RT5645_IF1_ADC2_IN1_SEL (0x1 << 10)
2106#define RT5645_IF1_ADC2_IN1_SFT 10
2107#define RT5645_DIG_GATE_CTRL 0x1
2108
2109/* General Control2 (0xfb) */
2110#define RT5645_RXDC_SRC_MASK (0x1 << 7)
2111#define RT5645_RXDC_SRC_STO (0x0 << 7)
2112#define RT5645_RXDC_SRC_MONO (0x1 << 7)
2113#define RT5645_RXDC_SRC_SFT (7)
2114#define RT5645_RXDP2_SEL_MASK (0x1 << 3)
2115#define RT5645_RXDP2_SEL_IF2 (0x0 << 3)
2116#define RT5645_RXDP2_SEL_ADC (0x1 << 3)
2117#define RT5645_RXDP2_SEL_SFT (3)
2118
2119
2120/* Vendor ID (0xfd) */
2121#define RT5645_VER_C 0x2
2122#define RT5645_VER_D 0x3
2123
2124
2125/* Volume Rescale */
2126#define RT5645_VOL_RSCL_MAX 0x27
2127#define RT5645_VOL_RSCL_RANGE 0x1F
2128/* Debug String Length */
2129#define RT5645_REG_DISP_LEN 23
2130
2131
2132/* System Clock Source */
2133enum {
2134 RT5645_SCLK_S_MCLK,
2135 RT5645_SCLK_S_PLL1,
2136 RT5645_SCLK_S_RCCLK,
2137};
2138
2139/* PLL1 Source */
2140enum {
2141 RT5645_PLL1_S_MCLK,
2142 RT5645_PLL1_S_BCLK1,
2143 RT5645_PLL1_S_BCLK2,
2144};
2145
2146enum {
2147 RT5645_AIF1,
2148 RT5645_AIF2,
2149 RT5645_AIFS,
2150};
2151
2152enum {
2153 RT5645_DMIC_DATA_IN2P,
2154 RT5645_DMIC_DATA_GPIO6,
2155 RT5645_DMIC_DATA_GPIO10,
2156 RT5645_DMIC_DATA_GPIO12,
2157};
2158
2159enum {
2160 RT5645_DMIC_DATA_IN2N,
2161 RT5645_DMIC_DATA_GPIO5,
2162 RT5645_DMIC_DATA_GPIO11,
2163};
2164
2165struct rt5645_priv {
2166 struct snd_soc_codec *codec;
2167 struct rt5645_platform_data pdata;
2168 struct regmap *regmap;
2169
2170 int sysclk;
2171 int sysclk_src;
2172 int lrck[RT5645_AIFS];
2173 int bclk[RT5645_AIFS];
2174 int master[RT5645_AIFS];
2175
2176 int pll_src;
2177 int pll_in;
2178 int pll_out;
2179};
2180
2181#endif /* __RT5645_H__ */
diff --git a/sound/soc/codecs/rt5651.c b/sound/soc/codecs/rt5651.c
new file mode 100644
index 000000000000..ea4b1c652a26
--- /dev/null
+++ b/sound/soc/codecs/rt5651.c
@@ -0,0 +1,1818 @@
1/*
2 * rt5651.c -- RT5651 ALSA SoC audio codec driver
3 *
4 * Copyright 2014 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/regmap.h>
19#include <linux/platform_device.h>
20#include <linux/spi/spi.h>
21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
25#include <sound/soc-dapm.h>
26#include <sound/initval.h>
27#include <sound/tlv.h>
28
29#include "rl6231.h"
30#include "rt5651.h"
31
32#define RT5651_DEVICE_ID_VALUE 0x6281
33
34#define RT5651_PR_RANGE_BASE (0xff + 1)
35#define RT5651_PR_SPACING 0x100
36
37#define RT5651_PR_BASE (RT5651_PR_RANGE_BASE + (0 * RT5651_PR_SPACING))
38
39static const struct regmap_range_cfg rt5651_ranges[] = {
40 { .name = "PR", .range_min = RT5651_PR_BASE,
41 .range_max = RT5651_PR_BASE + 0xb4,
42 .selector_reg = RT5651_PRIV_INDEX,
43 .selector_mask = 0xff,
44 .selector_shift = 0x0,
45 .window_start = RT5651_PRIV_DATA,
46 .window_len = 0x1, },
47};
48
49static struct reg_default init_list[] = {
50 {RT5651_PR_BASE + 0x3d, 0x3e00},
51};
52
53static const struct reg_default rt5651_reg[] = {
54 { 0x00, 0x0000 },
55 { 0x02, 0xc8c8 },
56 { 0x03, 0xc8c8 },
57 { 0x05, 0x0000 },
58 { 0x0d, 0x0000 },
59 { 0x0e, 0x0000 },
60 { 0x0f, 0x0808 },
61 { 0x10, 0x0808 },
62 { 0x19, 0xafaf },
63 { 0x1a, 0xafaf },
64 { 0x1b, 0x0c00 },
65 { 0x1c, 0x2f2f },
66 { 0x1d, 0x2f2f },
67 { 0x1e, 0x0000 },
68 { 0x27, 0x7860 },
69 { 0x28, 0x7070 },
70 { 0x29, 0x8080 },
71 { 0x2a, 0x5252 },
72 { 0x2b, 0x5454 },
73 { 0x2f, 0x0000 },
74 { 0x30, 0x5000 },
75 { 0x3b, 0x0000 },
76 { 0x3c, 0x006f },
77 { 0x3d, 0x0000 },
78 { 0x3e, 0x006f },
79 { 0x45, 0x6000 },
80 { 0x4d, 0x0000 },
81 { 0x4e, 0x0000 },
82 { 0x4f, 0x0279 },
83 { 0x50, 0x0000 },
84 { 0x51, 0x0000 },
85 { 0x52, 0x0279 },
86 { 0x53, 0xf000 },
87 { 0x61, 0x0000 },
88 { 0x62, 0x0000 },
89 { 0x63, 0x00c0 },
90 { 0x64, 0x0000 },
91 { 0x65, 0x0000 },
92 { 0x66, 0x0000 },
93 { 0x70, 0x8000 },
94 { 0x71, 0x8000 },
95 { 0x73, 0x1104 },
96 { 0x74, 0x0c00 },
97 { 0x75, 0x1400 },
98 { 0x77, 0x0c00 },
99 { 0x78, 0x4000 },
100 { 0x79, 0x0123 },
101 { 0x80, 0x0000 },
102 { 0x81, 0x0000 },
103 { 0x82, 0x0000 },
104 { 0x83, 0x0800 },
105 { 0x84, 0x0000 },
106 { 0x85, 0x0008 },
107 { 0x89, 0x0000 },
108 { 0x8e, 0x0004 },
109 { 0x8f, 0x1100 },
110 { 0x90, 0x0000 },
111 { 0x93, 0x2000 },
112 { 0x94, 0x0200 },
113 { 0xb0, 0x2080 },
114 { 0xb1, 0x0000 },
115 { 0xb4, 0x2206 },
116 { 0xb5, 0x1f00 },
117 { 0xb6, 0x0000 },
118 { 0xbb, 0x0000 },
119 { 0xbc, 0x0000 },
120 { 0xbd, 0x0000 },
121 { 0xbe, 0x0000 },
122 { 0xbf, 0x0000 },
123 { 0xc0, 0x0400 },
124 { 0xc1, 0x0000 },
125 { 0xc2, 0x0000 },
126 { 0xcf, 0x0013 },
127 { 0xd0, 0x0680 },
128 { 0xd1, 0x1c17 },
129 { 0xd3, 0xb320 },
130 { 0xd9, 0x0809 },
131 { 0xfa, 0x0010 },
132 { 0xfe, 0x10ec },
133 { 0xff, 0x6281 },
134};
135
136static bool rt5651_volatile_register(struct device *dev, unsigned int reg)
137{
138 int i;
139
140 for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
141 if ((reg >= rt5651_ranges[i].window_start &&
142 reg <= rt5651_ranges[i].window_start +
143 rt5651_ranges[i].window_len) ||
144 (reg >= rt5651_ranges[i].range_min &&
145 reg <= rt5651_ranges[i].range_max)) {
146 return true;
147 }
148 }
149
150 switch (reg) {
151 case RT5651_RESET:
152 case RT5651_PRIV_DATA:
153 case RT5651_EQ_CTRL1:
154 case RT5651_ALC_1:
155 case RT5651_IRQ_CTRL2:
156 case RT5651_INT_IRQ_ST:
157 case RT5651_PGM_REG_ARR1:
158 case RT5651_PGM_REG_ARR3:
159 case RT5651_VENDOR_ID:
160 case RT5651_DEVICE_ID:
161 return true;
162 default:
163 return false;
164 }
165}
166
167static bool rt5651_readable_register(struct device *dev, unsigned int reg)
168{
169 int i;
170
171 for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
172 if ((reg >= rt5651_ranges[i].window_start &&
173 reg <= rt5651_ranges[i].window_start +
174 rt5651_ranges[i].window_len) ||
175 (reg >= rt5651_ranges[i].range_min &&
176 reg <= rt5651_ranges[i].range_max)) {
177 return true;
178 }
179 }
180
181 switch (reg) {
182 case RT5651_RESET:
183 case RT5651_VERSION_ID:
184 case RT5651_VENDOR_ID:
185 case RT5651_DEVICE_ID:
186 case RT5651_HP_VOL:
187 case RT5651_LOUT_CTRL1:
188 case RT5651_LOUT_CTRL2:
189 case RT5651_IN1_IN2:
190 case RT5651_IN3:
191 case RT5651_INL1_INR1_VOL:
192 case RT5651_INL2_INR2_VOL:
193 case RT5651_DAC1_DIG_VOL:
194 case RT5651_DAC2_DIG_VOL:
195 case RT5651_DAC2_CTRL:
196 case RT5651_ADC_DIG_VOL:
197 case RT5651_ADC_DATA:
198 case RT5651_ADC_BST_VOL:
199 case RT5651_STO1_ADC_MIXER:
200 case RT5651_STO2_ADC_MIXER:
201 case RT5651_AD_DA_MIXER:
202 case RT5651_STO_DAC_MIXER:
203 case RT5651_DD_MIXER:
204 case RT5651_DIG_INF_DATA:
205 case RT5651_PDM_CTL:
206 case RT5651_REC_L1_MIXER:
207 case RT5651_REC_L2_MIXER:
208 case RT5651_REC_R1_MIXER:
209 case RT5651_REC_R2_MIXER:
210 case RT5651_HPO_MIXER:
211 case RT5651_OUT_L1_MIXER:
212 case RT5651_OUT_L2_MIXER:
213 case RT5651_OUT_L3_MIXER:
214 case RT5651_OUT_R1_MIXER:
215 case RT5651_OUT_R2_MIXER:
216 case RT5651_OUT_R3_MIXER:
217 case RT5651_LOUT_MIXER:
218 case RT5651_PWR_DIG1:
219 case RT5651_PWR_DIG2:
220 case RT5651_PWR_ANLG1:
221 case RT5651_PWR_ANLG2:
222 case RT5651_PWR_MIXER:
223 case RT5651_PWR_VOL:
224 case RT5651_PRIV_INDEX:
225 case RT5651_PRIV_DATA:
226 case RT5651_I2S1_SDP:
227 case RT5651_I2S2_SDP:
228 case RT5651_ADDA_CLK1:
229 case RT5651_ADDA_CLK2:
230 case RT5651_DMIC:
231 case RT5651_TDM_CTL_1:
232 case RT5651_TDM_CTL_2:
233 case RT5651_TDM_CTL_3:
234 case RT5651_GLB_CLK:
235 case RT5651_PLL_CTRL1:
236 case RT5651_PLL_CTRL2:
237 case RT5651_PLL_MODE_1:
238 case RT5651_PLL_MODE_2:
239 case RT5651_PLL_MODE_3:
240 case RT5651_PLL_MODE_4:
241 case RT5651_PLL_MODE_5:
242 case RT5651_PLL_MODE_6:
243 case RT5651_PLL_MODE_7:
244 case RT5651_DEPOP_M1:
245 case RT5651_DEPOP_M2:
246 case RT5651_DEPOP_M3:
247 case RT5651_CHARGE_PUMP:
248 case RT5651_MICBIAS:
249 case RT5651_A_JD_CTL1:
250 case RT5651_EQ_CTRL1:
251 case RT5651_EQ_CTRL2:
252 case RT5651_ALC_1:
253 case RT5651_ALC_2:
254 case RT5651_ALC_3:
255 case RT5651_JD_CTRL1:
256 case RT5651_JD_CTRL2:
257 case RT5651_IRQ_CTRL1:
258 case RT5651_IRQ_CTRL2:
259 case RT5651_INT_IRQ_ST:
260 case RT5651_GPIO_CTRL1:
261 case RT5651_GPIO_CTRL2:
262 case RT5651_GPIO_CTRL3:
263 case RT5651_PGM_REG_ARR1:
264 case RT5651_PGM_REG_ARR2:
265 case RT5651_PGM_REG_ARR3:
266 case RT5651_PGM_REG_ARR4:
267 case RT5651_PGM_REG_ARR5:
268 case RT5651_SCB_FUNC:
269 case RT5651_SCB_CTRL:
270 case RT5651_BASE_BACK:
271 case RT5651_MP3_PLUS1:
272 case RT5651_MP3_PLUS2:
273 case RT5651_ADJ_HPF_CTRL1:
274 case RT5651_ADJ_HPF_CTRL2:
275 case RT5651_HP_CALIB_AMP_DET:
276 case RT5651_HP_CALIB2:
277 case RT5651_SV_ZCD1:
278 case RT5651_SV_ZCD2:
279 case RT5651_D_MISC:
280 case RT5651_DUMMY2:
281 case RT5651_DUMMY3:
282 return true;
283 default:
284 return false;
285 }
286}
287
288static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
289static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
290static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
291static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
292static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
293
294/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
295static unsigned int bst_tlv[] = {
296 TLV_DB_RANGE_HEAD(7),
297 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
298 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
299 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
300 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
301 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
302 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
303 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
304};
305
306/* Interface data select */
307static const char * const rt5651_data_select[] = {
308 "Normal", "Swap", "left copy to right", "right copy to left"};
309
310static SOC_ENUM_SINGLE_DECL(rt5651_if2_dac_enum, RT5651_DIG_INF_DATA,
311 RT5651_IF2_DAC_SEL_SFT, rt5651_data_select);
312
313static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_enum, RT5651_DIG_INF_DATA,
314 RT5651_IF2_ADC_SEL_SFT, rt5651_data_select);
315
316static const struct snd_kcontrol_new rt5651_snd_controls[] = {
317 /* Headphone Output Volume */
318 SOC_DOUBLE_TLV("HP Playback Volume", RT5651_HP_VOL,
319 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
320 /* OUTPUT Control */
321 SOC_DOUBLE_TLV("OUT Playback Volume", RT5651_LOUT_CTRL1,
322 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
323
324 /* DAC Digital Volume */
325 SOC_DOUBLE("DAC2 Playback Switch", RT5651_DAC2_CTRL,
326 RT5651_M_DAC_L2_VOL_SFT, RT5651_M_DAC_R2_VOL_SFT, 1, 1),
327 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5651_DAC1_DIG_VOL,
328 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
329 175, 0, dac_vol_tlv),
330 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5651_DAC2_DIG_VOL,
331 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
332 175, 0, dac_vol_tlv),
333 /* IN1/IN2 Control */
334 SOC_SINGLE_TLV("IN1 Boost", RT5651_IN1_IN2,
335 RT5651_BST_SFT1, 8, 0, bst_tlv),
336 SOC_SINGLE_TLV("IN2 Boost", RT5651_IN1_IN2,
337 RT5651_BST_SFT2, 8, 0, bst_tlv),
338 /* INL/INR Volume Control */
339 SOC_DOUBLE_TLV("IN Capture Volume", RT5651_INL1_INR1_VOL,
340 RT5651_INL_VOL_SFT, RT5651_INR_VOL_SFT,
341 31, 1, in_vol_tlv),
342 /* ADC Digital Volume Control */
343 SOC_DOUBLE("ADC Capture Switch", RT5651_ADC_DIG_VOL,
344 RT5651_L_MUTE_SFT, RT5651_R_MUTE_SFT, 1, 1),
345 SOC_DOUBLE_TLV("ADC Capture Volume", RT5651_ADC_DIG_VOL,
346 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
347 127, 0, adc_vol_tlv),
348 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5651_ADC_DATA,
349 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
350 127, 0, adc_vol_tlv),
351 /* ADC Boost Volume Control */
352 SOC_DOUBLE_TLV("ADC Boost Gain", RT5651_ADC_BST_VOL,
353 RT5651_ADC_L_BST_SFT, RT5651_ADC_R_BST_SFT,
354 3, 0, adc_bst_tlv),
355
356 /* ASRC */
357 SOC_SINGLE("IF1 ASRC Switch", RT5651_PLL_MODE_1,
358 RT5651_STO1_T_SFT, 1, 0),
359 SOC_SINGLE("IF2 ASRC Switch", RT5651_PLL_MODE_1,
360 RT5651_STO2_T_SFT, 1, 0),
361 SOC_SINGLE("DMIC ASRC Switch", RT5651_PLL_MODE_1,
362 RT5651_DMIC_1_M_SFT, 1, 0),
363
364 SOC_ENUM("ADC IF2 Data Switch", rt5651_if2_adc_enum),
365 SOC_ENUM("DAC IF2 Data Switch", rt5651_if2_dac_enum),
366};
367
368/**
369 * set_dmic_clk - Set parameter of dmic.
370 *
371 * @w: DAPM widget.
372 * @kcontrol: The kcontrol of this widget.
373 * @event: Event id.
374 *
375 */
376static int set_dmic_clk(struct snd_soc_dapm_widget *w,
377 struct snd_kcontrol *kcontrol, int event)
378{
379 struct snd_soc_codec *codec = w->codec;
380 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
381 int idx = -EINVAL;
382
383 idx = rl6231_calc_dmic_clk(rt5651->sysclk);
384
385 if (idx < 0)
386 dev_err(codec->dev, "Failed to set DMIC clock\n");
387 else
388 snd_soc_update_bits(codec, RT5651_DMIC, RT5651_DMIC_CLK_MASK,
389 idx << RT5651_DMIC_CLK_SFT);
390
391 return idx;
392}
393
394static int is_sysclk_from_pll(struct snd_soc_dapm_widget *source,
395 struct snd_soc_dapm_widget *sink)
396{
397 unsigned int val;
398
399 val = snd_soc_read(source->codec, RT5651_GLB_CLK);
400 val &= RT5651_SCLK_SRC_MASK;
401 if (val == RT5651_SCLK_SRC_PLL1)
402 return 1;
403 else
404 return 0;
405}
406
407/* Digital Mixer */
408static const struct snd_kcontrol_new rt5651_sto1_adc_l_mix[] = {
409 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
410 RT5651_M_STO1_ADC_L1_SFT, 1, 1),
411 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
412 RT5651_M_STO1_ADC_L2_SFT, 1, 1),
413};
414
415static const struct snd_kcontrol_new rt5651_sto1_adc_r_mix[] = {
416 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
417 RT5651_M_STO1_ADC_R1_SFT, 1, 1),
418 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
419 RT5651_M_STO1_ADC_R2_SFT, 1, 1),
420};
421
422static const struct snd_kcontrol_new rt5651_sto2_adc_l_mix[] = {
423 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
424 RT5651_M_STO2_ADC_L1_SFT, 1, 1),
425 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
426 RT5651_M_STO2_ADC_L2_SFT, 1, 1),
427};
428
429static const struct snd_kcontrol_new rt5651_sto2_adc_r_mix[] = {
430 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
431 RT5651_M_STO2_ADC_R1_SFT, 1, 1),
432 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
433 RT5651_M_STO2_ADC_R2_SFT, 1, 1),
434};
435
436static const struct snd_kcontrol_new rt5651_dac_l_mix[] = {
437 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
438 RT5651_M_ADCMIX_L_SFT, 1, 1),
439 SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
440 RT5651_M_IF1_DAC_L_SFT, 1, 1),
441};
442
443static const struct snd_kcontrol_new rt5651_dac_r_mix[] = {
444 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
445 RT5651_M_ADCMIX_R_SFT, 1, 1),
446 SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
447 RT5651_M_IF1_DAC_R_SFT, 1, 1),
448};
449
450static const struct snd_kcontrol_new rt5651_sto_dac_l_mix[] = {
451 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
452 RT5651_M_DAC_L1_MIXL_SFT, 1, 1),
453 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_STO_DAC_MIXER,
454 RT5651_M_DAC_L2_MIXL_SFT, 1, 1),
455 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
456 RT5651_M_DAC_R1_MIXL_SFT, 1, 1),
457};
458
459static const struct snd_kcontrol_new rt5651_sto_dac_r_mix[] = {
460 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
461 RT5651_M_DAC_R1_MIXR_SFT, 1, 1),
462 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_STO_DAC_MIXER,
463 RT5651_M_DAC_R2_MIXR_SFT, 1, 1),
464 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
465 RT5651_M_DAC_L1_MIXR_SFT, 1, 1),
466};
467
468static const struct snd_kcontrol_new rt5651_dd_dac_l_mix[] = {
469 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_DD_MIXER,
470 RT5651_M_STO_DD_L1_SFT, 1, 1),
471 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
472 RT5651_M_STO_DD_L2_SFT, 1, 1),
473 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
474 RT5651_M_STO_DD_R2_L_SFT, 1, 1),
475};
476
477static const struct snd_kcontrol_new rt5651_dd_dac_r_mix[] = {
478 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_DD_MIXER,
479 RT5651_M_STO_DD_R1_SFT, 1, 1),
480 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
481 RT5651_M_STO_DD_R2_SFT, 1, 1),
482 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
483 RT5651_M_STO_DD_L2_R_SFT, 1, 1),
484};
485
486/* Analog Input Mixer */
487static const struct snd_kcontrol_new rt5651_rec_l_mix[] = {
488 SOC_DAPM_SINGLE("INL1 Switch", RT5651_REC_L2_MIXER,
489 RT5651_M_IN1_L_RM_L_SFT, 1, 1),
490 SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_L2_MIXER,
491 RT5651_M_BST3_RM_L_SFT, 1, 1),
492 SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_L2_MIXER,
493 RT5651_M_BST2_RM_L_SFT, 1, 1),
494 SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_L2_MIXER,
495 RT5651_M_BST1_RM_L_SFT, 1, 1),
496};
497
498static const struct snd_kcontrol_new rt5651_rec_r_mix[] = {
499 SOC_DAPM_SINGLE("INR1 Switch", RT5651_REC_R2_MIXER,
500 RT5651_M_IN1_R_RM_R_SFT, 1, 1),
501 SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_R2_MIXER,
502 RT5651_M_BST3_RM_R_SFT, 1, 1),
503 SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_R2_MIXER,
504 RT5651_M_BST2_RM_R_SFT, 1, 1),
505 SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_R2_MIXER,
506 RT5651_M_BST1_RM_R_SFT, 1, 1),
507};
508
509/* Analog Output Mixer */
510
511static const struct snd_kcontrol_new rt5651_out_l_mix[] = {
512 SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_L3_MIXER,
513 RT5651_M_BST1_OM_L_SFT, 1, 1),
514 SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_L3_MIXER,
515 RT5651_M_BST2_OM_L_SFT, 1, 1),
516 SOC_DAPM_SINGLE("INL1 Switch", RT5651_OUT_L3_MIXER,
517 RT5651_M_IN1_L_OM_L_SFT, 1, 1),
518 SOC_DAPM_SINGLE("REC MIXL Switch", RT5651_OUT_L3_MIXER,
519 RT5651_M_RM_L_OM_L_SFT, 1, 1),
520 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_OUT_L3_MIXER,
521 RT5651_M_DAC_L1_OM_L_SFT, 1, 1),
522};
523
524static const struct snd_kcontrol_new rt5651_out_r_mix[] = {
525 SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_R3_MIXER,
526 RT5651_M_BST2_OM_R_SFT, 1, 1),
527 SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_R3_MIXER,
528 RT5651_M_BST1_OM_R_SFT, 1, 1),
529 SOC_DAPM_SINGLE("INR1 Switch", RT5651_OUT_R3_MIXER,
530 RT5651_M_IN1_R_OM_R_SFT, 1, 1),
531 SOC_DAPM_SINGLE("REC MIXR Switch", RT5651_OUT_R3_MIXER,
532 RT5651_M_RM_R_OM_R_SFT, 1, 1),
533 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_OUT_R3_MIXER,
534 RT5651_M_DAC_R1_OM_R_SFT, 1, 1),
535};
536
537static const struct snd_kcontrol_new rt5651_hpo_mix[] = {
538 SOC_DAPM_SINGLE("HPO MIX DAC1 Switch", RT5651_HPO_MIXER,
539 RT5651_M_DAC1_HM_SFT, 1, 1),
540 SOC_DAPM_SINGLE("HPO MIX HPVOL Switch", RT5651_HPO_MIXER,
541 RT5651_M_HPVOL_HM_SFT, 1, 1),
542};
543
544static const struct snd_kcontrol_new rt5651_lout_mix[] = {
545 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_LOUT_MIXER,
546 RT5651_M_DAC_L1_LM_SFT, 1, 1),
547 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_LOUT_MIXER,
548 RT5651_M_DAC_R1_LM_SFT, 1, 1),
549 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5651_LOUT_MIXER,
550 RT5651_M_OV_L_LM_SFT, 1, 1),
551 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5651_LOUT_MIXER,
552 RT5651_M_OV_R_LM_SFT, 1, 1),
553};
554
555static const struct snd_kcontrol_new outvol_l_control =
556 SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
557 RT5651_VOL_L_SFT, 1, 1);
558
559static const struct snd_kcontrol_new outvol_r_control =
560 SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
561 RT5651_VOL_R_SFT, 1, 1);
562
563static const struct snd_kcontrol_new lout_l_mute_control =
564 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
565 RT5651_L_MUTE_SFT, 1, 1);
566
567static const struct snd_kcontrol_new lout_r_mute_control =
568 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
569 RT5651_R_MUTE_SFT, 1, 1);
570
571static const struct snd_kcontrol_new hpovol_l_control =
572 SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
573 RT5651_VOL_L_SFT, 1, 1);
574
575static const struct snd_kcontrol_new hpovol_r_control =
576 SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
577 RT5651_VOL_R_SFT, 1, 1);
578
579static const struct snd_kcontrol_new hpo_l_mute_control =
580 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
581 RT5651_L_MUTE_SFT, 1, 1);
582
583static const struct snd_kcontrol_new hpo_r_mute_control =
584 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
585 RT5651_R_MUTE_SFT, 1, 1);
586
587/* INL/R source */
588static const char * const rt5651_inl_src[] = {"IN2P", "HPOVOLLP"};
589
590static SOC_ENUM_SINGLE_DECL(
591 rt5651_inl_enum, RT5651_INL1_INR1_VOL,
592 RT5651_INL_SEL_SFT, rt5651_inl_src);
593
594static const struct snd_kcontrol_new rt5651_inl1_mux =
595 SOC_DAPM_ENUM("INL1 source", rt5651_inl_enum);
596
597static const char * const rt5651_inr1_src[] = {"IN2N", "HPOVOLRP"};
598
599static SOC_ENUM_SINGLE_DECL(
600 rt5651_inr1_enum, RT5651_INL1_INR1_VOL,
601 RT5651_INR_SEL_SFT, rt5651_inr1_src);
602
603static const struct snd_kcontrol_new rt5651_inr1_mux =
604 SOC_DAPM_ENUM("INR1 source", rt5651_inr1_enum);
605
606static const char * const rt5651_inl2_src[] = {"IN3P", "OUTVOLLP"};
607
608static SOC_ENUM_SINGLE_DECL(
609 rt5651_inl2_enum, RT5651_INL2_INR2_VOL,
610 RT5651_INL_SEL_SFT, rt5651_inl2_src);
611
612static const struct snd_kcontrol_new rt5651_inl2_mux =
613 SOC_DAPM_ENUM("INL2 source", rt5651_inl2_enum);
614
615static const char * const rt5651_inr2_src[] = {"IN3N", "OUTVOLRP"};
616
617static SOC_ENUM_SINGLE_DECL(
618 rt5651_inr2_enum, RT5651_INL2_INR2_VOL,
619 RT5651_INR_SEL_SFT, rt5651_inr2_src);
620
621static const struct snd_kcontrol_new rt5651_inr2_mux =
622 SOC_DAPM_ENUM("INR2 source", rt5651_inr2_enum);
623
624
625/* Stereo ADC source */
626static const char * const rt5651_stereo1_adc1_src[] = {"DD MIX", "ADC"};
627
628static SOC_ENUM_SINGLE_DECL(
629 rt5651_stereo1_adc1_enum, RT5651_STO1_ADC_MIXER,
630 RT5651_STO1_ADC_1_SRC_SFT, rt5651_stereo1_adc1_src);
631
632static const struct snd_kcontrol_new rt5651_sto1_adc_l1_mux =
633 SOC_DAPM_ENUM("Stereo1 ADC L1 source", rt5651_stereo1_adc1_enum);
634
635static const struct snd_kcontrol_new rt5651_sto1_adc_r1_mux =
636 SOC_DAPM_ENUM("Stereo1 ADC R1 source", rt5651_stereo1_adc1_enum);
637
638static const char * const rt5651_stereo1_adc2_src[] = {"DMIC", "DD MIX"};
639
640static SOC_ENUM_SINGLE_DECL(
641 rt5651_stereo1_adc2_enum, RT5651_STO1_ADC_MIXER,
642 RT5651_STO1_ADC_2_SRC_SFT, rt5651_stereo1_adc2_src);
643
644static const struct snd_kcontrol_new rt5651_sto1_adc_l2_mux =
645 SOC_DAPM_ENUM("Stereo1 ADC L2 source", rt5651_stereo1_adc2_enum);
646
647static const struct snd_kcontrol_new rt5651_sto1_adc_r2_mux =
648 SOC_DAPM_ENUM("Stereo1 ADC R2 source", rt5651_stereo1_adc2_enum);
649
650/* Mono ADC source */
651static const char * const rt5651_sto2_adc_l1_src[] = {"DD MIXL", "ADCL"};
652
653static SOC_ENUM_SINGLE_DECL(
654 rt5651_sto2_adc_l1_enum, RT5651_STO1_ADC_MIXER,
655 RT5651_STO2_ADC_L1_SRC_SFT, rt5651_sto2_adc_l1_src);
656
657static const struct snd_kcontrol_new rt5651_sto2_adc_l1_mux =
658 SOC_DAPM_ENUM("Stereo2 ADC1 left source", rt5651_sto2_adc_l1_enum);
659
660static const char * const rt5651_sto2_adc_l2_src[] = {"DMIC L", "DD MIXL"};
661
662static SOC_ENUM_SINGLE_DECL(
663 rt5651_sto2_adc_l2_enum, RT5651_STO1_ADC_MIXER,
664 RT5651_STO2_ADC_L2_SRC_SFT, rt5651_sto2_adc_l2_src);
665
666static const struct snd_kcontrol_new rt5651_sto2_adc_l2_mux =
667 SOC_DAPM_ENUM("Stereo2 ADC2 left source", rt5651_sto2_adc_l2_enum);
668
669static const char * const rt5651_sto2_adc_r1_src[] = {"DD MIXR", "ADCR"};
670
671static SOC_ENUM_SINGLE_DECL(
672 rt5651_sto2_adc_r1_enum, RT5651_STO1_ADC_MIXER,
673 RT5651_STO2_ADC_R1_SRC_SFT, rt5651_sto2_adc_r1_src);
674
675static const struct snd_kcontrol_new rt5651_sto2_adc_r1_mux =
676 SOC_DAPM_ENUM("Stereo2 ADC1 right source", rt5651_sto2_adc_r1_enum);
677
678static const char * const rt5651_sto2_adc_r2_src[] = {"DMIC R", "DD MIXR"};
679
680static SOC_ENUM_SINGLE_DECL(
681 rt5651_sto2_adc_r2_enum, RT5651_STO1_ADC_MIXER,
682 RT5651_STO2_ADC_R2_SRC_SFT, rt5651_sto2_adc_r2_src);
683
684static const struct snd_kcontrol_new rt5651_sto2_adc_r2_mux =
685 SOC_DAPM_ENUM("Stereo2 ADC2 right source", rt5651_sto2_adc_r2_enum);
686
687/* DAC2 channel source */
688
689static const char * const rt5651_dac_src[] = {"IF1", "IF2"};
690
691static SOC_ENUM_SINGLE_DECL(rt5651_dac_l2_enum, RT5651_DAC2_CTRL,
692 RT5651_SEL_DAC_L2_SFT, rt5651_dac_src);
693
694static const struct snd_kcontrol_new rt5651_dac_l2_mux =
695 SOC_DAPM_ENUM("DAC2 left channel source", rt5651_dac_l2_enum);
696
697static SOC_ENUM_SINGLE_DECL(
698 rt5651_dac_r2_enum, RT5651_DAC2_CTRL,
699 RT5651_SEL_DAC_R2_SFT, rt5651_dac_src);
700
701static const struct snd_kcontrol_new rt5651_dac_r2_mux =
702 SOC_DAPM_ENUM("DAC2 right channel source", rt5651_dac_r2_enum);
703
704/* IF2_ADC channel source */
705
706static const char * const rt5651_adc_src[] = {"IF1 ADC1", "IF1 ADC2"};
707
708static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_src_enum, RT5651_DIG_INF_DATA,
709 RT5651_IF2_ADC_SRC_SFT, rt5651_adc_src);
710
711static const struct snd_kcontrol_new rt5651_if2_adc_src_mux =
712 SOC_DAPM_ENUM("IF2 ADC channel source", rt5651_if2_adc_src_enum);
713
714/* PDM select */
715static const char * const rt5651_pdm_sel[] = {"DD MIX", "Stereo DAC MIX"};
716
717static SOC_ENUM_SINGLE_DECL(
718 rt5651_pdm_l_sel_enum, RT5651_PDM_CTL,
719 RT5651_PDM_L_SEL_SFT, rt5651_pdm_sel);
720
721static SOC_ENUM_SINGLE_DECL(
722 rt5651_pdm_r_sel_enum, RT5651_PDM_CTL,
723 RT5651_PDM_R_SEL_SFT, rt5651_pdm_sel);
724
725static const struct snd_kcontrol_new rt5651_pdm_l_mux =
726 SOC_DAPM_ENUM("PDM L select", rt5651_pdm_l_sel_enum);
727
728static const struct snd_kcontrol_new rt5651_pdm_r_mux =
729 SOC_DAPM_ENUM("PDM R select", rt5651_pdm_r_sel_enum);
730
731static int rt5651_amp_power_event(struct snd_soc_dapm_widget *w,
732 struct snd_kcontrol *kcontrol, int event)
733{
734 struct snd_soc_codec *codec = w->codec;
735 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
736
737 switch (event) {
738 case SND_SOC_DAPM_POST_PMU:
739 /* depop parameters */
740 regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
741 RT5651_CHPUMP_INT_REG1, 0x0700, 0x0200);
742 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
743 RT5651_DEPOP_MASK, RT5651_DEPOP_MAN);
744 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
745 RT5651_HP_CP_MASK | RT5651_HP_SG_MASK |
746 RT5651_HP_CB_MASK, RT5651_HP_CP_PU |
747 RT5651_HP_SG_DIS | RT5651_HP_CB_PU);
748 regmap_write(rt5651->regmap, RT5651_PR_BASE +
749 RT5651_HP_DCC_INT1, 0x9f00);
750 /* headphone amp power on */
751 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
752 RT5651_PWR_FV1 | RT5651_PWR_FV2, 0);
753 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
754 RT5651_PWR_HA,
755 RT5651_PWR_HA);
756 usleep_range(10000, 15000);
757 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
758 RT5651_PWR_FV1 | RT5651_PWR_FV2 ,
759 RT5651_PWR_FV1 | RT5651_PWR_FV2);
760 break;
761
762 default:
763 return 0;
764 }
765
766 return 0;
767}
768
769static int rt5651_hp_event(struct snd_soc_dapm_widget *w,
770 struct snd_kcontrol *kcontrol, int event)
771{
772 struct snd_soc_codec *codec = w->codec;
773 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
774
775 switch (event) {
776 case SND_SOC_DAPM_POST_PMU:
777 /* headphone unmute sequence */
778 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
779 RT5651_DEPOP_MASK | RT5651_DIG_DP_MASK,
780 RT5651_DEPOP_AUTO | RT5651_DIG_DP_EN);
781 regmap_update_bits(rt5651->regmap, RT5651_CHARGE_PUMP,
782 RT5651_PM_HP_MASK, RT5651_PM_HP_HV);
783
784 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M3,
785 RT5651_CP_FQ1_MASK | RT5651_CP_FQ2_MASK |
786 RT5651_CP_FQ3_MASK,
787 (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ1_SFT) |
788 (RT5651_CP_FQ_12_KHZ << RT5651_CP_FQ2_SFT) |
789 (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ3_SFT));
790
791 regmap_write(rt5651->regmap, RT5651_PR_BASE +
792 RT5651_MAMP_INT_REG2, 0x1c00);
793 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
794 RT5651_HP_CP_MASK | RT5651_HP_SG_MASK,
795 RT5651_HP_CP_PD | RT5651_HP_SG_EN);
796 regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
797 RT5651_CHPUMP_INT_REG1, 0x0700, 0x0400);
798 rt5651->hp_mute = 0;
799 break;
800
801 case SND_SOC_DAPM_PRE_PMD:
802 rt5651->hp_mute = 1;
803 usleep_range(70000, 75000);
804 break;
805
806 default:
807 return 0;
808 }
809
810 return 0;
811}
812
813static int rt5651_hp_post_event(struct snd_soc_dapm_widget *w,
814 struct snd_kcontrol *kcontrol, int event)
815{
816 struct snd_soc_codec *codec = w->codec;
817 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
818
819 switch (event) {
820 case SND_SOC_DAPM_POST_PMU:
821 if (!rt5651->hp_mute)
822 usleep_range(80000, 85000);
823
824 break;
825
826 default:
827 return 0;
828 }
829
830 return 0;
831}
832
833static int rt5651_bst1_event(struct snd_soc_dapm_widget *w,
834 struct snd_kcontrol *kcontrol, int event)
835{
836 struct snd_soc_codec *codec = w->codec;
837
838 switch (event) {
839 case SND_SOC_DAPM_POST_PMU:
840 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
841 RT5651_PWR_BST1_OP2, RT5651_PWR_BST1_OP2);
842 break;
843
844 case SND_SOC_DAPM_PRE_PMD:
845 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
846 RT5651_PWR_BST1_OP2, 0);
847 break;
848
849 default:
850 return 0;
851 }
852
853 return 0;
854}
855
856static int rt5651_bst2_event(struct snd_soc_dapm_widget *w,
857 struct snd_kcontrol *kcontrol, int event)
858{
859 struct snd_soc_codec *codec = w->codec;
860
861 switch (event) {
862 case SND_SOC_DAPM_POST_PMU:
863 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
864 RT5651_PWR_BST2_OP2, RT5651_PWR_BST2_OP2);
865 break;
866
867 case SND_SOC_DAPM_PRE_PMD:
868 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
869 RT5651_PWR_BST2_OP2, 0);
870 break;
871
872 default:
873 return 0;
874 }
875
876 return 0;
877}
878
879static int rt5651_bst3_event(struct snd_soc_dapm_widget *w,
880 struct snd_kcontrol *kcontrol, int event)
881{
882 struct snd_soc_codec *codec = w->codec;
883
884 switch (event) {
885 case SND_SOC_DAPM_POST_PMU:
886 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
887 RT5651_PWR_BST3_OP2, RT5651_PWR_BST3_OP2);
888 break;
889
890 case SND_SOC_DAPM_PRE_PMD:
891 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
892 RT5651_PWR_BST3_OP2, 0);
893 break;
894
895 default:
896 return 0;
897 }
898
899 return 0;
900}
901
902static const struct snd_soc_dapm_widget rt5651_dapm_widgets[] = {
903 /* ASRC */
904 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5651_PLL_MODE_2,
905 15, 0, NULL, 0),
906 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5651_PLL_MODE_2,
907 14, 0, NULL, 0),
908 SND_SOC_DAPM_SUPPLY_S("STO1 DAC ASRC", 1, RT5651_PLL_MODE_2,
909 13, 0, NULL, 0),
910 SND_SOC_DAPM_SUPPLY_S("STO2 DAC ASRC", 1, RT5651_PLL_MODE_2,
911 12, 0, NULL, 0),
912 SND_SOC_DAPM_SUPPLY_S("ADC ASRC", 1, RT5651_PLL_MODE_2,
913 11, 0, NULL, 0),
914
915 SND_SOC_DAPM_SUPPLY("PLL1", RT5651_PWR_ANLG2,
916 RT5651_PWR_PLL_BIT, 0, NULL, 0),
917 /* Input Side */
918 /* micbias */
919 SND_SOC_DAPM_SUPPLY("LDO", RT5651_PWR_ANLG1,
920 RT5651_PWR_LDO_BIT, 0, NULL, 0),
921 SND_SOC_DAPM_MICBIAS("micbias1", RT5651_PWR_ANLG2,
922 RT5651_PWR_MB1_BIT, 0),
923 /* Input Lines */
924 SND_SOC_DAPM_INPUT("MIC1"),
925 SND_SOC_DAPM_INPUT("MIC2"),
926 SND_SOC_DAPM_INPUT("MIC3"),
927
928 SND_SOC_DAPM_INPUT("IN1P"),
929 SND_SOC_DAPM_INPUT("IN2P"),
930 SND_SOC_DAPM_INPUT("IN2N"),
931 SND_SOC_DAPM_INPUT("IN3P"),
932 SND_SOC_DAPM_INPUT("DMIC L1"),
933 SND_SOC_DAPM_INPUT("DMIC R1"),
934 SND_SOC_DAPM_SUPPLY("DMIC CLK", RT5651_DMIC, RT5651_DMIC_1_EN_SFT,
935 0, set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
936 /* Boost */
937 SND_SOC_DAPM_PGA_E("BST1", RT5651_PWR_ANLG2,
938 RT5651_PWR_BST1_BIT, 0, NULL, 0, rt5651_bst1_event,
939 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
940 SND_SOC_DAPM_PGA_E("BST2", RT5651_PWR_ANLG2,
941 RT5651_PWR_BST2_BIT, 0, NULL, 0, rt5651_bst2_event,
942 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
943 SND_SOC_DAPM_PGA_E("BST3", RT5651_PWR_ANLG2,
944 RT5651_PWR_BST3_BIT, 0, NULL, 0, rt5651_bst3_event,
945 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
946 /* Input Volume */
947 SND_SOC_DAPM_PGA("INL1 VOL", RT5651_PWR_VOL,
948 RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
949 SND_SOC_DAPM_PGA("INR1 VOL", RT5651_PWR_VOL,
950 RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
951 SND_SOC_DAPM_PGA("INL2 VOL", RT5651_PWR_VOL,
952 RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
953 SND_SOC_DAPM_PGA("INR2 VOL", RT5651_PWR_VOL,
954 RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
955 /* IN Mux */
956 SND_SOC_DAPM_MUX("INL1 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inl1_mux),
957 SND_SOC_DAPM_MUX("INR1 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inr1_mux),
958 SND_SOC_DAPM_MUX("INL2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inl2_mux),
959 SND_SOC_DAPM_MUX("INR2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inr2_mux),
960 /* REC Mixer */
961 SND_SOC_DAPM_MIXER("RECMIXL", RT5651_PWR_MIXER, RT5651_PWR_RM_L_BIT, 0,
962 rt5651_rec_l_mix, ARRAY_SIZE(rt5651_rec_l_mix)),
963 SND_SOC_DAPM_MIXER("RECMIXR", RT5651_PWR_MIXER, RT5651_PWR_RM_R_BIT, 0,
964 rt5651_rec_r_mix, ARRAY_SIZE(rt5651_rec_r_mix)),
965 /* ADCs */
966 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
967 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
968 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5651_PWR_DIG1,
969 RT5651_PWR_ADC_L_BIT, 0, NULL, 0),
970 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5651_PWR_DIG1,
971 RT5651_PWR_ADC_R_BIT, 0, NULL, 0),
972 /* ADC Mux */
973 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
974 &rt5651_sto1_adc_l2_mux),
975 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
976 &rt5651_sto1_adc_r2_mux),
977 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
978 &rt5651_sto1_adc_l1_mux),
979 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
980 &rt5651_sto1_adc_r1_mux),
981 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
982 &rt5651_sto2_adc_l2_mux),
983 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
984 &rt5651_sto2_adc_l1_mux),
985 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
986 &rt5651_sto2_adc_r1_mux),
987 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
988 &rt5651_sto2_adc_r2_mux),
989 /* ADC Mixer */
990 SND_SOC_DAPM_SUPPLY("Stereo1 Filter", RT5651_PWR_DIG2,
991 RT5651_PWR_ADC_STO1_F_BIT, 0, NULL, 0),
992 SND_SOC_DAPM_SUPPLY("Stereo2 Filter", RT5651_PWR_DIG2,
993 RT5651_PWR_ADC_STO2_F_BIT, 0, NULL, 0),
994 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0,
995 rt5651_sto1_adc_l_mix,
996 ARRAY_SIZE(rt5651_sto1_adc_l_mix)),
997 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0,
998 rt5651_sto1_adc_r_mix,
999 ARRAY_SIZE(rt5651_sto1_adc_r_mix)),
1000 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0,
1001 rt5651_sto2_adc_l_mix,
1002 ARRAY_SIZE(rt5651_sto2_adc_l_mix)),
1003 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0,
1004 rt5651_sto2_adc_r_mix,
1005 ARRAY_SIZE(rt5651_sto2_adc_r_mix)),
1006
1007 /* Digital Interface */
1008 SND_SOC_DAPM_SUPPLY("I2S1", RT5651_PWR_DIG1,
1009 RT5651_PWR_I2S1_BIT, 0, NULL, 0),
1010 SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1011 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1012 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1013 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1014 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1015 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1016 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1017 SND_SOC_DAPM_SUPPLY("I2S2", RT5651_PWR_DIG1,
1018 RT5651_PWR_I2S2_BIT, 0, NULL, 0),
1019 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1020 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1021 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1022 SND_SOC_DAPM_MUX("IF2 ADC", SND_SOC_NOPM, 0, 0,
1023 &rt5651_if2_adc_src_mux),
1024
1025 /* Digital Interface Select */
1026
1027 SND_SOC_DAPM_MUX("PDM L Mux", RT5651_PDM_CTL,
1028 RT5651_M_PDM_L_SFT, 1, &rt5651_pdm_l_mux),
1029 SND_SOC_DAPM_MUX("PDM R Mux", RT5651_PDM_CTL,
1030 RT5651_M_PDM_R_SFT, 1, &rt5651_pdm_r_mux),
1031 /* Audio Interface */
1032 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1033 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1034 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1035 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1036
1037 /* Audio DSP */
1038 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
1039
1040 /* Output Side */
1041 /* DAC mixer before sound effect */
1042 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1043 rt5651_dac_l_mix, ARRAY_SIZE(rt5651_dac_l_mix)),
1044 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1045 rt5651_dac_r_mix, ARRAY_SIZE(rt5651_dac_r_mix)),
1046
1047 /* DAC2 channel Mux */
1048 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_l2_mux),
1049 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_r2_mux),
1050 SND_SOC_DAPM_PGA("DAC L2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
1051 SND_SOC_DAPM_PGA("DAC R2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
1052
1053 SND_SOC_DAPM_SUPPLY("Stero1 DAC Power", RT5651_PWR_DIG2,
1054 RT5651_PWR_DAC_STO1_F_BIT, 0, NULL, 0),
1055 SND_SOC_DAPM_SUPPLY("Stero2 DAC Power", RT5651_PWR_DIG2,
1056 RT5651_PWR_DAC_STO2_F_BIT, 0, NULL, 0),
1057 /* DAC Mixer */
1058 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1059 rt5651_sto_dac_l_mix,
1060 ARRAY_SIZE(rt5651_sto_dac_l_mix)),
1061 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1062 rt5651_sto_dac_r_mix,
1063 ARRAY_SIZE(rt5651_sto_dac_r_mix)),
1064 SND_SOC_DAPM_MIXER("DD MIXL", SND_SOC_NOPM, 0, 0,
1065 rt5651_dd_dac_l_mix,
1066 ARRAY_SIZE(rt5651_dd_dac_l_mix)),
1067 SND_SOC_DAPM_MIXER("DD MIXR", SND_SOC_NOPM, 0, 0,
1068 rt5651_dd_dac_r_mix,
1069 ARRAY_SIZE(rt5651_dd_dac_r_mix)),
1070
1071 /* DACs */
1072 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
1073 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
1074 SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5651_PWR_DIG1,
1075 RT5651_PWR_DAC_L1_BIT, 0, NULL, 0),
1076 SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5651_PWR_DIG1,
1077 RT5651_PWR_DAC_R1_BIT, 0, NULL, 0),
1078 /* OUT Mixer */
1079 SND_SOC_DAPM_MIXER("OUT MIXL", RT5651_PWR_MIXER, RT5651_PWR_OM_L_BIT,
1080 0, rt5651_out_l_mix, ARRAY_SIZE(rt5651_out_l_mix)),
1081 SND_SOC_DAPM_MIXER("OUT MIXR", RT5651_PWR_MIXER, RT5651_PWR_OM_R_BIT,
1082 0, rt5651_out_r_mix, ARRAY_SIZE(rt5651_out_r_mix)),
1083 /* Ouput Volume */
1084 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5651_PWR_VOL,
1085 RT5651_PWR_OV_L_BIT, 0, &outvol_l_control),
1086 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5651_PWR_VOL,
1087 RT5651_PWR_OV_R_BIT, 0, &outvol_r_control),
1088 SND_SOC_DAPM_SWITCH("HPOVOL L", RT5651_PWR_VOL,
1089 RT5651_PWR_HV_L_BIT, 0, &hpovol_l_control),
1090 SND_SOC_DAPM_SWITCH("HPOVOL R", RT5651_PWR_VOL,
1091 RT5651_PWR_HV_R_BIT, 0, &hpovol_r_control),
1092 SND_SOC_DAPM_PGA("INL1", RT5651_PWR_VOL,
1093 RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
1094 SND_SOC_DAPM_PGA("INR1", RT5651_PWR_VOL,
1095 RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
1096 SND_SOC_DAPM_PGA("INL2", RT5651_PWR_VOL,
1097 RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
1098 SND_SOC_DAPM_PGA("INR2", RT5651_PWR_VOL,
1099 RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
1100 /* HPO/LOUT/Mono Mixer */
1101 SND_SOC_DAPM_MIXER("HPOL MIX", SND_SOC_NOPM, 0, 0,
1102 rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
1103 SND_SOC_DAPM_MIXER("HPOR MIX", SND_SOC_NOPM, 0, 0,
1104 rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
1105 SND_SOC_DAPM_SUPPLY("HP L Amp", RT5651_PWR_ANLG1,
1106 RT5651_PWR_HP_L_BIT, 0, NULL, 0),
1107 SND_SOC_DAPM_SUPPLY("HP R Amp", RT5651_PWR_ANLG1,
1108 RT5651_PWR_HP_R_BIT, 0, NULL, 0),
1109 SND_SOC_DAPM_MIXER("LOUT MIX", RT5651_PWR_ANLG1, RT5651_PWR_LM_BIT, 0,
1110 rt5651_lout_mix, ARRAY_SIZE(rt5651_lout_mix)),
1111
1112 SND_SOC_DAPM_SUPPLY("Amp Power", RT5651_PWR_ANLG1,
1113 RT5651_PWR_HA_BIT, 0, rt5651_amp_power_event,
1114 SND_SOC_DAPM_POST_PMU),
1115 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5651_hp_event,
1116 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1117 SND_SOC_DAPM_SWITCH("HPO L Playback", SND_SOC_NOPM, 0, 0,
1118 &hpo_l_mute_control),
1119 SND_SOC_DAPM_SWITCH("HPO R Playback", SND_SOC_NOPM, 0, 0,
1120 &hpo_r_mute_control),
1121 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
1122 &lout_l_mute_control),
1123 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
1124 &lout_r_mute_control),
1125 SND_SOC_DAPM_POST("HP Post", rt5651_hp_post_event),
1126
1127 /* Output Lines */
1128 SND_SOC_DAPM_OUTPUT("HPOL"),
1129 SND_SOC_DAPM_OUTPUT("HPOR"),
1130 SND_SOC_DAPM_OUTPUT("LOUTL"),
1131 SND_SOC_DAPM_OUTPUT("LOUTR"),
1132 SND_SOC_DAPM_OUTPUT("PDML"),
1133 SND_SOC_DAPM_OUTPUT("PDMR"),
1134};
1135
1136static const struct snd_soc_dapm_route rt5651_dapm_routes[] = {
1137 {"Stero1 DAC Power", NULL, "STO1 DAC ASRC"},
1138 {"Stero2 DAC Power", NULL, "STO2 DAC ASRC"},
1139 {"I2S1", NULL, "I2S1 ASRC"},
1140 {"I2S2", NULL, "I2S2 ASRC"},
1141
1142 {"IN1P", NULL, "LDO"},
1143 {"IN2P", NULL, "LDO"},
1144 {"IN3P", NULL, "LDO"},
1145
1146 {"IN1P", NULL, "MIC1"},
1147 {"IN2P", NULL, "MIC2"},
1148 {"IN2N", NULL, "MIC2"},
1149 {"IN3P", NULL, "MIC3"},
1150
1151 {"BST1", NULL, "IN1P"},
1152 {"BST2", NULL, "IN2P"},
1153 {"BST2", NULL, "IN2N"},
1154 {"BST3", NULL, "IN3P"},
1155
1156 {"INL1 VOL", NULL, "IN2P"},
1157 {"INR1 VOL", NULL, "IN2N"},
1158
1159 {"RECMIXL", "INL1 Switch", "INL1 VOL"},
1160 {"RECMIXL", "BST3 Switch", "BST3"},
1161 {"RECMIXL", "BST2 Switch", "BST2"},
1162 {"RECMIXL", "BST1 Switch", "BST1"},
1163
1164 {"RECMIXR", "INR1 Switch", "INR1 VOL"},
1165 {"RECMIXR", "BST3 Switch", "BST3"},
1166 {"RECMIXR", "BST2 Switch", "BST2"},
1167 {"RECMIXR", "BST1 Switch", "BST1"},
1168
1169 {"ADC L", NULL, "RECMIXL"},
1170 {"ADC L", NULL, "ADC L Power"},
1171 {"ADC R", NULL, "RECMIXR"},
1172 {"ADC R", NULL, "ADC R Power"},
1173
1174 {"DMIC L1", NULL, "DMIC CLK"},
1175 {"DMIC R1", NULL, "DMIC CLK"},
1176
1177 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1178 {"Stereo1 ADC L2 Mux", "DD MIX", "DD MIXL"},
1179 {"Stereo1 ADC L1 Mux", "ADC", "ADC L"},
1180 {"Stereo1 ADC L1 Mux", "DD MIX", "DD MIXL"},
1181
1182 {"Stereo1 ADC R1 Mux", "ADC", "ADC R"},
1183 {"Stereo1 ADC R1 Mux", "DD MIX", "DD MIXR"},
1184 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1185 {"Stereo1 ADC R2 Mux", "DD MIX", "DD MIXR"},
1186
1187 {"Stereo2 ADC L2 Mux", "DMIC L", "DMIC L1"},
1188 {"Stereo2 ADC L2 Mux", "DD MIXL", "DD MIXL"},
1189 {"Stereo2 ADC L1 Mux", "DD MIXL", "DD MIXL"},
1190 {"Stereo2 ADC L1 Mux", "ADCL", "ADC L"},
1191
1192 {"Stereo2 ADC R1 Mux", "DD MIXR", "DD MIXR"},
1193 {"Stereo2 ADC R1 Mux", "ADCR", "ADC R"},
1194 {"Stereo2 ADC R2 Mux", "DMIC R", "DMIC R1"},
1195 {"Stereo2 ADC R2 Mux", "DD MIXR", "DD MIXR"},
1196
1197 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1198 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1199 {"Stereo1 ADC MIXL", NULL, "Stereo1 Filter"},
1200 {"Stereo1 Filter", NULL, "PLL1", is_sysclk_from_pll},
1201 {"Stereo1 Filter", NULL, "ADC ASRC"},
1202
1203 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1204 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1205 {"Stereo1 ADC MIXR", NULL, "Stereo1 Filter"},
1206
1207 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
1208 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
1209 {"Stereo2 ADC MIXL", NULL, "Stereo2 Filter"},
1210 {"Stereo2 Filter", NULL, "PLL1", is_sysclk_from_pll},
1211 {"Stereo2 Filter", NULL, "ADC ASRC"},
1212
1213 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
1214 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
1215 {"Stereo2 ADC MIXR", NULL, "Stereo2 Filter"},
1216
1217 {"IF1 ADC2", NULL, "Stereo2 ADC MIXL"},
1218 {"IF1 ADC2", NULL, "Stereo2 ADC MIXR"},
1219 {"IF1 ADC1", NULL, "Stereo1 ADC MIXL"},
1220 {"IF1 ADC1", NULL, "Stereo1 ADC MIXR"},
1221
1222 {"IF1 ADC1", NULL, "I2S1"},
1223
1224 {"IF2 ADC", "IF1 ADC1", "IF1 ADC1"},
1225 {"IF2 ADC", "IF1 ADC2", "IF1 ADC2"},
1226 {"IF2 ADC", NULL, "I2S2"},
1227
1228 {"AIF1TX", NULL, "IF1 ADC1"},
1229 {"AIF1TX", NULL, "IF1 ADC2"},
1230 {"AIF2TX", NULL, "IF2 ADC"},
1231
1232 {"IF1 DAC", NULL, "AIF1RX"},
1233 {"IF1 DAC", NULL, "I2S1"},
1234 {"IF2 DAC", NULL, "AIF2RX"},
1235 {"IF2 DAC", NULL, "I2S2"},
1236
1237 {"IF1 DAC1 L", NULL, "IF1 DAC"},
1238 {"IF1 DAC1 R", NULL, "IF1 DAC"},
1239 {"IF1 DAC2 L", NULL, "IF1 DAC"},
1240 {"IF1 DAC2 R", NULL, "IF1 DAC"},
1241 {"IF2 DAC L", NULL, "IF2 DAC"},
1242 {"IF2 DAC R", NULL, "IF2 DAC"},
1243
1244 {"DAC MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1245 {"DAC MIXL", "INF1 Switch", "IF1 DAC1 L"},
1246 {"DAC MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1247 {"DAC MIXR", "INF1 Switch", "IF1 DAC1 R"},
1248
1249 {"Audio DSP", NULL, "DAC MIXL"},
1250 {"Audio DSP", NULL, "DAC MIXR"},
1251
1252 {"DAC L2 Mux", "IF1", "IF1 DAC2 L"},
1253 {"DAC L2 Mux", "IF2", "IF2 DAC L"},
1254 {"DAC L2 Volume", NULL, "DAC L2 Mux"},
1255
1256 {"DAC R2 Mux", "IF1", "IF1 DAC2 R"},
1257 {"DAC R2 Mux", "IF2", "IF2 DAC R"},
1258 {"DAC R2 Volume", NULL, "DAC R2 Mux"},
1259
1260 {"Stereo DAC MIXL", "DAC L1 Switch", "Audio DSP"},
1261 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
1262 {"Stereo DAC MIXL", "DAC R1 Switch", "DAC MIXR"},
1263 {"Stereo DAC MIXL", NULL, "Stero1 DAC Power"},
1264 {"Stereo DAC MIXL", NULL, "Stero2 DAC Power"},
1265 {"Stereo DAC MIXR", "DAC R1 Switch", "Audio DSP"},
1266 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
1267 {"Stereo DAC MIXR", "DAC L1 Switch", "DAC MIXL"},
1268 {"Stereo DAC MIXR", NULL, "Stero1 DAC Power"},
1269 {"Stereo DAC MIXR", NULL, "Stero2 DAC Power"},
1270
1271 {"PDM L Mux", "Stereo DAC MIX", "Stereo DAC MIXL"},
1272 {"PDM L Mux", "DD MIX", "DAC MIXL"},
1273 {"PDM R Mux", "Stereo DAC MIX", "Stereo DAC MIXR"},
1274 {"PDM R Mux", "DD MIX", "DAC MIXR"},
1275
1276 {"DAC L1", NULL, "Stereo DAC MIXL"},
1277 {"DAC L1", NULL, "PLL1", is_sysclk_from_pll},
1278 {"DAC L1", NULL, "DAC L1 Power"},
1279 {"DAC R1", NULL, "Stereo DAC MIXR"},
1280 {"DAC R1", NULL, "PLL1", is_sysclk_from_pll},
1281 {"DAC R1", NULL, "DAC R1 Power"},
1282
1283 {"DD MIXL", "DAC L1 Switch", "DAC MIXL"},
1284 {"DD MIXL", "DAC L2 Switch", "DAC L2 Volume"},
1285 {"DD MIXL", "DAC R2 Switch", "DAC R2 Volume"},
1286 {"DD MIXL", NULL, "Stero2 DAC Power"},
1287
1288 {"DD MIXR", "DAC R1 Switch", "DAC MIXR"},
1289 {"DD MIXR", "DAC R2 Switch", "DAC R2 Volume"},
1290 {"DD MIXR", "DAC L2 Switch", "DAC L2 Volume"},
1291 {"DD MIXR", NULL, "Stero2 DAC Power"},
1292
1293 {"OUT MIXL", "BST1 Switch", "BST1"},
1294 {"OUT MIXL", "BST2 Switch", "BST2"},
1295 {"OUT MIXL", "INL1 Switch", "INL1 VOL"},
1296 {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
1297 {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
1298
1299 {"OUT MIXR", "BST2 Switch", "BST2"},
1300 {"OUT MIXR", "BST1 Switch", "BST1"},
1301 {"OUT MIXR", "INR1 Switch", "INR1 VOL"},
1302 {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
1303 {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
1304
1305 {"HPOVOL L", "Switch", "OUT MIXL"},
1306 {"HPOVOL R", "Switch", "OUT MIXR"},
1307 {"OUTVOL L", "Switch", "OUT MIXL"},
1308 {"OUTVOL R", "Switch", "OUT MIXR"},
1309
1310 {"HPOL MIX", "HPO MIX DAC1 Switch", "DAC L1"},
1311 {"HPOL MIX", "HPO MIX HPVOL Switch", "HPOVOL L"},
1312 {"HPOL MIX", NULL, "HP L Amp"},
1313 {"HPOR MIX", "HPO MIX DAC1 Switch", "DAC R1"},
1314 {"HPOR MIX", "HPO MIX HPVOL Switch", "HPOVOL R"},
1315 {"HPOR MIX", NULL, "HP R Amp"},
1316
1317 {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
1318 {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
1319 {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
1320 {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
1321
1322 {"HP Amp", NULL, "HPOL MIX"},
1323 {"HP Amp", NULL, "HPOR MIX"},
1324 {"HP Amp", NULL, "Amp Power"},
1325 {"HPO L Playback", "Switch", "HP Amp"},
1326 {"HPO R Playback", "Switch", "HP Amp"},
1327 {"HPOL", NULL, "HPO L Playback"},
1328 {"HPOR", NULL, "HPO R Playback"},
1329
1330 {"LOUT L Playback", "Switch", "LOUT MIX"},
1331 {"LOUT R Playback", "Switch", "LOUT MIX"},
1332 {"LOUTL", NULL, "LOUT L Playback"},
1333 {"LOUTL", NULL, "Amp Power"},
1334 {"LOUTR", NULL, "LOUT R Playback"},
1335 {"LOUTR", NULL, "Amp Power"},
1336
1337 {"PDML", NULL, "PDM L Mux"},
1338 {"PDMR", NULL, "PDM R Mux"},
1339};
1340
1341static int rt5651_hw_params(struct snd_pcm_substream *substream,
1342 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1343{
1344 struct snd_soc_codec *codec = dai->codec;
1345 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1346 unsigned int val_len = 0, val_clk, mask_clk;
1347 int pre_div, bclk_ms, frame_size;
1348
1349 rt5651->lrck[dai->id] = params_rate(params);
1350 pre_div = rl6231_get_clk_info(rt5651->sysclk, rt5651->lrck[dai->id]);
1351
1352 if (pre_div < 0) {
1353 dev_err(codec->dev, "Unsupported clock setting\n");
1354 return -EINVAL;
1355 }
1356 frame_size = snd_soc_params_to_frame_size(params);
1357 if (frame_size < 0) {
1358 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
1359 return -EINVAL;
1360 }
1361 bclk_ms = frame_size > 32 ? 1 : 0;
1362 rt5651->bclk[dai->id] = rt5651->lrck[dai->id] * (32 << bclk_ms);
1363
1364 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
1365 rt5651->bclk[dai->id], rt5651->lrck[dai->id]);
1366 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1367 bclk_ms, pre_div, dai->id);
1368
1369 switch (params_format(params)) {
1370 case SNDRV_PCM_FORMAT_S16_LE:
1371 break;
1372 case SNDRV_PCM_FORMAT_S20_3LE:
1373 val_len |= RT5651_I2S_DL_20;
1374 break;
1375 case SNDRV_PCM_FORMAT_S24_LE:
1376 val_len |= RT5651_I2S_DL_24;
1377 break;
1378 case SNDRV_PCM_FORMAT_S8:
1379 val_len |= RT5651_I2S_DL_8;
1380 break;
1381 default:
1382 return -EINVAL;
1383 }
1384
1385 switch (dai->id) {
1386 case RT5651_AIF1:
1387 mask_clk = RT5651_I2S_PD1_MASK;
1388 val_clk = pre_div << RT5651_I2S_PD1_SFT;
1389 snd_soc_update_bits(codec, RT5651_I2S1_SDP,
1390 RT5651_I2S_DL_MASK, val_len);
1391 snd_soc_update_bits(codec, RT5651_ADDA_CLK1, mask_clk, val_clk);
1392 break;
1393 case RT5651_AIF2:
1394 mask_clk = RT5651_I2S_BCLK_MS2_MASK | RT5651_I2S_PD2_MASK;
1395 val_clk = pre_div << RT5651_I2S_PD2_SFT;
1396 snd_soc_update_bits(codec, RT5651_I2S2_SDP,
1397 RT5651_I2S_DL_MASK, val_len);
1398 snd_soc_update_bits(codec, RT5651_ADDA_CLK1, mask_clk, val_clk);
1399 break;
1400 default:
1401 dev_err(codec->dev, "Wrong dai->id: %d\n", dai->id);
1402 return -EINVAL;
1403 }
1404
1405 return 0;
1406}
1407
1408static int rt5651_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1409{
1410 struct snd_soc_codec *codec = dai->codec;
1411 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1412 unsigned int reg_val = 0;
1413
1414 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1415 case SND_SOC_DAIFMT_CBM_CFM:
1416 rt5651->master[dai->id] = 1;
1417 break;
1418 case SND_SOC_DAIFMT_CBS_CFS:
1419 reg_val |= RT5651_I2S_MS_S;
1420 rt5651->master[dai->id] = 0;
1421 break;
1422 default:
1423 return -EINVAL;
1424 }
1425
1426 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1427 case SND_SOC_DAIFMT_NB_NF:
1428 break;
1429 case SND_SOC_DAIFMT_IB_NF:
1430 reg_val |= RT5651_I2S_BP_INV;
1431 break;
1432 default:
1433 return -EINVAL;
1434 }
1435
1436 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1437 case SND_SOC_DAIFMT_I2S:
1438 break;
1439 case SND_SOC_DAIFMT_LEFT_J:
1440 reg_val |= RT5651_I2S_DF_LEFT;
1441 break;
1442 case SND_SOC_DAIFMT_DSP_A:
1443 reg_val |= RT5651_I2S_DF_PCM_A;
1444 break;
1445 case SND_SOC_DAIFMT_DSP_B:
1446 reg_val |= RT5651_I2S_DF_PCM_B;
1447 break;
1448 default:
1449 return -EINVAL;
1450 }
1451
1452 switch (dai->id) {
1453 case RT5651_AIF1:
1454 snd_soc_update_bits(codec, RT5651_I2S1_SDP,
1455 RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
1456 RT5651_I2S_DF_MASK, reg_val);
1457 break;
1458 case RT5651_AIF2:
1459 snd_soc_update_bits(codec, RT5651_I2S2_SDP,
1460 RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
1461 RT5651_I2S_DF_MASK, reg_val);
1462 break;
1463 default:
1464 dev_err(codec->dev, "Wrong dai->id: %d\n", dai->id);
1465 return -EINVAL;
1466 }
1467 return 0;
1468}
1469
1470static int rt5651_set_dai_sysclk(struct snd_soc_dai *dai,
1471 int clk_id, unsigned int freq, int dir)
1472{
1473 struct snd_soc_codec *codec = dai->codec;
1474 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1475 unsigned int reg_val = 0;
1476
1477 if (freq == rt5651->sysclk && clk_id == rt5651->sysclk_src)
1478 return 0;
1479
1480 switch (clk_id) {
1481 case RT5651_SCLK_S_MCLK:
1482 reg_val |= RT5651_SCLK_SRC_MCLK;
1483 break;
1484 case RT5651_SCLK_S_PLL1:
1485 reg_val |= RT5651_SCLK_SRC_PLL1;
1486 break;
1487 case RT5651_SCLK_S_RCCLK:
1488 reg_val |= RT5651_SCLK_SRC_RCCLK;
1489 break;
1490 default:
1491 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
1492 return -EINVAL;
1493 }
1494 snd_soc_update_bits(codec, RT5651_GLB_CLK,
1495 RT5651_SCLK_SRC_MASK, reg_val);
1496 rt5651->sysclk = freq;
1497 rt5651->sysclk_src = clk_id;
1498
1499 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
1500
1501 return 0;
1502}
1503
1504static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
1505 unsigned int freq_in, unsigned int freq_out)
1506{
1507 struct snd_soc_codec *codec = dai->codec;
1508 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1509 struct rl6231_pll_code pll_code;
1510 int ret;
1511
1512 if (source == rt5651->pll_src && freq_in == rt5651->pll_in &&
1513 freq_out == rt5651->pll_out)
1514 return 0;
1515
1516 if (!freq_in || !freq_out) {
1517 dev_dbg(codec->dev, "PLL disabled\n");
1518
1519 rt5651->pll_in = 0;
1520 rt5651->pll_out = 0;
1521 snd_soc_update_bits(codec, RT5651_GLB_CLK,
1522 RT5651_SCLK_SRC_MASK, RT5651_SCLK_SRC_MCLK);
1523 return 0;
1524 }
1525
1526 switch (source) {
1527 case RT5651_PLL1_S_MCLK:
1528 snd_soc_update_bits(codec, RT5651_GLB_CLK,
1529 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_MCLK);
1530 break;
1531 case RT5651_PLL1_S_BCLK1:
1532 snd_soc_update_bits(codec, RT5651_GLB_CLK,
1533 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK1);
1534 break;
1535 case RT5651_PLL1_S_BCLK2:
1536 snd_soc_update_bits(codec, RT5651_GLB_CLK,
1537 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK2);
1538 break;
1539 default:
1540 dev_err(codec->dev, "Unknown PLL source %d\n", source);
1541 return -EINVAL;
1542 }
1543
1544 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1545 if (ret < 0) {
1546 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
1547 return ret;
1548 }
1549
1550 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
1551 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
1552 pll_code.n_code, pll_code.k_code);
1553
1554 snd_soc_write(codec, RT5651_PLL_CTRL1,
1555 pll_code.n_code << RT5651_PLL_N_SFT | pll_code.k_code);
1556 snd_soc_write(codec, RT5651_PLL_CTRL2,
1557 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5651_PLL_M_SFT |
1558 pll_code.m_bp << RT5651_PLL_M_BP_SFT);
1559
1560 rt5651->pll_in = freq_in;
1561 rt5651->pll_out = freq_out;
1562 rt5651->pll_src = source;
1563
1564 return 0;
1565}
1566
1567static int rt5651_set_bias_level(struct snd_soc_codec *codec,
1568 enum snd_soc_bias_level level)
1569{
1570 switch (level) {
1571 case SND_SOC_BIAS_PREPARE:
1572 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
1573 snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1574 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1575 RT5651_PWR_BG | RT5651_PWR_VREF2,
1576 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1577 RT5651_PWR_BG | RT5651_PWR_VREF2);
1578 usleep_range(10000, 15000);
1579 snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1580 RT5651_PWR_FV1 | RT5651_PWR_FV2,
1581 RT5651_PWR_FV1 | RT5651_PWR_FV2);
1582 snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1583 RT5651_PWR_LDO_DVO_MASK,
1584 RT5651_PWR_LDO_DVO_1_2V);
1585 snd_soc_update_bits(codec, RT5651_D_MISC, 0x1, 0x1);
1586 if (snd_soc_read(codec, RT5651_PLL_MODE_1) & 0x9200)
1587 snd_soc_update_bits(codec, RT5651_D_MISC,
1588 0xc00, 0xc00);
1589 }
1590 break;
1591
1592 case SND_SOC_BIAS_STANDBY:
1593 snd_soc_write(codec, RT5651_D_MISC, 0x0010);
1594 snd_soc_write(codec, RT5651_PWR_DIG1, 0x0000);
1595 snd_soc_write(codec, RT5651_PWR_DIG2, 0x0000);
1596 snd_soc_write(codec, RT5651_PWR_VOL, 0x0000);
1597 snd_soc_write(codec, RT5651_PWR_MIXER, 0x0000);
1598 snd_soc_write(codec, RT5651_PWR_ANLG1, 0x0000);
1599 snd_soc_write(codec, RT5651_PWR_ANLG2, 0x0000);
1600 break;
1601
1602 default:
1603 break;
1604 }
1605 codec->dapm.bias_level = level;
1606
1607 return 0;
1608}
1609
1610static int rt5651_probe(struct snd_soc_codec *codec)
1611{
1612 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1613
1614 rt5651->codec = codec;
1615
1616 snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1617 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1618 RT5651_PWR_BG | RT5651_PWR_VREF2,
1619 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1620 RT5651_PWR_BG | RT5651_PWR_VREF2);
1621 usleep_range(10000, 15000);
1622 snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1623 RT5651_PWR_FV1 | RT5651_PWR_FV2,
1624 RT5651_PWR_FV1 | RT5651_PWR_FV2);
1625
1626 rt5651_set_bias_level(codec, SND_SOC_BIAS_OFF);
1627
1628 return 0;
1629}
1630
1631#ifdef CONFIG_PM
1632static int rt5651_suspend(struct snd_soc_codec *codec)
1633{
1634 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1635
1636 regcache_cache_only(rt5651->regmap, true);
1637 regcache_mark_dirty(rt5651->regmap);
1638 return 0;
1639}
1640
1641static int rt5651_resume(struct snd_soc_codec *codec)
1642{
1643 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1644
1645 regcache_cache_only(rt5651->regmap, false);
1646 snd_soc_cache_sync(codec);
1647
1648 return 0;
1649}
1650#else
1651#define rt5651_suspend NULL
1652#define rt5651_resume NULL
1653#endif
1654
1655#define RT5651_STEREO_RATES SNDRV_PCM_RATE_8000_96000
1656#define RT5651_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1657 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1658
1659static const struct snd_soc_dai_ops rt5651_aif_dai_ops = {
1660 .hw_params = rt5651_hw_params,
1661 .set_fmt = rt5651_set_dai_fmt,
1662 .set_sysclk = rt5651_set_dai_sysclk,
1663 .set_pll = rt5651_set_dai_pll,
1664};
1665
1666static struct snd_soc_dai_driver rt5651_dai[] = {
1667 {
1668 .name = "rt5651-aif1",
1669 .id = RT5651_AIF1,
1670 .playback = {
1671 .stream_name = "AIF1 Playback",
1672 .channels_min = 1,
1673 .channels_max = 2,
1674 .rates = RT5651_STEREO_RATES,
1675 .formats = RT5651_FORMATS,
1676 },
1677 .capture = {
1678 .stream_name = "AIF1 Capture",
1679 .channels_min = 1,
1680 .channels_max = 2,
1681 .rates = RT5651_STEREO_RATES,
1682 .formats = RT5651_FORMATS,
1683 },
1684 .ops = &rt5651_aif_dai_ops,
1685 },
1686 {
1687 .name = "rt5651-aif2",
1688 .id = RT5651_AIF2,
1689 .playback = {
1690 .stream_name = "AIF2 Playback",
1691 .channels_min = 1,
1692 .channels_max = 2,
1693 .rates = RT5651_STEREO_RATES,
1694 .formats = RT5651_FORMATS,
1695 },
1696 .capture = {
1697 .stream_name = "AIF2 Capture",
1698 .channels_min = 1,
1699 .channels_max = 2,
1700 .rates = RT5651_STEREO_RATES,
1701 .formats = RT5651_FORMATS,
1702 },
1703 .ops = &rt5651_aif_dai_ops,
1704 },
1705};
1706
1707static struct snd_soc_codec_driver soc_codec_dev_rt5651 = {
1708 .probe = rt5651_probe,
1709 .suspend = rt5651_suspend,
1710 .resume = rt5651_resume,
1711 .set_bias_level = rt5651_set_bias_level,
1712 .idle_bias_off = true,
1713 .controls = rt5651_snd_controls,
1714 .num_controls = ARRAY_SIZE(rt5651_snd_controls),
1715 .dapm_widgets = rt5651_dapm_widgets,
1716 .num_dapm_widgets = ARRAY_SIZE(rt5651_dapm_widgets),
1717 .dapm_routes = rt5651_dapm_routes,
1718 .num_dapm_routes = ARRAY_SIZE(rt5651_dapm_routes),
1719};
1720
1721static const struct regmap_config rt5651_regmap = {
1722 .reg_bits = 8,
1723 .val_bits = 16,
1724
1725 .max_register = RT5651_DEVICE_ID + 1 + (ARRAY_SIZE(rt5651_ranges) *
1726 RT5651_PR_SPACING),
1727 .volatile_reg = rt5651_volatile_register,
1728 .readable_reg = rt5651_readable_register,
1729
1730 .cache_type = REGCACHE_RBTREE,
1731 .reg_defaults = rt5651_reg,
1732 .num_reg_defaults = ARRAY_SIZE(rt5651_reg),
1733 .ranges = rt5651_ranges,
1734 .num_ranges = ARRAY_SIZE(rt5651_ranges),
1735};
1736
1737static const struct i2c_device_id rt5651_i2c_id[] = {
1738 { "rt5651", 0 },
1739 { }
1740};
1741MODULE_DEVICE_TABLE(i2c, rt5651_i2c_id);
1742
1743static int rt5651_i2c_probe(struct i2c_client *i2c,
1744 const struct i2c_device_id *id)
1745{
1746 struct rt5651_platform_data *pdata = dev_get_platdata(&i2c->dev);
1747 struct rt5651_priv *rt5651;
1748 int ret;
1749
1750 rt5651 = devm_kzalloc(&i2c->dev, sizeof(*rt5651),
1751 GFP_KERNEL);
1752 if (NULL == rt5651)
1753 return -ENOMEM;
1754
1755 i2c_set_clientdata(i2c, rt5651);
1756
1757 if (pdata)
1758 rt5651->pdata = *pdata;
1759
1760 rt5651->regmap = devm_regmap_init_i2c(i2c, &rt5651_regmap);
1761 if (IS_ERR(rt5651->regmap)) {
1762 ret = PTR_ERR(rt5651->regmap);
1763 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1764 ret);
1765 return ret;
1766 }
1767
1768 regmap_read(rt5651->regmap, RT5651_DEVICE_ID, &ret);
1769 if (ret != RT5651_DEVICE_ID_VALUE) {
1770 dev_err(&i2c->dev,
1771 "Device with ID register %x is not rt5651\n", ret);
1772 return -ENODEV;
1773 }
1774
1775 regmap_write(rt5651->regmap, RT5651_RESET, 0);
1776
1777 ret = regmap_register_patch(rt5651->regmap, init_list,
1778 ARRAY_SIZE(init_list));
1779 if (ret != 0)
1780 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
1781
1782 if (rt5651->pdata.in2_diff)
1783 regmap_update_bits(rt5651->regmap, RT5651_IN1_IN2,
1784 RT5651_IN_DF2, RT5651_IN_DF2);
1785
1786 if (rt5651->pdata.dmic_en)
1787 regmap_update_bits(rt5651->regmap, RT5651_GPIO_CTRL1,
1788 RT5651_GP2_PIN_MASK, RT5651_GP2_PIN_DMIC1_SCL);
1789
1790 rt5651->hp_mute = 1;
1791
1792 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5651,
1793 rt5651_dai, ARRAY_SIZE(rt5651_dai));
1794
1795 return ret;
1796}
1797
1798static int rt5651_i2c_remove(struct i2c_client *i2c)
1799{
1800 snd_soc_unregister_codec(&i2c->dev);
1801
1802 return 0;
1803}
1804
1805static struct i2c_driver rt5651_i2c_driver = {
1806 .driver = {
1807 .name = "rt5651",
1808 .owner = THIS_MODULE,
1809 },
1810 .probe = rt5651_i2c_probe,
1811 .remove = rt5651_i2c_remove,
1812 .id_table = rt5651_i2c_id,
1813};
1814module_i2c_driver(rt5651_i2c_driver);
1815
1816MODULE_DESCRIPTION("ASoC RT5651 driver");
1817MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1818MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/rt5651.h b/sound/soc/codecs/rt5651.h
new file mode 100644
index 000000000000..1bd33cfa6411
--- /dev/null
+++ b/sound/soc/codecs/rt5651.h
@@ -0,0 +1,2080 @@
1/*
2 * rt5651.h -- RT5651 ALSA SoC audio driver
3 *
4 * Copyright 2011 Realtek Microelectronics
5 * Author: Johnny Hsu <johnnyhsu@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __RT5651_H__
13#define __RT5651_H__
14
15#include <sound/rt5651.h>
16
17/* Info */
18#define RT5651_RESET 0x00
19#define RT5651_VERSION_ID 0xfd
20#define RT5651_VENDOR_ID 0xfe
21#define RT5651_DEVICE_ID 0xff
22/* I/O - Output */
23#define RT5651_HP_VOL 0x02
24#define RT5651_LOUT_CTRL1 0x03
25#define RT5651_LOUT_CTRL2 0x05
26/* I/O - Input */
27#define RT5651_IN1_IN2 0x0d
28#define RT5651_IN3 0x0e
29#define RT5651_INL1_INR1_VOL 0x0f
30#define RT5651_INL2_INR2_VOL 0x10
31/* I/O - ADC/DAC/DMIC */
32#define RT5651_DAC1_DIG_VOL 0x19
33#define RT5651_DAC2_DIG_VOL 0x1a
34#define RT5651_DAC2_CTRL 0x1b
35#define RT5651_ADC_DIG_VOL 0x1c
36#define RT5651_ADC_DATA 0x1d
37#define RT5651_ADC_BST_VOL 0x1e
38/* Mixer - D-D */
39#define RT5651_STO1_ADC_MIXER 0x27
40#define RT5651_STO2_ADC_MIXER 0x28
41#define RT5651_AD_DA_MIXER 0x29
42#define RT5651_STO_DAC_MIXER 0x2a
43#define RT5651_DD_MIXER 0x2b
44#define RT5651_DIG_INF_DATA 0x2f
45/* PDM */
46#define RT5651_PDM_CTL 0x30
47#define RT5651_PDM_I2C_CTL1 0x31
48#define RT5651_PDM_I2C_CTL2 0x32
49#define RT5651_PDM_I2C_DATA_W 0x33
50#define RT5651_PDM_I2C_DATA_R 0x34
51/* Mixer - ADC */
52#define RT5651_REC_L1_MIXER 0x3b
53#define RT5651_REC_L2_MIXER 0x3c
54#define RT5651_REC_R1_MIXER 0x3d
55#define RT5651_REC_R2_MIXER 0x3e
56/* Mixer - DAC */
57#define RT5651_HPO_MIXER 0x45
58#define RT5651_OUT_L1_MIXER 0x4d
59#define RT5651_OUT_L2_MIXER 0x4e
60#define RT5651_OUT_L3_MIXER 0x4f
61#define RT5651_OUT_R1_MIXER 0x50
62#define RT5651_OUT_R2_MIXER 0x51
63#define RT5651_OUT_R3_MIXER 0x52
64#define RT5651_LOUT_MIXER 0x53
65/* Power */
66#define RT5651_PWR_DIG1 0x61
67#define RT5651_PWR_DIG2 0x62
68#define RT5651_PWR_ANLG1 0x63
69#define RT5651_PWR_ANLG2 0x64
70#define RT5651_PWR_MIXER 0x65
71#define RT5651_PWR_VOL 0x66
72/* Private Register Control */
73#define RT5651_PRIV_INDEX 0x6a
74#define RT5651_PRIV_DATA 0x6c
75/* Format - ADC/DAC */
76#define RT5651_I2S1_SDP 0x70
77#define RT5651_I2S2_SDP 0x71
78#define RT5651_ADDA_CLK1 0x73
79#define RT5651_ADDA_CLK2 0x74
80#define RT5651_DMIC 0x75
81/* TDM Control */
82#define RT5651_TDM_CTL_1 0x77
83#define RT5651_TDM_CTL_2 0x78
84#define RT5651_TDM_CTL_3 0x79
85/* Function - Analog */
86#define RT5651_GLB_CLK 0x80
87#define RT5651_PLL_CTRL1 0x81
88#define RT5651_PLL_CTRL2 0x82
89#define RT5651_PLL_MODE_1 0x83
90#define RT5651_PLL_MODE_2 0x84
91#define RT5651_PLL_MODE_3 0x85
92#define RT5651_PLL_MODE_4 0x86
93#define RT5651_PLL_MODE_5 0x87
94#define RT5651_PLL_MODE_6 0x89
95#define RT5651_PLL_MODE_7 0x8a
96#define RT5651_DEPOP_M1 0x8e
97#define RT5651_DEPOP_M2 0x8f
98#define RT5651_DEPOP_M3 0x90
99#define RT5651_CHARGE_PUMP 0x91
100#define RT5651_MICBIAS 0x93
101#define RT5651_A_JD_CTL1 0x94
102/* Function - Digital */
103#define RT5651_EQ_CTRL1 0xb0
104#define RT5651_EQ_CTRL2 0xb1
105#define RT5651_ALC_1 0xb4
106#define RT5651_ALC_2 0xb5
107#define RT5651_ALC_3 0xb6
108#define RT5651_JD_CTRL1 0xbb
109#define RT5651_JD_CTRL2 0xbc
110#define RT5651_IRQ_CTRL1 0xbd
111#define RT5651_IRQ_CTRL2 0xbe
112#define RT5651_INT_IRQ_ST 0xbf
113#define RT5651_GPIO_CTRL1 0xc0
114#define RT5651_GPIO_CTRL2 0xc1
115#define RT5651_GPIO_CTRL3 0xc2
116#define RT5651_PGM_REG_ARR1 0xc8
117#define RT5651_PGM_REG_ARR2 0xc9
118#define RT5651_PGM_REG_ARR3 0xca
119#define RT5651_PGM_REG_ARR4 0xcb
120#define RT5651_PGM_REG_ARR5 0xcc
121#define RT5651_SCB_FUNC 0xcd
122#define RT5651_SCB_CTRL 0xce
123#define RT5651_BASE_BACK 0xcf
124#define RT5651_MP3_PLUS1 0xd0
125#define RT5651_MP3_PLUS2 0xd1
126#define RT5651_ADJ_HPF_CTRL1 0xd3
127#define RT5651_ADJ_HPF_CTRL2 0xd4
128#define RT5651_HP_CALIB_AMP_DET 0xd6
129#define RT5651_HP_CALIB2 0xd7
130#define RT5651_SV_ZCD1 0xd9
131#define RT5651_SV_ZCD2 0xda
132#define RT5651_D_MISC 0xfa
133/* Dummy Register */
134#define RT5651_DUMMY2 0xfb
135#define RT5651_DUMMY3 0xfc
136
137
138/* Index of Codec Private Register definition */
139#define RT5651_BIAS_CUR1 0x12
140#define RT5651_BIAS_CUR3 0x14
141#define RT5651_CLSD_INT_REG1 0x1c
142#define RT5651_CHPUMP_INT_REG1 0x24
143#define RT5651_MAMP_INT_REG2 0x37
144#define RT5651_CHOP_DAC_ADC 0x3d
145#define RT5651_3D_SPK 0x63
146#define RT5651_WND_1 0x6c
147#define RT5651_WND_2 0x6d
148#define RT5651_WND_3 0x6e
149#define RT5651_WND_4 0x6f
150#define RT5651_WND_5 0x70
151#define RT5651_WND_8 0x73
152#define RT5651_DIP_SPK_INF 0x75
153#define RT5651_HP_DCC_INT1 0x77
154#define RT5651_EQ_BW_LOP 0xa0
155#define RT5651_EQ_GN_LOP 0xa1
156#define RT5651_EQ_FC_BP1 0xa2
157#define RT5651_EQ_BW_BP1 0xa3
158#define RT5651_EQ_GN_BP1 0xa4
159#define RT5651_EQ_FC_BP2 0xa5
160#define RT5651_EQ_BW_BP2 0xa6
161#define RT5651_EQ_GN_BP2 0xa7
162#define RT5651_EQ_FC_BP3 0xa8
163#define RT5651_EQ_BW_BP3 0xa9
164#define RT5651_EQ_GN_BP3 0xaa
165#define RT5651_EQ_FC_BP4 0xab
166#define RT5651_EQ_BW_BP4 0xac
167#define RT5651_EQ_GN_BP4 0xad
168#define RT5651_EQ_FC_HIP1 0xae
169#define RT5651_EQ_GN_HIP1 0xaf
170#define RT5651_EQ_FC_HIP2 0xb0
171#define RT5651_EQ_BW_HIP2 0xb1
172#define RT5651_EQ_GN_HIP2 0xb2
173#define RT5651_EQ_PRE_VOL 0xb3
174#define RT5651_EQ_PST_VOL 0xb4
175
176
177/* global definition */
178#define RT5651_L_MUTE (0x1 << 15)
179#define RT5651_L_MUTE_SFT 15
180#define RT5651_VOL_L_MUTE (0x1 << 14)
181#define RT5651_VOL_L_SFT 14
182#define RT5651_R_MUTE (0x1 << 7)
183#define RT5651_R_MUTE_SFT 7
184#define RT5651_VOL_R_MUTE (0x1 << 6)
185#define RT5651_VOL_R_SFT 6
186#define RT5651_L_VOL_MASK (0x3f << 8)
187#define RT5651_L_VOL_SFT 8
188#define RT5651_R_VOL_MASK (0x3f)
189#define RT5651_R_VOL_SFT 0
190
191/* LOUT Control 2(0x05) */
192#define RT5651_EN_DFO (0x1 << 15)
193
194/* IN1 and IN2 Control (0x0d) */
195/* IN3 and IN4 Control (0x0e) */
196#define RT5651_BST_MASK1 (0xf<<12)
197#define RT5651_BST_SFT1 12
198#define RT5651_BST_MASK2 (0xf<<8)
199#define RT5651_BST_SFT2 8
200#define RT5651_IN_DF1 (0x1 << 7)
201#define RT5651_IN_SFT1 7
202#define RT5651_IN_DF2 (0x1 << 6)
203#define RT5651_IN_SFT2 6
204
205/* INL1 and INR1 Volume Control (0x0f) */
206/* INL2 and INR2 Volume Control (0x10) */
207#define RT5651_INL_SEL_MASK (0x1 << 15)
208#define RT5651_INL_SEL_SFT 15
209#define RT5651_INL_SEL_IN4P (0x0 << 15)
210#define RT5651_INL_SEL_MONOP (0x1 << 15)
211#define RT5651_INL_VOL_MASK (0x1f << 8)
212#define RT5651_INL_VOL_SFT 8
213#define RT5651_INR_SEL_MASK (0x1 << 7)
214#define RT5651_INR_SEL_SFT 7
215#define RT5651_INR_SEL_IN4N (0x0 << 7)
216#define RT5651_INR_SEL_MONON (0x1 << 7)
217#define RT5651_INR_VOL_MASK (0x1f)
218#define RT5651_INR_VOL_SFT 0
219
220/* DAC1 Digital Volume (0x19) */
221#define RT5651_DAC_L1_VOL_MASK (0xff << 8)
222#define RT5651_DAC_L1_VOL_SFT 8
223#define RT5651_DAC_R1_VOL_MASK (0xff)
224#define RT5651_DAC_R1_VOL_SFT 0
225
226/* DAC2 Digital Volume (0x1a) */
227#define RT5651_DAC_L2_VOL_MASK (0xff << 8)
228#define RT5651_DAC_L2_VOL_SFT 8
229#define RT5651_DAC_R2_VOL_MASK (0xff)
230#define RT5651_DAC_R2_VOL_SFT 0
231
232/* DAC2 Control (0x1b) */
233#define RT5651_M_DAC_L2_VOL (0x1 << 13)
234#define RT5651_M_DAC_L2_VOL_SFT 13
235#define RT5651_M_DAC_R2_VOL (0x1 << 12)
236#define RT5651_M_DAC_R2_VOL_SFT 12
237#define RT5651_SEL_DAC_L2 (0x1 << 11)
238#define RT5651_IF2_DAC_L2 (0x1 << 11)
239#define RT5651_IF1_DAC_L2 (0x0 << 11)
240#define RT5651_SEL_DAC_L2_SFT 11
241#define RT5651_SEL_DAC_R2 (0x1 << 10)
242#define RT5651_IF2_DAC_R2 (0x1 << 11)
243#define RT5651_IF1_DAC_R2 (0x0 << 11)
244#define RT5651_SEL_DAC_R2_SFT 10
245
246/* ADC Digital Volume Control (0x1c) */
247#define RT5651_ADC_L_VOL_MASK (0x7f << 8)
248#define RT5651_ADC_L_VOL_SFT 8
249#define RT5651_ADC_R_VOL_MASK (0x7f)
250#define RT5651_ADC_R_VOL_SFT 0
251
252/* Mono ADC Digital Volume Control (0x1d) */
253#define RT5651_M_MONO_ADC_L (0x1 << 15)
254#define RT5651_M_MONO_ADC_L_SFT 15
255#define RT5651_MONO_ADC_L_VOL_MASK (0x7f << 8)
256#define RT5651_MONO_ADC_L_VOL_SFT 8
257#define RT5651_M_MONO_ADC_R (0x1 << 7)
258#define RT5651_M_MONO_ADC_R_SFT 7
259#define RT5651_MONO_ADC_R_VOL_MASK (0x7f)
260#define RT5651_MONO_ADC_R_VOL_SFT 0
261
262/* ADC Boost Volume Control (0x1e) */
263#define RT5651_ADC_L_BST_MASK (0x3 << 14)
264#define RT5651_ADC_L_BST_SFT 14
265#define RT5651_ADC_R_BST_MASK (0x3 << 12)
266#define RT5651_ADC_R_BST_SFT 12
267#define RT5651_ADC_COMP_MASK (0x3 << 10)
268#define RT5651_ADC_COMP_SFT 10
269
270/* Stereo ADC1 Mixer Control (0x27) */
271#define RT5651_M_STO1_ADC_L1 (0x1 << 14)
272#define RT5651_M_STO1_ADC_L1_SFT 14
273#define RT5651_M_STO1_ADC_L2 (0x1 << 13)
274#define RT5651_M_STO1_ADC_L2_SFT 13
275#define RT5651_STO1_ADC_1_SRC_MASK (0x1 << 12)
276#define RT5651_STO1_ADC_1_SRC_SFT 12
277#define RT5651_STO1_ADC_1_SRC_ADC (0x1 << 12)
278#define RT5651_STO1_ADC_1_SRC_DACMIX (0x0 << 12)
279#define RT5651_STO1_ADC_2_SRC_MASK (0x1 << 11)
280#define RT5651_STO1_ADC_2_SRC_SFT 11
281#define RT5651_STO1_ADC_2_SRC_DMIC (0x0 << 11)
282#define RT5651_STO1_ADC_2_SRC_DACMIXR (0x1 << 11)
283#define RT5651_M_STO1_ADC_R1 (0x1 << 6)
284#define RT5651_M_STO1_ADC_R1_SFT 6
285#define RT5651_M_STO1_ADC_R2 (0x1 << 5)
286#define RT5651_M_STO1_ADC_R2_SFT 5
287
288/* Stereo ADC2 Mixer Control (0x28) */
289#define RT5651_M_STO2_ADC_L1 (0x1 << 14)
290#define RT5651_M_STO2_ADC_L1_SFT 14
291#define RT5651_M_STO2_ADC_L2 (0x1 << 13)
292#define RT5651_M_STO2_ADC_L2_SFT 13
293#define RT5651_STO2_ADC_L1_SRC_MASK (0x1 << 12)
294#define RT5651_STO2_ADC_L1_SRC_SFT 12
295#define RT5651_STO2_ADC_L1_SRC_DACMIXL (0x0 << 12)
296#define RT5651_STO2_ADC_L1_SRC_ADCL (0x1 << 12)
297#define RT5651_STO2_ADC_L2_SRC_MASK (0x1 << 11)
298#define RT5651_STO2_ADC_L2_SRC_SFT 11
299#define RT5651_STO2_ADC_L2_SRC_DMIC (0x0 << 11)
300#define RT5651_STO2_ADC_L2_SRC_DACMIXR (0x1 << 11)
301#define RT5651_M_STO2_ADC_R1 (0x1 << 6)
302#define RT5651_M_STO2_ADC_R1_SFT 6
303#define RT5651_M_STO2_ADC_R2 (0x1 << 5)
304#define RT5651_M_STO2_ADC_R2_SFT 5
305#define RT5651_STO2_ADC_R1_SRC_MASK (0x1 << 4)
306#define RT5651_STO2_ADC_R1_SRC_SFT 4
307#define RT5651_STO2_ADC_R1_SRC_ADCR (0x1 << 4)
308#define RT5651_STO2_ADC_R1_SRC_DACMIXR (0x0 << 4)
309#define RT5651_STO2_ADC_R2_SRC_MASK (0x1 << 3)
310#define RT5651_STO2_ADC_R2_SRC_SFT 3
311#define RT5651_STO2_ADC_R2_SRC_DMIC (0x0 << 3)
312#define RT5651_STO2_ADC_R2_SRC_DACMIXR (0x1 << 3)
313
314/* ADC Mixer to DAC Mixer Control (0x29) */
315#define RT5651_M_ADCMIX_L (0x1 << 15)
316#define RT5651_M_ADCMIX_L_SFT 15
317#define RT5651_M_IF1_DAC_L (0x1 << 14)
318#define RT5651_M_IF1_DAC_L_SFT 14
319#define RT5651_M_ADCMIX_R (0x1 << 7)
320#define RT5651_M_ADCMIX_R_SFT 7
321#define RT5651_M_IF1_DAC_R (0x1 << 6)
322#define RT5651_M_IF1_DAC_R_SFT 6
323
324/* Stereo DAC Mixer Control (0x2a) */
325#define RT5651_M_DAC_L1_MIXL (0x1 << 14)
326#define RT5651_M_DAC_L1_MIXL_SFT 14
327#define RT5651_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
328#define RT5651_DAC_L1_STO_L_VOL_SFT 13
329#define RT5651_M_DAC_L2_MIXL (0x1 << 12)
330#define RT5651_M_DAC_L2_MIXL_SFT 12
331#define RT5651_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
332#define RT5651_DAC_L2_STO_L_VOL_SFT 11
333#define RT5651_M_DAC_R1_MIXL (0x1 << 9)
334#define RT5651_M_DAC_R1_MIXL_SFT 9
335#define RT5651_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
336#define RT5651_DAC_R1_STO_L_VOL_SFT 8
337#define RT5651_M_DAC_R1_MIXR (0x1 << 6)
338#define RT5651_M_DAC_R1_MIXR_SFT 6
339#define RT5651_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
340#define RT5651_DAC_R1_STO_R_VOL_SFT 5
341#define RT5651_M_DAC_R2_MIXR (0x1 << 4)
342#define RT5651_M_DAC_R2_MIXR_SFT 4
343#define RT5651_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
344#define RT5651_DAC_R2_STO_R_VOL_SFT 3
345#define RT5651_M_DAC_L1_MIXR (0x1 << 1)
346#define RT5651_M_DAC_L1_MIXR_SFT 1
347#define RT5651_DAC_L1_STO_R_VOL_MASK (0x1)
348#define RT5651_DAC_L1_STO_R_VOL_SFT 0
349
350/* DD Mixer Control (0x2b) */
351#define RT5651_M_STO_DD_L1 (0x1 << 14)
352#define RT5651_M_STO_DD_L1_SFT 14
353#define RT5651_STO_DD_L1_VOL_MASK (0x1 << 13)
354#define RT5651_DAC_DD_L1_VOL_SFT 13
355#define RT5651_M_STO_DD_L2 (0x1 << 12)
356#define RT5651_M_STO_DD_L2_SFT 12
357#define RT5651_STO_DD_L2_VOL_MASK (0x1 << 11)
358#define RT5651_STO_DD_L2_VOL_SFT 11
359#define RT5651_M_STO_DD_R2_L (0x1 << 10)
360#define RT5651_M_STO_DD_R2_L_SFT 10
361#define RT5651_STO_DD_R2_L_VOL_MASK (0x1 << 9)
362#define RT5651_STO_DD_R2_L_VOL_SFT 9
363#define RT5651_M_STO_DD_R1 (0x1 << 6)
364#define RT5651_M_STO_DD_R1_SFT 6
365#define RT5651_STO_DD_R1_VOL_MASK (0x1 << 5)
366#define RT5651_STO_DD_R1_VOL_SFT 5
367#define RT5651_M_STO_DD_R2 (0x1 << 4)
368#define RT5651_M_STO_DD_R2_SFT 4
369#define RT5651_STO_DD_R2_VOL_MASK (0x1 << 3)
370#define RT5651_STO_DD_R2_VOL_SFT 3
371#define RT5651_M_STO_DD_L2_R (0x1 << 2)
372#define RT5651_M_STO_DD_L2_R_SFT 2
373#define RT5651_STO_DD_L2_R_VOL_MASK (0x1 << 1)
374#define RT5651_STO_DD_L2_R_VOL_SFT 1
375
376/* Digital Mixer Control (0x2c) */
377#define RT5651_M_STO_L_DAC_L (0x1 << 15)
378#define RT5651_M_STO_L_DAC_L_SFT 15
379#define RT5651_STO_L_DAC_L_VOL_MASK (0x1 << 14)
380#define RT5651_STO_L_DAC_L_VOL_SFT 14
381#define RT5651_M_DAC_L2_DAC_L (0x1 << 13)
382#define RT5651_M_DAC_L2_DAC_L_SFT 13
383#define RT5651_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
384#define RT5651_DAC_L2_DAC_L_VOL_SFT 12
385#define RT5651_M_STO_R_DAC_R (0x1 << 11)
386#define RT5651_M_STO_R_DAC_R_SFT 11
387#define RT5651_STO_R_DAC_R_VOL_MASK (0x1 << 10)
388#define RT5651_STO_R_DAC_R_VOL_SFT 10
389#define RT5651_M_DAC_R2_DAC_R (0x1 << 9)
390#define RT5651_M_DAC_R2_DAC_R_SFT 9
391#define RT5651_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
392#define RT5651_DAC_R2_DAC_R_VOL_SFT 8
393
394/* DSP Path Control 1 (0x2d) */
395#define RT5651_RXDP_SRC_MASK (0x1 << 15)
396#define RT5651_RXDP_SRC_SFT 15
397#define RT5651_RXDP_SRC_NOR (0x0 << 15)
398#define RT5651_RXDP_SRC_DIV3 (0x1 << 15)
399#define RT5651_TXDP_SRC_MASK (0x1 << 14)
400#define RT5651_TXDP_SRC_SFT 14
401#define RT5651_TXDP_SRC_NOR (0x0 << 14)
402#define RT5651_TXDP_SRC_DIV3 (0x1 << 14)
403
404/* DSP Path Control 2 (0x2e) */
405#define RT5651_DAC_L2_SEL_MASK (0x3 << 14)
406#define RT5651_DAC_L2_SEL_SFT 14
407#define RT5651_DAC_L2_SEL_IF2 (0x0 << 14)
408#define RT5651_DAC_L2_SEL_IF3 (0x1 << 14)
409#define RT5651_DAC_L2_SEL_TXDC (0x2 << 14)
410#define RT5651_DAC_L2_SEL_BASS (0x3 << 14)
411#define RT5651_DAC_R2_SEL_MASK (0x3 << 12)
412#define RT5651_DAC_R2_SEL_SFT 12
413#define RT5651_DAC_R2_SEL_IF2 (0x0 << 12)
414#define RT5651_DAC_R2_SEL_IF3 (0x1 << 12)
415#define RT5651_DAC_R2_SEL_TXDC (0x2 << 12)
416#define RT5651_IF2_ADC_L_SEL_MASK (0x1 << 11)
417#define RT5651_IF2_ADC_L_SEL_SFT 11
418#define RT5651_IF2_ADC_L_SEL_TXDP (0x0 << 11)
419#define RT5651_IF2_ADC_L_SEL_PASS (0x1 << 11)
420#define RT5651_IF2_ADC_R_SEL_MASK (0x1 << 10)
421#define RT5651_IF2_ADC_R_SEL_SFT 10
422#define RT5651_IF2_ADC_R_SEL_TXDP (0x0 << 10)
423#define RT5651_IF2_ADC_R_SEL_PASS (0x1 << 10)
424#define RT5651_RXDC_SEL_MASK (0x3 << 8)
425#define RT5651_RXDC_SEL_SFT 8
426#define RT5651_RXDC_SEL_NOR (0x0 << 8)
427#define RT5651_RXDC_SEL_L2R (0x1 << 8)
428#define RT5651_RXDC_SEL_R2L (0x2 << 8)
429#define RT5651_RXDC_SEL_SWAP (0x3 << 8)
430#define RT5651_RXDP_SEL_MASK (0x3 << 6)
431#define RT5651_RXDP_SEL_SFT 6
432#define RT5651_RXDP_SEL_NOR (0x0 << 6)
433#define RT5651_RXDP_SEL_L2R (0x1 << 6)
434#define RT5651_RXDP_SEL_R2L (0x2 << 6)
435#define RT5651_RXDP_SEL_SWAP (0x3 << 6)
436#define RT5651_TXDC_SEL_MASK (0x3 << 4)
437#define RT5651_TXDC_SEL_SFT 4
438#define RT5651_TXDC_SEL_NOR (0x0 << 4)
439#define RT5651_TXDC_SEL_L2R (0x1 << 4)
440#define RT5651_TXDC_SEL_R2L (0x2 << 4)
441#define RT5651_TXDC_SEL_SWAP (0x3 << 4)
442#define RT5651_TXDP_SEL_MASK (0x3 << 2)
443#define RT5651_TXDP_SEL_SFT 2
444#define RT5651_TXDP_SEL_NOR (0x0 << 2)
445#define RT5651_TXDP_SEL_L2R (0x1 << 2)
446#define RT5651_TXDP_SEL_R2L (0x2 << 2)
447#define RT5651_TRXDP_SEL_SWAP (0x3 << 2)
448
449/* Digital Interface Data Control (0x2f) */
450#define RT5651_IF2_DAC_SEL_MASK (0x3 << 10)
451#define RT5651_IF2_DAC_SEL_SFT 10
452#define RT5651_IF2_DAC_SEL_NOR (0x0 << 10)
453#define RT5651_IF2_DAC_SEL_SWAP (0x1 << 10)
454#define RT5651_IF2_DAC_SEL_L2R (0x2 << 10)
455#define RT5651_IF2_DAC_SEL_R2L (0x3 << 10)
456#define RT5651_IF2_ADC_SEL_MASK (0x3 << 8)
457#define RT5651_IF2_ADC_SEL_SFT 8
458#define RT5651_IF2_ADC_SEL_NOR (0x0 << 8)
459#define RT5651_IF2_ADC_SEL_SWAP (0x1 << 8)
460#define RT5651_IF2_ADC_SEL_L2R (0x2 << 8)
461#define RT5651_IF2_ADC_SEL_R2L (0x3 << 8)
462#define RT5651_IF2_ADC_SRC_MASK (0x1 << 7)
463#define RT5651_IF2_ADC_SRC_SFT 7
464#define RT5651_IF1_ADC1 (0x0 << 7)
465#define RT5651_IF1_ADC2 (0x1 << 7)
466
467/* PDM Output Control (0x30) */
468#define RT5651_PDM_L_SEL_MASK (0x1 << 15)
469#define RT5651_PDM_L_SEL_SFT 15
470#define RT5651_PDM_L_SEL_DD_L (0x0 << 15)
471#define RT5651_PDM_L_SEL_STO_L (0x1 << 15)
472#define RT5651_M_PDM_L (0x1 << 14)
473#define RT5651_M_PDM_L_SFT 14
474#define RT5651_PDM_R_SEL_MASK (0x1 << 13)
475#define RT5651_PDM_R_SEL_SFT 13
476#define RT5651_PDM_R_SEL_DD_L (0x0 << 13)
477#define RT5651_PDM_R_SEL_STO_L (0x1 << 13)
478#define RT5651_M_PDM_R (0x1 << 12)
479#define RT5651_M_PDM_R_SFT 12
480#define RT5651_PDM_BUSY (0x1 << 6)
481#define RT5651_PDM_BUSY_SFT 6
482#define RT5651_PDM_PATTERN_SEL_MASK (0x1 << 5)
483#define RT5651_PDM_PATTERN_SEL_64 (0x0 << 5)
484#define RT5651_PDM_PATTERN_SEL_128 (0x1 << 5)
485#define RT5651_PDM_VOL_MASK (0x1 << 4)
486#define RT5651_PDM_VOL_SFT 4
487#define RT5651_PDM_DIV_MASK (0x3)
488#define RT5651_PDM_DIV_SFT 0
489#define RT5651_PDM_DIV_1 0
490#define RT5651_PDM_DIV_2 1
491#define RT5651_PDM_DIV_3 2
492#define RT5651_PDM_DIV_4 3
493
494/* PDM I2C/Data Control 1 (0x31) */
495#define RT5651_PDM_I2C_ID_MASK (0xf << 12)
496#define PT5631_PDM_CMD_EXE (0x1 << 11)
497#define RT5651_PDM_I2C_CMD_MASK (0x1 << 10)
498#define RT5651_PDM_I2C_CMD_R (0x0 << 10)
499#define RT5651_PDM_I2C_CMD_W (0x1 << 10)
500#define RT5651_PDM_I2C_CMD_EXE (0x1 << 9)
501#define RT5651_PDM_I2C_NORMAL (0x0 << 8)
502#define RT5651_PDM_I2C_BUSY (0x1 << 8)
503
504/* PDM I2C/Data Control 2 (0x32) */
505#define RT5651_PDM_I2C_ADDR (0xff << 8)
506#define RT5651_PDM_I2C_CMD_PATTERN (0xff)
507
508
509/* REC Left Mixer Control 1 (0x3b) */
510#define RT5651_G_LN_L2_RM_L_MASK (0x7 << 13)
511#define RT5651_G_IN_L2_RM_L_SFT 13
512#define RT5651_G_LN_L1_RM_L_MASK (0x7 << 10)
513#define RT5651_G_IN_L1_RM_L_SFT 10
514#define RT5651_G_BST3_RM_L_MASK (0x7 << 4)
515#define RT5651_G_BST3_RM_L_SFT 4
516#define RT5651_G_BST2_RM_L_MASK (0x7 << 1)
517#define RT5651_G_BST2_RM_L_SFT 1
518
519/* REC Left Mixer Control 2 (0x3c) */
520#define RT5651_G_BST1_RM_L_MASK (0x7 << 13)
521#define RT5651_G_BST1_RM_L_SFT 13
522#define RT5651_G_OM_L_RM_L_MASK (0x7 << 10)
523#define RT5651_G_OM_L_RM_L_SFT 10
524#define RT5651_M_IN2_L_RM_L (0x1 << 6)
525#define RT5651_M_IN2_L_RM_L_SFT 6
526#define RT5651_M_IN1_L_RM_L (0x1 << 5)
527#define RT5651_M_IN1_L_RM_L_SFT 5
528#define RT5651_M_BST3_RM_L (0x1 << 3)
529#define RT5651_M_BST3_RM_L_SFT 3
530#define RT5651_M_BST2_RM_L (0x1 << 2)
531#define RT5651_M_BST2_RM_L_SFT 2
532#define RT5651_M_BST1_RM_L (0x1 << 1)
533#define RT5651_M_BST1_RM_L_SFT 1
534#define RT5651_M_OM_L_RM_L (0x1)
535#define RT5651_M_OM_L_RM_L_SFT 0
536
537/* REC Right Mixer Control 1 (0x3d) */
538#define RT5651_G_IN2_R_RM_R_MASK (0x7 << 13)
539#define RT5651_G_IN2_R_RM_R_SFT 13
540#define RT5651_G_IN1_R_RM_R_MASK (0x7 << 10)
541#define RT5651_G_IN1_R_RM_R_SFT 10
542#define RT5651_G_BST3_RM_R_MASK (0x7 << 4)
543#define RT5651_G_BST3_RM_R_SFT 4
544#define RT5651_G_BST2_RM_R_MASK (0x7 << 1)
545#define RT5651_G_BST2_RM_R_SFT 1
546
547/* REC Right Mixer Control 2 (0x3e) */
548#define RT5651_G_BST1_RM_R_MASK (0x7 << 13)
549#define RT5651_G_BST1_RM_R_SFT 13
550#define RT5651_G_OM_R_RM_R_MASK (0x7 << 10)
551#define RT5651_G_OM_R_RM_R_SFT 10
552#define RT5651_M_IN2_R_RM_R (0x1 << 6)
553#define RT5651_M_IN2_R_RM_R_SFT 6
554#define RT5651_M_IN1_R_RM_R (0x1 << 5)
555#define RT5651_M_IN1_R_RM_R_SFT 5
556#define RT5651_M_BST3_RM_R (0x1 << 3)
557#define RT5651_M_BST3_RM_R_SFT 3
558#define RT5651_M_BST2_RM_R (0x1 << 2)
559#define RT5651_M_BST2_RM_R_SFT 2
560#define RT5651_M_BST1_RM_R (0x1 << 1)
561#define RT5651_M_BST1_RM_R_SFT 1
562#define RT5651_M_OM_R_RM_R (0x1)
563#define RT5651_M_OM_R_RM_R_SFT 0
564
565/* HPMIX Control (0x45) */
566#define RT5651_M_DAC1_HM (0x1 << 14)
567#define RT5651_M_DAC1_HM_SFT 14
568#define RT5651_M_HPVOL_HM (0x1 << 13)
569#define RT5651_M_HPVOL_HM_SFT 13
570#define RT5651_G_HPOMIX_MASK (0x1 << 12)
571#define RT5651_G_HPOMIX_SFT 12
572
573/* SPK Left Mixer Control (0x46) */
574#define RT5651_G_RM_L_SM_L_MASK (0x3 << 14)
575#define RT5651_G_RM_L_SM_L_SFT 14
576#define RT5651_G_IN_L_SM_L_MASK (0x3 << 12)
577#define RT5651_G_IN_L_SM_L_SFT 12
578#define RT5651_G_DAC_L1_SM_L_MASK (0x3 << 10)
579#define RT5651_G_DAC_L1_SM_L_SFT 10
580#define RT5651_G_DAC_L2_SM_L_MASK (0x3 << 8)
581#define RT5651_G_DAC_L2_SM_L_SFT 8
582#define RT5651_G_OM_L_SM_L_MASK (0x3 << 6)
583#define RT5651_G_OM_L_SM_L_SFT 6
584#define RT5651_M_RM_L_SM_L (0x1 << 5)
585#define RT5651_M_RM_L_SM_L_SFT 5
586#define RT5651_M_IN_L_SM_L (0x1 << 4)
587#define RT5651_M_IN_L_SM_L_SFT 4
588#define RT5651_M_DAC_L1_SM_L (0x1 << 3)
589#define RT5651_M_DAC_L1_SM_L_SFT 3
590#define RT5651_M_DAC_L2_SM_L (0x1 << 2)
591#define RT5651_M_DAC_L2_SM_L_SFT 2
592#define RT5651_M_OM_L_SM_L (0x1 << 1)
593#define RT5651_M_OM_L_SM_L_SFT 1
594
595/* SPK Right Mixer Control (0x47) */
596#define RT5651_G_RM_R_SM_R_MASK (0x3 << 14)
597#define RT5651_G_RM_R_SM_R_SFT 14
598#define RT5651_G_IN_R_SM_R_MASK (0x3 << 12)
599#define RT5651_G_IN_R_SM_R_SFT 12
600#define RT5651_G_DAC_R1_SM_R_MASK (0x3 << 10)
601#define RT5651_G_DAC_R1_SM_R_SFT 10
602#define RT5651_G_DAC_R2_SM_R_MASK (0x3 << 8)
603#define RT5651_G_DAC_R2_SM_R_SFT 8
604#define RT5651_G_OM_R_SM_R_MASK (0x3 << 6)
605#define RT5651_G_OM_R_SM_R_SFT 6
606#define RT5651_M_RM_R_SM_R (0x1 << 5)
607#define RT5651_M_RM_R_SM_R_SFT 5
608#define RT5651_M_IN_R_SM_R (0x1 << 4)
609#define RT5651_M_IN_R_SM_R_SFT 4
610#define RT5651_M_DAC_R1_SM_R (0x1 << 3)
611#define RT5651_M_DAC_R1_SM_R_SFT 3
612#define RT5651_M_DAC_R2_SM_R (0x1 << 2)
613#define RT5651_M_DAC_R2_SM_R_SFT 2
614#define RT5651_M_OM_R_SM_R (0x1 << 1)
615#define RT5651_M_OM_R_SM_R_SFT 1
616
617/* SPOLMIX Control (0x48) */
618#define RT5651_M_DAC_R1_SPM_L (0x1 << 15)
619#define RT5651_M_DAC_R1_SPM_L_SFT 15
620#define RT5651_M_DAC_L1_SPM_L (0x1 << 14)
621#define RT5651_M_DAC_L1_SPM_L_SFT 14
622#define RT5651_M_SV_R_SPM_L (0x1 << 13)
623#define RT5651_M_SV_R_SPM_L_SFT 13
624#define RT5651_M_SV_L_SPM_L (0x1 << 12)
625#define RT5651_M_SV_L_SPM_L_SFT 12
626#define RT5651_M_BST1_SPM_L (0x1 << 11)
627#define RT5651_M_BST1_SPM_L_SFT 11
628
629/* SPORMIX Control (0x49) */
630#define RT5651_M_DAC_R1_SPM_R (0x1 << 13)
631#define RT5651_M_DAC_R1_SPM_R_SFT 13
632#define RT5651_M_SV_R_SPM_R (0x1 << 12)
633#define RT5651_M_SV_R_SPM_R_SFT 12
634#define RT5651_M_BST1_SPM_R (0x1 << 11)
635#define RT5651_M_BST1_SPM_R_SFT 11
636
637/* SPOLMIX / SPORMIX Ratio Control (0x4a) */
638#define RT5651_SPO_CLSD_RATIO_MASK (0x7)
639#define RT5651_SPO_CLSD_RATIO_SFT 0
640
641/* Mono Output Mixer Control (0x4c) */
642#define RT5651_M_DAC_R2_MM (0x1 << 15)
643#define RT5651_M_DAC_R2_MM_SFT 15
644#define RT5651_M_DAC_L2_MM (0x1 << 14)
645#define RT5651_M_DAC_L2_MM_SFT 14
646#define RT5651_M_OV_R_MM (0x1 << 13)
647#define RT5651_M_OV_R_MM_SFT 13
648#define RT5651_M_OV_L_MM (0x1 << 12)
649#define RT5651_M_OV_L_MM_SFT 12
650#define RT5651_M_BST1_MM (0x1 << 11)
651#define RT5651_M_BST1_MM_SFT 11
652#define RT5651_G_MONOMIX_MASK (0x1 << 10)
653#define RT5651_G_MONOMIX_SFT 10
654
655/* Output Left Mixer Control 1 (0x4d) */
656#define RT5651_G_BST2_OM_L_MASK (0x7 << 10)
657#define RT5651_G_BST2_OM_L_SFT 10
658#define RT5651_G_BST1_OM_L_MASK (0x7 << 7)
659#define RT5651_G_BST1_OM_L_SFT 7
660#define RT5651_G_IN1_L_OM_L_MASK (0x7 << 4)
661#define RT5651_G_IN1_L_OM_L_SFT 4
662#define RT5651_G_RM_L_OM_L_MASK (0x7 << 1)
663#define RT5651_G_RM_L_OM_L_SFT 1
664
665/* Output Left Mixer Control 2 (0x4e) */
666#define RT5651_G_DAC_L1_OM_L_MASK (0x7 << 7)
667#define RT5651_G_DAC_L1_OM_L_SFT 7
668#define RT5651_G_IN2_L_OM_L_MASK (0x7 << 4)
669#define RT5651_G_IN2_L_OM_L_SFT 4
670
671/* Output Left Mixer Control 3 (0x4f) */
672#define RT5651_M_IN2_L_OM_L (0x1 << 9)
673#define RT5651_M_IN2_L_OM_L_SFT 9
674#define RT5651_M_BST2_OM_L (0x1 << 6)
675#define RT5651_M_BST2_OM_L_SFT 6
676#define RT5651_M_BST1_OM_L (0x1 << 5)
677#define RT5651_M_BST1_OM_L_SFT 5
678#define RT5651_M_IN1_L_OM_L (0x1 << 4)
679#define RT5651_M_IN1_L_OM_L_SFT 4
680#define RT5651_M_RM_L_OM_L (0x1 << 3)
681#define RT5651_M_RM_L_OM_L_SFT 3
682#define RT5651_M_DAC_L1_OM_L (0x1)
683#define RT5651_M_DAC_L1_OM_L_SFT 0
684
685/* Output Right Mixer Control 1 (0x50) */
686#define RT5651_G_BST2_OM_R_MASK (0x7 << 10)
687#define RT5651_G_BST2_OM_R_SFT 10
688#define RT5651_G_BST1_OM_R_MASK (0x7 << 7)
689#define RT5651_G_BST1_OM_R_SFT 7
690#define RT5651_G_IN1_R_OM_R_MASK (0x7 << 4)
691#define RT5651_G_IN1_R_OM_R_SFT 4
692#define RT5651_G_RM_R_OM_R_MASK (0x7 << 1)
693#define RT5651_G_RM_R_OM_R_SFT 1
694
695/* Output Right Mixer Control 2 (0x51) */
696#define RT5651_G_DAC_R1_OM_R_MASK (0x7 << 7)
697#define RT5651_G_DAC_R1_OM_R_SFT 7
698#define RT5651_G_IN2_R_OM_R_MASK (0x7 << 4)
699#define RT5651_G_IN2_R_OM_R_SFT 4
700
701/* Output Right Mixer Control 3 (0x52) */
702#define RT5651_M_IN2_R_OM_R (0x1 << 9)
703#define RT5651_M_IN2_R_OM_R_SFT 9
704#define RT5651_M_BST2_OM_R (0x1 << 6)
705#define RT5651_M_BST2_OM_R_SFT 6
706#define RT5651_M_BST1_OM_R (0x1 << 5)
707#define RT5651_M_BST1_OM_R_SFT 5
708#define RT5651_M_IN1_R_OM_R (0x1 << 4)
709#define RT5651_M_IN1_R_OM_R_SFT 4
710#define RT5651_M_RM_R_OM_R (0x1 << 3)
711#define RT5651_M_RM_R_OM_R_SFT 3
712#define RT5651_M_DAC_R1_OM_R (0x1)
713#define RT5651_M_DAC_R1_OM_R_SFT 0
714
715/* LOUT Mixer Control (0x53) */
716#define RT5651_M_DAC_L1_LM (0x1 << 15)
717#define RT5651_M_DAC_L1_LM_SFT 15
718#define RT5651_M_DAC_R1_LM (0x1 << 14)
719#define RT5651_M_DAC_R1_LM_SFT 14
720#define RT5651_M_OV_L_LM (0x1 << 13)
721#define RT5651_M_OV_L_LM_SFT 13
722#define RT5651_M_OV_R_LM (0x1 << 12)
723#define RT5651_M_OV_R_LM_SFT 12
724#define RT5651_G_LOUTMIX_MASK (0x1 << 11)
725#define RT5651_G_LOUTMIX_SFT 11
726
727/* Power Management for Digital 1 (0x61) */
728#define RT5651_PWR_I2S1 (0x1 << 15)
729#define RT5651_PWR_I2S1_BIT 15
730#define RT5651_PWR_I2S2 (0x1 << 14)
731#define RT5651_PWR_I2S2_BIT 14
732#define RT5651_PWR_DAC_L1 (0x1 << 12)
733#define RT5651_PWR_DAC_L1_BIT 12
734#define RT5651_PWR_DAC_R1 (0x1 << 11)
735#define RT5651_PWR_DAC_R1_BIT 11
736#define RT5651_PWR_ADC_L (0x1 << 2)
737#define RT5651_PWR_ADC_L_BIT 2
738#define RT5651_PWR_ADC_R (0x1 << 1)
739#define RT5651_PWR_ADC_R_BIT 1
740
741/* Power Management for Digital 2 (0x62) */
742#define RT5651_PWR_ADC_STO1_F (0x1 << 15)
743#define RT5651_PWR_ADC_STO1_F_BIT 15
744#define RT5651_PWR_ADC_STO2_F (0x1 << 14)
745#define RT5651_PWR_ADC_STO2_F_BIT 14
746#define RT5651_PWR_DAC_STO1_F (0x1 << 11)
747#define RT5651_PWR_DAC_STO1_F_BIT 11
748#define RT5651_PWR_DAC_STO2_F (0x1 << 10)
749#define RT5651_PWR_DAC_STO2_F_BIT 10
750#define RT5651_PWR_PDM (0x1 << 9)
751#define RT5651_PWR_PDM_BIT 9
752
753/* Power Management for Analog 1 (0x63) */
754#define RT5651_PWR_VREF1 (0x1 << 15)
755#define RT5651_PWR_VREF1_BIT 15
756#define RT5651_PWR_FV1 (0x1 << 14)
757#define RT5651_PWR_FV1_BIT 14
758#define RT5651_PWR_MB (0x1 << 13)
759#define RT5651_PWR_MB_BIT 13
760#define RT5651_PWR_LM (0x1 << 12)
761#define RT5651_PWR_LM_BIT 12
762#define RT5651_PWR_BG (0x1 << 11)
763#define RT5651_PWR_BG_BIT 11
764#define RT5651_PWR_HP_L (0x1 << 7)
765#define RT5651_PWR_HP_L_BIT 7
766#define RT5651_PWR_HP_R (0x1 << 6)
767#define RT5651_PWR_HP_R_BIT 6
768#define RT5651_PWR_HA (0x1 << 5)
769#define RT5651_PWR_HA_BIT 5
770#define RT5651_PWR_VREF2 (0x1 << 4)
771#define RT5651_PWR_VREF2_BIT 4
772#define RT5651_PWR_FV2 (0x1 << 3)
773#define RT5651_PWR_FV2_BIT 3
774#define RT5651_PWR_LDO (0x1 << 2)
775#define RT5651_PWR_LDO_BIT 2
776#define RT5651_PWR_LDO_DVO_MASK (0x3)
777#define RT5651_PWR_LDO_DVO_1_0V 0
778#define RT5651_PWR_LDO_DVO_1_1V 1
779#define RT5651_PWR_LDO_DVO_1_2V 2
780#define RT5651_PWR_LDO_DVO_1_3V 3
781
782/* Power Management for Analog 2 (0x64) */
783#define RT5651_PWR_BST1 (0x1 << 15)
784#define RT5651_PWR_BST1_BIT 15
785#define RT5651_PWR_BST2 (0x1 << 14)
786#define RT5651_PWR_BST2_BIT 14
787#define RT5651_PWR_BST3 (0x1 << 13)
788#define RT5651_PWR_BST3_BIT 13
789#define RT5651_PWR_MB1 (0x1 << 11)
790#define RT5651_PWR_MB1_BIT 11
791#define RT5651_PWR_PLL (0x1 << 9)
792#define RT5651_PWR_PLL_BIT 9
793#define RT5651_PWR_BST1_OP2 (0x1 << 5)
794#define RT5651_PWR_BST1_OP2_BIT 5
795#define RT5651_PWR_BST2_OP2 (0x1 << 4)
796#define RT5651_PWR_BST2_OP2_BIT 4
797#define RT5651_PWR_BST3_OP2 (0x1 << 3)
798#define RT5651_PWR_BST3_OP2_BIT 3
799#define RT5651_PWR_JD_M (0x1 << 2)
800#define RT5651_PWM_JD_M_BIT 2
801#define RT5651_PWR_JD2 (0x1 << 1)
802#define RT5651_PWM_JD2_BIT 1
803#define RT5651_PWR_JD3 (0x1)
804#define RT5651_PWM_JD3_BIT 0
805
806/* Power Management for Mixer (0x65) */
807#define RT5651_PWR_OM_L (0x1 << 15)
808#define RT5651_PWR_OM_L_BIT 15
809#define RT5651_PWR_OM_R (0x1 << 14)
810#define RT5651_PWR_OM_R_BIT 14
811#define RT5651_PWR_RM_L (0x1 << 11)
812#define RT5651_PWR_RM_L_BIT 11
813#define RT5651_PWR_RM_R (0x1 << 10)
814#define RT5651_PWR_RM_R_BIT 10
815
816/* Power Management for Volume (0x66) */
817#define RT5651_PWR_OV_L (0x1 << 13)
818#define RT5651_PWR_OV_L_BIT 13
819#define RT5651_PWR_OV_R (0x1 << 12)
820#define RT5651_PWR_OV_R_BIT 12
821#define RT5651_PWR_HV_L (0x1 << 11)
822#define RT5651_PWR_HV_L_BIT 11
823#define RT5651_PWR_HV_R (0x1 << 10)
824#define RT5651_PWR_HV_R_BIT 10
825#define RT5651_PWR_IN1_L (0x1 << 9)
826#define RT5651_PWR_IN1_L_BIT 9
827#define RT5651_PWR_IN1_R (0x1 << 8)
828#define RT5651_PWR_IN1_R_BIT 8
829#define RT5651_PWR_IN2_L (0x1 << 7)
830#define RT5651_PWR_IN2_L_BIT 7
831#define RT5651_PWR_IN2_R (0x1 << 6)
832#define RT5651_PWR_IN2_R_BIT 6
833
834/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71) */
835#define RT5651_I2S_MS_MASK (0x1 << 15)
836#define RT5651_I2S_MS_SFT 15
837#define RT5651_I2S_MS_M (0x0 << 15)
838#define RT5651_I2S_MS_S (0x1 << 15)
839#define RT5651_I2S_O_CP_MASK (0x3 << 10)
840#define RT5651_I2S_O_CP_SFT 10
841#define RT5651_I2S_O_CP_OFF (0x0 << 10)
842#define RT5651_I2S_O_CP_U_LAW (0x1 << 10)
843#define RT5651_I2S_O_CP_A_LAW (0x2 << 10)
844#define RT5651_I2S_I_CP_MASK (0x3 << 8)
845#define RT5651_I2S_I_CP_SFT 8
846#define RT5651_I2S_I_CP_OFF (0x0 << 8)
847#define RT5651_I2S_I_CP_U_LAW (0x1 << 8)
848#define RT5651_I2S_I_CP_A_LAW (0x2 << 8)
849#define RT5651_I2S_BP_MASK (0x1 << 7)
850#define RT5651_I2S_BP_SFT 7
851#define RT5651_I2S_BP_NOR (0x0 << 7)
852#define RT5651_I2S_BP_INV (0x1 << 7)
853#define RT5651_I2S_DL_MASK (0x3 << 2)
854#define RT5651_I2S_DL_SFT 2
855#define RT5651_I2S_DL_16 (0x0 << 2)
856#define RT5651_I2S_DL_20 (0x1 << 2)
857#define RT5651_I2S_DL_24 (0x2 << 2)
858#define RT5651_I2S_DL_8 (0x3 << 2)
859#define RT5651_I2S_DF_MASK (0x3)
860#define RT5651_I2S_DF_SFT 0
861#define RT5651_I2S_DF_I2S (0x0)
862#define RT5651_I2S_DF_LEFT (0x1)
863#define RT5651_I2S_DF_PCM_A (0x2)
864#define RT5651_I2S_DF_PCM_B (0x3)
865
866/* ADC/DAC Clock Control 1 (0x73) */
867#define RT5651_I2S_PD1_MASK (0x7 << 12)
868#define RT5651_I2S_PD1_SFT 12
869#define RT5651_I2S_PD1_1 (0x0 << 12)
870#define RT5651_I2S_PD1_2 (0x1 << 12)
871#define RT5651_I2S_PD1_3 (0x2 << 12)
872#define RT5651_I2S_PD1_4 (0x3 << 12)
873#define RT5651_I2S_PD1_6 (0x4 << 12)
874#define RT5651_I2S_PD1_8 (0x5 << 12)
875#define RT5651_I2S_PD1_12 (0x6 << 12)
876#define RT5651_I2S_PD1_16 (0x7 << 12)
877#define RT5651_I2S_BCLK_MS2_MASK (0x1 << 11)
878#define RT5651_I2S_BCLK_MS2_SFT 11
879#define RT5651_I2S_BCLK_MS2_32 (0x0 << 11)
880#define RT5651_I2S_BCLK_MS2_64 (0x1 << 11)
881#define RT5651_I2S_PD2_MASK (0x7 << 8)
882#define RT5651_I2S_PD2_SFT 8
883#define RT5651_I2S_PD2_1 (0x0 << 8)
884#define RT5651_I2S_PD2_2 (0x1 << 8)
885#define RT5651_I2S_PD2_3 (0x2 << 8)
886#define RT5651_I2S_PD2_4 (0x3 << 8)
887#define RT5651_I2S_PD2_6 (0x4 << 8)
888#define RT5651_I2S_PD2_8 (0x5 << 8)
889#define RT5651_I2S_PD2_12 (0x6 << 8)
890#define RT5651_I2S_PD2_16 (0x7 << 8)
891#define RT5651_DAC_OSR_MASK (0x3 << 2)
892#define RT5651_DAC_OSR_SFT 2
893#define RT5651_DAC_OSR_128 (0x0 << 2)
894#define RT5651_DAC_OSR_64 (0x1 << 2)
895#define RT5651_DAC_OSR_32 (0x2 << 2)
896#define RT5651_DAC_OSR_128_3 (0x3 << 2)
897#define RT5651_ADC_OSR_MASK (0x3)
898#define RT5651_ADC_OSR_SFT 0
899#define RT5651_ADC_OSR_128 (0x0)
900#define RT5651_ADC_OSR_64 (0x1)
901#define RT5651_ADC_OSR_32 (0x2)
902#define RT5651_ADC_OSR_128_3 (0x3)
903
904/* ADC/DAC Clock Control 2 (0x74) */
905#define RT5651_DAHPF_EN (0x1 << 11)
906#define RT5651_DAHPF_EN_SFT 11
907#define RT5651_ADHPF_EN (0x1 << 10)
908#define RT5651_ADHPF_EN_SFT 10
909
910/* Digital Microphone Control (0x75) */
911#define RT5651_DMIC_1_EN_MASK (0x1 << 15)
912#define RT5651_DMIC_1_EN_SFT 15
913#define RT5651_DMIC_1_DIS (0x0 << 15)
914#define RT5651_DMIC_1_EN (0x1 << 15)
915#define RT5651_DMIC_1L_LH_MASK (0x1 << 13)
916#define RT5651_DMIC_1L_LH_SFT 13
917#define RT5651_DMIC_1L_LH_FALLING (0x0 << 13)
918#define RT5651_DMIC_1L_LH_RISING (0x1 << 13)
919#define RT5651_DMIC_1R_LH_MASK (0x1 << 12)
920#define RT5651_DMIC_1R_LH_SFT 12
921#define RT5651_DMIC_1R_LH_FALLING (0x0 << 12)
922#define RT5651_DMIC_1R_LH_RISING (0x1 << 12)
923#define RT5651_DMIC_1_DP_MASK (0x3 << 10)
924#define RT5651_DMIC_1_DP_SFT 10
925#define RT5651_DMIC_1_DP_GPIO6 (0x0 << 10)
926#define RT5651_DMIC_1_DP_IN1P (0x1 << 10)
927#define RT5651_DMIC_2_DP_GPIO8 (0x2 << 10)
928#define RT5651_DMIC_CLK_MASK (0x7 << 5)
929#define RT5651_DMIC_CLK_SFT 5
930
931/* TDM Control 1 (0x77) */
932#define RT5651_TDM_INTEL_SEL_MASK (0x1 << 15)
933#define RT5651_TDM_INTEL_SEL_SFT 15
934#define RT5651_TDM_INTEL_SEL_64 (0x0 << 15)
935#define RT5651_TDM_INTEL_SEL_50 (0x1 << 15)
936#define RT5651_TDM_MODE_SEL_MASK (0x1 << 14)
937#define RT5651_TDM_MODE_SEL_SFT 14
938#define RT5651_TDM_MODE_SEL_NOR (0x0 << 14)
939#define RT5651_TDM_MODE_SEL_TDM (0x1 << 14)
940#define RT5651_TDM_CH_NUM_SEL_MASK (0x3 << 12)
941#define RT5651_TDM_CH_NUM_SEL_SFT 12
942#define RT5651_TDM_CH_NUM_SEL_2 (0x0 << 12)
943#define RT5651_TDM_CH_NUM_SEL_4 (0x1 << 12)
944#define RT5651_TDM_CH_NUM_SEL_6 (0x2 << 12)
945#define RT5651_TDM_CH_NUM_SEL_8 (0x3 << 12)
946#define RT5651_TDM_CH_LEN_SEL_MASK (0x3 << 10)
947#define RT5651_TDM_CH_LEN_SEL_SFT 10
948#define RT5651_TDM_CH_LEN_SEL_16 (0x0 << 10)
949#define RT5651_TDM_CH_LEN_SEL_20 (0x1 << 10)
950#define RT5651_TDM_CH_LEN_SEL_24 (0x2 << 10)
951#define RT5651_TDM_CH_LEN_SEL_32 (0x3 << 10)
952#define RT5651_TDM_ADC_SEL_MASK (0x1 << 9)
953#define RT5651_TDM_ADC_SEL_SFT 9
954#define RT5651_TDM_ADC_SEL_NOR (0x0 << 9)
955#define RT5651_TDM_ADC_SEL_SWAP (0x1 << 9)
956#define RT5651_TDM_ADC_START_SEL_MASK (0x1 << 8)
957#define RT5651_TDM_ADC_START_SEL_SFT 8
958#define RT5651_TDM_ADC_START_SEL_SL0 (0x0 << 8)
959#define RT5651_TDM_ADC_START_SEL_SL4 (0x1 << 8)
960#define RT5651_TDM_I2S_CH2_SEL_MASK (0x3 << 6)
961#define RT5651_TDM_I2S_CH2_SEL_SFT 6
962#define RT5651_TDM_I2S_CH2_SEL_LR (0x0 << 6)
963#define RT5651_TDM_I2S_CH2_SEL_RL (0x1 << 6)
964#define RT5651_TDM_I2S_CH2_SEL_LL (0x2 << 6)
965#define RT5651_TDM_I2S_CH2_SEL_RR (0x3 << 6)
966#define RT5651_TDM_I2S_CH4_SEL_MASK (0x3 << 4)
967#define RT5651_TDM_I2S_CH4_SEL_SFT 4
968#define RT5651_TDM_I2S_CH4_SEL_LR (0x0 << 4)
969#define RT5651_TDM_I2S_CH4_SEL_RL (0x1 << 4)
970#define RT5651_TDM_I2S_CH4_SEL_LL (0x2 << 4)
971#define RT5651_TDM_I2S_CH4_SEL_RR (0x3 << 4)
972#define RT5651_TDM_I2S_CH6_SEL_MASK (0x3 << 2)
973#define RT5651_TDM_I2S_CH6_SEL_SFT 2
974#define RT5651_TDM_I2S_CH6_SEL_LR (0x0 << 2)
975#define RT5651_TDM_I2S_CH6_SEL_RL (0x1 << 2)
976#define RT5651_TDM_I2S_CH6_SEL_LL (0x2 << 2)
977#define RT5651_TDM_I2S_CH6_SEL_RR (0x3 << 2)
978#define RT5651_TDM_I2S_CH8_SEL_MASK (0x3)
979#define RT5651_TDM_I2S_CH8_SEL_SFT 0
980#define RT5651_TDM_I2S_CH8_SEL_LR (0x0)
981#define RT5651_TDM_I2S_CH8_SEL_RL (0x1)
982#define RT5651_TDM_I2S_CH8_SEL_LL (0x2)
983#define RT5651_TDM_I2S_CH8_SEL_RR (0x3)
984
985/* TDM Control 2 (0x78) */
986#define RT5651_TDM_LRCK_POL_SEL_MASK (0x1 << 15)
987#define RT5651_TDM_LRCK_POL_SEL_SFT 15
988#define RT5651_TDM_LRCK_POL_SEL_NOR (0x0 << 15)
989#define RT5651_TDM_LRCK_POL_SEL_INV (0x1 << 15)
990#define RT5651_TDM_CH_VAL_SEL_MASK (0x1 << 14)
991#define RT5651_TDM_CH_VAL_SEL_SFT 14
992#define RT5651_TDM_CH_VAL_SEL_CH01 (0x0 << 14)
993#define RT5651_TDM_CH_VAL_SEL_CH0123 (0x1 << 14)
994#define RT5651_TDM_CH_VAL_EN (0x1 << 13)
995#define RT5651_TDM_CH_VAL_SFT 13
996#define RT5651_TDM_LPBK_EN (0x1 << 12)
997#define RT5651_TDM_LPBK_SFT 12
998#define RT5651_TDM_LRCK_PULSE_SEL_MASK (0x1 << 11)
999#define RT5651_TDM_LRCK_PULSE_SEL_SFT 11
1000#define RT5651_TDM_LRCK_PULSE_SEL_BCLK (0x0 << 11)
1001#define RT5651_TDM_LRCK_PULSE_SEL_CH (0x1 << 11)
1002#define RT5651_TDM_END_EDGE_SEL_MASK (0x1 << 10)
1003#define RT5651_TDM_END_EDGE_SEL_SFT 10
1004#define RT5651_TDM_END_EDGE_SEL_POS (0x0 << 10)
1005#define RT5651_TDM_END_EDGE_SEL_NEG (0x1 << 10)
1006#define RT5651_TDM_END_EDGE_EN (0x1 << 9)
1007#define RT5651_TDM_END_EDGE_EN_SFT 9
1008#define RT5651_TDM_TRAN_EDGE_SEL_MASK (0x1 << 8)
1009#define RT5651_TDM_TRAN_EDGE_SEL_SFT 8
1010#define RT5651_TDM_TRAN_EDGE_SEL_POS (0x0 << 8)
1011#define RT5651_TDM_TRAN_EDGE_SEL_NEG (0x1 << 8)
1012#define RT5651_M_TDM2_L (0x1 << 7)
1013#define RT5651_M_TDM2_L_SFT 7
1014#define RT5651_M_TDM2_R (0x1 << 6)
1015#define RT5651_M_TDM2_R_SFT 6
1016#define RT5651_M_TDM4_L (0x1 << 5)
1017#define RT5651_M_TDM4_L_SFT 5
1018#define RT5651_M_TDM4_R (0x1 << 4)
1019#define RT5651_M_TDM4_R_SFT 4
1020
1021/* TDM Control 3 (0x79) */
1022#define RT5651_CH2_L_SEL_MASK (0x7 << 12)
1023#define RT5651_CH2_L_SEL_SFT 12
1024#define RT5651_CH2_L_SEL_SL0 (0x0 << 12)
1025#define RT5651_CH2_L_SEL_SL1 (0x1 << 12)
1026#define RT5651_CH2_L_SEL_SL2 (0x2 << 12)
1027#define RT5651_CH2_L_SEL_SL3 (0x3 << 12)
1028#define RT5651_CH2_L_SEL_SL4 (0x4 << 12)
1029#define RT5651_CH2_L_SEL_SL5 (0x5 << 12)
1030#define RT5651_CH2_L_SEL_SL6 (0x6 << 12)
1031#define RT5651_CH2_L_SEL_SL7 (0x7 << 12)
1032#define RT5651_CH2_R_SEL_MASK (0x7 << 8)
1033#define RT5651_CH2_R_SEL_SFT 8
1034#define RT5651_CH2_R_SEL_SL0 (0x0 << 8)
1035#define RT5651_CH2_R_SEL_SL1 (0x1 << 8)
1036#define RT5651_CH2_R_SEL_SL2 (0x2 << 8)
1037#define RT5651_CH2_R_SEL_SL3 (0x3 << 8)
1038#define RT5651_CH2_R_SEL_SL4 (0x4 << 8)
1039#define RT5651_CH2_R_SEL_SL5 (0x5 << 8)
1040#define RT5651_CH2_R_SEL_SL6 (0x6 << 8)
1041#define RT5651_CH2_R_SEL_SL7 (0x7 << 8)
1042#define RT5651_CH4_L_SEL_MASK (0x7 << 4)
1043#define RT5651_CH4_L_SEL_SFT 4
1044#define RT5651_CH4_L_SEL_SL0 (0x0 << 4)
1045#define RT5651_CH4_L_SEL_SL1 (0x1 << 4)
1046#define RT5651_CH4_L_SEL_SL2 (0x2 << 4)
1047#define RT5651_CH4_L_SEL_SL3 (0x3 << 4)
1048#define RT5651_CH4_L_SEL_SL4 (0x4 << 4)
1049#define RT5651_CH4_L_SEL_SL5 (0x5 << 4)
1050#define RT5651_CH4_L_SEL_SL6 (0x6 << 4)
1051#define RT5651_CH4_L_SEL_SL7 (0x7 << 4)
1052#define RT5651_CH4_R_SEL_MASK (0x7)
1053#define RT5651_CH4_R_SEL_SFT 0
1054#define RT5651_CH4_R_SEL_SL0 (0x0)
1055#define RT5651_CH4_R_SEL_SL1 (0x1)
1056#define RT5651_CH4_R_SEL_SL2 (0x2)
1057#define RT5651_CH4_R_SEL_SL3 (0x3)
1058#define RT5651_CH4_R_SEL_SL4 (0x4)
1059#define RT5651_CH4_R_SEL_SL5 (0x5)
1060#define RT5651_CH4_R_SEL_SL6 (0x6)
1061#define RT5651_CH4_R_SEL_SL7 (0x7)
1062
1063/* Global Clock Control (0x80) */
1064#define RT5651_SCLK_SRC_MASK (0x3 << 14)
1065#define RT5651_SCLK_SRC_SFT 14
1066#define RT5651_SCLK_SRC_MCLK (0x0 << 14)
1067#define RT5651_SCLK_SRC_PLL1 (0x1 << 14)
1068#define RT5651_SCLK_SRC_RCCLK (0x2 << 14)
1069#define RT5651_PLL1_SRC_MASK (0x3 << 12)
1070#define RT5651_PLL1_SRC_SFT 12
1071#define RT5651_PLL1_SRC_MCLK (0x0 << 12)
1072#define RT5651_PLL1_SRC_BCLK1 (0x1 << 12)
1073#define RT5651_PLL1_SRC_BCLK2 (0x2 << 12)
1074#define RT5651_PLL1_PD_MASK (0x1 << 3)
1075#define RT5651_PLL1_PD_SFT 3
1076#define RT5651_PLL1_PD_1 (0x0 << 3)
1077#define RT5651_PLL1_PD_2 (0x1 << 3)
1078
1079#define RT5651_PLL_INP_MAX 40000000
1080#define RT5651_PLL_INP_MIN 256000
1081/* PLL M/N/K Code Control 1 (0x81) */
1082#define RT5651_PLL_N_MAX 0x1ff
1083#define RT5651_PLL_N_MASK (RT5651_PLL_N_MAX << 7)
1084#define RT5651_PLL_N_SFT 7
1085#define RT5651_PLL_K_MAX 0x1f
1086#define RT5651_PLL_K_MASK (RT5651_PLL_K_MAX)
1087#define RT5651_PLL_K_SFT 0
1088
1089/* PLL M/N/K Code Control 2 (0x82) */
1090#define RT5651_PLL_M_MAX 0xf
1091#define RT5651_PLL_M_MASK (RT5651_PLL_M_MAX << 12)
1092#define RT5651_PLL_M_SFT 12
1093#define RT5651_PLL_M_BP (0x1 << 11)
1094#define RT5651_PLL_M_BP_SFT 11
1095
1096/* PLL tracking mode 1 (0x83) */
1097#define RT5651_STO1_T_MASK (0x1 << 15)
1098#define RT5651_STO1_T_SFT 15
1099#define RT5651_STO1_T_SCLK (0x0 << 15)
1100#define RT5651_STO1_T_LRCK1 (0x1 << 15)
1101#define RT5651_STO2_T_MASK (0x1 << 12)
1102#define RT5651_STO2_T_SFT 12
1103#define RT5651_STO2_T_I2S2 (0x0 << 12)
1104#define RT5651_STO2_T_LRCK2 (0x1 << 12)
1105#define RT5651_ASRC2_REF_MASK (0x1 << 11)
1106#define RT5651_ASRC2_REF_SFT 11
1107#define RT5651_ASRC2_REF_LRCK2 (0x0 << 11)
1108#define RT5651_ASRC2_REF_LRCK1 (0x1 << 11)
1109#define RT5651_DMIC_1_M_MASK (0x1 << 9)
1110#define RT5651_DMIC_1_M_SFT 9
1111#define RT5651_DMIC_1_M_NOR (0x0 << 9)
1112#define RT5651_DMIC_1_M_ASYN (0x1 << 9)
1113
1114/* PLL tracking mode 2 (0x84) */
1115#define RT5651_STO1_ASRC_EN (0x1 << 15)
1116#define RT5651_STO1_ASRC_EN_SFT 15
1117#define RT5651_STO2_ASRC_EN (0x1 << 14)
1118#define RT5651_STO2_ASRC_EN_SFT 14
1119#define RT5651_STO1_DAC_M_MASK (0x1 << 13)
1120#define RT5651_STO1_DAC_M_SFT 13
1121#define RT5651_STO1_DAC_M_NOR (0x0 << 13)
1122#define RT5651_STO1_DAC_M_ASRC (0x1 << 13)
1123#define RT5651_STO2_DAC_M_MASK (0x1 << 12)
1124#define RT5651_STO2_DAC_M_SFT 12
1125#define RT5651_STO2_DAC_M_NOR (0x0 << 12)
1126#define RT5651_STO2_DAC_M_ASRC (0x1 << 12)
1127#define RT5651_ADC_M_MASK (0x1 << 11)
1128#define RT5651_ADC_M_SFT 11
1129#define RT5651_ADC_M_NOR (0x0 << 11)
1130#define RT5651_ADC_M_ASRC (0x1 << 11)
1131#define RT5651_I2S1_R_D_MASK (0x1 << 4)
1132#define RT5651_I2S1_R_D_SFT 4
1133#define RT5651_I2S1_R_D_DIS (0x0 << 4)
1134#define RT5651_I2S1_R_D_EN (0x1 << 4)
1135#define RT5651_I2S2_R_D_MASK (0x1 << 3)
1136#define RT5651_I2S2_R_D_SFT 3
1137#define RT5651_I2S2_R_D_DIS (0x0 << 3)
1138#define RT5651_I2S2_R_D_EN (0x1 << 3)
1139#define RT5651_PRE_SCLK_MASK (0x3)
1140#define RT5651_PRE_SCLK_SFT 0
1141#define RT5651_PRE_SCLK_512 (0x0)
1142#define RT5651_PRE_SCLK_1024 (0x1)
1143#define RT5651_PRE_SCLK_2048 (0x2)
1144
1145/* PLL tracking mode 3 (0x85) */
1146#define RT5651_I2S1_RATE_MASK (0xf << 12)
1147#define RT5651_I2S1_RATE_SFT 12
1148#define RT5651_I2S2_RATE_MASK (0xf << 8)
1149#define RT5651_I2S2_RATE_SFT 8
1150#define RT5651_G_ASRC_LP_MASK (0x1 << 3)
1151#define RT5651_G_ASRC_LP_SFT 3
1152#define RT5651_ASRC_LP_F_M (0x1 << 2)
1153#define RT5651_ASRC_LP_F_SFT 2
1154#define RT5651_ASRC_LP_F_NOR (0x0 << 2)
1155#define RT5651_ASRC_LP_F_SB (0x1 << 2)
1156#define RT5651_FTK_PH_DET_MASK (0x3)
1157#define RT5651_FTK_PH_DET_SFT 0
1158#define RT5651_FTK_PH_DET_DIV1 (0x0)
1159#define RT5651_FTK_PH_DET_DIV2 (0x1)
1160#define RT5651_FTK_PH_DET_DIV4 (0x2)
1161#define RT5651_FTK_PH_DET_DIV8 (0x3)
1162
1163/*PLL tracking mode 6 (0x89) */
1164#define RT5651_I2S1_PD_MASK (0x7 << 12)
1165#define RT5651_I2S1_PD_SFT 12
1166#define RT5651_I2S2_PD_MASK (0x7 << 8)
1167#define RT5651_I2S2_PD_SFT 8
1168
1169/*PLL tracking mode 7 (0x8a) */
1170#define RT5651_FSI1_RATE_MASK (0xf << 12)
1171#define RT5651_FSI1_RATE_SFT 12
1172#define RT5651_FSI2_RATE_MASK (0xf << 8)
1173#define RT5651_FSI2_RATE_SFT 8
1174
1175/* HPOUT Over Current Detection (0x8b) */
1176#define RT5651_HP_OVCD_MASK (0x1 << 10)
1177#define RT5651_HP_OVCD_SFT 10
1178#define RT5651_HP_OVCD_DIS (0x0 << 10)
1179#define RT5651_HP_OVCD_EN (0x1 << 10)
1180#define RT5651_HP_OC_TH_MASK (0x3 << 8)
1181#define RT5651_HP_OC_TH_SFT 8
1182#define RT5651_HP_OC_TH_90 (0x0 << 8)
1183#define RT5651_HP_OC_TH_105 (0x1 << 8)
1184#define RT5651_HP_OC_TH_120 (0x2 << 8)
1185#define RT5651_HP_OC_TH_135 (0x3 << 8)
1186
1187/* Depop Mode Control 1 (0x8e) */
1188#define RT5651_SMT_TRIG_MASK (0x1 << 15)
1189#define RT5651_SMT_TRIG_SFT 15
1190#define RT5651_SMT_TRIG_DIS (0x0 << 15)
1191#define RT5651_SMT_TRIG_EN (0x1 << 15)
1192#define RT5651_HP_L_SMT_MASK (0x1 << 9)
1193#define RT5651_HP_L_SMT_SFT 9
1194#define RT5651_HP_L_SMT_DIS (0x0 << 9)
1195#define RT5651_HP_L_SMT_EN (0x1 << 9)
1196#define RT5651_HP_R_SMT_MASK (0x1 << 8)
1197#define RT5651_HP_R_SMT_SFT 8
1198#define RT5651_HP_R_SMT_DIS (0x0 << 8)
1199#define RT5651_HP_R_SMT_EN (0x1 << 8)
1200#define RT5651_HP_CD_PD_MASK (0x1 << 7)
1201#define RT5651_HP_CD_PD_SFT 7
1202#define RT5651_HP_CD_PD_DIS (0x0 << 7)
1203#define RT5651_HP_CD_PD_EN (0x1 << 7)
1204#define RT5651_RSTN_MASK (0x1 << 6)
1205#define RT5651_RSTN_SFT 6
1206#define RT5651_RSTN_DIS (0x0 << 6)
1207#define RT5651_RSTN_EN (0x1 << 6)
1208#define RT5651_RSTP_MASK (0x1 << 5)
1209#define RT5651_RSTP_SFT 5
1210#define RT5651_RSTP_DIS (0x0 << 5)
1211#define RT5651_RSTP_EN (0x1 << 5)
1212#define RT5651_HP_CO_MASK (0x1 << 4)
1213#define RT5651_HP_CO_SFT 4
1214#define RT5651_HP_CO_DIS (0x0 << 4)
1215#define RT5651_HP_CO_EN (0x1 << 4)
1216#define RT5651_HP_CP_MASK (0x1 << 3)
1217#define RT5651_HP_CP_SFT 3
1218#define RT5651_HP_CP_PD (0x0 << 3)
1219#define RT5651_HP_CP_PU (0x1 << 3)
1220#define RT5651_HP_SG_MASK (0x1 << 2)
1221#define RT5651_HP_SG_SFT 2
1222#define RT5651_HP_SG_DIS (0x0 << 2)
1223#define RT5651_HP_SG_EN (0x1 << 2)
1224#define RT5651_HP_DP_MASK (0x1 << 1)
1225#define RT5651_HP_DP_SFT 1
1226#define RT5651_HP_DP_PD (0x0 << 1)
1227#define RT5651_HP_DP_PU (0x1 << 1)
1228#define RT5651_HP_CB_MASK (0x1)
1229#define RT5651_HP_CB_SFT 0
1230#define RT5651_HP_CB_PD (0x0)
1231#define RT5651_HP_CB_PU (0x1)
1232
1233/* Depop Mode Control 2 (0x8f) */
1234#define RT5651_DEPOP_MASK (0x1 << 13)
1235#define RT5651_DEPOP_SFT 13
1236#define RT5651_DEPOP_AUTO (0x0 << 13)
1237#define RT5651_DEPOP_MAN (0x1 << 13)
1238#define RT5651_RAMP_MASK (0x1 << 12)
1239#define RT5651_RAMP_SFT 12
1240#define RT5651_RAMP_DIS (0x0 << 12)
1241#define RT5651_RAMP_EN (0x1 << 12)
1242#define RT5651_BPS_MASK (0x1 << 11)
1243#define RT5651_BPS_SFT 11
1244#define RT5651_BPS_DIS (0x0 << 11)
1245#define RT5651_BPS_EN (0x1 << 11)
1246#define RT5651_FAST_UPDN_MASK (0x1 << 10)
1247#define RT5651_FAST_UPDN_SFT 10
1248#define RT5651_FAST_UPDN_DIS (0x0 << 10)
1249#define RT5651_FAST_UPDN_EN (0x1 << 10)
1250#define RT5651_MRES_MASK (0x3 << 8)
1251#define RT5651_MRES_SFT 8
1252#define RT5651_MRES_15MO (0x0 << 8)
1253#define RT5651_MRES_25MO (0x1 << 8)
1254#define RT5651_MRES_35MO (0x2 << 8)
1255#define RT5651_MRES_45MO (0x3 << 8)
1256#define RT5651_VLO_MASK (0x1 << 7)
1257#define RT5651_VLO_SFT 7
1258#define RT5651_VLO_3V (0x0 << 7)
1259#define RT5651_VLO_32V (0x1 << 7)
1260#define RT5651_DIG_DP_MASK (0x1 << 6)
1261#define RT5651_DIG_DP_SFT 6
1262#define RT5651_DIG_DP_DIS (0x0 << 6)
1263#define RT5651_DIG_DP_EN (0x1 << 6)
1264#define RT5651_DP_TH_MASK (0x3 << 4)
1265#define RT5651_DP_TH_SFT 4
1266
1267/* Depop Mode Control 3 (0x90) */
1268#define RT5651_CP_SYS_MASK (0x7 << 12)
1269#define RT5651_CP_SYS_SFT 12
1270#define RT5651_CP_FQ1_MASK (0x7 << 8)
1271#define RT5651_CP_FQ1_SFT 8
1272#define RT5651_CP_FQ2_MASK (0x7 << 4)
1273#define RT5651_CP_FQ2_SFT 4
1274#define RT5651_CP_FQ3_MASK (0x7)
1275#define RT5651_CP_FQ3_SFT 0
1276#define RT5651_CP_FQ_1_5_KHZ 0
1277#define RT5651_CP_FQ_3_KHZ 1
1278#define RT5651_CP_FQ_6_KHZ 2
1279#define RT5651_CP_FQ_12_KHZ 3
1280#define RT5651_CP_FQ_24_KHZ 4
1281#define RT5651_CP_FQ_48_KHZ 5
1282#define RT5651_CP_FQ_96_KHZ 6
1283#define RT5651_CP_FQ_192_KHZ 7
1284
1285/* HPOUT charge pump (0x91) */
1286#define RT5651_OSW_L_MASK (0x1 << 11)
1287#define RT5651_OSW_L_SFT 11
1288#define RT5651_OSW_L_DIS (0x0 << 11)
1289#define RT5651_OSW_L_EN (0x1 << 11)
1290#define RT5651_OSW_R_MASK (0x1 << 10)
1291#define RT5651_OSW_R_SFT 10
1292#define RT5651_OSW_R_DIS (0x0 << 10)
1293#define RT5651_OSW_R_EN (0x1 << 10)
1294#define RT5651_PM_HP_MASK (0x3 << 8)
1295#define RT5651_PM_HP_SFT 8
1296#define RT5651_PM_HP_LV (0x0 << 8)
1297#define RT5651_PM_HP_MV (0x1 << 8)
1298#define RT5651_PM_HP_HV (0x2 << 8)
1299#define RT5651_IB_HP_MASK (0x3 << 6)
1300#define RT5651_IB_HP_SFT 6
1301#define RT5651_IB_HP_125IL (0x0 << 6)
1302#define RT5651_IB_HP_25IL (0x1 << 6)
1303#define RT5651_IB_HP_5IL (0x2 << 6)
1304#define RT5651_IB_HP_1IL (0x3 << 6)
1305
1306/* Micbias Control (0x93) */
1307#define RT5651_MIC1_BS_MASK (0x1 << 15)
1308#define RT5651_MIC1_BS_SFT 15
1309#define RT5651_MIC1_BS_9AV (0x0 << 15)
1310#define RT5651_MIC1_BS_75AV (0x1 << 15)
1311#define RT5651_MIC1_CLK_MASK (0x1 << 13)
1312#define RT5651_MIC1_CLK_SFT 13
1313#define RT5651_MIC1_CLK_DIS (0x0 << 13)
1314#define RT5651_MIC1_CLK_EN (0x1 << 13)
1315#define RT5651_MIC1_OVCD_MASK (0x1 << 11)
1316#define RT5651_MIC1_OVCD_SFT 11
1317#define RT5651_MIC1_OVCD_DIS (0x0 << 11)
1318#define RT5651_MIC1_OVCD_EN (0x1 << 11)
1319#define RT5651_MIC1_OVTH_MASK (0x3 << 9)
1320#define RT5651_MIC1_OVTH_SFT 9
1321#define RT5651_MIC1_OVTH_600UA (0x0 << 9)
1322#define RT5651_MIC1_OVTH_1500UA (0x1 << 9)
1323#define RT5651_MIC1_OVTH_2000UA (0x2 << 9)
1324#define RT5651_PWR_MB_MASK (0x1 << 5)
1325#define RT5651_PWR_MB_SFT 5
1326#define RT5651_PWR_MB_PD (0x0 << 5)
1327#define RT5651_PWR_MB_PU (0x1 << 5)
1328#define RT5651_PWR_CLK12M_MASK (0x1 << 4)
1329#define RT5651_PWR_CLK12M_SFT 4
1330#define RT5651_PWR_CLK12M_PD (0x0 << 4)
1331#define RT5651_PWR_CLK12M_PU (0x1 << 4)
1332
1333/* Analog JD Control 1 (0x94) */
1334#define RT5651_JD2_CMP_MASK (0x7 << 12)
1335#define RT5651_JD2_CMP_SFT 12
1336#define RT5651_JD_PU (0x1 << 11)
1337#define RT5651_JD_PU_SFT 11
1338#define RT5651_JD_PD (0x1 << 10)
1339#define RT5651_JD_PD_SFT 10
1340#define RT5651_JD_MODE_SEL_MASK (0x3 << 8)
1341#define RT5651_JD_MODE_SEL_SFT 8
1342#define RT5651_JD_MODE_SEL_M0 (0x0 << 8)
1343#define RT5651_JD_MODE_SEL_M1 (0x1 << 8)
1344#define RT5651_JD_MODE_SEL_M2 (0x2 << 8)
1345#define RT5651_JD_M_CMP (0x7 << 4)
1346#define RT5651_JD_M_CMP_SFT 4
1347#define RT5651_JD_M_PU (0x1 << 3)
1348#define RT5651_JD_M_PU_SFT 3
1349#define RT5651_JD_M_PD (0x1 << 2)
1350#define RT5651_JD_M_PD_SFT 2
1351#define RT5651_JD_M_MODE_SEL_MASK (0x3)
1352#define RT5651_JD_M_MODE_SEL_SFT 0
1353#define RT5651_JD_M_MODE_SEL_M0 (0x0)
1354#define RT5651_JD_M_MODE_SEL_M1 (0x1)
1355#define RT5651_JD_M_MODE_SEL_M2 (0x2)
1356
1357/* Analog JD Control 2 (0x95) */
1358#define RT5651_JD3_CMP_MASK (0x7 << 12)
1359#define RT5651_JD3_CMP_SFT 12
1360
1361/* EQ Control 1 (0xb0) */
1362#define RT5651_EQ_SRC_MASK (0x1 << 15)
1363#define RT5651_EQ_SRC_SFT 15
1364#define RT5651_EQ_SRC_DAC (0x0 << 15)
1365#define RT5651_EQ_SRC_ADC (0x1 << 15)
1366#define RT5651_EQ_UPD (0x1 << 14)
1367#define RT5651_EQ_UPD_BIT 14
1368#define RT5651_EQ_CD_MASK (0x1 << 13)
1369#define RT5651_EQ_CD_SFT 13
1370#define RT5651_EQ_CD_DIS (0x0 << 13)
1371#define RT5651_EQ_CD_EN (0x1 << 13)
1372#define RT5651_EQ_DITH_MASK (0x3 << 8)
1373#define RT5651_EQ_DITH_SFT 8
1374#define RT5651_EQ_DITH_NOR (0x0 << 8)
1375#define RT5651_EQ_DITH_LSB (0x1 << 8)
1376#define RT5651_EQ_DITH_LSB_1 (0x2 << 8)
1377#define RT5651_EQ_DITH_LSB_2 (0x3 << 8)
1378#define RT5651_EQ_CD_F (0x1 << 7)
1379#define RT5651_EQ_CD_F_BIT 7
1380#define RT5651_EQ_STA_HP2 (0x1 << 6)
1381#define RT5651_EQ_STA_HP2_BIT 6
1382#define RT5651_EQ_STA_HP1 (0x1 << 5)
1383#define RT5651_EQ_STA_HP1_BIT 5
1384#define RT5651_EQ_STA_BP4 (0x1 << 4)
1385#define RT5651_EQ_STA_BP4_BIT 4
1386#define RT5651_EQ_STA_BP3 (0x1 << 3)
1387#define RT5651_EQ_STA_BP3_BIT 3
1388#define RT5651_EQ_STA_BP2 (0x1 << 2)
1389#define RT5651_EQ_STA_BP2_BIT 2
1390#define RT5651_EQ_STA_BP1 (0x1 << 1)
1391#define RT5651_EQ_STA_BP1_BIT 1
1392#define RT5651_EQ_STA_LP (0x1)
1393#define RT5651_EQ_STA_LP_BIT 0
1394
1395/* EQ Control 2 (0xb1) */
1396#define RT5651_EQ_HPF1_M_MASK (0x1 << 8)
1397#define RT5651_EQ_HPF1_M_SFT 8
1398#define RT5651_EQ_HPF1_M_HI (0x0 << 8)
1399#define RT5651_EQ_HPF1_M_1ST (0x1 << 8)
1400#define RT5651_EQ_LPF1_M_MASK (0x1 << 7)
1401#define RT5651_EQ_LPF1_M_SFT 7
1402#define RT5651_EQ_LPF1_M_LO (0x0 << 7)
1403#define RT5651_EQ_LPF1_M_1ST (0x1 << 7)
1404#define RT5651_EQ_HPF2_MASK (0x1 << 6)
1405#define RT5651_EQ_HPF2_SFT 6
1406#define RT5651_EQ_HPF2_DIS (0x0 << 6)
1407#define RT5651_EQ_HPF2_EN (0x1 << 6)
1408#define RT5651_EQ_HPF1_MASK (0x1 << 5)
1409#define RT5651_EQ_HPF1_SFT 5
1410#define RT5651_EQ_HPF1_DIS (0x0 << 5)
1411#define RT5651_EQ_HPF1_EN (0x1 << 5)
1412#define RT5651_EQ_BPF4_MASK (0x1 << 4)
1413#define RT5651_EQ_BPF4_SFT 4
1414#define RT5651_EQ_BPF4_DIS (0x0 << 4)
1415#define RT5651_EQ_BPF4_EN (0x1 << 4)
1416#define RT5651_EQ_BPF3_MASK (0x1 << 3)
1417#define RT5651_EQ_BPF3_SFT 3
1418#define RT5651_EQ_BPF3_DIS (0x0 << 3)
1419#define RT5651_EQ_BPF3_EN (0x1 << 3)
1420#define RT5651_EQ_BPF2_MASK (0x1 << 2)
1421#define RT5651_EQ_BPF2_SFT 2
1422#define RT5651_EQ_BPF2_DIS (0x0 << 2)
1423#define RT5651_EQ_BPF2_EN (0x1 << 2)
1424#define RT5651_EQ_BPF1_MASK (0x1 << 1)
1425#define RT5651_EQ_BPF1_SFT 1
1426#define RT5651_EQ_BPF1_DIS (0x0 << 1)
1427#define RT5651_EQ_BPF1_EN (0x1 << 1)
1428#define RT5651_EQ_LPF_MASK (0x1)
1429#define RT5651_EQ_LPF_SFT 0
1430#define RT5651_EQ_LPF_DIS (0x0)
1431#define RT5651_EQ_LPF_EN (0x1)
1432#define RT5651_EQ_CTRL_MASK (0x7f)
1433
1434/* Memory Test (0xb2) */
1435#define RT5651_MT_MASK (0x1 << 15)
1436#define RT5651_MT_SFT 15
1437#define RT5651_MT_DIS (0x0 << 15)
1438#define RT5651_MT_EN (0x1 << 15)
1439
1440/* ALC Control 1 (0xb4) */
1441#define RT5651_ALC_P_MASK (0x1 << 15)
1442#define RT5651_ALC_P_SFT 15
1443#define RT5651_ALC_P_DAC (0x0 << 15)
1444#define RT5651_ALC_P_ADC (0x1 << 15)
1445#define RT5651_ALC_MASK (0x1 << 14)
1446#define RT5651_ALC_SFT 14
1447#define RT5651_ALC_DIS (0x0 << 14)
1448#define RT5651_ALC_EN (0x1 << 14)
1449#define RT5651_ALC_UPD (0x1 << 13)
1450#define RT5651_ALC_UPD_BIT 13
1451#define RT5651_ALC_AR_MASK (0x1f << 8)
1452#define RT5651_ALC_AR_SFT 8
1453#define RT5651_ALC_R_MASK (0x7 << 5)
1454#define RT5651_ALC_R_SFT 5
1455#define RT5651_ALC_R_48K (0x1 << 5)
1456#define RT5651_ALC_R_96K (0x2 << 5)
1457#define RT5651_ALC_R_192K (0x3 << 5)
1458#define RT5651_ALC_R_441K (0x5 << 5)
1459#define RT5651_ALC_R_882K (0x6 << 5)
1460#define RT5651_ALC_R_1764K (0x7 << 5)
1461#define RT5651_ALC_RC_MASK (0x1f)
1462#define RT5651_ALC_RC_SFT 0
1463
1464/* ALC Control 2 (0xb5) */
1465#define RT5651_ALC_POB_MASK (0x3f << 8)
1466#define RT5651_ALC_POB_SFT 8
1467#define RT5651_ALC_DRC_MASK (0x1 << 7)
1468#define RT5651_ALC_DRC_SFT 7
1469#define RT5651_ALC_DRC_DIS (0x0 << 7)
1470#define RT5651_ALC_DRC_EN (0x1 << 7)
1471#define RT5651_ALC_CPR_MASK (0x3 << 5)
1472#define RT5651_ALC_CPR_SFT 5
1473#define RT5651_ALC_CPR_1_1 (0x0 << 5)
1474#define RT5651_ALC_CPR_1_2 (0x1 << 5)
1475#define RT5651_ALC_CPR_1_4 (0x2 << 5)
1476#define RT5651_ALC_CPR_1_8 (0x3 << 5)
1477#define RT5651_ALC_PRB_MASK (0x1f)
1478#define RT5651_ALC_PRB_SFT 0
1479
1480/* ALC Control 3 (0xb6) */
1481#define RT5651_ALC_NGB_MASK (0xf << 12)
1482#define RT5651_ALC_NGB_SFT 12
1483#define RT5651_ALC_TAR_MASK (0x1f << 7)
1484#define RT5651_ALC_TAR_SFT 7
1485#define RT5651_ALC_NG_MASK (0x1 << 6)
1486#define RT5651_ALC_NG_SFT 6
1487#define RT5651_ALC_NG_DIS (0x0 << 6)
1488#define RT5651_ALC_NG_EN (0x1 << 6)
1489#define RT5651_ALC_NGH_MASK (0x1 << 5)
1490#define RT5651_ALC_NGH_SFT 5
1491#define RT5651_ALC_NGH_DIS (0x0 << 5)
1492#define RT5651_ALC_NGH_EN (0x1 << 5)
1493#define RT5651_ALC_NGT_MASK (0x1f)
1494#define RT5651_ALC_NGT_SFT 0
1495
1496/* Jack Detect Control 1 (0xbb) */
1497#define RT5651_JD_MASK (0x7 << 13)
1498#define RT5651_JD_SFT 13
1499#define RT5651_JD_DIS (0x0 << 13)
1500#define RT5651_JD_GPIO1 (0x1 << 13)
1501#define RT5651_JD_GPIO2 (0x2 << 13)
1502#define RT5651_JD_GPIO3 (0x3 << 13)
1503#define RT5651_JD_GPIO4 (0x4 << 13)
1504#define RT5651_JD_GPIO5 (0x5 << 13)
1505#define RT5651_JD_GPIO6 (0x6 << 13)
1506#define RT5651_JD_HP_MASK (0x1 << 11)
1507#define RT5651_JD_HP_SFT 11
1508#define RT5651_JD_HP_DIS (0x0 << 11)
1509#define RT5651_JD_HP_EN (0x1 << 11)
1510#define RT5651_JD_HP_TRG_MASK (0x1 << 10)
1511#define RT5651_JD_HP_TRG_SFT 10
1512#define RT5651_JD_HP_TRG_LO (0x0 << 10)
1513#define RT5651_JD_HP_TRG_HI (0x1 << 10)
1514#define RT5651_JD_SPL_MASK (0x1 << 9)
1515#define RT5651_JD_SPL_SFT 9
1516#define RT5651_JD_SPL_DIS (0x0 << 9)
1517#define RT5651_JD_SPL_EN (0x1 << 9)
1518#define RT5651_JD_SPL_TRG_MASK (0x1 << 8)
1519#define RT5651_JD_SPL_TRG_SFT 8
1520#define RT5651_JD_SPL_TRG_LO (0x0 << 8)
1521#define RT5651_JD_SPL_TRG_HI (0x1 << 8)
1522#define RT5651_JD_SPR_MASK (0x1 << 7)
1523#define RT5651_JD_SPR_SFT 7
1524#define RT5651_JD_SPR_DIS (0x0 << 7)
1525#define RT5651_JD_SPR_EN (0x1 << 7)
1526#define RT5651_JD_SPR_TRG_MASK (0x1 << 6)
1527#define RT5651_JD_SPR_TRG_SFT 6
1528#define RT5651_JD_SPR_TRG_LO (0x0 << 6)
1529#define RT5651_JD_SPR_TRG_HI (0x1 << 6)
1530#define RT5651_JD_LO_MASK (0x1 << 3)
1531#define RT5651_JD_LO_SFT 3
1532#define RT5651_JD_LO_DIS (0x0 << 3)
1533#define RT5651_JD_LO_EN (0x1 << 3)
1534#define RT5651_JD_LO_TRG_MASK (0x1 << 2)
1535#define RT5651_JD_LO_TRG_SFT 2
1536#define RT5651_JD_LO_TRG_LO (0x0 << 2)
1537#define RT5651_JD_LO_TRG_HI (0x1 << 2)
1538
1539/* Jack Detect Control 2 (0xbc) */
1540#define RT5651_JD_TRG_SEL_MASK (0x7 << 9)
1541#define RT5651_JD_TRG_SEL_SFT 9
1542#define RT5651_JD_TRG_SEL_GPIO (0x0 << 9)
1543#define RT5651_JD_TRG_SEL_JD1_1 (0x1 << 9)
1544#define RT5651_JD_TRG_SEL_JD1_2 (0x2 << 9)
1545#define RT5651_JD_TRG_SEL_JD2 (0x3 << 9)
1546#define RT5651_JD_TRG_SEL_JD3 (0x4 << 9)
1547#define RT5651_JD3_IRQ_EN (0x1 << 8)
1548#define RT5651_JD3_IRQ_EN_SFT 8
1549#define RT5651_JD3_EN_STKY (0x1 << 7)
1550#define RT5651_JD3_EN_STKY_SFT 7
1551#define RT5651_JD3_INV (0x1 << 6)
1552#define RT5651_JD3_INV_SFT 6
1553
1554/* IRQ Control 1 (0xbd) */
1555#define RT5651_IRQ_JD_MASK (0x1 << 15)
1556#define RT5651_IRQ_JD_SFT 15
1557#define RT5651_IRQ_JD_BP (0x0 << 15)
1558#define RT5651_IRQ_JD_NOR (0x1 << 15)
1559#define RT5651_JD_STKY_MASK (0x1 << 13)
1560#define RT5651_JD_STKY_SFT 13
1561#define RT5651_JD_STKY_DIS (0x0 << 13)
1562#define RT5651_JD_STKY_EN (0x1 << 13)
1563#define RT5651_JD_P_MASK (0x1 << 11)
1564#define RT5651_JD_P_SFT 11
1565#define RT5651_JD_P_NOR (0x0 << 11)
1566#define RT5651_JD_P_INV (0x1 << 11)
1567#define RT5651_JD1_1_IRQ_EN (0x1 << 9)
1568#define RT5651_JD1_1_IRQ_EN_SFT 9
1569#define RT5651_JD1_1_EN_STKY (0x1 << 8)
1570#define RT5651_JD1_1_EN_STKY_SFT 8
1571#define RT5651_JD1_1_INV (0x1 << 7)
1572#define RT5651_JD1_1_INV_SFT 7
1573#define RT5651_JD1_2_IRQ_EN (0x1 << 6)
1574#define RT5651_JD1_2_IRQ_EN_SFT 6
1575#define RT5651_JD1_2_EN_STKY (0x1 << 5)
1576#define RT5651_JD1_2_EN_STKY_SFT 5
1577#define RT5651_JD1_2_INV (0x1 << 4)
1578#define RT5651_JD1_2_INV_SFT 4
1579#define RT5651_JD2_IRQ_EN (0x1 << 3)
1580#define RT5651_JD2_IRQ_EN_SFT 3
1581#define RT5651_JD2_EN_STKY (0x1 << 2)
1582#define RT5651_JD2_EN_STKY_SFT 2
1583#define RT5651_JD2_INV (0x1 << 1)
1584#define RT5651_JD2_INV_SFT 1
1585
1586/* IRQ Control 2 (0xbe) */
1587#define RT5651_IRQ_MB1_OC_MASK (0x1 << 15)
1588#define RT5651_IRQ_MB1_OC_SFT 15
1589#define RT5651_IRQ_MB1_OC_BP (0x0 << 15)
1590#define RT5651_IRQ_MB1_OC_NOR (0x1 << 15)
1591#define RT5651_MB1_OC_STKY_MASK (0x1 << 11)
1592#define RT5651_MB1_OC_STKY_SFT 11
1593#define RT5651_MB1_OC_STKY_DIS (0x0 << 11)
1594#define RT5651_MB1_OC_STKY_EN (0x1 << 11)
1595#define RT5651_MB1_OC_P_MASK (0x1 << 7)
1596#define RT5651_MB1_OC_P_SFT 7
1597#define RT5651_MB1_OC_P_NOR (0x0 << 7)
1598#define RT5651_MB1_OC_P_INV (0x1 << 7)
1599#define RT5651_MB2_OC_P_MASK (0x1 << 6)
1600#define RT5651_MB1_OC_CLR (0x1 << 3)
1601#define RT5651_MB1_OC_CLR_SFT 3
1602#define RT5651_STA_GPIO8 (0x1)
1603#define RT5651_STA_GPIO8_BIT 0
1604
1605/* Internal Status and GPIO status (0xbf) */
1606#define RT5651_STA_JD3 (0x1 << 15)
1607#define RT5651_STA_JD3_BIT 15
1608#define RT5651_STA_JD2 (0x1 << 14)
1609#define RT5651_STA_JD2_BIT 14
1610#define RT5651_STA_JD1_2 (0x1 << 13)
1611#define RT5651_STA_JD1_2_BIT 13
1612#define RT5651_STA_JD1_1 (0x1 << 12)
1613#define RT5651_STA_JD1_1_BIT 12
1614#define RT5651_STA_GP7 (0x1 << 11)
1615#define RT5651_STA_GP7_BIT 11
1616#define RT5651_STA_GP6 (0x1 << 10)
1617#define RT5651_STA_GP6_BIT 10
1618#define RT5651_STA_GP5 (0x1 << 9)
1619#define RT5651_STA_GP5_BIT 9
1620#define RT5651_STA_GP1 (0x1 << 8)
1621#define RT5651_STA_GP1_BIT 8
1622#define RT5651_STA_GP2 (0x1 << 7)
1623#define RT5651_STA_GP2_BIT 7
1624#define RT5651_STA_GP3 (0x1 << 6)
1625#define RT5651_STA_GP3_BIT 6
1626#define RT5651_STA_GP4 (0x1 << 5)
1627#define RT5651_STA_GP4_BIT 5
1628#define RT5651_STA_GP_JD (0x1 << 4)
1629#define RT5651_STA_GP_JD_BIT 4
1630
1631/* GPIO Control 1 (0xc0) */
1632#define RT5651_GP1_PIN_MASK (0x1 << 15)
1633#define RT5651_GP1_PIN_SFT 15
1634#define RT5651_GP1_PIN_GPIO1 (0x0 << 15)
1635#define RT5651_GP1_PIN_IRQ (0x1 << 15)
1636#define RT5651_GP2_PIN_MASK (0x1 << 14)
1637#define RT5651_GP2_PIN_SFT 14
1638#define RT5651_GP2_PIN_GPIO2 (0x0 << 14)
1639#define RT5651_GP2_PIN_DMIC1_SCL (0x1 << 14)
1640#define RT5651_GPIO_M_MASK (0x1 << 9)
1641#define RT5651_GPIO_M_SFT 9
1642#define RT5651_GPIO_M_FLT (0x0 << 9)
1643#define RT5651_GPIO_M_PH (0x1 << 9)
1644#define RT5651_I2S2_SEL_MASK (0x1 << 8)
1645#define RT5651_I2S2_SEL_SFT 8
1646#define RT5651_I2S2_SEL_I2S (0x0 << 8)
1647#define RT5651_I2S2_SEL_GPIO (0x1 << 8)
1648#define RT5651_GP5_PIN_MASK (0x1 << 7)
1649#define RT5651_GP5_PIN_SFT 7
1650#define RT5651_GP5_PIN_GPIO5 (0x0 << 7)
1651#define RT5651_GP5_PIN_IRQ (0x1 << 7)
1652#define RT5651_GP6_PIN_MASK (0x1 << 6)
1653#define RT5651_GP6_PIN_SFT 6
1654#define RT5651_GP6_PIN_GPIO6 (0x0 << 6)
1655#define RT5651_GP6_PIN_DMIC_SDA (0x1 << 6)
1656#define RT5651_GP7_PIN_MASK (0x1 << 5)
1657#define RT5651_GP7_PIN_SFT 5
1658#define RT5651_GP7_PIN_GPIO7 (0x0 << 5)
1659#define RT5651_GP7_PIN_IRQ (0x1 << 5)
1660#define RT5651_GP8_PIN_MASK (0x1 << 4)
1661#define RT5651_GP8_PIN_SFT 4
1662#define RT5651_GP8_PIN_GPIO8 (0x0 << 4)
1663#define RT5651_GP8_PIN_DMIC_SDA (0x1 << 4)
1664#define RT5651_GPIO_PDM_SEL_MASK (0x1 << 3)
1665#define RT5651_GPIO_PDM_SEL_SFT 3
1666#define RT5651_GPIO_PDM_SEL_GPIO (0x0 << 3)
1667#define RT5651_GPIO_PDM_SEL_PDM (0x1 << 3)
1668
1669/* GPIO Control 2 (0xc1) */
1670#define RT5651_GP5_DR_MASK (0x1 << 14)
1671#define RT5651_GP5_DR_SFT 14
1672#define RT5651_GP5_DR_IN (0x0 << 14)
1673#define RT5651_GP5_DR_OUT (0x1 << 14)
1674#define RT5651_GP5_OUT_MASK (0x1 << 13)
1675#define RT5651_GP5_OUT_SFT 13
1676#define RT5651_GP5_OUT_LO (0x0 << 13)
1677#define RT5651_GP5_OUT_HI (0x1 << 13)
1678#define RT5651_GP5_P_MASK (0x1 << 12)
1679#define RT5651_GP5_P_SFT 12
1680#define RT5651_GP5_P_NOR (0x0 << 12)
1681#define RT5651_GP5_P_INV (0x1 << 12)
1682#define RT5651_GP4_DR_MASK (0x1 << 11)
1683#define RT5651_GP4_DR_SFT 11
1684#define RT5651_GP4_DR_IN (0x0 << 11)
1685#define RT5651_GP4_DR_OUT (0x1 << 11)
1686#define RT5651_GP4_OUT_MASK (0x1 << 10)
1687#define RT5651_GP4_OUT_SFT 10
1688#define RT5651_GP4_OUT_LO (0x0 << 10)
1689#define RT5651_GP4_OUT_HI (0x1 << 10)
1690#define RT5651_GP4_P_MASK (0x1 << 9)
1691#define RT5651_GP4_P_SFT 9
1692#define RT5651_GP4_P_NOR (0x0 << 9)
1693#define RT5651_GP4_P_INV (0x1 << 9)
1694#define RT5651_GP3_DR_MASK (0x1 << 8)
1695#define RT5651_GP3_DR_SFT 8
1696#define RT5651_GP3_DR_IN (0x0 << 8)
1697#define RT5651_GP3_DR_OUT (0x1 << 8)
1698#define RT5651_GP3_OUT_MASK (0x1 << 7)
1699#define RT5651_GP3_OUT_SFT 7
1700#define RT5651_GP3_OUT_LO (0x0 << 7)
1701#define RT5651_GP3_OUT_HI (0x1 << 7)
1702#define RT5651_GP3_P_MASK (0x1 << 6)
1703#define RT5651_GP3_P_SFT 6
1704#define RT5651_GP3_P_NOR (0x0 << 6)
1705#define RT5651_GP3_P_INV (0x1 << 6)
1706#define RT5651_GP2_DR_MASK (0x1 << 5)
1707#define RT5651_GP2_DR_SFT 5
1708#define RT5651_GP2_DR_IN (0x0 << 5)
1709#define RT5651_GP2_DR_OUT (0x1 << 5)
1710#define RT5651_GP2_OUT_MASK (0x1 << 4)
1711#define RT5651_GP2_OUT_SFT 4
1712#define RT5651_GP2_OUT_LO (0x0 << 4)
1713#define RT5651_GP2_OUT_HI (0x1 << 4)
1714#define RT5651_GP2_P_MASK (0x1 << 3)
1715#define RT5651_GP2_P_SFT 3
1716#define RT5651_GP2_P_NOR (0x0 << 3)
1717#define RT5651_GP2_P_INV (0x1 << 3)
1718#define RT5651_GP1_DR_MASK (0x1 << 2)
1719#define RT5651_GP1_DR_SFT 2
1720#define RT5651_GP1_DR_IN (0x0 << 2)
1721#define RT5651_GP1_DR_OUT (0x1 << 2)
1722#define RT5651_GP1_OUT_MASK (0x1 << 1)
1723#define RT5651_GP1_OUT_SFT 1
1724#define RT5651_GP1_OUT_LO (0x0 << 1)
1725#define RT5651_GP1_OUT_HI (0x1 << 1)
1726#define RT5651_GP1_P_MASK (0x1)
1727#define RT5651_GP1_P_SFT 0
1728#define RT5651_GP1_P_NOR (0x0)
1729#define RT5651_GP1_P_INV (0x1)
1730
1731/* GPIO Control 3 (0xc2) */
1732#define RT5651_GP8_DR_MASK (0x1 << 8)
1733#define RT5651_GP8_DR_SFT 8
1734#define RT5651_GP8_DR_IN (0x0 << 8)
1735#define RT5651_GP8_DR_OUT (0x1 << 8)
1736#define RT5651_GP8_OUT_MASK (0x1 << 7)
1737#define RT5651_GP8_OUT_SFT 7
1738#define RT5651_GP8_OUT_LO (0x0 << 7)
1739#define RT5651_GP8_OUT_HI (0x1 << 7)
1740#define RT5651_GP8_P_MASK (0x1 << 6)
1741#define RT5651_GP8_P_SFT 6
1742#define RT5651_GP8_P_NOR (0x0 << 6)
1743#define RT5651_GP8_P_INV (0x1 << 6)
1744#define RT5651_GP7_DR_MASK (0x1 << 5)
1745#define RT5651_GP7_DR_SFT 5
1746#define RT5651_GP7_DR_IN (0x0 << 5)
1747#define RT5651_GP7_DR_OUT (0x1 << 5)
1748#define RT5651_GP7_OUT_MASK (0x1 << 4)
1749#define RT5651_GP7_OUT_SFT 4
1750#define RT5651_GP7_OUT_LO (0x0 << 4)
1751#define RT5651_GP7_OUT_HI (0x1 << 4)
1752#define RT5651_GP7_P_MASK (0x1 << 3)
1753#define RT5651_GP7_P_SFT 3
1754#define RT5651_GP7_P_NOR (0x0 << 3)
1755#define RT5651_GP7_P_INV (0x1 << 3)
1756#define RT5651_GP6_DR_MASK (0x1 << 2)
1757#define RT5651_GP6_DR_SFT 2
1758#define RT5651_GP6_DR_IN (0x0 << 2)
1759#define RT5651_GP6_DR_OUT (0x1 << 2)
1760#define RT5651_GP6_OUT_MASK (0x1 << 1)
1761#define RT5651_GP6_OUT_SFT 1
1762#define RT5651_GP6_OUT_LO (0x0 << 1)
1763#define RT5651_GP6_OUT_HI (0x1 << 1)
1764#define RT5651_GP6_P_MASK (0x1)
1765#define RT5651_GP6_P_SFT 0
1766#define RT5651_GP6_P_NOR (0x0)
1767#define RT5651_GP6_P_INV (0x1)
1768
1769/* Scramble Control (0xce) */
1770#define RT5651_SCB_SWAP_MASK (0x1 << 15)
1771#define RT5651_SCB_SWAP_SFT 15
1772#define RT5651_SCB_SWAP_DIS (0x0 << 15)
1773#define RT5651_SCB_SWAP_EN (0x1 << 15)
1774#define RT5651_SCB_MASK (0x1 << 14)
1775#define RT5651_SCB_SFT 14
1776#define RT5651_SCB_DIS (0x0 << 14)
1777#define RT5651_SCB_EN (0x1 << 14)
1778
1779/* Baseback Control (0xcf) */
1780#define RT5651_BB_MASK (0x1 << 15)
1781#define RT5651_BB_SFT 15
1782#define RT5651_BB_DIS (0x0 << 15)
1783#define RT5651_BB_EN (0x1 << 15)
1784#define RT5651_BB_CT_MASK (0x7 << 12)
1785#define RT5651_BB_CT_SFT 12
1786#define RT5651_BB_CT_A (0x0 << 12)
1787#define RT5651_BB_CT_B (0x1 << 12)
1788#define RT5651_BB_CT_C (0x2 << 12)
1789#define RT5651_BB_CT_D (0x3 << 12)
1790#define RT5651_M_BB_L_MASK (0x1 << 9)
1791#define RT5651_M_BB_L_SFT 9
1792#define RT5651_M_BB_R_MASK (0x1 << 8)
1793#define RT5651_M_BB_R_SFT 8
1794#define RT5651_M_BB_HPF_L_MASK (0x1 << 7)
1795#define RT5651_M_BB_HPF_L_SFT 7
1796#define RT5651_M_BB_HPF_R_MASK (0x1 << 6)
1797#define RT5651_M_BB_HPF_R_SFT 6
1798#define RT5651_G_BB_BST_MASK (0x3f)
1799#define RT5651_G_BB_BST_SFT 0
1800
1801/* MP3 Plus Control 1 (0xd0) */
1802#define RT5651_M_MP3_L_MASK (0x1 << 15)
1803#define RT5651_M_MP3_L_SFT 15
1804#define RT5651_M_MP3_R_MASK (0x1 << 14)
1805#define RT5651_M_MP3_R_SFT 14
1806#define RT5651_M_MP3_MASK (0x1 << 13)
1807#define RT5651_M_MP3_SFT 13
1808#define RT5651_M_MP3_DIS (0x0 << 13)
1809#define RT5651_M_MP3_EN (0x1 << 13)
1810#define RT5651_EG_MP3_MASK (0x1f << 8)
1811#define RT5651_EG_MP3_SFT 8
1812#define RT5651_MP3_HLP_MASK (0x1 << 7)
1813#define RT5651_MP3_HLP_SFT 7
1814#define RT5651_MP3_HLP_DIS (0x0 << 7)
1815#define RT5651_MP3_HLP_EN (0x1 << 7)
1816#define RT5651_M_MP3_ORG_L_MASK (0x1 << 6)
1817#define RT5651_M_MP3_ORG_L_SFT 6
1818#define RT5651_M_MP3_ORG_R_MASK (0x1 << 5)
1819#define RT5651_M_MP3_ORG_R_SFT 5
1820
1821/* MP3 Plus Control 2 (0xd1) */
1822#define RT5651_MP3_WT_MASK (0x1 << 13)
1823#define RT5651_MP3_WT_SFT 13
1824#define RT5651_MP3_WT_1_4 (0x0 << 13)
1825#define RT5651_MP3_WT_1_2 (0x1 << 13)
1826#define RT5651_OG_MP3_MASK (0x1f << 8)
1827#define RT5651_OG_MP3_SFT 8
1828#define RT5651_HG_MP3_MASK (0x3f)
1829#define RT5651_HG_MP3_SFT 0
1830
1831/* 3D HP Control 1 (0xd2) */
1832#define RT5651_3D_CF_MASK (0x1 << 15)
1833#define RT5651_3D_CF_SFT 15
1834#define RT5651_3D_CF_DIS (0x0 << 15)
1835#define RT5651_3D_CF_EN (0x1 << 15)
1836#define RT5651_3D_HP_MASK (0x1 << 14)
1837#define RT5651_3D_HP_SFT 14
1838#define RT5651_3D_HP_DIS (0x0 << 14)
1839#define RT5651_3D_HP_EN (0x1 << 14)
1840#define RT5651_3D_BT_MASK (0x1 << 13)
1841#define RT5651_3D_BT_SFT 13
1842#define RT5651_3D_BT_DIS (0x0 << 13)
1843#define RT5651_3D_BT_EN (0x1 << 13)
1844#define RT5651_3D_1F_MIX_MASK (0x3 << 11)
1845#define RT5651_3D_1F_MIX_SFT 11
1846#define RT5651_3D_HP_M_MASK (0x1 << 10)
1847#define RT5651_3D_HP_M_SFT 10
1848#define RT5651_3D_HP_M_SUR (0x0 << 10)
1849#define RT5651_3D_HP_M_FRO (0x1 << 10)
1850#define RT5651_M_3D_HRTF_MASK (0x1 << 9)
1851#define RT5651_M_3D_HRTF_SFT 9
1852#define RT5651_M_3D_D2H_MASK (0x1 << 8)
1853#define RT5651_M_3D_D2H_SFT 8
1854#define RT5651_M_3D_D2R_MASK (0x1 << 7)
1855#define RT5651_M_3D_D2R_SFT 7
1856#define RT5651_M_3D_REVB_MASK (0x1 << 6)
1857#define RT5651_M_3D_REVB_SFT 6
1858
1859/* Adjustable high pass filter control 1 (0xd3) */
1860#define RT5651_2ND_HPF_MASK (0x1 << 15)
1861#define RT5651_2ND_HPF_SFT 15
1862#define RT5651_2ND_HPF_DIS (0x0 << 15)
1863#define RT5651_2ND_HPF_EN (0x1 << 15)
1864#define RT5651_HPF_CF_L_MASK (0x7 << 12)
1865#define RT5651_HPF_CF_L_SFT 12
1866#define RT5651_HPF_CF_R_MASK (0x7 << 8)
1867#define RT5651_HPF_CF_R_SFT 8
1868#define RT5651_ZD_T_MASK (0x3 << 6)
1869#define RT5651_ZD_T_SFT 6
1870#define RT5651_ZD_F_MASK (0x3 << 4)
1871#define RT5651_ZD_F_SFT 4
1872#define RT5651_ZD_F_IM (0x0 << 4)
1873#define RT5651_ZD_F_ZC_IM (0x1 << 4)
1874#define RT5651_ZD_F_ZC_IOD (0x2 << 4)
1875#define RT5651_ZD_F_UN (0x3 << 4)
1876
1877/* Adjustable high pass filter control 2 (0xd4) */
1878#define RT5651_HPF_CF_L_NUM_MASK (0x3f << 8)
1879#define RT5651_HPF_CF_L_NUM_SFT 8
1880#define RT5651_HPF_CF_R_NUM_MASK (0x3f)
1881#define RT5651_HPF_CF_R_NUM_SFT 0
1882
1883/* HP calibration control and Amp detection (0xd6) */
1884#define RT5651_SI_DAC_MASK (0x1 << 11)
1885#define RT5651_SI_DAC_SFT 11
1886#define RT5651_SI_DAC_AUTO (0x0 << 11)
1887#define RT5651_SI_DAC_TEST (0x1 << 11)
1888#define RT5651_DC_CAL_M_MASK (0x1 << 10)
1889#define RT5651_DC_CAL_M_SFT 10
1890#define RT5651_DC_CAL_M_NOR (0x0 << 10)
1891#define RT5651_DC_CAL_M_CAL (0x1 << 10)
1892#define RT5651_DC_CAL_MASK (0x1 << 9)
1893#define RT5651_DC_CAL_SFT 9
1894#define RT5651_DC_CAL_DIS (0x0 << 9)
1895#define RT5651_DC_CAL_EN (0x1 << 9)
1896#define RT5651_HPD_RCV_MASK (0x7 << 6)
1897#define RT5651_HPD_RCV_SFT 6
1898#define RT5651_HPD_PS_MASK (0x1 << 5)
1899#define RT5651_HPD_PS_SFT 5
1900#define RT5651_HPD_PS_DIS (0x0 << 5)
1901#define RT5651_HPD_PS_EN (0x1 << 5)
1902#define RT5651_CAL_M_MASK (0x1 << 4)
1903#define RT5651_CAL_M_SFT 4
1904#define RT5651_CAL_M_DEP (0x0 << 4)
1905#define RT5651_CAL_M_CAL (0x1 << 4)
1906#define RT5651_CAL_MASK (0x1 << 3)
1907#define RT5651_CAL_SFT 3
1908#define RT5651_CAL_DIS (0x0 << 3)
1909#define RT5651_CAL_EN (0x1 << 3)
1910#define RT5651_CAL_TEST_MASK (0x1 << 2)
1911#define RT5651_CAL_TEST_SFT 2
1912#define RT5651_CAL_TEST_DIS (0x0 << 2)
1913#define RT5651_CAL_TEST_EN (0x1 << 2)
1914#define RT5651_CAL_P_MASK (0x3)
1915#define RT5651_CAL_P_SFT 0
1916#define RT5651_CAL_P_NONE (0x0)
1917#define RT5651_CAL_P_CAL (0x1)
1918#define RT5651_CAL_P_DAC_CAL (0x2)
1919
1920/* Soft volume and zero cross control 1 (0xd9) */
1921#define RT5651_SV_MASK (0x1 << 15)
1922#define RT5651_SV_SFT 15
1923#define RT5651_SV_DIS (0x0 << 15)
1924#define RT5651_SV_EN (0x1 << 15)
1925#define RT5651_OUT_SV_MASK (0x1 << 13)
1926#define RT5651_OUT_SV_SFT 13
1927#define RT5651_OUT_SV_DIS (0x0 << 13)
1928#define RT5651_OUT_SV_EN (0x1 << 13)
1929#define RT5651_HP_SV_MASK (0x1 << 12)
1930#define RT5651_HP_SV_SFT 12
1931#define RT5651_HP_SV_DIS (0x0 << 12)
1932#define RT5651_HP_SV_EN (0x1 << 12)
1933#define RT5651_ZCD_DIG_MASK (0x1 << 11)
1934#define RT5651_ZCD_DIG_SFT 11
1935#define RT5651_ZCD_DIG_DIS (0x0 << 11)
1936#define RT5651_ZCD_DIG_EN (0x1 << 11)
1937#define RT5651_ZCD_MASK (0x1 << 10)
1938#define RT5651_ZCD_SFT 10
1939#define RT5651_ZCD_PD (0x0 << 10)
1940#define RT5651_ZCD_PU (0x1 << 10)
1941#define RT5651_M_ZCD_MASK (0x3f << 4)
1942#define RT5651_M_ZCD_SFT 4
1943#define RT5651_M_ZCD_OM_L (0x1 << 7)
1944#define RT5651_M_ZCD_OM_R (0x1 << 6)
1945#define RT5651_M_ZCD_RM_L (0x1 << 5)
1946#define RT5651_M_ZCD_RM_R (0x1 << 4)
1947#define RT5651_SV_DLY_MASK (0xf)
1948#define RT5651_SV_DLY_SFT 0
1949
1950/* Soft volume and zero cross control 2 (0xda) */
1951#define RT5651_ZCD_HP_MASK (0x1 << 15)
1952#define RT5651_ZCD_HP_SFT 15
1953#define RT5651_ZCD_HP_DIS (0x0 << 15)
1954#define RT5651_ZCD_HP_EN (0x1 << 15)
1955
1956/* Digital Misc Control (0xfa) */
1957#define RT5651_I2S2_MS_SP_MASK (0x1 << 8)
1958#define RT5651_I2S2_MS_SP_SEL 8
1959#define RT5651_I2S2_MS_SP_64 (0x0 << 8)
1960#define RT5651_I2S2_MS_SP_50 (0x1 << 8)
1961#define RT5651_CLK_DET_EN (0x1 << 3)
1962#define RT5651_CLK_DET_EN_SFT 3
1963#define RT5651_AMP_DET_EN (0x1 << 1)
1964#define RT5651_AMP_DET_EN_SFT 1
1965#define RT5651_D_GATE_EN (0x1)
1966#define RT5651_D_GATE_EN_SFT 0
1967
1968/* Codec Private Register definition */
1969/* 3D Speaker Control (0x63) */
1970#define RT5651_3D_SPK_MASK (0x1 << 15)
1971#define RT5651_3D_SPK_SFT 15
1972#define RT5651_3D_SPK_DIS (0x0 << 15)
1973#define RT5651_3D_SPK_EN (0x1 << 15)
1974#define RT5651_3D_SPK_M_MASK (0x3 << 13)
1975#define RT5651_3D_SPK_M_SFT 13
1976#define RT5651_3D_SPK_CG_MASK (0x1f << 8)
1977#define RT5651_3D_SPK_CG_SFT 8
1978#define RT5651_3D_SPK_SG_MASK (0x1f)
1979#define RT5651_3D_SPK_SG_SFT 0
1980
1981/* Wind Noise Detection Control 1 (0x6c) */
1982#define RT5651_WND_MASK (0x1 << 15)
1983#define RT5651_WND_SFT 15
1984#define RT5651_WND_DIS (0x0 << 15)
1985#define RT5651_WND_EN (0x1 << 15)
1986
1987/* Wind Noise Detection Control 2 (0x6d) */
1988#define RT5651_WND_FC_NW_MASK (0x3f << 10)
1989#define RT5651_WND_FC_NW_SFT 10
1990#define RT5651_WND_FC_WK_MASK (0x3f << 4)
1991#define RT5651_WND_FC_WK_SFT 4
1992
1993/* Wind Noise Detection Control 3 (0x6e) */
1994#define RT5651_HPF_FC_MASK (0x3f << 6)
1995#define RT5651_HPF_FC_SFT 6
1996#define RT5651_WND_FC_ST_MASK (0x3f)
1997#define RT5651_WND_FC_ST_SFT 0
1998
1999/* Wind Noise Detection Control 4 (0x6f) */
2000#define RT5651_WND_TH_LO_MASK (0x3ff)
2001#define RT5651_WND_TH_LO_SFT 0
2002
2003/* Wind Noise Detection Control 5 (0x70) */
2004#define RT5651_WND_TH_HI_MASK (0x3ff)
2005#define RT5651_WND_TH_HI_SFT 0
2006
2007/* Wind Noise Detection Control 8 (0x73) */
2008#define RT5651_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2009#define RT5651_WND_WIND_SFT 13
2010#define RT5651_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2011#define RT5651_WND_STRONG_SFT 12
2012enum {
2013 RT5651_NO_WIND,
2014 RT5651_BREEZE,
2015 RT5651_STORM,
2016};
2017
2018/* Dipole Speaker Interface (0x75) */
2019#define RT5651_DP_ATT_MASK (0x3 << 14)
2020#define RT5651_DP_ATT_SFT 14
2021#define RT5651_DP_SPK_MASK (0x1 << 10)
2022#define RT5651_DP_SPK_SFT 10
2023#define RT5651_DP_SPK_DIS (0x0 << 10)
2024#define RT5651_DP_SPK_EN (0x1 << 10)
2025
2026/* EQ Pre Volume Control (0xb3) */
2027#define RT5651_EQ_PRE_VOL_MASK (0xffff)
2028#define RT5651_EQ_PRE_VOL_SFT 0
2029
2030/* EQ Post Volume Control (0xb4) */
2031#define RT5651_EQ_PST_VOL_MASK (0xffff)
2032#define RT5651_EQ_PST_VOL_SFT 0
2033
2034/* System Clock Source */
2035enum {
2036 RT5651_SCLK_S_MCLK,
2037 RT5651_SCLK_S_PLL1,
2038 RT5651_SCLK_S_RCCLK,
2039};
2040
2041/* PLL1 Source */
2042enum {
2043 RT5651_PLL1_S_MCLK,
2044 RT5651_PLL1_S_BCLK1,
2045 RT5651_PLL1_S_BCLK2,
2046};
2047
2048enum {
2049 RT5651_AIF1,
2050 RT5651_AIF2,
2051 RT5651_AIFS,
2052};
2053
2054struct rt5651_pll_code {
2055 bool m_bp; /* Indicates bypass m code or not. */
2056 int m_code;
2057 int n_code;
2058 int k_code;
2059};
2060
2061struct rt5651_priv {
2062 struct snd_soc_codec *codec;
2063 struct rt5651_platform_data pdata;
2064 struct regmap *regmap;
2065
2066 int sysclk;
2067 int sysclk_src;
2068 int lrck[RT5651_AIFS];
2069 int bclk[RT5651_AIFS];
2070 int master[RT5651_AIFS];
2071
2072 int pll_src;
2073 int pll_in;
2074 int pll_out;
2075
2076 int dmic_en;
2077 bool hp_mute;
2078};
2079
2080#endif /* __RT5651_H__ */
diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c
new file mode 100644
index 000000000000..833231e27340
--- /dev/null
+++ b/sound/soc/codecs/rt5677.c
@@ -0,0 +1,3498 @@
1/*
2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/fs.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/regmap.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <linux/spi/spi.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29
30#include "rt5677.h"
31
32#define RT5677_DEVICE_ID 0x6327
33
34#define RT5677_PR_RANGE_BASE (0xff + 1)
35#define RT5677_PR_SPACING 0x100
36
37#define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
38
39static const struct regmap_range_cfg rt5677_ranges[] = {
40 {
41 .name = "PR",
42 .range_min = RT5677_PR_BASE,
43 .range_max = RT5677_PR_BASE + 0xfd,
44 .selector_reg = RT5677_PRIV_INDEX,
45 .selector_mask = 0xff,
46 .selector_shift = 0x0,
47 .window_start = RT5677_PRIV_DATA,
48 .window_len = 0x1,
49 },
50};
51
52static const struct reg_default init_list[] = {
53 {RT5677_PR_BASE + 0x3d, 0x364d},
54 {RT5677_PR_BASE + 0x17, 0x4fc0},
55 {RT5677_PR_BASE + 0x13, 0x0312},
56 {RT5677_PR_BASE + 0x1e, 0x0000},
57 {RT5677_PR_BASE + 0x12, 0x0eaa},
58 {RT5677_PR_BASE + 0x14, 0x018a},
59};
60#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
61
62static const struct reg_default rt5677_reg[] = {
63 {RT5677_RESET , 0x0000},
64 {RT5677_LOUT1 , 0xa800},
65 {RT5677_IN1 , 0x0000},
66 {RT5677_MICBIAS , 0x0000},
67 {RT5677_SLIMBUS_PARAM , 0x0000},
68 {RT5677_SLIMBUS_RX , 0x0000},
69 {RT5677_SLIMBUS_CTRL , 0x0000},
70 {RT5677_SIDETONE_CTRL , 0x000b},
71 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
72 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
73 {RT5677_DAC4_DIG_VOL , 0xafaf},
74 {RT5677_DAC3_DIG_VOL , 0xafaf},
75 {RT5677_DAC1_DIG_VOL , 0xafaf},
76 {RT5677_DAC2_DIG_VOL , 0xafaf},
77 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
78 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
79 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
80 {RT5677_STO1_2_ADC_BST , 0x0000},
81 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
82 {RT5677_ADC_BST_CTRL2 , 0x0000},
83 {RT5677_STO3_4_ADC_BST , 0x0000},
84 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
85 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
86 {RT5677_STO4_ADC_MIXER , 0xd4c0},
87 {RT5677_STO3_ADC_MIXER , 0xd4c0},
88 {RT5677_STO2_ADC_MIXER , 0xd4c0},
89 {RT5677_STO1_ADC_MIXER , 0xd4c0},
90 {RT5677_MONO_ADC_MIXER , 0xd4d1},
91 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
92 {RT5677_STO1_DAC_MIXER , 0xaaaa},
93 {RT5677_MONO_DAC_MIXER , 0xaaaa},
94 {RT5677_DD1_MIXER , 0xaaaa},
95 {RT5677_DD2_MIXER , 0xaaaa},
96 {RT5677_IF3_DATA , 0x0000},
97 {RT5677_IF4_DATA , 0x0000},
98 {RT5677_PDM_OUT_CTRL , 0x8888},
99 {RT5677_PDM_DATA_CTRL1 , 0x0000},
100 {RT5677_PDM_DATA_CTRL2 , 0x0000},
101 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
102 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
103 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
104 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
105 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
106 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
107 {RT5677_TDM1_CTRL1 , 0x0300},
108 {RT5677_TDM1_CTRL2 , 0x0000},
109 {RT5677_TDM1_CTRL3 , 0x4000},
110 {RT5677_TDM1_CTRL4 , 0x0123},
111 {RT5677_TDM1_CTRL5 , 0x4567},
112 {RT5677_TDM2_CTRL1 , 0x0300},
113 {RT5677_TDM2_CTRL2 , 0x0000},
114 {RT5677_TDM2_CTRL3 , 0x4000},
115 {RT5677_TDM2_CTRL4 , 0x0123},
116 {RT5677_TDM2_CTRL5 , 0x4567},
117 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
118 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
119 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
120 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
121 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
122 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
123 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
124 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
125 {RT5677_DMIC_CTRL1 , 0x1505},
126 {RT5677_DMIC_CTRL2 , 0x0055},
127 {RT5677_HAP_GENE_CTRL1 , 0x0111},
128 {RT5677_HAP_GENE_CTRL2 , 0x0064},
129 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
130 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
131 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
132 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
133 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
134 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
135 {RT5677_HAP_GENE_CTRL9 , 0xf000},
136 {RT5677_HAP_GENE_CTRL10 , 0x0000},
137 {RT5677_PWR_DIG1 , 0x0000},
138 {RT5677_PWR_DIG2 , 0x0000},
139 {RT5677_PWR_ANLG1 , 0x0055},
140 {RT5677_PWR_ANLG2 , 0x0000},
141 {RT5677_PWR_DSP1 , 0x0001},
142 {RT5677_PWR_DSP_ST , 0x0000},
143 {RT5677_PWR_DSP2 , 0x0000},
144 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
145 {RT5677_PRIV_INDEX , 0x0000},
146 {RT5677_PRIV_DATA , 0x0000},
147 {RT5677_I2S4_SDP , 0x8000},
148 {RT5677_I2S1_SDP , 0x8000},
149 {RT5677_I2S2_SDP , 0x8000},
150 {RT5677_I2S3_SDP , 0x8000},
151 {RT5677_CLK_TREE_CTRL1 , 0x1111},
152 {RT5677_CLK_TREE_CTRL2 , 0x1111},
153 {RT5677_CLK_TREE_CTRL3 , 0x0000},
154 {RT5677_PLL1_CTRL1 , 0x0000},
155 {RT5677_PLL1_CTRL2 , 0x0000},
156 {RT5677_PLL2_CTRL1 , 0x0c60},
157 {RT5677_PLL2_CTRL2 , 0x2000},
158 {RT5677_GLB_CLK1 , 0x0000},
159 {RT5677_GLB_CLK2 , 0x0000},
160 {RT5677_ASRC_1 , 0x0000},
161 {RT5677_ASRC_2 , 0x0000},
162 {RT5677_ASRC_3 , 0x0000},
163 {RT5677_ASRC_4 , 0x0000},
164 {RT5677_ASRC_5 , 0x0000},
165 {RT5677_ASRC_6 , 0x0000},
166 {RT5677_ASRC_7 , 0x0000},
167 {RT5677_ASRC_8 , 0x0000},
168 {RT5677_ASRC_9 , 0x0000},
169 {RT5677_ASRC_10 , 0x0000},
170 {RT5677_ASRC_11 , 0x0000},
171 {RT5677_ASRC_12 , 0x0008},
172 {RT5677_ASRC_13 , 0x0000},
173 {RT5677_ASRC_14 , 0x0000},
174 {RT5677_ASRC_15 , 0x0000},
175 {RT5677_ASRC_16 , 0x0000},
176 {RT5677_ASRC_17 , 0x0000},
177 {RT5677_ASRC_18 , 0x0000},
178 {RT5677_ASRC_19 , 0x0000},
179 {RT5677_ASRC_20 , 0x0000},
180 {RT5677_ASRC_21 , 0x000c},
181 {RT5677_ASRC_22 , 0x0000},
182 {RT5677_ASRC_23 , 0x0000},
183 {RT5677_VAD_CTRL1 , 0x2184},
184 {RT5677_VAD_CTRL2 , 0x010a},
185 {RT5677_VAD_CTRL3 , 0x0aea},
186 {RT5677_VAD_CTRL4 , 0x000c},
187 {RT5677_VAD_CTRL5 , 0x0000},
188 {RT5677_DSP_INB_CTRL1 , 0x0000},
189 {RT5677_DSP_INB_CTRL2 , 0x0000},
190 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
191 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
192 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
193 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
194 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
195 {RT5677_ADC_EQ_CTRL1 , 0x6000},
196 {RT5677_ADC_EQ_CTRL2 , 0x0000},
197 {RT5677_EQ_CTRL1 , 0xc000},
198 {RT5677_EQ_CTRL2 , 0x0000},
199 {RT5677_EQ_CTRL3 , 0x0000},
200 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
201 {RT5677_JD_CTRL1 , 0x0000},
202 {RT5677_JD_CTRL2 , 0x0000},
203 {RT5677_JD_CTRL3 , 0x0000},
204 {RT5677_IRQ_CTRL1 , 0x0000},
205 {RT5677_IRQ_CTRL2 , 0x0000},
206 {RT5677_GPIO_ST , 0x0000},
207 {RT5677_GPIO_CTRL1 , 0x0000},
208 {RT5677_GPIO_CTRL2 , 0x0000},
209 {RT5677_GPIO_CTRL3 , 0x0000},
210 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
211 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
212 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
213 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
214 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
215 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
216 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
217 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
218 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
219 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
220 {RT5677_MB_DRC_CTRL1 , 0x0f20},
221 {RT5677_DRC1_CTRL1 , 0x001f},
222 {RT5677_DRC1_CTRL2 , 0x020c},
223 {RT5677_DRC1_CTRL3 , 0x1f00},
224 {RT5677_DRC1_CTRL4 , 0x0000},
225 {RT5677_DRC1_CTRL5 , 0x0000},
226 {RT5677_DRC1_CTRL6 , 0x0029},
227 {RT5677_DRC2_CTRL1 , 0x001f},
228 {RT5677_DRC2_CTRL2 , 0x020c},
229 {RT5677_DRC2_CTRL3 , 0x1f00},
230 {RT5677_DRC2_CTRL4 , 0x0000},
231 {RT5677_DRC2_CTRL5 , 0x0000},
232 {RT5677_DRC2_CTRL6 , 0x0029},
233 {RT5677_DRC1_HL_CTRL1 , 0x8000},
234 {RT5677_DRC1_HL_CTRL2 , 0x0200},
235 {RT5677_DRC2_HL_CTRL1 , 0x8000},
236 {RT5677_DRC2_HL_CTRL2 , 0x0200},
237 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
238 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
239 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
240 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
241 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
242 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
243 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
244 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
245 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
246 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
247 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
248 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
249 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
250 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
251 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
252 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
253 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
254 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
255 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
256 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
257 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
258 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
259 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
260 {RT5677_DIG_MISC , 0x0000},
261 {RT5677_GEN_CTRL1 , 0x0000},
262 {RT5677_GEN_CTRL2 , 0x0000},
263 {RT5677_VENDOR_ID , 0x0000},
264 {RT5677_VENDOR_ID1 , 0x10ec},
265 {RT5677_VENDOR_ID2 , 0x6327},
266};
267
268static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
269{
270 int i;
271
272 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
273 if (reg >= rt5677_ranges[i].range_min &&
274 reg <= rt5677_ranges[i].range_max) {
275 return true;
276 }
277 }
278
279 switch (reg) {
280 case RT5677_RESET:
281 case RT5677_SLIMBUS_PARAM:
282 case RT5677_PDM_DATA_CTRL1:
283 case RT5677_PDM_DATA_CTRL2:
284 case RT5677_PDM1_DATA_CTRL4:
285 case RT5677_PDM2_DATA_CTRL4:
286 case RT5677_I2C_MASTER_CTRL1:
287 case RT5677_I2C_MASTER_CTRL7:
288 case RT5677_I2C_MASTER_CTRL8:
289 case RT5677_HAP_GENE_CTRL2:
290 case RT5677_PWR_DSP_ST:
291 case RT5677_PRIV_DATA:
292 case RT5677_PLL1_CTRL2:
293 case RT5677_PLL2_CTRL2:
294 case RT5677_ASRC_22:
295 case RT5677_ASRC_23:
296 case RT5677_VAD_CTRL5:
297 case RT5677_ADC_EQ_CTRL1:
298 case RT5677_EQ_CTRL1:
299 case RT5677_IRQ_CTRL1:
300 case RT5677_IRQ_CTRL2:
301 case RT5677_GPIO_ST:
302 case RT5677_DSP_INB1_SRC_CTRL4:
303 case RT5677_DSP_INB2_SRC_CTRL4:
304 case RT5677_DSP_INB3_SRC_CTRL4:
305 case RT5677_DSP_OUTB1_SRC_CTRL4:
306 case RT5677_DSP_OUTB2_SRC_CTRL4:
307 case RT5677_VENDOR_ID:
308 case RT5677_VENDOR_ID1:
309 case RT5677_VENDOR_ID2:
310 return true;
311 default:
312 return false;
313 }
314}
315
316static bool rt5677_readable_register(struct device *dev, unsigned int reg)
317{
318 int i;
319
320 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
321 if (reg >= rt5677_ranges[i].range_min &&
322 reg <= rt5677_ranges[i].range_max) {
323 return true;
324 }
325 }
326
327 switch (reg) {
328 case RT5677_RESET:
329 case RT5677_LOUT1:
330 case RT5677_IN1:
331 case RT5677_MICBIAS:
332 case RT5677_SLIMBUS_PARAM:
333 case RT5677_SLIMBUS_RX:
334 case RT5677_SLIMBUS_CTRL:
335 case RT5677_SIDETONE_CTRL:
336 case RT5677_ANA_DAC1_2_3_SRC:
337 case RT5677_IF_DSP_DAC3_4_MIXER:
338 case RT5677_DAC4_DIG_VOL:
339 case RT5677_DAC3_DIG_VOL:
340 case RT5677_DAC1_DIG_VOL:
341 case RT5677_DAC2_DIG_VOL:
342 case RT5677_IF_DSP_DAC2_MIXER:
343 case RT5677_STO1_ADC_DIG_VOL:
344 case RT5677_MONO_ADC_DIG_VOL:
345 case RT5677_STO1_2_ADC_BST:
346 case RT5677_STO2_ADC_DIG_VOL:
347 case RT5677_ADC_BST_CTRL2:
348 case RT5677_STO3_4_ADC_BST:
349 case RT5677_STO3_ADC_DIG_VOL:
350 case RT5677_STO4_ADC_DIG_VOL:
351 case RT5677_STO4_ADC_MIXER:
352 case RT5677_STO3_ADC_MIXER:
353 case RT5677_STO2_ADC_MIXER:
354 case RT5677_STO1_ADC_MIXER:
355 case RT5677_MONO_ADC_MIXER:
356 case RT5677_ADC_IF_DSP_DAC1_MIXER:
357 case RT5677_STO1_DAC_MIXER:
358 case RT5677_MONO_DAC_MIXER:
359 case RT5677_DD1_MIXER:
360 case RT5677_DD2_MIXER:
361 case RT5677_IF3_DATA:
362 case RT5677_IF4_DATA:
363 case RT5677_PDM_OUT_CTRL:
364 case RT5677_PDM_DATA_CTRL1:
365 case RT5677_PDM_DATA_CTRL2:
366 case RT5677_PDM1_DATA_CTRL2:
367 case RT5677_PDM1_DATA_CTRL3:
368 case RT5677_PDM1_DATA_CTRL4:
369 case RT5677_PDM2_DATA_CTRL2:
370 case RT5677_PDM2_DATA_CTRL3:
371 case RT5677_PDM2_DATA_CTRL4:
372 case RT5677_TDM1_CTRL1:
373 case RT5677_TDM1_CTRL2:
374 case RT5677_TDM1_CTRL3:
375 case RT5677_TDM1_CTRL4:
376 case RT5677_TDM1_CTRL5:
377 case RT5677_TDM2_CTRL1:
378 case RT5677_TDM2_CTRL2:
379 case RT5677_TDM2_CTRL3:
380 case RT5677_TDM2_CTRL4:
381 case RT5677_TDM2_CTRL5:
382 case RT5677_I2C_MASTER_CTRL1:
383 case RT5677_I2C_MASTER_CTRL2:
384 case RT5677_I2C_MASTER_CTRL3:
385 case RT5677_I2C_MASTER_CTRL4:
386 case RT5677_I2C_MASTER_CTRL5:
387 case RT5677_I2C_MASTER_CTRL6:
388 case RT5677_I2C_MASTER_CTRL7:
389 case RT5677_I2C_MASTER_CTRL8:
390 case RT5677_DMIC_CTRL1:
391 case RT5677_DMIC_CTRL2:
392 case RT5677_HAP_GENE_CTRL1:
393 case RT5677_HAP_GENE_CTRL2:
394 case RT5677_HAP_GENE_CTRL3:
395 case RT5677_HAP_GENE_CTRL4:
396 case RT5677_HAP_GENE_CTRL5:
397 case RT5677_HAP_GENE_CTRL6:
398 case RT5677_HAP_GENE_CTRL7:
399 case RT5677_HAP_GENE_CTRL8:
400 case RT5677_HAP_GENE_CTRL9:
401 case RT5677_HAP_GENE_CTRL10:
402 case RT5677_PWR_DIG1:
403 case RT5677_PWR_DIG2:
404 case RT5677_PWR_ANLG1:
405 case RT5677_PWR_ANLG2:
406 case RT5677_PWR_DSP1:
407 case RT5677_PWR_DSP_ST:
408 case RT5677_PWR_DSP2:
409 case RT5677_ADC_DAC_HPF_CTRL1:
410 case RT5677_PRIV_INDEX:
411 case RT5677_PRIV_DATA:
412 case RT5677_I2S4_SDP:
413 case RT5677_I2S1_SDP:
414 case RT5677_I2S2_SDP:
415 case RT5677_I2S3_SDP:
416 case RT5677_CLK_TREE_CTRL1:
417 case RT5677_CLK_TREE_CTRL2:
418 case RT5677_CLK_TREE_CTRL3:
419 case RT5677_PLL1_CTRL1:
420 case RT5677_PLL1_CTRL2:
421 case RT5677_PLL2_CTRL1:
422 case RT5677_PLL2_CTRL2:
423 case RT5677_GLB_CLK1:
424 case RT5677_GLB_CLK2:
425 case RT5677_ASRC_1:
426 case RT5677_ASRC_2:
427 case RT5677_ASRC_3:
428 case RT5677_ASRC_4:
429 case RT5677_ASRC_5:
430 case RT5677_ASRC_6:
431 case RT5677_ASRC_7:
432 case RT5677_ASRC_8:
433 case RT5677_ASRC_9:
434 case RT5677_ASRC_10:
435 case RT5677_ASRC_11:
436 case RT5677_ASRC_12:
437 case RT5677_ASRC_13:
438 case RT5677_ASRC_14:
439 case RT5677_ASRC_15:
440 case RT5677_ASRC_16:
441 case RT5677_ASRC_17:
442 case RT5677_ASRC_18:
443 case RT5677_ASRC_19:
444 case RT5677_ASRC_20:
445 case RT5677_ASRC_21:
446 case RT5677_ASRC_22:
447 case RT5677_ASRC_23:
448 case RT5677_VAD_CTRL1:
449 case RT5677_VAD_CTRL2:
450 case RT5677_VAD_CTRL3:
451 case RT5677_VAD_CTRL4:
452 case RT5677_VAD_CTRL5:
453 case RT5677_DSP_INB_CTRL1:
454 case RT5677_DSP_INB_CTRL2:
455 case RT5677_DSP_IN_OUTB_CTRL:
456 case RT5677_DSP_OUTB0_1_DIG_VOL:
457 case RT5677_DSP_OUTB2_3_DIG_VOL:
458 case RT5677_DSP_OUTB4_5_DIG_VOL:
459 case RT5677_DSP_OUTB6_7_DIG_VOL:
460 case RT5677_ADC_EQ_CTRL1:
461 case RT5677_ADC_EQ_CTRL2:
462 case RT5677_EQ_CTRL1:
463 case RT5677_EQ_CTRL2:
464 case RT5677_EQ_CTRL3:
465 case RT5677_SOFT_VOL_ZERO_CROSS1:
466 case RT5677_JD_CTRL1:
467 case RT5677_JD_CTRL2:
468 case RT5677_JD_CTRL3:
469 case RT5677_IRQ_CTRL1:
470 case RT5677_IRQ_CTRL2:
471 case RT5677_GPIO_ST:
472 case RT5677_GPIO_CTRL1:
473 case RT5677_GPIO_CTRL2:
474 case RT5677_GPIO_CTRL3:
475 case RT5677_STO1_ADC_HI_FILTER1:
476 case RT5677_STO1_ADC_HI_FILTER2:
477 case RT5677_MONO_ADC_HI_FILTER1:
478 case RT5677_MONO_ADC_HI_FILTER2:
479 case RT5677_STO2_ADC_HI_FILTER1:
480 case RT5677_STO2_ADC_HI_FILTER2:
481 case RT5677_STO3_ADC_HI_FILTER1:
482 case RT5677_STO3_ADC_HI_FILTER2:
483 case RT5677_STO4_ADC_HI_FILTER1:
484 case RT5677_STO4_ADC_HI_FILTER2:
485 case RT5677_MB_DRC_CTRL1:
486 case RT5677_DRC1_CTRL1:
487 case RT5677_DRC1_CTRL2:
488 case RT5677_DRC1_CTRL3:
489 case RT5677_DRC1_CTRL4:
490 case RT5677_DRC1_CTRL5:
491 case RT5677_DRC1_CTRL6:
492 case RT5677_DRC2_CTRL1:
493 case RT5677_DRC2_CTRL2:
494 case RT5677_DRC2_CTRL3:
495 case RT5677_DRC2_CTRL4:
496 case RT5677_DRC2_CTRL5:
497 case RT5677_DRC2_CTRL6:
498 case RT5677_DRC1_HL_CTRL1:
499 case RT5677_DRC1_HL_CTRL2:
500 case RT5677_DRC2_HL_CTRL1:
501 case RT5677_DRC2_HL_CTRL2:
502 case RT5677_DSP_INB1_SRC_CTRL1:
503 case RT5677_DSP_INB1_SRC_CTRL2:
504 case RT5677_DSP_INB1_SRC_CTRL3:
505 case RT5677_DSP_INB1_SRC_CTRL4:
506 case RT5677_DSP_INB2_SRC_CTRL1:
507 case RT5677_DSP_INB2_SRC_CTRL2:
508 case RT5677_DSP_INB2_SRC_CTRL3:
509 case RT5677_DSP_INB2_SRC_CTRL4:
510 case RT5677_DSP_INB3_SRC_CTRL1:
511 case RT5677_DSP_INB3_SRC_CTRL2:
512 case RT5677_DSP_INB3_SRC_CTRL3:
513 case RT5677_DSP_INB3_SRC_CTRL4:
514 case RT5677_DSP_OUTB1_SRC_CTRL1:
515 case RT5677_DSP_OUTB1_SRC_CTRL2:
516 case RT5677_DSP_OUTB1_SRC_CTRL3:
517 case RT5677_DSP_OUTB1_SRC_CTRL4:
518 case RT5677_DSP_OUTB2_SRC_CTRL1:
519 case RT5677_DSP_OUTB2_SRC_CTRL2:
520 case RT5677_DSP_OUTB2_SRC_CTRL3:
521 case RT5677_DSP_OUTB2_SRC_CTRL4:
522 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
523 case RT5677_DSP_OUTB_45_MIXER_CTRL:
524 case RT5677_DSP_OUTB_67_MIXER_CTRL:
525 case RT5677_DIG_MISC:
526 case RT5677_GEN_CTRL1:
527 case RT5677_GEN_CTRL2:
528 case RT5677_VENDOR_ID:
529 case RT5677_VENDOR_ID1:
530 case RT5677_VENDOR_ID2:
531 return true;
532 default:
533 return false;
534 }
535}
536
537static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
538static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
539static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
540static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
541static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
542
543/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
544static unsigned int bst_tlv[] = {
545 TLV_DB_RANGE_HEAD(7),
546 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
547 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
548 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
549 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
550 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
551 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
552 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
553};
554
555static const struct snd_kcontrol_new rt5677_snd_controls[] = {
556 /* OUTPUT Control */
557 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
558 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
559 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
560 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
561 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
562 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
563
564 /* DAC Digital Volume */
565 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
566 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
567 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
568 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
569 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
570 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
571 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
572 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
573
574 /* IN1/IN2 Control */
575 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
576 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
577
578 /* ADC Digital Volume Control */
579 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
580 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
581 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
582 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
583 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
584 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
585 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
586 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
587 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
588 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
589
590 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
591 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
592 adc_vol_tlv),
593 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
594 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
595 adc_vol_tlv),
596 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
597 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
598 adc_vol_tlv),
599 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
600 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
601 adc_vol_tlv),
602 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
603 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 127, 0,
604 adc_vol_tlv),
605
606 /* ADC Boost Volume Control */
607 SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5677_STO1_2_ADC_BST,
608 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
609 adc_bst_tlv),
610 SOC_DOUBLE_TLV("STO2 ADC Boost Gain", RT5677_STO1_2_ADC_BST,
611 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
612 adc_bst_tlv),
613 SOC_DOUBLE_TLV("STO3 ADC Boost Gain", RT5677_STO3_4_ADC_BST,
614 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
615 adc_bst_tlv),
616 SOC_DOUBLE_TLV("STO4 ADC Boost Gain", RT5677_STO3_4_ADC_BST,
617 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
618 adc_bst_tlv),
619 SOC_DOUBLE_TLV("Mono ADC Boost Gain", RT5677_ADC_BST_CTRL2,
620 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
621 adc_bst_tlv),
622};
623
624/**
625 * set_dmic_clk - Set parameter of dmic.
626 *
627 * @w: DAPM widget.
628 * @kcontrol: The kcontrol of this widget.
629 * @event: Event id.
630 *
631 * Choose dmic clock between 1MHz and 3MHz.
632 * It is better for clock to approximate 3MHz.
633 */
634static int set_dmic_clk(struct snd_soc_dapm_widget *w,
635 struct snd_kcontrol *kcontrol, int event)
636{
637 struct snd_soc_codec *codec = w->codec;
638 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
639 int div[] = {2, 3, 4, 6, 8, 12}, idx = -EINVAL, i;
640 int rate, red, bound, temp;
641
642 rate = rt5677->sysclk;
643 red = 3000000 * 12;
644 for (i = 0; i < ARRAY_SIZE(div); i++) {
645 bound = div[i] * 3000000;
646 if (rate > bound)
647 continue;
648 temp = bound - rate;
649 if (temp < red) {
650 red = temp;
651 idx = i;
652 }
653 }
654
655 if (idx < 0)
656 dev_err(codec->dev, "Failed to set DMIC clock\n");
657 else
658 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
659 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
660 return idx;
661}
662
663static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
664 struct snd_soc_dapm_widget *sink)
665{
666 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(source->codec);
667 unsigned int val;
668
669 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
670 val &= RT5677_SCLK_SRC_MASK;
671 if (val == RT5677_SCLK_SRC_PLL1)
672 return 1;
673 else
674 return 0;
675}
676
677/* Digital Mixer */
678static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
679 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
680 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
681 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
682 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
683};
684
685static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
686 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
687 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
688 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
689 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
690};
691
692static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
693 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
694 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
695 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
696 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
697};
698
699static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
700 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
701 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
702 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
703 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
704};
705
706static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
707 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
708 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
709 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
710 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
711};
712
713static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
714 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
715 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
716 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
717 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
718};
719
720static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
721 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
722 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
723 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
724 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
725};
726
727static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
728 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
729 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
730 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
731 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
732};
733
734static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
735 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
736 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
737 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
738 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
739};
740
741static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
742 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
743 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
744 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
745 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
746};
747
748static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
749 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
750 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
751 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
752 RT5677_M_DAC1_L_SFT, 1, 1),
753};
754
755static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
756 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
757 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
758 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
759 RT5677_M_DAC1_R_SFT, 1, 1),
760};
761
762static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
763 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
764 RT5677_M_ST_DAC1_L_SFT, 1, 1),
765 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
766 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
767 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
768 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
769 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
770 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
771};
772
773static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
774 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
775 RT5677_M_ST_DAC1_R_SFT, 1, 1),
776 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
777 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
778 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
779 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
780 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
781 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
782};
783
784static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
785 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
786 RT5677_M_ST_DAC2_L_SFT, 1, 1),
787 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
788 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
789 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
790 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
791 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
792 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
793};
794
795static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
796 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
797 RT5677_M_ST_DAC2_R_SFT, 1, 1),
798 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
799 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
800 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
801 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
802 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
803 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
804};
805
806static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
807 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
808 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
809 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
810 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
811 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
812 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
813 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
814 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
815};
816
817static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
818 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
819 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
820 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
821 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
822 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
823 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
824 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
825 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
826};
827
828static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
829 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
830 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
831 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
832 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
833 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
834 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
835 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
836 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
837};
838
839static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
840 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
841 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
842 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
843 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
844 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
845 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
846 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
847 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
848};
849
850static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
851 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
852 RT5677_DSP_IB_01_H_SFT, 1, 1),
853 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
854 RT5677_DSP_IB_23_H_SFT, 1, 1),
855 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
856 RT5677_DSP_IB_45_H_SFT, 1, 1),
857 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
858 RT5677_DSP_IB_6_H_SFT, 1, 1),
859 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
860 RT5677_DSP_IB_7_H_SFT, 1, 1),
861 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
862 RT5677_DSP_IB_8_H_SFT, 1, 1),
863 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
864 RT5677_DSP_IB_9_H_SFT, 1, 1),
865};
866
867static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
868 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
869 RT5677_DSP_IB_01_L_SFT, 1, 1),
870 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
871 RT5677_DSP_IB_23_L_SFT, 1, 1),
872 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
873 RT5677_DSP_IB_45_L_SFT, 1, 1),
874 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
875 RT5677_DSP_IB_6_L_SFT, 1, 1),
876 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
877 RT5677_DSP_IB_7_L_SFT, 1, 1),
878 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
879 RT5677_DSP_IB_8_L_SFT, 1, 1),
880 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
881 RT5677_DSP_IB_9_L_SFT, 1, 1),
882};
883
884static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
885 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
886 RT5677_DSP_IB_01_H_SFT, 1, 1),
887 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
888 RT5677_DSP_IB_23_H_SFT, 1, 1),
889 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
890 RT5677_DSP_IB_45_H_SFT, 1, 1),
891 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
892 RT5677_DSP_IB_6_H_SFT, 1, 1),
893 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
894 RT5677_DSP_IB_7_H_SFT, 1, 1),
895 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
896 RT5677_DSP_IB_8_H_SFT, 1, 1),
897 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
898 RT5677_DSP_IB_9_H_SFT, 1, 1),
899};
900
901static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
902 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
903 RT5677_DSP_IB_01_L_SFT, 1, 1),
904 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
905 RT5677_DSP_IB_23_L_SFT, 1, 1),
906 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
907 RT5677_DSP_IB_45_L_SFT, 1, 1),
908 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
909 RT5677_DSP_IB_6_L_SFT, 1, 1),
910 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
911 RT5677_DSP_IB_7_L_SFT, 1, 1),
912 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
913 RT5677_DSP_IB_8_L_SFT, 1, 1),
914 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
915 RT5677_DSP_IB_9_L_SFT, 1, 1),
916};
917
918static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
919 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
920 RT5677_DSP_IB_01_H_SFT, 1, 1),
921 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
922 RT5677_DSP_IB_23_H_SFT, 1, 1),
923 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
924 RT5677_DSP_IB_45_H_SFT, 1, 1),
925 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
926 RT5677_DSP_IB_6_H_SFT, 1, 1),
927 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
928 RT5677_DSP_IB_7_H_SFT, 1, 1),
929 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
930 RT5677_DSP_IB_8_H_SFT, 1, 1),
931 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
932 RT5677_DSP_IB_9_H_SFT, 1, 1),
933};
934
935static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
936 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
937 RT5677_DSP_IB_01_L_SFT, 1, 1),
938 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
939 RT5677_DSP_IB_23_L_SFT, 1, 1),
940 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
941 RT5677_DSP_IB_45_L_SFT, 1, 1),
942 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
943 RT5677_DSP_IB_6_L_SFT, 1, 1),
944 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
945 RT5677_DSP_IB_7_L_SFT, 1, 1),
946 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
947 RT5677_DSP_IB_8_L_SFT, 1, 1),
948 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
949 RT5677_DSP_IB_9_L_SFT, 1, 1),
950};
951
952
953/* Mux */
954/* DAC1 L/R source */ /* MX-29 [10:8] */
955static const char * const rt5677_dac1_src[] = {
956 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
957 "OB 01"
958};
959
960static SOC_ENUM_SINGLE_DECL(
961 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
962 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
963
964static const struct snd_kcontrol_new rt5677_dac1_mux =
965 SOC_DAPM_ENUM("DAC1 source", rt5677_dac1_enum);
966
967/* ADDA1 L/R source */ /* MX-29 [1:0] */
968static const char * const rt5677_adda1_src[] = {
969 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
970};
971
972static SOC_ENUM_SINGLE_DECL(
973 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
974 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
975
976static const struct snd_kcontrol_new rt5677_adda1_mux =
977 SOC_DAPM_ENUM("ADDA1 source", rt5677_adda1_enum);
978
979
980/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
981static const char * const rt5677_dac2l_src[] = {
982 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
983 "OB 2",
984};
985
986static SOC_ENUM_SINGLE_DECL(
987 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
988 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
989
990static const struct snd_kcontrol_new rt5677_dac2_l_mux =
991 SOC_DAPM_ENUM("DAC2 L source", rt5677_dac2l_enum);
992
993static const char * const rt5677_dac2r_src[] = {
994 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
995 "OB 3", "Haptic Generator", "VAD ADC"
996};
997
998static SOC_ENUM_SINGLE_DECL(
999 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1000 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1001
1002static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1003 SOC_DAPM_ENUM("DAC2 R source", rt5677_dac2r_enum);
1004
1005/*DAC3 L/R source*/ /* MX-16 [6:4] [2:0] */
1006static const char * const rt5677_dac3l_src[] = {
1007 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1008 "SLB DAC 4", "OB 4"
1009};
1010
1011static SOC_ENUM_SINGLE_DECL(
1012 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1013 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1014
1015static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1016 SOC_DAPM_ENUM("DAC3 L source", rt5677_dac3l_enum);
1017
1018static const char * const rt5677_dac3r_src[] = {
1019 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1020 "SLB DAC 5", "OB 5"
1021};
1022
1023static SOC_ENUM_SINGLE_DECL(
1024 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1025 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1026
1027static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1028 SOC_DAPM_ENUM("DAC3 R source", rt5677_dac3r_enum);
1029
1030/*DAC4 L/R source*/ /* MX-16 [14:12] [10:8] */
1031static const char * const rt5677_dac4l_src[] = {
1032 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1033 "SLB DAC 6", "OB 6"
1034};
1035
1036static SOC_ENUM_SINGLE_DECL(
1037 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1038 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1039
1040static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1041 SOC_DAPM_ENUM("DAC4 L source", rt5677_dac4l_enum);
1042
1043static const char * const rt5677_dac4r_src[] = {
1044 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1045 "SLB DAC 7", "OB 7"
1046};
1047
1048static SOC_ENUM_SINGLE_DECL(
1049 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1050 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1051
1052static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1053 SOC_DAPM_ENUM("DAC4 R source", rt5677_dac4r_enum);
1054
1055/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1056static const char * const rt5677_iob_bypass_src[] = {
1057 "Bypass", "Pass SRC"
1058};
1059
1060static SOC_ENUM_SINGLE_DECL(
1061 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1062 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1063
1064static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1065 SOC_DAPM_ENUM("OB01 Bypass source", rt5677_ob01_bypass_src_enum);
1066
1067static SOC_ENUM_SINGLE_DECL(
1068 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1069 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1070
1071static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1072 SOC_DAPM_ENUM("OB23 Bypass source", rt5677_ob23_bypass_src_enum);
1073
1074static SOC_ENUM_SINGLE_DECL(
1075 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1076 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1077
1078static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1079 SOC_DAPM_ENUM("IB01 Bypass source", rt5677_ib01_bypass_src_enum);
1080
1081static SOC_ENUM_SINGLE_DECL(
1082 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1083 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1084
1085static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1086 SOC_DAPM_ENUM("IB23 Bypass source", rt5677_ib23_bypass_src_enum);
1087
1088static SOC_ENUM_SINGLE_DECL(
1089 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1090 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1091
1092static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1093 SOC_DAPM_ENUM("IB45 Bypass source", rt5677_ib45_bypass_src_enum);
1094
1095/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1096static const char * const rt5677_stereo_adc2_src[] = {
1097 "DD MIX1", "DMIC", "Stereo DAC MIX"
1098};
1099
1100static SOC_ENUM_SINGLE_DECL(
1101 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1102 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1103
1104static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1105 SOC_DAPM_ENUM("Stereo1 ADC2 source", rt5677_stereo1_adc2_enum);
1106
1107static SOC_ENUM_SINGLE_DECL(
1108 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1109 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1110
1111static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1112 SOC_DAPM_ENUM("Stereo2 ADC2 source", rt5677_stereo2_adc2_enum);
1113
1114static SOC_ENUM_SINGLE_DECL(
1115 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1116 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1117
1118static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1119 SOC_DAPM_ENUM("Stereo3 ADC2 source", rt5677_stereo3_adc2_enum);
1120
1121/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1122static const char * const rt5677_dmic_src[] = {
1123 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1124};
1125
1126static SOC_ENUM_SINGLE_DECL(
1127 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1128 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1129
1130static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1131 SOC_DAPM_ENUM("Mono DMIC L source", rt5677_mono_dmic_l_enum);
1132
1133static SOC_ENUM_SINGLE_DECL(
1134 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1135 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1136
1137static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1138 SOC_DAPM_ENUM("Mono DMIC R source", rt5677_mono_dmic_r_enum);
1139
1140static SOC_ENUM_SINGLE_DECL(
1141 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1142 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1143
1144static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1145 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5677_stereo1_dmic_enum);
1146
1147static SOC_ENUM_SINGLE_DECL(
1148 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1149 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1150
1151static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1152 SOC_DAPM_ENUM("Stereo2 DMIC source", rt5677_stereo2_dmic_enum);
1153
1154static SOC_ENUM_SINGLE_DECL(
1155 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1156 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1157
1158static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1159 SOC_DAPM_ENUM("Stereo3 DMIC source", rt5677_stereo3_dmic_enum);
1160
1161static SOC_ENUM_SINGLE_DECL(
1162 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1163 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1164
1165static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1166 SOC_DAPM_ENUM("Stereo4 DMIC source", rt5677_stereo4_dmic_enum);
1167
1168/* Stereo2 ADC source */ /* MX-26 [0] */
1169static const char * const rt5677_stereo2_adc_lr_src[] = {
1170 "L", "LR"
1171};
1172
1173static SOC_ENUM_SINGLE_DECL(
1174 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1175 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1176
1177static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1178 SOC_DAPM_ENUM("Stereo2 ADC LR source", rt5677_stereo2_adc_lr_enum);
1179
1180/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1181static const char * const rt5677_stereo_adc1_src[] = {
1182 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1183};
1184
1185static SOC_ENUM_SINGLE_DECL(
1186 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1187 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1188
1189static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1190 SOC_DAPM_ENUM("Stereo1 ADC1 source", rt5677_stereo1_adc1_enum);
1191
1192static SOC_ENUM_SINGLE_DECL(
1193 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1194 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1195
1196static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1197 SOC_DAPM_ENUM("Stereo2 ADC1 source", rt5677_stereo2_adc1_enum);
1198
1199static SOC_ENUM_SINGLE_DECL(
1200 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1201 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1202
1203static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1204 SOC_DAPM_ENUM("Stereo3 ADC1 source", rt5677_stereo3_adc1_enum);
1205
1206/* Mono ADC Left source 2 */ /* MX-28 [11:10] */
1207static const char * const rt5677_mono_adc2_l_src[] = {
1208 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1209};
1210
1211static SOC_ENUM_SINGLE_DECL(
1212 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1213 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1214
1215static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1216 SOC_DAPM_ENUM("Mono ADC2 L source", rt5677_mono_adc2_l_enum);
1217
1218/* Mono ADC Left source 1 */ /* MX-28 [13:12] */
1219static const char * const rt5677_mono_adc1_l_src[] = {
1220 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1221};
1222
1223static SOC_ENUM_SINGLE_DECL(
1224 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1225 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1226
1227static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1228 SOC_DAPM_ENUM("Mono ADC1 L source", rt5677_mono_adc1_l_enum);
1229
1230/* Mono ADC Right source 2 */ /* MX-28 [3:2] */
1231static const char * const rt5677_mono_adc2_r_src[] = {
1232 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1233};
1234
1235static SOC_ENUM_SINGLE_DECL(
1236 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1237 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1238
1239static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1240 SOC_DAPM_ENUM("Mono ADC2 R source", rt5677_mono_adc2_r_enum);
1241
1242/* Mono ADC Right source 1 */ /* MX-28 [5:4] */
1243static const char * const rt5677_mono_adc1_r_src[] = {
1244 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1245};
1246
1247static SOC_ENUM_SINGLE_DECL(
1248 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1249 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1250
1251static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1252 SOC_DAPM_ENUM("Mono ADC1 R source", rt5677_mono_adc1_r_enum);
1253
1254/* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1255static const char * const rt5677_stereo4_adc2_src[] = {
1256 "DD MIX1", "DMIC", "DD MIX2"
1257};
1258
1259static SOC_ENUM_SINGLE_DECL(
1260 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1261 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1262
1263static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1264 SOC_DAPM_ENUM("Stereo4 ADC2 source", rt5677_stereo4_adc2_enum);
1265
1266
1267/* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1268static const char * const rt5677_stereo4_adc1_src[] = {
1269 "DD MIX1", "ADC1/2", "DD MIX2"
1270};
1271
1272static SOC_ENUM_SINGLE_DECL(
1273 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1274 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1275
1276static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1277 SOC_DAPM_ENUM("Stereo4 ADC1 source", rt5677_stereo4_adc1_enum);
1278
1279/* InBound0/1 Source */ /* MX-A3 [14:12] */
1280static const char * const rt5677_inbound01_src[] = {
1281 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1282 "VAD ADC/DAC1 FS"
1283};
1284
1285static SOC_ENUM_SINGLE_DECL(
1286 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1287 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1288
1289static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1290 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1291
1292/* InBound2/3 Source */ /* MX-A3 [10:8] */
1293static const char * const rt5677_inbound23_src[] = {
1294 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1295 "DAC1 FS", "IF4 DAC"
1296};
1297
1298static SOC_ENUM_SINGLE_DECL(
1299 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1300 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1301
1302static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1303 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1304
1305/* InBound4/5 Source */ /* MX-A3 [6:4] */
1306static const char * const rt5677_inbound45_src[] = {
1307 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1308 "IF3 DAC"
1309};
1310
1311static SOC_ENUM_SINGLE_DECL(
1312 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1313 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1314
1315static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1316 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1317
1318/* InBound6 Source */ /* MX-A3 [2:0] */
1319static const char * const rt5677_inbound6_src[] = {
1320 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1321 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1322};
1323
1324static SOC_ENUM_SINGLE_DECL(
1325 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1326 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1327
1328static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1329 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1330
1331/* InBound7 Source */ /* MX-A4 [14:12] */
1332static const char * const rt5677_inbound7_src[] = {
1333 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1334 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1335};
1336
1337static SOC_ENUM_SINGLE_DECL(
1338 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1339 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1340
1341static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1342 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1343
1344/* InBound8 Source */ /* MX-A4 [10:8] */
1345static const char * const rt5677_inbound8_src[] = {
1346 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1347 "MONO ADC MIX L", "DACL1 FS"
1348};
1349
1350static SOC_ENUM_SINGLE_DECL(
1351 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1352 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1353
1354static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1355 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1356
1357/* InBound9 Source */ /* MX-A4 [6:4] */
1358static const char * const rt5677_inbound9_src[] = {
1359 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1360 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1361};
1362
1363static SOC_ENUM_SINGLE_DECL(
1364 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1365 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1366
1367static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1368 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1369
1370/* VAD Source */ /* MX-9F [6:4] */
1371static const char * const rt5677_vad_src[] = {
1372 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1373 "STO3 ADC MIX L"
1374};
1375
1376static SOC_ENUM_SINGLE_DECL(
1377 rt5677_vad_enum, RT5677_VAD_CTRL4,
1378 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1379
1380static const struct snd_kcontrol_new rt5677_vad_src_mux =
1381 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1382
1383/* Sidetone Source */ /* MX-13 [11:9] */
1384static const char * const rt5677_sidetone_src[] = {
1385 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1386};
1387
1388static SOC_ENUM_SINGLE_DECL(
1389 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
1390 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
1391
1392static const struct snd_kcontrol_new rt5677_sidetone_mux =
1393 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
1394
1395/* DAC1/2 Source */ /* MX-15 [1:0] */
1396static const char * const rt5677_dac12_src[] = {
1397 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1398};
1399
1400static SOC_ENUM_SINGLE_DECL(
1401 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
1402 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
1403
1404static const struct snd_kcontrol_new rt5677_dac12_mux =
1405 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
1406
1407/* DAC3 Source */ /* MX-15 [5:4] */
1408static const char * const rt5677_dac3_src[] = {
1409 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
1410};
1411
1412static SOC_ENUM_SINGLE_DECL(
1413 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
1414 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
1415
1416static const struct snd_kcontrol_new rt5677_dac3_mux =
1417 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
1418
1419/* PDM channel source */ /* MX-31 [13:12][9:8][5:4][1:0] */
1420static const char * const rt5677_pdm_src[] = {
1421 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1422};
1423
1424static SOC_ENUM_SINGLE_DECL(
1425 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
1426 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
1427
1428static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
1429 SOC_DAPM_ENUM("PDM1 source", rt5677_pdm1_l_enum);
1430
1431static SOC_ENUM_SINGLE_DECL(
1432 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
1433 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
1434
1435static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
1436 SOC_DAPM_ENUM("PDM2 source", rt5677_pdm2_l_enum);
1437
1438static SOC_ENUM_SINGLE_DECL(
1439 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
1440 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
1441
1442static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
1443 SOC_DAPM_ENUM("PDM1 source", rt5677_pdm1_r_enum);
1444
1445static SOC_ENUM_SINGLE_DECL(
1446 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
1447 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
1448
1449static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
1450 SOC_DAPM_ENUM("PDM2 source", rt5677_pdm2_r_enum);
1451
1452/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0]*/
1453static const char * const rt5677_if12_adc1_src[] = {
1454 "STO1 ADC MIX", "OB01", "VAD ADC"
1455};
1456
1457static SOC_ENUM_SINGLE_DECL(
1458 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
1459 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
1460
1461static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
1462 SOC_DAPM_ENUM("IF1 ADC1 source", rt5677_if1_adc1_enum);
1463
1464static SOC_ENUM_SINGLE_DECL(
1465 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
1466 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
1467
1468static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
1469 SOC_DAPM_ENUM("IF2 ADC1 source", rt5677_if2_adc1_enum);
1470
1471static SOC_ENUM_SINGLE_DECL(
1472 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
1473 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
1474
1475static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
1476 SOC_DAPM_ENUM("SLB ADC1 source", rt5677_slb_adc1_enum);
1477
1478/* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
1479static const char * const rt5677_if12_adc2_src[] = {
1480 "STO2 ADC MIX", "OB23"
1481};
1482
1483static SOC_ENUM_SINGLE_DECL(
1484 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
1485 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
1486
1487static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
1488 SOC_DAPM_ENUM("IF1 ADC2 source", rt5677_if1_adc2_enum);
1489
1490static SOC_ENUM_SINGLE_DECL(
1491 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
1492 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
1493
1494static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
1495 SOC_DAPM_ENUM("IF2 ADC2 source", rt5677_if2_adc2_enum);
1496
1497static SOC_ENUM_SINGLE_DECL(
1498 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
1499 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
1500
1501static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
1502 SOC_DAPM_ENUM("SLB ADC2 source", rt5677_slb_adc2_enum);
1503
1504/* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
1505static const char * const rt5677_if12_adc3_src[] = {
1506 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
1507};
1508
1509static SOC_ENUM_SINGLE_DECL(
1510 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
1511 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
1512
1513static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
1514 SOC_DAPM_ENUM("IF1 ADC3 source", rt5677_if1_adc3_enum);
1515
1516static SOC_ENUM_SINGLE_DECL(
1517 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
1518 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
1519
1520static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
1521 SOC_DAPM_ENUM("IF2 ADC3 source", rt5677_if2_adc3_enum);
1522
1523static SOC_ENUM_SINGLE_DECL(
1524 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
1525 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
1526
1527static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
1528 SOC_DAPM_ENUM("SLB ADC3 source", rt5677_slb_adc3_enum);
1529
1530/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
1531static const char * const rt5677_if12_adc4_src[] = {
1532 "STO4 ADC MIX", "OB67", "OB01"
1533};
1534
1535static SOC_ENUM_SINGLE_DECL(
1536 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
1537 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
1538
1539static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
1540 SOC_DAPM_ENUM("IF1 ADC4 source", rt5677_if1_adc4_enum);
1541
1542static SOC_ENUM_SINGLE_DECL(
1543 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
1544 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
1545
1546static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
1547 SOC_DAPM_ENUM("IF2 ADC4 source", rt5677_if2_adc4_enum);
1548
1549static SOC_ENUM_SINGLE_DECL(
1550 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
1551 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
1552
1553static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
1554 SOC_DAPM_ENUM("SLB ADC4 source", rt5677_slb_adc4_enum);
1555
1556/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4]*/
1557static const char * const rt5677_if34_adc_src[] = {
1558 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
1559 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
1560};
1561
1562static SOC_ENUM_SINGLE_DECL(
1563 rt5677_if3_adc_enum, RT5677_IF3_DATA,
1564 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
1565
1566static const struct snd_kcontrol_new rt5677_if3_adc_mux =
1567 SOC_DAPM_ENUM("IF3 ADC source", rt5677_if3_adc_enum);
1568
1569static SOC_ENUM_SINGLE_DECL(
1570 rt5677_if4_adc_enum, RT5677_IF4_DATA,
1571 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
1572
1573static const struct snd_kcontrol_new rt5677_if4_adc_mux =
1574 SOC_DAPM_ENUM("IF4 ADC source", rt5677_if4_adc_enum);
1575
1576static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
1577 struct snd_kcontrol *kcontrol, int event)
1578{
1579 struct snd_soc_codec *codec = w->codec;
1580 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1581
1582 switch (event) {
1583 case SND_SOC_DAPM_POST_PMU:
1584 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1585 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
1586 break;
1587
1588 case SND_SOC_DAPM_PRE_PMD:
1589 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1590 RT5677_PWR_BST1_P, 0);
1591 break;
1592
1593 default:
1594 return 0;
1595 }
1596
1597 return 0;
1598}
1599
1600static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
1601 struct snd_kcontrol *kcontrol, int event)
1602{
1603 struct snd_soc_codec *codec = w->codec;
1604 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1605
1606 switch (event) {
1607 case SND_SOC_DAPM_POST_PMU:
1608 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1609 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
1610 break;
1611
1612 case SND_SOC_DAPM_PRE_PMD:
1613 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1614 RT5677_PWR_BST2_P, 0);
1615 break;
1616
1617 default:
1618 return 0;
1619 }
1620
1621 return 0;
1622}
1623
1624static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
1625 struct snd_kcontrol *kcontrol, int event)
1626{
1627 struct snd_soc_codec *codec = w->codec;
1628 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1629
1630 switch (event) {
1631 case SND_SOC_DAPM_POST_PMU:
1632 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
1633 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
1634 break;
1635 default:
1636 return 0;
1637 }
1638
1639 return 0;
1640}
1641
1642static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
1643 struct snd_kcontrol *kcontrol, int event)
1644{
1645 struct snd_soc_codec *codec = w->codec;
1646 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1647
1648 switch (event) {
1649 case SND_SOC_DAPM_POST_PMU:
1650 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
1651 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
1652 break;
1653 default:
1654 return 0;
1655 }
1656
1657 return 0;
1658}
1659
1660static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
1661 struct snd_kcontrol *kcontrol, int event)
1662{
1663 struct snd_soc_codec *codec = w->codec;
1664 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1665
1666 switch (event) {
1667 case SND_SOC_DAPM_POST_PMU:
1668 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1669 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
1670 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
1671 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
1672 break;
1673 default:
1674 return 0;
1675 }
1676
1677 return 0;
1678}
1679
1680static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
1681 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
1682 0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU),
1683 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
1684 0, rt5677_set_pll2_event, SND_SOC_DAPM_POST_PMU),
1685
1686 /* Input Side */
1687 /* micbias */
1688 SND_SOC_DAPM_SUPPLY("micbias1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
1689 0, rt5677_set_micbias1_event, SND_SOC_DAPM_POST_PMU),
1690
1691 /* Input Lines */
1692 SND_SOC_DAPM_INPUT("DMIC L1"),
1693 SND_SOC_DAPM_INPUT("DMIC R1"),
1694 SND_SOC_DAPM_INPUT("DMIC L2"),
1695 SND_SOC_DAPM_INPUT("DMIC R2"),
1696 SND_SOC_DAPM_INPUT("DMIC L3"),
1697 SND_SOC_DAPM_INPUT("DMIC R3"),
1698 SND_SOC_DAPM_INPUT("DMIC L4"),
1699 SND_SOC_DAPM_INPUT("DMIC R4"),
1700
1701 SND_SOC_DAPM_INPUT("IN1P"),
1702 SND_SOC_DAPM_INPUT("IN1N"),
1703 SND_SOC_DAPM_INPUT("IN2P"),
1704 SND_SOC_DAPM_INPUT("IN2N"),
1705
1706 SND_SOC_DAPM_INPUT("Haptic Generator"),
1707
1708 SND_SOC_DAPM_PGA("DMIC1", RT5677_DMIC_CTRL1, RT5677_DMIC_1_EN_SFT, 0,
1709 NULL, 0),
1710 SND_SOC_DAPM_PGA("DMIC2", RT5677_DMIC_CTRL1, RT5677_DMIC_2_EN_SFT, 0,
1711 NULL, 0),
1712 SND_SOC_DAPM_PGA("DMIC3", RT5677_DMIC_CTRL1, RT5677_DMIC_3_EN_SFT, 0,
1713 NULL, 0),
1714 SND_SOC_DAPM_PGA("DMIC4", RT5677_DMIC_CTRL2, RT5677_DMIC_4_EN_SFT, 0,
1715 NULL, 0),
1716
1717 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1718 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1719
1720 /* Boost */
1721 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
1722 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
1723 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1724 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
1725 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
1726 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1727
1728 /* ADCs */
1729 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
1730 0, 0),
1731 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
1732 0, 0),
1733 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
1734
1735 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
1736 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
1737 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
1738 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
1739 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
1740 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
1741 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
1742 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
1743
1744 /* ADC Mux */
1745 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1746 &rt5677_sto1_dmic_mux),
1747 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1748 &rt5677_sto1_adc1_mux),
1749 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1750 &rt5677_sto1_adc2_mux),
1751 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
1752 &rt5677_sto2_dmic_mux),
1753 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1754 &rt5677_sto2_adc1_mux),
1755 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1756 &rt5677_sto2_adc2_mux),
1757 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
1758 &rt5677_sto2_adc_lr_mux),
1759 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
1760 &rt5677_sto3_dmic_mux),
1761 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1762 &rt5677_sto3_adc1_mux),
1763 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1764 &rt5677_sto3_adc2_mux),
1765 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
1766 &rt5677_sto4_dmic_mux),
1767 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1768 &rt5677_sto4_adc1_mux),
1769 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1770 &rt5677_sto4_adc2_mux),
1771 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1772 &rt5677_mono_dmic_l_mux),
1773 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1774 &rt5677_mono_dmic_r_mux),
1775 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
1776 &rt5677_mono_adc2_l_mux),
1777 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
1778 &rt5677_mono_adc1_l_mux),
1779 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
1780 &rt5677_mono_adc1_r_mux),
1781 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
1782 &rt5677_mono_adc2_r_mux),
1783
1784 /* ADC Mixer */
1785 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
1786 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
1787 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
1788 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
1789 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
1790 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
1791 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
1792 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
1793 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1794 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
1795 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1796 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
1797 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
1798 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
1799 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
1800 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
1801 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
1802 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
1803 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
1804 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
1805 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
1806 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
1807 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
1808 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
1809 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
1810 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1811 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1812 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
1813 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
1814 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1815 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1816 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
1817
1818 /* ADC PGA */
1819 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1820 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1821 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1822 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1823 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1824 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1825 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1826 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1827 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1828 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1829 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1830 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1831 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1832 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1833 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1834 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1835 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1836 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1837
1838 /* DSP */
1839 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
1840 &rt5677_ib9_src_mux),
1841 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
1842 &rt5677_ib8_src_mux),
1843 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
1844 &rt5677_ib7_src_mux),
1845 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
1846 &rt5677_ib6_src_mux),
1847 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
1848 &rt5677_ib45_src_mux),
1849 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
1850 &rt5677_ib23_src_mux),
1851 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
1852 &rt5677_ib01_src_mux),
1853 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
1854 &rt5677_ib45_bypass_src_mux),
1855 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
1856 &rt5677_ib23_bypass_src_mux),
1857 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
1858 &rt5677_ib01_bypass_src_mux),
1859 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
1860 &rt5677_ob23_bypass_src_mux),
1861 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
1862 &rt5677_ob01_bypass_src_mux),
1863
1864 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
1865 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
1866
1867 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
1868 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
1869 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
1870 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
1871 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
1872 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
1873
1874 /* Digital Interface */
1875 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
1876 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
1877 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1878 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1879 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1880 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1881 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1882 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
1883 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
1884 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
1885 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
1886 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
1887 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
1888 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
1889 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1890 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1891 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1892 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1893
1894 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
1895 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
1896 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1897 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1898 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1899 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1900 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1901 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
1902 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
1903 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
1904 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
1905 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
1906 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
1907 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
1908 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1909 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1910 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1911 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1912
1913 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
1914 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
1915 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1916 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1917 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1918 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1919 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1920 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1921
1922 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
1923 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
1924 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1925 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1926 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1927 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1928 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1929 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1930
1931 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
1932 RT5677_PWR_SLB_BIT, 0, NULL, 0),
1933 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1934 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1935 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1936 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1937 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1938 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
1939 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
1940 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
1941 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
1942 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
1943 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
1944 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
1945 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1946 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1947 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1948 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1949
1950 /* Digital Interface Select */
1951 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1952 &rt5677_if1_adc1_mux),
1953 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1954 &rt5677_if1_adc2_mux),
1955 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
1956 &rt5677_if1_adc3_mux),
1957 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
1958 &rt5677_if1_adc4_mux),
1959 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1960 &rt5677_if2_adc1_mux),
1961 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1962 &rt5677_if2_adc2_mux),
1963 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
1964 &rt5677_if2_adc3_mux),
1965 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
1966 &rt5677_if2_adc4_mux),
1967 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
1968 &rt5677_if3_adc_mux),
1969 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
1970 &rt5677_if4_adc_mux),
1971 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
1972 &rt5677_slb_adc1_mux),
1973 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
1974 &rt5677_slb_adc2_mux),
1975 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
1976 &rt5677_slb_adc3_mux),
1977 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
1978 &rt5677_slb_adc4_mux),
1979
1980 /* Audio Interface */
1981 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1982 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1983 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1984 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1985 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1986 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1987 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
1988 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
1989 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
1990 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
1991
1992 /* Sidetone Mux */
1993 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
1994 &rt5677_sidetone_mux),
1995 /* VAD Mux*/
1996 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
1997 &rt5677_vad_src_mux),
1998
1999 /* Tensilica DSP */
2000 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2001 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
2002 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
2003 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
2004 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
2005 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
2006 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
2007 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
2008 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
2009 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
2010 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
2011 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
2012 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
2013
2014 /* Output Side */
2015 /* DAC mixer before sound effect */
2016 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2017 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
2018 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2019 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
2020 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
2021
2022 /* DAC Mux */
2023 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
2024 &rt5677_dac1_mux),
2025 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
2026 &rt5677_adda1_mux),
2027 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
2028 &rt5677_dac12_mux),
2029 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
2030 &rt5677_dac3_mux),
2031
2032 /* DAC2 channel Mux */
2033 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2034 &rt5677_dac2_l_mux),
2035 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2036 &rt5677_dac2_r_mux),
2037
2038 /* DAC3 channel Mux */
2039 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
2040 &rt5677_dac3_l_mux),
2041 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
2042 &rt5677_dac3_r_mux),
2043
2044 /* DAC4 channel Mux */
2045 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
2046 &rt5677_dac4_l_mux),
2047 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
2048 &rt5677_dac4_r_mux),
2049
2050 /* DAC Mixer */
2051 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
2052 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
2053 SND_SOC_DAPM_SUPPLY("dac mono left filter", RT5677_PWR_DIG2,
2054 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
2055 SND_SOC_DAPM_SUPPLY("dac mono right filter", RT5677_PWR_DIG2,
2056 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
2057
2058 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2059 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
2060 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2061 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
2062 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2063 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
2064 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2065 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
2066 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
2067 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
2068 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
2069 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
2070 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
2071 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
2072 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
2073 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
2074 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2075 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2076 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2077 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2078
2079 /* DACs */
2080 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
2081 RT5677_PWR_DAC1_BIT, 0),
2082 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
2083 RT5677_PWR_DAC2_BIT, 0),
2084 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
2085 RT5677_PWR_DAC3_BIT, 0),
2086
2087 /* PDM */
2088 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
2089 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
2090 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
2091 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
2092
2093 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
2094 1, &rt5677_pdm1_l_mux),
2095 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
2096 1, &rt5677_pdm1_r_mux),
2097 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
2098 1, &rt5677_pdm2_l_mux),
2099 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
2100 1, &rt5677_pdm2_r_mux),
2101
2102 SND_SOC_DAPM_PGA_S("LOUT1 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
2103 0, NULL, 0),
2104 SND_SOC_DAPM_PGA_S("LOUT2 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
2105 0, NULL, 0),
2106 SND_SOC_DAPM_PGA_S("LOUT3 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
2107 0, NULL, 0),
2108
2109 /* Output Lines */
2110 SND_SOC_DAPM_OUTPUT("LOUT1"),
2111 SND_SOC_DAPM_OUTPUT("LOUT2"),
2112 SND_SOC_DAPM_OUTPUT("LOUT3"),
2113 SND_SOC_DAPM_OUTPUT("PDM1L"),
2114 SND_SOC_DAPM_OUTPUT("PDM1R"),
2115 SND_SOC_DAPM_OUTPUT("PDM2L"),
2116 SND_SOC_DAPM_OUTPUT("PDM2R"),
2117};
2118
2119static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
2120 { "DMIC1", NULL, "DMIC L1" },
2121 { "DMIC1", NULL, "DMIC R1" },
2122 { "DMIC2", NULL, "DMIC L2" },
2123 { "DMIC2", NULL, "DMIC R2" },
2124 { "DMIC3", NULL, "DMIC L3" },
2125 { "DMIC3", NULL, "DMIC R3" },
2126 { "DMIC4", NULL, "DMIC L4" },
2127 { "DMIC4", NULL, "DMIC R4" },
2128
2129 { "DMIC L1", NULL, "DMIC CLK" },
2130 { "DMIC R1", NULL, "DMIC CLK" },
2131 { "DMIC L2", NULL, "DMIC CLK" },
2132 { "DMIC R2", NULL, "DMIC CLK" },
2133 { "DMIC L3", NULL, "DMIC CLK" },
2134 { "DMIC R3", NULL, "DMIC CLK" },
2135 { "DMIC L4", NULL, "DMIC CLK" },
2136 { "DMIC R4", NULL, "DMIC CLK" },
2137
2138 { "BST1", NULL, "IN1P" },
2139 { "BST1", NULL, "IN1N" },
2140 { "BST2", NULL, "IN2P" },
2141 { "BST2", NULL, "IN2N" },
2142
2143 { "IN1P", NULL, "micbias1" },
2144 { "IN1N", NULL, "micbias1" },
2145 { "IN2P", NULL, "micbias1" },
2146 { "IN2N", NULL, "micbias1" },
2147
2148 { "ADC 1", NULL, "BST1" },
2149 { "ADC 1", NULL, "ADC 1 power" },
2150 { "ADC 1", NULL, "ADC1 clock" },
2151 { "ADC 2", NULL, "BST2" },
2152 { "ADC 2", NULL, "ADC 2 power" },
2153 { "ADC 2", NULL, "ADC2 clock" },
2154
2155 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2156 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2157 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
2158 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
2159
2160 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
2161 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
2162 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
2163 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
2164
2165 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
2166 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
2167 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
2168 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
2169
2170 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
2171 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
2172 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
2173 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
2174
2175 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
2176 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
2177 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
2178 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
2179
2180 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
2181 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
2182 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
2183 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
2184
2185 { "ADC 1_2", NULL, "ADC 1" },
2186 { "ADC 1_2", NULL, "ADC 2" },
2187
2188 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2189 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2190 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2191
2192 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2193 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2194 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2195
2196 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2197 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2198 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2199
2200 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2201 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
2202 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2203
2204 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2205 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2206 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2207
2208 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2209 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2210 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2211
2212 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2213 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2214 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
2215
2216 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2217 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2218 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
2219
2220 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
2221 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
2222 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2223
2224 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
2225 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
2226 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2227
2228 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
2229 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
2230 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2231
2232 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
2233 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
2234 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2235
2236 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2237 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2238 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2239 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2240
2241 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2242 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2243 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2244
2245 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2246 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2247 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2248
2249 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
2250 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
2251
2252 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2253 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2254 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2255 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2256
2257 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
2258 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
2259
2260 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
2261 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
2262
2263 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
2264 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
2265 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2266
2267 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
2268 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
2269 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2270
2271 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
2272 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
2273
2274 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2275 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2276 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2277 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2278
2279 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
2280 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
2281 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2282
2283 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
2284 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
2285 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2286
2287 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
2288 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
2289
2290 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2291 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2292 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2293 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2294
2295 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
2296 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
2297 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2298
2299 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
2300 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
2301 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2302
2303 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
2304 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
2305
2306 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
2307 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
2308 { "Mono ADC MIXL", NULL, "adc mono left filter" },
2309 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2310
2311 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
2312 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
2313 { "Mono ADC MIXR", NULL, "adc mono right filter" },
2314 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2315
2316 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
2317 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
2318
2319 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2320 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
2321 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
2322 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2323 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2324
2325 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2326 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2327 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2328
2329 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2330 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2331
2332 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2333 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2334 { "IF1 ADC3 Mux", "OB45", "OB45" },
2335
2336 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2337 { "IF1 ADC4 Mux", "OB67", "OB67" },
2338 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2339
2340 { "AIF1TX", NULL, "I2S1" },
2341 { "AIF1TX", NULL, "IF1 ADC1 Mux" },
2342 { "AIF1TX", NULL, "IF1 ADC2 Mux" },
2343 { "AIF1TX", NULL, "IF1 ADC3 Mux" },
2344 { "AIF1TX", NULL, "IF1 ADC4 Mux" },
2345
2346 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2347 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2348 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2349
2350 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2351 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2352
2353 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2354 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2355 { "IF2 ADC3 Mux", "OB45", "OB45" },
2356
2357 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2358 { "IF2 ADC4 Mux", "OB67", "OB67" },
2359 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2360
2361 { "AIF2TX", NULL, "I2S2" },
2362 { "AIF2TX", NULL, "IF2 ADC1 Mux" },
2363 { "AIF2TX", NULL, "IF2 ADC2 Mux" },
2364 { "AIF2TX", NULL, "IF2 ADC3 Mux" },
2365 { "AIF2TX", NULL, "IF2 ADC4 Mux" },
2366
2367 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2368 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2369 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2370 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2371 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
2372 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
2373 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
2374 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
2375
2376 { "AIF3TX", NULL, "I2S3" },
2377 { "AIF3TX", NULL, "IF3 ADC Mux" },
2378
2379 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2380 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2381 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2382 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2383 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
2384 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
2385 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
2386 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
2387
2388 { "AIF4TX", NULL, "I2S4" },
2389 { "AIF4TX", NULL, "IF4 ADC Mux" },
2390
2391 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2392 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2393 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2394
2395 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2396 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2397
2398 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2399 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2400 { "SLB ADC3 Mux", "OB45", "OB45" },
2401
2402 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2403 { "SLB ADC4 Mux", "OB67", "OB67" },
2404 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2405
2406 { "SLBTX", NULL, "SLB" },
2407 { "SLBTX", NULL, "SLB ADC1 Mux" },
2408 { "SLBTX", NULL, "SLB ADC2 Mux" },
2409 { "SLBTX", NULL, "SLB ADC3 Mux" },
2410 { "SLBTX", NULL, "SLB ADC4 Mux" },
2411
2412 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
2413 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
2414 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
2415 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2416 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
2417
2418 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
2419 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
2420
2421 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
2422 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
2423 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
2424 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2425 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
2426 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
2427
2428 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
2429 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
2430
2431 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
2432 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
2433 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
2434 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2435 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
2436
2437 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
2438 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
2439
2440 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" },
2441 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" },
2442 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
2443 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
2444 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
2445 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2446 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2447 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2448
2449 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" },
2450 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" },
2451 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
2452 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
2453 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
2454 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
2455 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
2456 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
2457
2458 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2459 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2460 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2461 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
2462 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
2463 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
2464
2465 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
2466 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
2467 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
2468 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
2469 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
2470 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
2471 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
2472
2473 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2474 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2475 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2476 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
2477 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
2478 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
2479 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
2480
2481 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2482 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2483 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2484 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
2485 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
2486 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
2487 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
2488
2489 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2490 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2491 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2492 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
2493 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
2494 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
2495 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
2496
2497 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2498 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2499 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2500 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
2501 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
2502 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
2503 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
2504
2505 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2506 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2507 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2508 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
2509 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
2510 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
2511 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
2512
2513 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2514 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2515 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2516 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
2517 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
2518 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
2519 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
2520
2521 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
2522 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
2523 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
2524 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
2525
2526 { "OutBound2", NULL, "OB23 Bypass Mux" },
2527 { "OutBound3", NULL, "OB23 Bypass Mux" },
2528 { "OutBound4", NULL, "OB4 MIX" },
2529 { "OutBound5", NULL, "OB5 MIX" },
2530 { "OutBound6", NULL, "OB6 MIX" },
2531 { "OutBound7", NULL, "OB7 MIX" },
2532
2533 { "OB45", NULL, "OutBound4" },
2534 { "OB45", NULL, "OutBound5" },
2535 { "OB67", NULL, "OutBound6" },
2536 { "OB67", NULL, "OutBound7" },
2537
2538 { "IF1 DAC0", NULL, "AIF1RX" },
2539 { "IF1 DAC1", NULL, "AIF1RX" },
2540 { "IF1 DAC2", NULL, "AIF1RX" },
2541 { "IF1 DAC3", NULL, "AIF1RX" },
2542 { "IF1 DAC4", NULL, "AIF1RX" },
2543 { "IF1 DAC5", NULL, "AIF1RX" },
2544 { "IF1 DAC6", NULL, "AIF1RX" },
2545 { "IF1 DAC7", NULL, "AIF1RX" },
2546 { "IF1 DAC0", NULL, "I2S1" },
2547 { "IF1 DAC1", NULL, "I2S1" },
2548 { "IF1 DAC2", NULL, "I2S1" },
2549 { "IF1 DAC3", NULL, "I2S1" },
2550 { "IF1 DAC4", NULL, "I2S1" },
2551 { "IF1 DAC5", NULL, "I2S1" },
2552 { "IF1 DAC6", NULL, "I2S1" },
2553 { "IF1 DAC7", NULL, "I2S1" },
2554
2555 { "IF1 DAC01", NULL, "IF1 DAC0" },
2556 { "IF1 DAC01", NULL, "IF1 DAC1" },
2557 { "IF1 DAC23", NULL, "IF1 DAC2" },
2558 { "IF1 DAC23", NULL, "IF1 DAC3" },
2559 { "IF1 DAC45", NULL, "IF1 DAC4" },
2560 { "IF1 DAC45", NULL, "IF1 DAC5" },
2561 { "IF1 DAC67", NULL, "IF1 DAC6" },
2562 { "IF1 DAC67", NULL, "IF1 DAC7" },
2563
2564 { "IF2 DAC0", NULL, "AIF2RX" },
2565 { "IF2 DAC1", NULL, "AIF2RX" },
2566 { "IF2 DAC2", NULL, "AIF2RX" },
2567 { "IF2 DAC3", NULL, "AIF2RX" },
2568 { "IF2 DAC4", NULL, "AIF2RX" },
2569 { "IF2 DAC5", NULL, "AIF2RX" },
2570 { "IF2 DAC6", NULL, "AIF2RX" },
2571 { "IF2 DAC7", NULL, "AIF2RX" },
2572 { "IF2 DAC0", NULL, "I2S2" },
2573 { "IF2 DAC1", NULL, "I2S2" },
2574 { "IF2 DAC2", NULL, "I2S2" },
2575 { "IF2 DAC3", NULL, "I2S2" },
2576 { "IF2 DAC4", NULL, "I2S2" },
2577 { "IF2 DAC5", NULL, "I2S2" },
2578 { "IF2 DAC6", NULL, "I2S2" },
2579 { "IF2 DAC7", NULL, "I2S2" },
2580
2581 { "IF2 DAC01", NULL, "IF2 DAC0" },
2582 { "IF2 DAC01", NULL, "IF2 DAC1" },
2583 { "IF2 DAC23", NULL, "IF2 DAC2" },
2584 { "IF2 DAC23", NULL, "IF2 DAC3" },
2585 { "IF2 DAC45", NULL, "IF2 DAC4" },
2586 { "IF2 DAC45", NULL, "IF2 DAC5" },
2587 { "IF2 DAC67", NULL, "IF2 DAC6" },
2588 { "IF2 DAC67", NULL, "IF2 DAC7" },
2589
2590 { "IF3 DAC", NULL, "AIF3RX" },
2591 { "IF3 DAC", NULL, "I2S3" },
2592
2593 { "IF4 DAC", NULL, "AIF4RX" },
2594 { "IF4 DAC", NULL, "I2S4" },
2595
2596 { "IF3 DAC L", NULL, "IF3 DAC" },
2597 { "IF3 DAC R", NULL, "IF3 DAC" },
2598
2599 { "IF4 DAC L", NULL, "IF4 DAC" },
2600 { "IF4 DAC R", NULL, "IF4 DAC" },
2601
2602 { "SLB DAC0", NULL, "SLBRX" },
2603 { "SLB DAC1", NULL, "SLBRX" },
2604 { "SLB DAC2", NULL, "SLBRX" },
2605 { "SLB DAC3", NULL, "SLBRX" },
2606 { "SLB DAC4", NULL, "SLBRX" },
2607 { "SLB DAC5", NULL, "SLBRX" },
2608 { "SLB DAC6", NULL, "SLBRX" },
2609 { "SLB DAC7", NULL, "SLBRX" },
2610 { "SLB DAC0", NULL, "SLB" },
2611 { "SLB DAC1", NULL, "SLB" },
2612 { "SLB DAC2", NULL, "SLB" },
2613 { "SLB DAC3", NULL, "SLB" },
2614 { "SLB DAC4", NULL, "SLB" },
2615 { "SLB DAC5", NULL, "SLB" },
2616 { "SLB DAC6", NULL, "SLB" },
2617 { "SLB DAC7", NULL, "SLB" },
2618
2619 { "SLB DAC01", NULL, "SLB DAC0" },
2620 { "SLB DAC01", NULL, "SLB DAC1" },
2621 { "SLB DAC23", NULL, "SLB DAC2" },
2622 { "SLB DAC23", NULL, "SLB DAC3" },
2623 { "SLB DAC45", NULL, "SLB DAC4" },
2624 { "SLB DAC45", NULL, "SLB DAC5" },
2625 { "SLB DAC67", NULL, "SLB DAC6" },
2626 { "SLB DAC67", NULL, "SLB DAC7" },
2627
2628 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2629 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2630 { "ADDA1 Mux", "OB 67", "OB67" },
2631
2632 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
2633 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
2634 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
2635 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
2636 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
2637 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
2638
2639 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
2640 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
2641 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2642 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
2643 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
2644 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2645
2646 { "DAC1 FS", NULL, "DAC1 MIXL" },
2647 { "DAC1 FS", NULL, "DAC1 MIXR" },
2648
2649 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" },
2650 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" },
2651 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
2652 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
2653 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
2654 { "DAC2 L Mux", "OB 2", "OutBound2" },
2655
2656 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" },
2657 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" },
2658 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
2659 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
2660 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
2661 { "DAC2 R Mux", "OB 3", "OutBound3" },
2662 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
2663 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
2664
2665 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" },
2666 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" },
2667 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
2668 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
2669 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
2670 { "DAC3 L Mux", "OB 4", "OutBound4" },
2671
2672 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" },
2673 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" },
2674 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
2675 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
2676 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
2677 { "DAC3 R Mux", "OB 5", "OutBound5" },
2678
2679 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" },
2680 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" },
2681 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
2682 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
2683 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
2684 { "DAC4 L Mux", "OB 6", "OutBound6" },
2685
2686 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" },
2687 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" },
2688 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
2689 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
2690 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
2691 { "DAC4 R Mux", "OB 7", "OutBound7" },
2692
2693 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
2694 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
2695 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
2696 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
2697 { "Sidetone Mux", "ADC1", "ADC 1" },
2698 { "Sidetone Mux", "ADC2", "ADC 2" },
2699
2700 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
2701 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
2702 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
2703 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
2704 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2705 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
2706 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
2707 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
2708 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
2709 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2710
2711 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
2712 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
2713 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
2714 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
2715 { "Mono DAC MIXL", NULL, "dac mono left filter" },
2716 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
2717 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
2718 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
2719 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
2720 { "Mono DAC MIXR", NULL, "dac mono right filter" },
2721
2722 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2723 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
2724 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
2725 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
2726 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2727 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
2728 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
2729 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
2730
2731 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2732 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
2733 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
2734 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
2735 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2736 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
2737 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
2738 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
2739
2740 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
2741 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
2742 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
2743 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
2744 { "DD1 MIX", NULL, "DD1 MIXL" },
2745 { "DD1 MIX", NULL, "DD1 MIXR" },
2746 { "DD2 MIX", NULL, "DD2 MIXL" },
2747 { "DD2 MIX", NULL, "DD2 MIXR" },
2748
2749 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
2750 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
2751 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
2752 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
2753
2754 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2755 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2756 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
2757 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
2758
2759 { "DAC 1", NULL, "DAC12 SRC Mux" },
2760 { "DAC 1", NULL, "PLL1", is_sys_clk_from_pll },
2761 { "DAC 2", NULL, "DAC12 SRC Mux" },
2762 { "DAC 2", NULL, "PLL1", is_sys_clk_from_pll },
2763 { "DAC 3", NULL, "DAC3 SRC Mux" },
2764 { "DAC 3", NULL, "PLL1", is_sys_clk_from_pll },
2765
2766 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
2767 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
2768 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
2769 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
2770 { "PDM1 L Mux", NULL, "PDM1 Power" },
2771 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
2772 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
2773 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
2774 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
2775 { "PDM1 R Mux", NULL, "PDM1 Power" },
2776 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
2777 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
2778 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
2779 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
2780 { "PDM2 L Mux", NULL, "PDM2 Power" },
2781 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
2782 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
2783 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
2784 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
2785 { "PDM2 R Mux", NULL, "PDM2 Power" },
2786
2787 { "LOUT1 amp", NULL, "DAC 1" },
2788 { "LOUT2 amp", NULL, "DAC 2" },
2789 { "LOUT3 amp", NULL, "DAC 3" },
2790
2791 { "LOUT1", NULL, "LOUT1 amp" },
2792 { "LOUT2", NULL, "LOUT2 amp" },
2793 { "LOUT3", NULL, "LOUT3 amp" },
2794
2795 { "PDM1L", NULL, "PDM1 L Mux" },
2796 { "PDM1R", NULL, "PDM1 R Mux" },
2797 { "PDM2L", NULL, "PDM2 L Mux" },
2798 { "PDM2R", NULL, "PDM2 R Mux" },
2799};
2800
2801static int get_clk_info(int sclk, int rate)
2802{
2803 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
2804
2805 if (sclk <= 0 || rate <= 0)
2806 return -EINVAL;
2807
2808 rate = rate << 8;
2809 for (i = 0; i < ARRAY_SIZE(pd); i++)
2810 if (sclk == rate * pd[i])
2811 return i;
2812
2813 return -EINVAL;
2814}
2815
2816static int rt5677_hw_params(struct snd_pcm_substream *substream,
2817 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2818{
2819 struct snd_soc_codec *codec = dai->codec;
2820 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2821 unsigned int val_len = 0, val_clk, mask_clk;
2822 int pre_div, bclk_ms, frame_size;
2823
2824 rt5677->lrck[dai->id] = params_rate(params);
2825 pre_div = get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
2826 if (pre_div < 0) {
2827 dev_err(codec->dev, "Unsupported clock setting\n");
2828 return -EINVAL;
2829 }
2830 frame_size = snd_soc_params_to_frame_size(params);
2831 if (frame_size < 0) {
2832 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2833 return -EINVAL;
2834 }
2835 bclk_ms = frame_size > 32;
2836 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
2837
2838 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2839 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
2840 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2841 bclk_ms, pre_div, dai->id);
2842
2843 switch (params_width(params)) {
2844 case 16:
2845 break;
2846 case 20:
2847 val_len |= RT5677_I2S_DL_20;
2848 break;
2849 case 24:
2850 val_len |= RT5677_I2S_DL_24;
2851 break;
2852 case 8:
2853 val_len |= RT5677_I2S_DL_8;
2854 break;
2855 default:
2856 return -EINVAL;
2857 }
2858
2859 switch (dai->id) {
2860 case RT5677_AIF1:
2861 mask_clk = RT5677_I2S_PD1_MASK;
2862 val_clk = pre_div << RT5677_I2S_PD1_SFT;
2863 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
2864 RT5677_I2S_DL_MASK, val_len);
2865 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2866 mask_clk, val_clk);
2867 break;
2868 case RT5677_AIF2:
2869 mask_clk = RT5677_I2S_PD2_MASK;
2870 val_clk = pre_div << RT5677_I2S_PD2_SFT;
2871 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
2872 RT5677_I2S_DL_MASK, val_len);
2873 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2874 mask_clk, val_clk);
2875 break;
2876 case RT5677_AIF3:
2877 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
2878 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
2879 pre_div << RT5677_I2S_PD3_SFT;
2880 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
2881 RT5677_I2S_DL_MASK, val_len);
2882 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2883 mask_clk, val_clk);
2884 break;
2885 case RT5677_AIF4:
2886 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
2887 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
2888 pre_div << RT5677_I2S_PD4_SFT;
2889 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
2890 RT5677_I2S_DL_MASK, val_len);
2891 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2892 mask_clk, val_clk);
2893 break;
2894 default:
2895 break;
2896 }
2897
2898 return 0;
2899}
2900
2901static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2902{
2903 struct snd_soc_codec *codec = dai->codec;
2904 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2905 unsigned int reg_val = 0;
2906
2907 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2908 case SND_SOC_DAIFMT_CBM_CFM:
2909 rt5677->master[dai->id] = 1;
2910 break;
2911 case SND_SOC_DAIFMT_CBS_CFS:
2912 reg_val |= RT5677_I2S_MS_S;
2913 rt5677->master[dai->id] = 0;
2914 break;
2915 default:
2916 return -EINVAL;
2917 }
2918
2919 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2920 case SND_SOC_DAIFMT_NB_NF:
2921 break;
2922 case SND_SOC_DAIFMT_IB_NF:
2923 reg_val |= RT5677_I2S_BP_INV;
2924 break;
2925 default:
2926 return -EINVAL;
2927 }
2928
2929 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2930 case SND_SOC_DAIFMT_I2S:
2931 break;
2932 case SND_SOC_DAIFMT_LEFT_J:
2933 reg_val |= RT5677_I2S_DF_LEFT;
2934 break;
2935 case SND_SOC_DAIFMT_DSP_A:
2936 reg_val |= RT5677_I2S_DF_PCM_A;
2937 break;
2938 case SND_SOC_DAIFMT_DSP_B:
2939 reg_val |= RT5677_I2S_DF_PCM_B;
2940 break;
2941 default:
2942 return -EINVAL;
2943 }
2944
2945 switch (dai->id) {
2946 case RT5677_AIF1:
2947 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
2948 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2949 RT5677_I2S_DF_MASK, reg_val);
2950 break;
2951 case RT5677_AIF2:
2952 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
2953 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2954 RT5677_I2S_DF_MASK, reg_val);
2955 break;
2956 case RT5677_AIF3:
2957 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
2958 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2959 RT5677_I2S_DF_MASK, reg_val);
2960 break;
2961 case RT5677_AIF4:
2962 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
2963 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2964 RT5677_I2S_DF_MASK, reg_val);
2965 break;
2966 default:
2967 break;
2968 }
2969
2970
2971 return 0;
2972}
2973
2974static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
2975 int clk_id, unsigned int freq, int dir)
2976{
2977 struct snd_soc_codec *codec = dai->codec;
2978 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2979 unsigned int reg_val = 0;
2980
2981 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
2982 return 0;
2983
2984 switch (clk_id) {
2985 case RT5677_SCLK_S_MCLK:
2986 reg_val |= RT5677_SCLK_SRC_MCLK;
2987 break;
2988 case RT5677_SCLK_S_PLL1:
2989 reg_val |= RT5677_SCLK_SRC_PLL1;
2990 break;
2991 case RT5677_SCLK_S_RCCLK:
2992 reg_val |= RT5677_SCLK_SRC_RCCLK;
2993 break;
2994 default:
2995 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2996 return -EINVAL;
2997 }
2998 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
2999 RT5677_SCLK_SRC_MASK, reg_val);
3000 rt5677->sysclk = freq;
3001 rt5677->sysclk_src = clk_id;
3002
3003 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
3004
3005 return 0;
3006}
3007
3008/**
3009 * rt5677_pll_calc - Calcualte PLL M/N/K code.
3010 * @freq_in: external clock provided to codec.
3011 * @freq_out: target clock which codec works on.
3012 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
3013 *
3014 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
3015 *
3016 * Returns 0 for success or negative error code.
3017 */
3018static int rt5677_pll_calc(const unsigned int freq_in,
3019 const unsigned int freq_out, struct rt5677_pll_code *pll_code)
3020{
3021 int max_n = RT5677_PLL_N_MAX, max_m = RT5677_PLL_M_MAX;
3022 int k, red, n_t, pll_out, in_t;
3023 int n = 0, m = 0, m_t = 0;
3024 int out_t, red_t = abs(freq_out - freq_in);
3025 bool m_bp = false, k_bp = false;
3026
3027 if (RT5677_PLL_INP_MAX < freq_in || RT5677_PLL_INP_MIN > freq_in)
3028 return -EINVAL;
3029
3030 k = 100000000 / freq_out - 2;
3031 if (k > RT5677_PLL_K_MAX)
3032 k = RT5677_PLL_K_MAX;
3033 for (n_t = 0; n_t <= max_n; n_t++) {
3034 in_t = freq_in / (k + 2);
3035 pll_out = freq_out / (n_t + 2);
3036 if (in_t < 0)
3037 continue;
3038 if (in_t == pll_out) {
3039 m_bp = true;
3040 n = n_t;
3041 goto code_find;
3042 }
3043 red = abs(in_t - pll_out);
3044 if (red < red_t) {
3045 m_bp = true;
3046 n = n_t;
3047 m = m_t;
3048 if (red == 0)
3049 goto code_find;
3050 red_t = red;
3051 }
3052 for (m_t = 0; m_t <= max_m; m_t++) {
3053 out_t = in_t / (m_t + 2);
3054 red = abs(out_t - pll_out);
3055 if (red < red_t) {
3056 m_bp = false;
3057 n = n_t;
3058 m = m_t;
3059 if (red == 0)
3060 goto code_find;
3061 red_t = red;
3062 }
3063 }
3064 }
3065 pr_debug("Only get approximation about PLL\n");
3066
3067code_find:
3068
3069 pll_code->m_bp = m_bp;
3070 pll_code->k_bp = k_bp;
3071 pll_code->m_code = m;
3072 pll_code->n_code = n;
3073 pll_code->k_code = k;
3074 return 0;
3075}
3076
3077static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
3078 unsigned int freq_in, unsigned int freq_out)
3079{
3080 struct snd_soc_codec *codec = dai->codec;
3081 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3082 struct rt5677_pll_code pll_code;
3083 int ret;
3084
3085 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
3086 freq_out == rt5677->pll_out)
3087 return 0;
3088
3089 if (!freq_in || !freq_out) {
3090 dev_dbg(codec->dev, "PLL disabled\n");
3091
3092 rt5677->pll_in = 0;
3093 rt5677->pll_out = 0;
3094 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3095 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
3096 return 0;
3097 }
3098
3099 switch (source) {
3100 case RT5677_PLL1_S_MCLK:
3101 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3102 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
3103 break;
3104 case RT5677_PLL1_S_BCLK1:
3105 case RT5677_PLL1_S_BCLK2:
3106 case RT5677_PLL1_S_BCLK3:
3107 case RT5677_PLL1_S_BCLK4:
3108 switch (dai->id) {
3109 case RT5677_AIF1:
3110 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3111 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
3112 break;
3113 case RT5677_AIF2:
3114 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3115 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
3116 break;
3117 case RT5677_AIF3:
3118 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3119 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
3120 break;
3121 case RT5677_AIF4:
3122 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3123 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
3124 break;
3125 default:
3126 break;
3127 }
3128 break;
3129 default:
3130 dev_err(codec->dev, "Unknown PLL source %d\n", source);
3131 return -EINVAL;
3132 }
3133
3134 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
3135 if (ret < 0) {
3136 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
3137 return ret;
3138 }
3139
3140 dev_dbg(codec->dev, "m_bypass=%d k_bypass=%d m=%d n=%d k=%d\n",
3141 pll_code.m_bp, pll_code.k_bp,
3142 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code,
3143 (pll_code.k_bp ? 0 : pll_code.k_code));
3144
3145 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
3146 pll_code.n_code << RT5677_PLL_N_SFT |
3147 pll_code.k_bp << RT5677_PLL_K_BP_SFT |
3148 (pll_code.k_bp ? 0 : pll_code.k_code));
3149 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
3150 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
3151 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
3152
3153 rt5677->pll_in = freq_in;
3154 rt5677->pll_out = freq_out;
3155 rt5677->pll_src = source;
3156
3157 return 0;
3158}
3159
3160static int rt5677_set_bias_level(struct snd_soc_codec *codec,
3161 enum snd_soc_bias_level level)
3162{
3163 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3164
3165 switch (level) {
3166 case SND_SOC_BIAS_ON:
3167 break;
3168
3169 case SND_SOC_BIAS_PREPARE:
3170 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
3171 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3172 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
3173 0x0055);
3174 regmap_update_bits(rt5677->regmap,
3175 RT5677_PR_BASE + RT5677_BIAS_CUR4,
3176 0x0f00, 0x0f00);
3177 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3178 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3179 RT5677_PWR_BG | RT5677_PWR_VREF2,
3180 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3181 RT5677_PWR_BG | RT5677_PWR_VREF2);
3182 mdelay(20);
3183 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3184 RT5677_PWR_FV1 | RT5677_PWR_FV2,
3185 RT5677_PWR_FV1 | RT5677_PWR_FV2);
3186 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
3187 RT5677_PWR_CORE, RT5677_PWR_CORE);
3188 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
3189 0x1, 0x1);
3190 }
3191 break;
3192
3193 case SND_SOC_BIAS_STANDBY:
3194 break;
3195
3196 case SND_SOC_BIAS_OFF:
3197 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
3198 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
3199 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
3200 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0000);
3201 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
3202 regmap_update_bits(rt5677->regmap,
3203 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
3204 break;
3205
3206 default:
3207 break;
3208 }
3209 codec->dapm.bias_level = level;
3210
3211 return 0;
3212}
3213
3214static int rt5677_probe(struct snd_soc_codec *codec)
3215{
3216 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3217
3218 rt5677->codec = codec;
3219
3220 rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
3221
3222 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
3223 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
3224
3225 return 0;
3226}
3227
3228static int rt5677_remove(struct snd_soc_codec *codec)
3229{
3230 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3231
3232 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
3233
3234 return 0;
3235}
3236
3237#ifdef CONFIG_PM
3238static int rt5677_suspend(struct snd_soc_codec *codec)
3239{
3240 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3241
3242 regcache_cache_only(rt5677->regmap, true);
3243 regcache_mark_dirty(rt5677->regmap);
3244
3245 return 0;
3246}
3247
3248static int rt5677_resume(struct snd_soc_codec *codec)
3249{
3250 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3251
3252 regcache_cache_only(rt5677->regmap, false);
3253 regcache_sync(rt5677->regmap);
3254
3255 return 0;
3256}
3257#else
3258#define rt5677_suspend NULL
3259#define rt5677_resume NULL
3260#endif
3261
3262#define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3263#define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3264 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3265
3266static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
3267 .hw_params = rt5677_hw_params,
3268 .set_fmt = rt5677_set_dai_fmt,
3269 .set_sysclk = rt5677_set_dai_sysclk,
3270 .set_pll = rt5677_set_dai_pll,
3271};
3272
3273static struct snd_soc_dai_driver rt5677_dai[] = {
3274 {
3275 .name = "rt5677-aif1",
3276 .id = RT5677_AIF1,
3277 .playback = {
3278 .stream_name = "AIF1 Playback",
3279 .channels_min = 1,
3280 .channels_max = 2,
3281 .rates = RT5677_STEREO_RATES,
3282 .formats = RT5677_FORMATS,
3283 },
3284 .capture = {
3285 .stream_name = "AIF1 Capture",
3286 .channels_min = 1,
3287 .channels_max = 2,
3288 .rates = RT5677_STEREO_RATES,
3289 .formats = RT5677_FORMATS,
3290 },
3291 .ops = &rt5677_aif_dai_ops,
3292 },
3293 {
3294 .name = "rt5677-aif2",
3295 .id = RT5677_AIF2,
3296 .playback = {
3297 .stream_name = "AIF2 Playback",
3298 .channels_min = 1,
3299 .channels_max = 2,
3300 .rates = RT5677_STEREO_RATES,
3301 .formats = RT5677_FORMATS,
3302 },
3303 .capture = {
3304 .stream_name = "AIF2 Capture",
3305 .channels_min = 1,
3306 .channels_max = 2,
3307 .rates = RT5677_STEREO_RATES,
3308 .formats = RT5677_FORMATS,
3309 },
3310 .ops = &rt5677_aif_dai_ops,
3311 },
3312 {
3313 .name = "rt5677-aif3",
3314 .id = RT5677_AIF3,
3315 .playback = {
3316 .stream_name = "AIF3 Playback",
3317 .channels_min = 1,
3318 .channels_max = 2,
3319 .rates = RT5677_STEREO_RATES,
3320 .formats = RT5677_FORMATS,
3321 },
3322 .capture = {
3323 .stream_name = "AIF3 Capture",
3324 .channels_min = 1,
3325 .channels_max = 2,
3326 .rates = RT5677_STEREO_RATES,
3327 .formats = RT5677_FORMATS,
3328 },
3329 .ops = &rt5677_aif_dai_ops,
3330 },
3331 {
3332 .name = "rt5677-aif4",
3333 .id = RT5677_AIF4,
3334 .playback = {
3335 .stream_name = "AIF4 Playback",
3336 .channels_min = 1,
3337 .channels_max = 2,
3338 .rates = RT5677_STEREO_RATES,
3339 .formats = RT5677_FORMATS,
3340 },
3341 .capture = {
3342 .stream_name = "AIF4 Capture",
3343 .channels_min = 1,
3344 .channels_max = 2,
3345 .rates = RT5677_STEREO_RATES,
3346 .formats = RT5677_FORMATS,
3347 },
3348 .ops = &rt5677_aif_dai_ops,
3349 },
3350 {
3351 .name = "rt5677-slimbus",
3352 .id = RT5677_AIF5,
3353 .playback = {
3354 .stream_name = "SLIMBus Playback",
3355 .channels_min = 1,
3356 .channels_max = 2,
3357 .rates = RT5677_STEREO_RATES,
3358 .formats = RT5677_FORMATS,
3359 },
3360 .capture = {
3361 .stream_name = "SLIMBus Capture",
3362 .channels_min = 1,
3363 .channels_max = 2,
3364 .rates = RT5677_STEREO_RATES,
3365 .formats = RT5677_FORMATS,
3366 },
3367 .ops = &rt5677_aif_dai_ops,
3368 },
3369};
3370
3371static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
3372 .probe = rt5677_probe,
3373 .remove = rt5677_remove,
3374 .suspend = rt5677_suspend,
3375 .resume = rt5677_resume,
3376 .set_bias_level = rt5677_set_bias_level,
3377 .idle_bias_off = true,
3378 .controls = rt5677_snd_controls,
3379 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
3380 .dapm_widgets = rt5677_dapm_widgets,
3381 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
3382 .dapm_routes = rt5677_dapm_routes,
3383 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
3384};
3385
3386static const struct regmap_config rt5677_regmap = {
3387 .reg_bits = 8,
3388 .val_bits = 16,
3389
3390 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
3391 RT5677_PR_SPACING),
3392
3393 .volatile_reg = rt5677_volatile_register,
3394 .readable_reg = rt5677_readable_register,
3395
3396 .cache_type = REGCACHE_RBTREE,
3397 .reg_defaults = rt5677_reg,
3398 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
3399 .ranges = rt5677_ranges,
3400 .num_ranges = ARRAY_SIZE(rt5677_ranges),
3401};
3402
3403static const struct i2c_device_id rt5677_i2c_id[] = {
3404 { "rt5677", 0 },
3405 { }
3406};
3407MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
3408
3409static int rt5677_i2c_probe(struct i2c_client *i2c,
3410 const struct i2c_device_id *id)
3411{
3412 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
3413 struct rt5677_priv *rt5677;
3414 int ret;
3415 unsigned int val;
3416
3417 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
3418 GFP_KERNEL);
3419 if (rt5677 == NULL)
3420 return -ENOMEM;
3421
3422 i2c_set_clientdata(i2c, rt5677);
3423
3424 if (pdata)
3425 rt5677->pdata = *pdata;
3426
3427 rt5677->regmap = devm_regmap_init_i2c(i2c, &rt5677_regmap);
3428 if (IS_ERR(rt5677->regmap)) {
3429 ret = PTR_ERR(rt5677->regmap);
3430 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3431 ret);
3432 return ret;
3433 }
3434
3435 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
3436 if (val != RT5677_DEVICE_ID) {
3437 dev_err(&i2c->dev,
3438 "Device with ID register %x is not rt5677\n", val);
3439 return -ENODEV;
3440 }
3441
3442 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
3443
3444 ret = regmap_register_patch(rt5677->regmap, init_list,
3445 ARRAY_SIZE(init_list));
3446 if (ret != 0)
3447 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3448
3449 if (rt5677->pdata.in1_diff)
3450 regmap_update_bits(rt5677->regmap, RT5677_IN1,
3451 RT5677_IN_DF1, RT5677_IN_DF1);
3452
3453 if (rt5677->pdata.in2_diff)
3454 regmap_update_bits(rt5677->regmap, RT5677_IN1,
3455 RT5677_IN_DF2, RT5677_IN_DF2);
3456
3457 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
3458 rt5677_dai, ARRAY_SIZE(rt5677_dai));
3459 if (ret < 0)
3460 goto err;
3461
3462 return 0;
3463err:
3464 return ret;
3465}
3466
3467static int rt5677_i2c_remove(struct i2c_client *i2c)
3468{
3469 snd_soc_unregister_codec(&i2c->dev);
3470
3471 return 0;
3472}
3473
3474static struct i2c_driver rt5677_i2c_driver = {
3475 .driver = {
3476 .name = "rt5677",
3477 .owner = THIS_MODULE,
3478 },
3479 .probe = rt5677_i2c_probe,
3480 .remove = rt5677_i2c_remove,
3481 .id_table = rt5677_i2c_id,
3482};
3483
3484static int __init rt5677_modinit(void)
3485{
3486 return i2c_add_driver(&rt5677_i2c_driver);
3487}
3488module_init(rt5677_modinit);
3489
3490static void __exit rt5677_modexit(void)
3491{
3492 i2c_del_driver(&rt5677_i2c_driver);
3493}
3494module_exit(rt5677_modexit);
3495
3496MODULE_DESCRIPTION("ASoC RT5677 driver");
3497MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
3498MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/rt5677.h b/sound/soc/codecs/rt5677.h
new file mode 100644
index 000000000000..af4e9c797408
--- /dev/null
+++ b/sound/soc/codecs/rt5677.h
@@ -0,0 +1,1451 @@
1/*
2 * rt5677.h -- RT5677 ALSA SoC audio driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __RT5677_H__
13#define __RT5677_H__
14
15#include <sound/rt5677.h>
16
17/* Info */
18#define RT5677_RESET 0x00
19#define RT5677_VENDOR_ID 0xfd
20#define RT5677_VENDOR_ID1 0xfe
21#define RT5677_VENDOR_ID2 0xff
22/* I/O - Output */
23#define RT5677_LOUT1 0x01
24/* I/O - Input */
25#define RT5677_IN1 0x03
26#define RT5677_MICBIAS 0x04
27/* I/O - SLIMBus */
28#define RT5677_SLIMBUS_PARAM 0x07
29#define RT5677_SLIMBUS_RX 0x08
30#define RT5677_SLIMBUS_CTRL 0x09
31/* I/O */
32#define RT5677_SIDETONE_CTRL 0x13
33/* I/O - ADC/DAC */
34#define RT5677_ANA_DAC1_2_3_SRC 0x15
35#define RT5677_IF_DSP_DAC3_4_MIXER 0x16
36#define RT5677_DAC4_DIG_VOL 0x17
37#define RT5677_DAC3_DIG_VOL 0x18
38#define RT5677_DAC1_DIG_VOL 0x19
39#define RT5677_DAC2_DIG_VOL 0x1a
40#define RT5677_IF_DSP_DAC2_MIXER 0x1b
41#define RT5677_STO1_ADC_DIG_VOL 0x1c
42#define RT5677_MONO_ADC_DIG_VOL 0x1d
43#define RT5677_STO1_2_ADC_BST 0x1e
44#define RT5677_STO2_ADC_DIG_VOL 0x1f
45/* Mixer - D-D */
46#define RT5677_ADC_BST_CTRL2 0x20
47#define RT5677_STO3_4_ADC_BST 0x21
48#define RT5677_STO3_ADC_DIG_VOL 0x22
49#define RT5677_STO4_ADC_DIG_VOL 0x23
50#define RT5677_STO4_ADC_MIXER 0x24
51#define RT5677_STO3_ADC_MIXER 0x25
52#define RT5677_STO2_ADC_MIXER 0x26
53#define RT5677_STO1_ADC_MIXER 0x27
54#define RT5677_MONO_ADC_MIXER 0x28
55#define RT5677_ADC_IF_DSP_DAC1_MIXER 0x29
56#define RT5677_STO1_DAC_MIXER 0x2a
57#define RT5677_MONO_DAC_MIXER 0x2b
58#define RT5677_DD1_MIXER 0x2c
59#define RT5677_DD2_MIXER 0x2d
60#define RT5677_IF3_DATA 0x2f
61#define RT5677_IF4_DATA 0x30
62/* Mixer - PDM */
63#define RT5677_PDM_OUT_CTRL 0x31
64#define RT5677_PDM_DATA_CTRL1 0x32
65#define RT5677_PDM_DATA_CTRL2 0x33
66#define RT5677_PDM1_DATA_CTRL2 0x34
67#define RT5677_PDM1_DATA_CTRL3 0x35
68#define RT5677_PDM1_DATA_CTRL4 0x36
69#define RT5677_PDM2_DATA_CTRL2 0x37
70#define RT5677_PDM2_DATA_CTRL3 0x38
71#define RT5677_PDM2_DATA_CTRL4 0x39
72/* TDM */
73#define RT5677_TDM1_CTRL1 0x3b
74#define RT5677_TDM1_CTRL2 0x3c
75#define RT5677_TDM1_CTRL3 0x3d
76#define RT5677_TDM1_CTRL4 0x3e
77#define RT5677_TDM1_CTRL5 0x3f
78#define RT5677_TDM2_CTRL1 0x40
79#define RT5677_TDM2_CTRL2 0x41
80#define RT5677_TDM2_CTRL3 0x42
81#define RT5677_TDM2_CTRL4 0x43
82#define RT5677_TDM2_CTRL5 0x44
83/* I2C_MASTER_CTRL */
84#define RT5677_I2C_MASTER_CTRL1 0x47
85#define RT5677_I2C_MASTER_CTRL2 0x48
86#define RT5677_I2C_MASTER_CTRL3 0x49
87#define RT5677_I2C_MASTER_CTRL4 0x4a
88#define RT5677_I2C_MASTER_CTRL5 0x4b
89#define RT5677_I2C_MASTER_CTRL6 0x4c
90#define RT5677_I2C_MASTER_CTRL7 0x4d
91#define RT5677_I2C_MASTER_CTRL8 0x4e
92/* DMIC */
93#define RT5677_DMIC_CTRL1 0x50
94#define RT5677_DMIC_CTRL2 0x51
95/* Haptic Generator */
96#define RT5677_HAP_GENE_CTRL1 0x56
97#define RT5677_HAP_GENE_CTRL2 0x57
98#define RT5677_HAP_GENE_CTRL3 0x58
99#define RT5677_HAP_GENE_CTRL4 0x59
100#define RT5677_HAP_GENE_CTRL5 0x5a
101#define RT5677_HAP_GENE_CTRL6 0x5b
102#define RT5677_HAP_GENE_CTRL7 0x5c
103#define RT5677_HAP_GENE_CTRL8 0x5d
104#define RT5677_HAP_GENE_CTRL9 0x5e
105#define RT5677_HAP_GENE_CTRL10 0x5f
106/* Power */
107#define RT5677_PWR_DIG1 0x61
108#define RT5677_PWR_DIG2 0x62
109#define RT5677_PWR_ANLG1 0x63
110#define RT5677_PWR_ANLG2 0x64
111#define RT5677_PWR_DSP1 0x65
112#define RT5677_PWR_DSP_ST 0x66
113#define RT5677_PWR_DSP2 0x67
114#define RT5677_ADC_DAC_HPF_CTRL1 0x68
115/* Private Register Control */
116#define RT5677_PRIV_INDEX 0x6a
117#define RT5677_PRIV_DATA 0x6c
118/* Format - ADC/DAC */
119#define RT5677_I2S4_SDP 0x6f
120#define RT5677_I2S1_SDP 0x70
121#define RT5677_I2S2_SDP 0x71
122#define RT5677_I2S3_SDP 0x72
123#define RT5677_CLK_TREE_CTRL1 0x73
124#define RT5677_CLK_TREE_CTRL2 0x74
125#define RT5677_CLK_TREE_CTRL3 0x75
126/* Function - Analog */
127#define RT5677_PLL1_CTRL1 0x7a
128#define RT5677_PLL1_CTRL2 0x7b
129#define RT5677_PLL2_CTRL1 0x7c
130#define RT5677_PLL2_CTRL2 0x7d
131#define RT5677_GLB_CLK1 0x80
132#define RT5677_GLB_CLK2 0x81
133#define RT5677_ASRC_1 0x83
134#define RT5677_ASRC_2 0x84
135#define RT5677_ASRC_3 0x85
136#define RT5677_ASRC_4 0x86
137#define RT5677_ASRC_5 0x87
138#define RT5677_ASRC_6 0x88
139#define RT5677_ASRC_7 0x89
140#define RT5677_ASRC_8 0x8a
141#define RT5677_ASRC_9 0x8b
142#define RT5677_ASRC_10 0x8c
143#define RT5677_ASRC_11 0x8d
144#define RT5677_ASRC_12 0x8e
145#define RT5677_ASRC_13 0x8f
146#define RT5677_ASRC_14 0x90
147#define RT5677_ASRC_15 0x91
148#define RT5677_ASRC_16 0x92
149#define RT5677_ASRC_17 0x93
150#define RT5677_ASRC_18 0x94
151#define RT5677_ASRC_19 0x95
152#define RT5677_ASRC_20 0x97
153#define RT5677_ASRC_21 0x98
154#define RT5677_ASRC_22 0x99
155#define RT5677_ASRC_23 0x9a
156#define RT5677_VAD_CTRL1 0x9c
157#define RT5677_VAD_CTRL2 0x9d
158#define RT5677_VAD_CTRL3 0x9e
159#define RT5677_VAD_CTRL4 0x9f
160#define RT5677_VAD_CTRL5 0xa0
161/* Function - Digital */
162#define RT5677_DSP_INB_CTRL1 0xa3
163#define RT5677_DSP_INB_CTRL2 0xa4
164#define RT5677_DSP_IN_OUTB_CTRL 0xa5
165#define RT5677_DSP_OUTB0_1_DIG_VOL 0xa6
166#define RT5677_DSP_OUTB2_3_DIG_VOL 0xa7
167#define RT5677_DSP_OUTB4_5_DIG_VOL 0xa8
168#define RT5677_DSP_OUTB6_7_DIG_VOL 0xa9
169#define RT5677_ADC_EQ_CTRL1 0xae
170#define RT5677_ADC_EQ_CTRL2 0xaf
171#define RT5677_EQ_CTRL1 0xb0
172#define RT5677_EQ_CTRL2 0xb1
173#define RT5677_EQ_CTRL3 0xb2
174#define RT5677_SOFT_VOL_ZERO_CROSS1 0xb3
175#define RT5677_JD_CTRL1 0xb5
176#define RT5677_JD_CTRL2 0xb6
177#define RT5677_JD_CTRL3 0xb8
178#define RT5677_IRQ_CTRL1 0xbd
179#define RT5677_IRQ_CTRL2 0xbe
180#define RT5677_GPIO_ST 0xbf
181#define RT5677_GPIO_CTRL1 0xc0
182#define RT5677_GPIO_CTRL2 0xc1
183#define RT5677_GPIO_CTRL3 0xc2
184#define RT5677_STO1_ADC_HI_FILTER1 0xc5
185#define RT5677_STO1_ADC_HI_FILTER2 0xc6
186#define RT5677_MONO_ADC_HI_FILTER1 0xc7
187#define RT5677_MONO_ADC_HI_FILTER2 0xc8
188#define RT5677_STO2_ADC_HI_FILTER1 0xc9
189#define RT5677_STO2_ADC_HI_FILTER2 0xca
190#define RT5677_STO3_ADC_HI_FILTER1 0xcb
191#define RT5677_STO3_ADC_HI_FILTER2 0xcc
192#define RT5677_STO4_ADC_HI_FILTER1 0xcd
193#define RT5677_STO4_ADC_HI_FILTER2 0xce
194#define RT5677_MB_DRC_CTRL1 0xd0
195#define RT5677_DRC1_CTRL1 0xd2
196#define RT5677_DRC1_CTRL2 0xd3
197#define RT5677_DRC1_CTRL3 0xd4
198#define RT5677_DRC1_CTRL4 0xd5
199#define RT5677_DRC1_CTRL5 0xd6
200#define RT5677_DRC1_CTRL6 0xd7
201#define RT5677_DRC2_CTRL1 0xd8
202#define RT5677_DRC2_CTRL2 0xd9
203#define RT5677_DRC2_CTRL3 0xda
204#define RT5677_DRC2_CTRL4 0xdb
205#define RT5677_DRC2_CTRL5 0xdc
206#define RT5677_DRC2_CTRL6 0xdd
207#define RT5677_DRC1_HL_CTRL1 0xde
208#define RT5677_DRC1_HL_CTRL2 0xdf
209#define RT5677_DRC2_HL_CTRL1 0xe0
210#define RT5677_DRC2_HL_CTRL2 0xe1
211#define RT5677_DSP_INB1_SRC_CTRL1 0xe3
212#define RT5677_DSP_INB1_SRC_CTRL2 0xe4
213#define RT5677_DSP_INB1_SRC_CTRL3 0xe5
214#define RT5677_DSP_INB1_SRC_CTRL4 0xe6
215#define RT5677_DSP_INB2_SRC_CTRL1 0xe7
216#define RT5677_DSP_INB2_SRC_CTRL2 0xe8
217#define RT5677_DSP_INB2_SRC_CTRL3 0xe9
218#define RT5677_DSP_INB2_SRC_CTRL4 0xea
219#define RT5677_DSP_INB3_SRC_CTRL1 0xeb
220#define RT5677_DSP_INB3_SRC_CTRL2 0xec
221#define RT5677_DSP_INB3_SRC_CTRL3 0xed
222#define RT5677_DSP_INB3_SRC_CTRL4 0xee
223#define RT5677_DSP_OUTB1_SRC_CTRL1 0xef
224#define RT5677_DSP_OUTB1_SRC_CTRL2 0xf0
225#define RT5677_DSP_OUTB1_SRC_CTRL3 0xf1
226#define RT5677_DSP_OUTB1_SRC_CTRL4 0xf2
227#define RT5677_DSP_OUTB2_SRC_CTRL1 0xf3
228#define RT5677_DSP_OUTB2_SRC_CTRL2 0xf4
229#define RT5677_DSP_OUTB2_SRC_CTRL3 0xf5
230#define RT5677_DSP_OUTB2_SRC_CTRL4 0xf6
231
232/* Virtual DSP Mixer Control */
233#define RT5677_DSP_OUTB_0123_MIXER_CTRL 0xf7
234#define RT5677_DSP_OUTB_45_MIXER_CTRL 0xf8
235#define RT5677_DSP_OUTB_67_MIXER_CTRL 0xf9
236
237/* General Control */
238#define RT5677_DIG_MISC 0xfa
239#define RT5677_GEN_CTRL1 0xfb
240#define RT5677_GEN_CTRL2 0xfc
241
242/* DSP Mode I2C Control*/
243#define RT5677_DSP_I2C_OP_CODE 0x00
244#define RT5677_DSP_I2C_ADDR_LSB 0x01
245#define RT5677_DSP_I2C_ADDR_MSB 0x02
246#define RT5677_DSP_I2C_DATA_LSB 0x03
247#define RT5677_DSP_I2C_DATA_MSB 0x04
248
249/* Index of Codec Private Register definition */
250#define RT5677_PR_DRC1_CTRL_1 0x01
251#define RT5677_PR_DRC1_CTRL_2 0x02
252#define RT5677_PR_DRC1_CTRL_3 0x03
253#define RT5677_PR_DRC1_CTRL_4 0x04
254#define RT5677_PR_DRC1_CTRL_5 0x05
255#define RT5677_PR_DRC1_CTRL_6 0x06
256#define RT5677_PR_DRC1_CTRL_7 0x07
257#define RT5677_PR_DRC2_CTRL_1 0x08
258#define RT5677_PR_DRC2_CTRL_2 0x09
259#define RT5677_PR_DRC2_CTRL_3 0x0a
260#define RT5677_PR_DRC2_CTRL_4 0x0b
261#define RT5677_PR_DRC2_CTRL_5 0x0c
262#define RT5677_PR_DRC2_CTRL_6 0x0d
263#define RT5677_PR_DRC2_CTRL_7 0x0e
264#define RT5677_BIAS_CUR1 0x10
265#define RT5677_BIAS_CUR2 0x12
266#define RT5677_BIAS_CUR3 0x13
267#define RT5677_BIAS_CUR4 0x14
268#define RT5677_BIAS_CUR5 0x15
269#define RT5677_VREF_LOUT_CTRL 0x17
270#define RT5677_DIG_VOL_CTRL1 0x1a
271#define RT5677_DIG_VOL_CTRL2 0x1b
272#define RT5677_ANA_ADC_GAIN_CTRL 0x1e
273#define RT5677_VAD_SRAM_TEST1 0x20
274#define RT5677_VAD_SRAM_TEST2 0x21
275#define RT5677_VAD_SRAM_TEST3 0x22
276#define RT5677_VAD_SRAM_TEST4 0x23
277#define RT5677_PAD_DRV_CTRL 0x26
278#define RT5677_DIG_IN_PIN_ST_CTRL1 0x29
279#define RT5677_DIG_IN_PIN_ST_CTRL2 0x2a
280#define RT5677_DIG_IN_PIN_ST_CTRL3 0x2b
281#define RT5677_PLL1_INT 0x38
282#define RT5677_PLL2_INT 0x39
283#define RT5677_TEST_CTRL1 0x3a
284#define RT5677_TEST_CTRL2 0x3b
285#define RT5677_TEST_CTRL3 0x3c
286#define RT5677_CHOP_DAC_ADC 0x3d
287#define RT5677_SOFT_DEPOP_DAC_CLK_CTRL 0x3e
288#define RT5677_CROSS_OVER_FILTER1 0x90
289#define RT5677_CROSS_OVER_FILTER2 0x91
290#define RT5677_CROSS_OVER_FILTER3 0x92
291#define RT5677_CROSS_OVER_FILTER4 0x93
292#define RT5677_CROSS_OVER_FILTER5 0x94
293#define RT5677_CROSS_OVER_FILTER6 0x95
294#define RT5677_CROSS_OVER_FILTER7 0x96
295#define RT5677_CROSS_OVER_FILTER8 0x97
296#define RT5677_CROSS_OVER_FILTER9 0x98
297#define RT5677_CROSS_OVER_FILTER10 0x99
298
299/* global definition */
300#define RT5677_L_MUTE (0x1 << 15)
301#define RT5677_L_MUTE_SFT 15
302#define RT5677_VOL_L_MUTE (0x1 << 14)
303#define RT5677_VOL_L_SFT 14
304#define RT5677_R_MUTE (0x1 << 7)
305#define RT5677_R_MUTE_SFT 7
306#define RT5677_VOL_R_MUTE (0x1 << 6)
307#define RT5677_VOL_R_SFT 6
308#define RT5677_L_VOL_MASK (0x3f << 8)
309#define RT5677_L_VOL_SFT 8
310#define RT5677_R_VOL_MASK (0x3f)
311#define RT5677_R_VOL_SFT 0
312
313/* LOUT1 Control (0x01) */
314#define RT5677_LOUT1_L_MUTE (0x1 << 15)
315#define RT5677_LOUT1_L_MUTE_SFT (15)
316#define RT5677_LOUT1_L_DF (0x1 << 14)
317#define RT5677_LOUT1_L_DF_SFT (14)
318#define RT5677_LOUT2_L_MUTE (0x1 << 13)
319#define RT5677_LOUT2_L_MUTE_SFT (13)
320#define RT5677_LOUT2_L_DF (0x1 << 12)
321#define RT5677_LOUT2_L_DF_SFT (12)
322#define RT5677_LOUT3_L_MUTE (0x1 << 11)
323#define RT5677_LOUT3_L_MUTE_SFT (11)
324#define RT5677_LOUT3_L_DF (0x1 << 10)
325#define RT5677_LOUT3_L_DF_SFT (10)
326#define RT5677_LOUT1_ENH_DRV (0x1 << 9)
327#define RT5677_LOUT1_ENH_DRV_SFT (9)
328#define RT5677_LOUT2_ENH_DRV (0x1 << 8)
329#define RT5677_LOUT2_ENH_DRV_SFT (8)
330#define RT5677_LOUT3_ENH_DRV (0x1 << 7)
331#define RT5677_LOUT3_ENH_DRV_SFT (7)
332
333/* IN1 Control (0x03) */
334#define RT5677_BST_MASK1 (0xf << 12)
335#define RT5677_BST_SFT1 12
336#define RT5677_BST_MASK2 (0xf << 8)
337#define RT5677_BST_SFT2 8
338#define RT5677_IN_DF1 (0x1 << 7)
339#define RT5677_IN_DF1_SFT 7
340#define RT5677_IN_DF2 (0x1 << 6)
341#define RT5677_IN_DF2_SFT 6
342
343/* Micbias Control (0x04) */
344#define RT5677_MICBIAS1_OUTVOLT_MASK (0x1 << 15)
345#define RT5677_MICBIAS1_OUTVOLT_SFT (15)
346#define RT5677_MICBIAS1_OUTVOLT_2_7V (0x0 << 15)
347#define RT5677_MICBIAS1_OUTVOLT_2_25V (0x1 << 15)
348#define RT5677_MICBIAS1_CTRL_VDD_MASK (0x1 << 14)
349#define RT5677_MICBIAS1_CTRL_VDD_SFT (14)
350#define RT5677_MICBIAS1_CTRL_VDD_1_8V (0x0 << 14)
351#define RT5677_MICBIAS1_CTRL_VDD_3_3V (0x1 << 14)
352#define RT5677_MICBIAS1_OVCD_MASK (0x1 << 11)
353#define RT5677_MICBIAS1_OVCD_SHIFT (11)
354#define RT5677_MICBIAS1_OVCD_DIS (0x0 << 11)
355#define RT5677_MICBIAS1_OVCD_EN (0x1 << 11)
356#define RT5677_MICBIAS1_OVTH_MASK (0x3 << 9)
357#define RT5677_MICBIAS1_OVTH_SFT 9
358#define RT5677_MICBIAS1_OVTH_640UA (0x0 << 9)
359#define RT5677_MICBIAS1_OVTH_1280UA (0x1 << 9)
360#define RT5677_MICBIAS1_OVTH_1920UA (0x2 << 9)
361
362/* SLIMbus Parameter (0x07) */
363
364/* SLIMbus Rx (0x08) */
365#define RT5677_SLB_ADC4_MASK (0x3 << 6)
366#define RT5677_SLB_ADC4_SFT 6
367#define RT5677_SLB_ADC3_MASK (0x3 << 4)
368#define RT5677_SLB_ADC3_SFT 4
369#define RT5677_SLB_ADC2_MASK (0x3 << 2)
370#define RT5677_SLB_ADC2_SFT 2
371#define RT5677_SLB_ADC1_MASK (0x3 << 0)
372#define RT5677_SLB_ADC1_SFT 0
373
374/* SLIMBus control (0x09) */
375
376/* Sidetone Control (0x13) */
377#define RT5677_ST_HPF_SEL_MASK (0x7 << 13)
378#define RT5677_ST_HPF_SEL_SFT 13
379#define RT5677_ST_HPF_PATH (0x1 << 12)
380#define RT5677_ST_HPF_PATH_SFT 12
381#define RT5677_ST_SEL_MASK (0x7 << 9)
382#define RT5677_ST_SEL_SFT 9
383#define RT5677_ST_EN (0x1 << 6)
384#define RT5677_ST_EN_SFT 6
385
386/* Analog DAC1/2/3 Source Control (0x15) */
387#define RT5677_ANA_DAC3_SRC_SEL_MASK (0x3 << 4)
388#define RT5677_ANA_DAC3_SRC_SEL_SFT 4
389#define RT5677_ANA_DAC1_2_SRC_SEL_MASK (0x3 << 0)
390#define RT5677_ANA_DAC1_2_SRC_SEL_SFT 0
391
392/* IF/DSP to DAC3/4 Mixer Control (0x16) */
393#define RT5677_M_DAC4_L_VOL (0x1 << 15)
394#define RT5677_M_DAC4_L_VOL_SFT 15
395#define RT5677_SEL_DAC4_L_SRC_MASK (0x7 << 12)
396#define RT5677_SEL_DAC4_L_SRC_SFT 12
397#define RT5677_M_DAC4_R_VOL (0x1 << 11)
398#define RT5677_M_DAC4_R_VOL_SFT 11
399#define RT5677_SEL_DAC4_R_SRC_MASK (0x7 << 8)
400#define RT5677_SEL_DAC4_R_SRC_SFT 8
401#define RT5677_M_DAC3_L_VOL (0x1 << 7)
402#define RT5677_M_DAC3_L_VOL_SFT 7
403#define RT5677_SEL_DAC3_L_SRC_MASK (0x7 << 4)
404#define RT5677_SEL_DAC3_L_SRC_SFT 4
405#define RT5677_M_DAC3_R_VOL (0x1 << 3)
406#define RT5677_M_DAC3_R_VOL_SFT 3
407#define RT5677_SEL_DAC3_R_SRC_MASK (0x7 << 0)
408#define RT5677_SEL_DAC3_R_SRC_SFT 0
409
410/* DAC4 Digital Volume (0x17) */
411#define RT5677_DAC4_L_VOL_MASK (0xff << 8)
412#define RT5677_DAC4_L_VOL_SFT 8
413#define RT5677_DAC4_R_VOL_MASK (0xff)
414#define RT5677_DAC4_R_VOL_SFT 0
415
416/* DAC3 Digital Volume (0x18) */
417#define RT5677_DAC3_L_VOL_MASK (0xff << 8)
418#define RT5677_DAC3_L_VOL_SFT 8
419#define RT5677_DAC3_R_VOL_MASK (0xff)
420#define RT5677_DAC3_R_VOL_SFT 0
421
422/* DAC3 Digital Volume (0x19) */
423#define RT5677_DAC1_L_VOL_MASK (0xff << 8)
424#define RT5677_DAC1_L_VOL_SFT 8
425#define RT5677_DAC1_R_VOL_MASK (0xff)
426#define RT5677_DAC1_R_VOL_SFT 0
427
428/* DAC2 Digital Volume (0x1a) */
429#define RT5677_DAC2_L_VOL_MASK (0xff << 8)
430#define RT5677_DAC2_L_VOL_SFT 8
431#define RT5677_DAC2_R_VOL_MASK (0xff)
432#define RT5677_DAC2_R_VOL_SFT 0
433
434/* IF/DSP to DAC2 Mixer Control (0x1b) */
435#define RT5677_M_DAC2_L_VOL (0x1 << 7)
436#define RT5677_M_DAC2_L_VOL_SFT 7
437#define RT5677_SEL_DAC2_L_SRC_MASK (0x7 << 4)
438#define RT5677_SEL_DAC2_L_SRC_SFT 4
439#define RT5677_M_DAC2_R_VOL (0x1 << 3)
440#define RT5677_M_DAC2_R_VOL_SFT 3
441#define RT5677_SEL_DAC2_R_SRC_MASK (0x7 << 0)
442#define RT5677_SEL_DAC2_R_SRC_SFT 0
443
444/* Stereo1 ADC Digital Volume Control (0x1c) */
445#define RT5677_STO1_ADC_L_VOL_MASK (0x7f << 8)
446#define RT5677_STO1_ADC_L_VOL_SFT 8
447#define RT5677_STO1_ADC_R_VOL_MASK (0x7f)
448#define RT5677_STO1_ADC_R_VOL_SFT 0
449
450/* Mono ADC Digital Volume Control (0x1d) */
451#define RT5677_MONO_ADC_L_VOL_MASK (0x7f << 8)
452#define RT5677_MONO_ADC_L_VOL_SFT 8
453#define RT5677_MONO_ADC_R_VOL_MASK (0x7f)
454#define RT5677_MONO_ADC_R_VOL_SFT 0
455
456/* Stereo 1/2 ADC Boost Gain Control (0x1e) */
457#define RT5677_STO1_ADC_L_BST_MASK (0x3 << 14)
458#define RT5677_STO1_ADC_L_BST_SFT 14
459#define RT5677_STO1_ADC_R_BST_MASK (0x3 << 12)
460#define RT5677_STO1_ADC_R_BST_SFT 12
461#define RT5677_STO1_ADC_COMP_MASK (0x3 << 10)
462#define RT5677_STO1_ADC_COMP_SFT 10
463#define RT5677_STO2_ADC_L_BST_MASK (0x3 << 8)
464#define RT5677_STO2_ADC_L_BST_SFT 8
465#define RT5677_STO2_ADC_R_BST_MASK (0x3 << 6)
466#define RT5677_STO2_ADC_R_BST_SFT 6
467#define RT5677_STO2_ADC_COMP_MASK (0x3 << 4)
468#define RT5677_STO2_ADC_COMP_SFT 4
469
470/* Stereo2 ADC Digital Volume Control (0x1f) */
471#define RT5677_STO2_ADC_L_VOL_MASK (0x7f << 8)
472#define RT5677_STO2_ADC_L_VOL_SFT 8
473#define RT5677_STO2_ADC_R_VOL_MASK (0x7f)
474#define RT5677_STO2_ADC_R_VOL_SFT 0
475
476/* ADC Boost Gain Control 2 (0x20) */
477#define RT5677_MONO_ADC_L_BST_MASK (0x3 << 14)
478#define RT5677_MONO_ADC_L_BST_SFT 14
479#define RT5677_MONO_ADC_R_BST_MASK (0x3 << 12)
480#define RT5677_MONO_ADC_R_BST_SFT 12
481#define RT5677_MONO_ADC_COMP_MASK (0x3 << 10)
482#define RT5677_MONO_ADC_COMP_SFT 10
483
484/* Stereo 3/4 ADC Boost Gain Control (0x21) */
485#define RT5677_STO3_ADC_L_BST_MASK (0x3 << 14)
486#define RT5677_STO3_ADC_L_BST_SFT 14
487#define RT5677_STO3_ADC_R_BST_MASK (0x3 << 12)
488#define RT5677_STO3_ADC_R_BST_SFT 12
489#define RT5677_STO3_ADC_COMP_MASK (0x3 << 10)
490#define RT5677_STO3_ADC_COMP_SFT 10
491#define RT5677_STO4_ADC_L_BST_MASK (0x3 << 8)
492#define RT5677_STO4_ADC_L_BST_SFT 8
493#define RT5677_STO4_ADC_R_BST_MASK (0x3 << 6)
494#define RT5677_STO4_ADC_R_BST_SFT 6
495#define RT5677_STO4_ADC_COMP_MASK (0x3 << 4)
496#define RT5677_STO4_ADC_COMP_SFT 4
497
498/* Stereo3 ADC Digital Volume Control (0x22) */
499#define RT5677_STO3_ADC_L_VOL_MASK (0x7f << 8)
500#define RT5677_STO3_ADC_L_VOL_SFT 8
501#define RT5677_STO3_ADC_R_VOL_MASK (0x7f)
502#define RT5677_STO3_ADC_R_VOL_SFT 0
503
504/* Stereo4 ADC Digital Volume Control (0x23) */
505#define RT5677_STO4_ADC_L_VOL_MASK (0x7f << 8)
506#define RT5677_STO4_ADC_L_VOL_SFT 8
507#define RT5677_STO4_ADC_R_VOL_MASK (0x7f)
508#define RT5677_STO4_ADC_R_VOL_SFT 0
509
510/* Stereo4 ADC Mixer control (0x24) */
511#define RT5677_M_STO4_ADC_L2 (0x1 << 15)
512#define RT5677_M_STO4_ADC_L2_SFT 15
513#define RT5677_M_STO4_ADC_L1 (0x1 << 14)
514#define RT5677_M_STO4_ADC_L1_SFT 14
515#define RT5677_SEL_STO4_ADC1_MASK (0x3 << 12)
516#define RT5677_SEL_STO4_ADC1_SFT 12
517#define RT5677_SEL_STO4_ADC2_MASK (0x3 << 10)
518#define RT5677_SEL_STO4_ADC2_SFT 10
519#define RT5677_SEL_STO4_DMIC_MASK (0x3 << 8)
520#define RT5677_SEL_STO4_DMIC_SFT 8
521#define RT5677_M_STO4_ADC_R1 (0x1 << 7)
522#define RT5677_M_STO4_ADC_R1_SFT 7
523#define RT5677_M_STO4_ADC_R2 (0x1 << 6)
524#define RT5677_M_STO4_ADC_R2_SFT 6
525
526/* Stereo3 ADC Mixer control (0x25) */
527#define RT5677_M_STO3_ADC_L2 (0x1 << 15)
528#define RT5677_M_STO3_ADC_L2_SFT 15
529#define RT5677_M_STO3_ADC_L1 (0x1 << 14)
530#define RT5677_M_STO3_ADC_L1_SFT 14
531#define RT5677_SEL_STO3_ADC1_MASK (0x3 << 12)
532#define RT5677_SEL_STO3_ADC1_SFT 12
533#define RT5677_SEL_STO3_ADC2_MASK (0x3 << 10)
534#define RT5677_SEL_STO3_ADC2_SFT 10
535#define RT5677_SEL_STO3_DMIC_MASK (0x3 << 8)
536#define RT5677_SEL_STO3_DMIC_SFT 8
537#define RT5677_M_STO3_ADC_R1 (0x1 << 7)
538#define RT5677_M_STO3_ADC_R1_SFT 7
539#define RT5677_M_STO3_ADC_R2 (0x1 << 6)
540#define RT5677_M_STO3_ADC_R2_SFT 6
541
542/* Stereo2 ADC Mixer Control (0x26) */
543#define RT5677_M_STO2_ADC_L2 (0x1 << 15)
544#define RT5677_M_STO2_ADC_L2_SFT 15
545#define RT5677_M_STO2_ADC_L1 (0x1 << 14)
546#define RT5677_M_STO2_ADC_L1_SFT 14
547#define RT5677_SEL_STO2_ADC1_MASK (0x3 << 12)
548#define RT5677_SEL_STO2_ADC1_SFT 12
549#define RT5677_SEL_STO2_ADC2_MASK (0x3 << 10)
550#define RT5677_SEL_STO2_ADC2_SFT 10
551#define RT5677_SEL_STO2_DMIC_MASK (0x3 << 8)
552#define RT5677_SEL_STO2_DMIC_SFT 8
553#define RT5677_M_STO2_ADC_R1 (0x1 << 7)
554#define RT5677_M_STO2_ADC_R1_SFT 7
555#define RT5677_M_STO2_ADC_R2 (0x1 << 6)
556#define RT5677_M_STO2_ADC_R2_SFT 6
557#define RT5677_SEL_STO2_LR_MIX_MASK (0x1 << 0)
558#define RT5677_SEL_STO2_LR_MIX_SFT 0
559#define RT5677_SEL_STO2_LR_MIX_L (0x0 << 0)
560#define RT5677_SEL_STO2_LR_MIX_LR (0x1 << 0)
561
562/* Stereo1 ADC Mixer control (0x27) */
563#define RT5677_M_STO1_ADC_L2 (0x1 << 15)
564#define RT5677_M_STO1_ADC_L2_SFT 15
565#define RT5677_M_STO1_ADC_L1 (0x1 << 14)
566#define RT5677_M_STO1_ADC_L1_SFT 14
567#define RT5677_SEL_STO1_ADC1_MASK (0x3 << 12)
568#define RT5677_SEL_STO1_ADC1_SFT 12
569#define RT5677_SEL_STO1_ADC2_MASK (0x3 << 10)
570#define RT5677_SEL_STO1_ADC2_SFT 10
571#define RT5677_SEL_STO1_DMIC_MASK (0x3 << 8)
572#define RT5677_SEL_STO1_DMIC_SFT 8
573#define RT5677_M_STO1_ADC_R1 (0x1 << 7)
574#define RT5677_M_STO1_ADC_R1_SFT 7
575#define RT5677_M_STO1_ADC_R2 (0x1 << 6)
576#define RT5677_M_STO1_ADC_R2_SFT 6
577
578/* Mono ADC Mixer control (0x28) */
579#define RT5677_M_MONO_ADC_L2 (0x1 << 15)
580#define RT5677_M_MONO_ADC_L2_SFT 15
581#define RT5677_M_MONO_ADC_L1 (0x1 << 14)
582#define RT5677_M_MONO_ADC_L1_SFT 14
583#define RT5677_SEL_MONO_ADC_L1_MASK (0x3 << 12)
584#define RT5677_SEL_MONO_ADC_L1_SFT 12
585#define RT5677_SEL_MONO_ADC_L2_MASK (0x3 << 10)
586#define RT5677_SEL_MONO_ADC_L2_SFT 10
587#define RT5677_SEL_MONO_DMIC_L_MASK (0x3 << 8)
588#define RT5677_SEL_MONO_DMIC_L_SFT 8
589#define RT5677_M_MONO_ADC_R1 (0x1 << 7)
590#define RT5677_M_MONO_ADC_R1_SFT 7
591#define RT5677_M_MONO_ADC_R2 (0x1 << 6)
592#define RT5677_M_MONO_ADC_R2_SFT 6
593#define RT5677_SEL_MONO_ADC_R1_MASK (0x3 << 4)
594#define RT5677_SEL_MONO_ADC_R1_SFT 4
595#define RT5677_SEL_MONO_ADC_R2_MASK (0x3 << 2)
596#define RT5677_SEL_MONO_ADC_R2_SFT 2
597#define RT5677_SEL_MONO_DMIC_R_MASK (0x3 << 0)
598#define RT5677_SEL_MONO_DMIC_R_SFT 0
599
600/* ADC/IF/DSP to DAC1 Mixer control (0x29) */
601#define RT5677_M_ADDA_MIXER1_L (0x1 << 15)
602#define RT5677_M_ADDA_MIXER1_L_SFT 15
603#define RT5677_M_DAC1_L (0x1 << 14)
604#define RT5677_M_DAC1_L_SFT 14
605#define RT5677_DAC1_L_SEL_MASK (0x7 << 8)
606#define RT5677_DAC1_L_SEL_SFT 8
607#define RT5677_M_ADDA_MIXER1_R (0x1 << 7)
608#define RT5677_M_ADDA_MIXER1_R_SFT 7
609#define RT5677_M_DAC1_R (0x1 << 6)
610#define RT5677_M_DAC1_R_SFT 6
611#define RT5677_ADDA1_SEL_MASK (0x3 << 0)
612#define RT5677_ADDA1_SEL_SFT 0
613
614/* Stereo1 DAC Mixer L/R Control (0x2a) */
615#define RT5677_M_ST_DAC1_L (0x1 << 15)
616#define RT5677_M_ST_DAC1_L_SFT 15
617#define RT5677_M_DAC1_L_STO_L (0x1 << 13)
618#define RT5677_M_DAC1_L_STO_L_SFT 13
619#define RT5677_DAC1_L_STO_L_VOL_MASK (0x1 << 12)
620#define RT5677_DAC1_L_STO_L_VOL_SFT 12
621#define RT5677_M_DAC2_L_STO_L (0x1 << 11)
622#define RT5677_M_DAC2_L_STO_L_SFT 11
623#define RT5677_DAC2_L_STO_L_VOL_MASK (0x1 << 10)
624#define RT5677_DAC2_L_STO_L_VOL_SFT 10
625#define RT5677_M_DAC1_R_STO_L (0x1 << 9)
626#define RT5677_M_DAC1_R_STO_L_SFT 9
627#define RT5677_DAC1_R_STO_L_VOL_MASK (0x1 << 8)
628#define RT5677_DAC1_R_STO_L_VOL_SFT 8
629#define RT5677_M_ST_DAC1_R (0x1 << 7)
630#define RT5677_M_ST_DAC1_R_SFT 7
631#define RT5677_M_DAC1_R_STO_R (0x1 << 5)
632#define RT5677_M_DAC1_R_STO_R_SFT 5
633#define RT5677_DAC1_R_STO_R_VOL_MASK (0x1 << 4)
634#define RT5677_DAC1_R_STO_R_VOL_SFT 4
635#define RT5677_M_DAC2_R_STO_R (0x1 << 3)
636#define RT5677_M_DAC2_R_STO_R_SFT 3
637#define RT5677_DAC2_R_STO_R_VOL_MASK (0x1 << 2)
638#define RT5677_DAC2_R_STO_R_VOL_SFT 2
639#define RT5677_M_DAC1_L_STO_R (0x1 << 1)
640#define RT5677_M_DAC1_L_STO_R_SFT 1
641#define RT5677_DAC1_L_STO_R_VOL_MASK (0x1 << 0)
642#define RT5677_DAC1_L_STO_R_VOL_SFT 0
643
644/* Mono DAC Mixer L/R Control (0x2b) */
645#define RT5677_M_ST_DAC2_L (0x1 << 15)
646#define RT5677_M_ST_DAC2_L_SFT 15
647#define RT5677_M_DAC2_L_MONO_L (0x1 << 13)
648#define RT5677_M_DAC2_L_MONO_L_SFT 13
649#define RT5677_DAC2_L_MONO_L_VOL_MASK (0x1 << 12)
650#define RT5677_DAC2_L_MONO_L_VOL_SFT 12
651#define RT5677_M_DAC2_R_MONO_L (0x1 << 11)
652#define RT5677_M_DAC2_R_MONO_L_SFT 11
653#define RT5677_DAC2_R_MONO_L_VOL_MASK (0x1 << 10)
654#define RT5677_DAC2_R_MONO_L_VOL_SFT 10
655#define RT5677_M_DAC1_L_MONO_L (0x1 << 9)
656#define RT5677_M_DAC1_L_MONO_L_SFT 9
657#define RT5677_DAC1_L_MONO_L_VOL_MASK (0x1 << 8)
658#define RT5677_DAC1_L_MONO_L_VOL_SFT 8
659#define RT5677_M_ST_DAC2_R (0x1 << 7)
660#define RT5677_M_ST_DAC2_R_SFT 7
661#define RT5677_M_DAC2_R_MONO_R (0x1 << 5)
662#define RT5677_M_DAC2_R_MONO_R_SFT 5
663#define RT5677_DAC2_R_MONO_R_VOL_MASK (0x1 << 4)
664#define RT5677_DAC2_R_MONO_R_VOL_SFT 4
665#define RT5677_M_DAC1_R_MONO_R (0x1 << 3)
666#define RT5677_M_DAC1_R_MONO_R_SFT 3
667#define RT5677_DAC1_R_MONO_R_VOL_MASK (0x1 << 2)
668#define RT5677_DAC1_R_MONO_R_VOL_SFT 2
669#define RT5677_M_DAC2_L_MONO_R (0x1 << 1)
670#define RT5677_M_DAC2_L_MONO_R_SFT 1
671#define RT5677_DAC2_L_MONO_R_VOL_MASK (0x1 << 0)
672#define RT5677_DAC2_L_MONO_R_VOL_SFT 0
673
674/* DD Mixer 1 Control (0x2c) */
675#define RT5677_M_STO_L_DD1_L (0x1 << 15)
676#define RT5677_M_STO_L_DD1_L_SFT 15
677#define RT5677_STO_L_DD1_L_VOL_MASK (0x1 << 14)
678#define RT5677_STO_L_DD1_L_VOL_SFT 14
679#define RT5677_M_MONO_L_DD1_L (0x1 << 13)
680#define RT5677_M_MONO_L_DD1_L_SFT 13
681#define RT5677_MONO_L_DD1_L_VOL_MASK (0x1 << 12)
682#define RT5677_MONO_L_DD1_L_VOL_SFT 12
683#define RT5677_M_DAC3_L_DD1_L (0x1 << 11)
684#define RT5677_M_DAC3_L_DD1_L_SFT 11
685#define RT5677_DAC3_L_DD1_L_VOL_MASK (0x1 << 10)
686#define RT5677_DAC3_L_DD1_L_VOL_SFT 10
687#define RT5677_M_DAC3_R_DD1_L (0x1 << 9)
688#define RT5677_M_DAC3_R_DD1_L_SFT 9
689#define RT5677_DAC3_R_DD1_L_VOL_MASK (0x1 << 8)
690#define RT5677_DAC3_R_DD1_L_VOL_SFT 8
691#define RT5677_M_STO_R_DD1_R (0x1 << 7)
692#define RT5677_M_STO_R_DD1_R_SFT 7
693#define RT5677_STO_R_DD1_R_VOL_MASK (0x1 << 6)
694#define RT5677_STO_R_DD1_R_VOL_SFT 6
695#define RT5677_M_MONO_R_DD1_R (0x1 << 5)
696#define RT5677_M_MONO_R_DD1_R_SFT 5
697#define RT5677_MONO_R_DD1_R_VOL_MASK (0x1 << 4)
698#define RT5677_MONO_R_DD1_R_VOL_SFT 4
699#define RT5677_M_DAC3_R_DD1_R (0x1 << 3)
700#define RT5677_M_DAC3_R_DD1_R_SFT 3
701#define RT5677_DAC3_R_DD1_R_VOL_MASK (0x1 << 2)
702#define RT5677_DAC3_R_DD1_R_VOL_SFT 2
703#define RT5677_M_DAC3_L_DD1_R (0x1 << 1)
704#define RT5677_M_DAC3_L_DD1_R_SFT 1
705#define RT5677_DAC3_L_DD1_R_VOL_MASK (0x1 << 0)
706#define RT5677_DAC3_L_DD1_R_VOL_SFT 0
707
708/* DD Mixer 2 Control (0x2d) */
709#define RT5677_M_STO_L_DD2_L (0x1 << 15)
710#define RT5677_M_STO_L_DD2_L_SFT 15
711#define RT5677_STO_L_DD2_L_VOL_MASK (0x1 << 14)
712#define RT5677_STO_L_DD2_L_VOL_SFT 14
713#define RT5677_M_MONO_L_DD2_L (0x1 << 13)
714#define RT5677_M_MONO_L_DD2_L_SFT 13
715#define RT5677_MONO_L_DD2_L_VOL_MASK (0x1 << 12)
716#define RT5677_MONO_L_DD2_L_VOL_SFT 12
717#define RT5677_M_DAC4_L_DD2_L (0x1 << 11)
718#define RT5677_M_DAC4_L_DD2_L_SFT 11
719#define RT5677_DAC4_L_DD2_L_VOL_MASK (0x1 << 10)
720#define RT5677_DAC4_L_DD2_L_VOL_SFT 10
721#define RT5677_M_DAC4_R_DD2_L (0x1 << 9)
722#define RT5677_M_DAC4_R_DD2_L_SFT 9
723#define RT5677_DAC4_R_DD2_L_VOL_MASK (0x1 << 8)
724#define RT5677_DAC4_R_DD2_L_VOL_SFT 8
725#define RT5677_M_STO_R_DD2_R (0x1 << 7)
726#define RT5677_M_STO_R_DD2_R_SFT 7
727#define RT5677_STO_R_DD2_R_VOL_MASK (0x1 << 6)
728#define RT5677_STO_R_DD2_R_VOL_SFT 6
729#define RT5677_M_MONO_R_DD2_R (0x1 << 5)
730#define RT5677_M_MONO_R_DD2_R_SFT 5
731#define RT5677_MONO_R_DD2_R_VOL_MASK (0x1 << 4)
732#define RT5677_MONO_R_DD2_R_VOL_SFT 4
733#define RT5677_M_DAC4_R_DD2_R (0x1 << 3)
734#define RT5677_M_DAC4_R_DD2_R_SFT 3
735#define RT5677_DAC4_R_DD2_R_VOL_MASK (0x1 << 2)
736#define RT5677_DAC4_R_DD2_R_VOL_SFT 2
737#define RT5677_M_DAC4_L_DD2_R (0x1 << 1)
738#define RT5677_M_DAC4_L_DD2_R_SFT 1
739#define RT5677_DAC4_L_DD2_R_VOL_MASK (0x1 << 0)
740#define RT5677_DAC4_L_DD2_R_VOL_SFT 0
741
742/* IF3 data control (0x2f) */
743#define RT5677_IF3_DAC_SEL_MASK (0x3 << 6)
744#define RT5677_IF3_DAC_SEL_SFT 6
745#define RT5677_IF3_ADC_SEL_MASK (0x3 << 4)
746#define RT5677_IF3_ADC_SEL_SFT 4
747#define RT5677_IF3_ADC_IN_MASK (0xf << 0)
748#define RT5677_IF3_ADC_IN_SFT 0
749
750/* IF4 data control (0x30) */
751#define RT5677_IF4_ADC_IN_MASK (0xf << 4)
752#define RT5677_IF4_ADC_IN_SFT 4
753#define RT5677_IF4_DAC_SEL_MASK (0x3 << 2)
754#define RT5677_IF4_DAC_SEL_SFT 2
755#define RT5677_IF4_ADC_SEL_MASK (0x3 << 0)
756#define RT5677_IF4_ADC_SEL_SFT 0
757
758/* PDM Output Control (0x31) */
759#define RT5677_M_PDM1_L (0x1 << 15)
760#define RT5677_M_PDM1_L_SFT 15
761#define RT5677_SEL_PDM1_L_MASK (0x3 << 12)
762#define RT5677_SEL_PDM1_L_SFT 12
763#define RT5677_M_PDM1_R (0x1 << 11)
764#define RT5677_M_PDM1_R_SFT 11
765#define RT5677_SEL_PDM1_R_MASK (0x3 << 8)
766#define RT5677_SEL_PDM1_R_SFT 8
767#define RT5677_M_PDM2_L (0x1 << 7)
768#define RT5677_M_PDM2_L_SFT 7
769#define RT5677_SEL_PDM2_L_MASK (0x3 << 4)
770#define RT5677_SEL_PDM2_L_SFT 4
771#define RT5677_M_PDM2_R (0x1 << 3)
772#define RT5677_M_PDM2_R_SFT 3
773#define RT5677_SEL_PDM2_R_MASK (0x3 << 0)
774#define RT5677_SEL_PDM2_R_SFT 0
775
776/* PDM I2C / Data Control 1 (0x32) */
777#define RT5677_PDM2_PW_DOWN (0x1 << 7)
778#define RT5677_PDM1_PW_DOWN (0x1 << 6)
779#define RT5677_PDM2_BUSY (0x1 << 5)
780#define RT5677_PDM1_BUSY (0x1 << 4)
781#define RT5677_PDM_PATTERN (0x1 << 3)
782#define RT5677_PDM_GAIN (0x1 << 2)
783#define RT5677_PDM_DIV_MASK (0x3 << 0)
784
785/* PDM I2C / Data Control 2 (0x33) */
786#define RT5677_PDM1_I2C_ID (0xf << 12)
787#define RT5677_PDM1_EXE (0x1 << 11)
788#define RT5677_PDM1_I2C_CMD (0x1 << 10)
789#define RT5677_PDM1_I2C_EXE (0x1 << 9)
790#define RT5677_PDM1_I2C_BUSY (0x1 << 8)
791#define RT5677_PDM2_I2C_ID (0xf << 4)
792#define RT5677_PDM2_EXE (0x1 << 3)
793#define RT5677_PDM2_I2C_CMD (0x1 << 2)
794#define RT5677_PDM2_I2C_EXE (0x1 << 1)
795#define RT5677_PDM2_I2C_BUSY (0x1 << 0)
796
797/* MX3C TDM1 control 1 (0x3c) */
798#define RT5677_IF1_ADC4_MASK (0x3 << 10)
799#define RT5677_IF1_ADC4_SFT 10
800#define RT5677_IF1_ADC3_MASK (0x3 << 8)
801#define RT5677_IF1_ADC3_SFT 8
802#define RT5677_IF1_ADC2_MASK (0x3 << 6)
803#define RT5677_IF1_ADC2_SFT 6
804#define RT5677_IF1_ADC1_MASK (0x3 << 4)
805#define RT5677_IF1_ADC1_SFT 4
806
807/* MX41 TDM2 control 1 (0x41) */
808#define RT5677_IF2_ADC4_MASK (0x3 << 10)
809#define RT5677_IF2_ADC4_SFT 10
810#define RT5677_IF2_ADC3_MASK (0x3 << 8)
811#define RT5677_IF2_ADC3_SFT 8
812#define RT5677_IF2_ADC2_MASK (0x3 << 6)
813#define RT5677_IF2_ADC2_SFT 6
814#define RT5677_IF2_ADC1_MASK (0x3 << 4)
815#define RT5677_IF2_ADC1_SFT 4
816
817/* Digital Microphone Control 1 (0x50) */
818#define RT5677_DMIC_1_EN_MASK (0x1 << 15)
819#define RT5677_DMIC_1_EN_SFT 15
820#define RT5677_DMIC_1_DIS (0x0 << 15)
821#define RT5677_DMIC_1_EN (0x1 << 15)
822#define RT5677_DMIC_2_EN_MASK (0x1 << 14)
823#define RT5677_DMIC_2_EN_SFT 14
824#define RT5677_DMIC_2_DIS (0x0 << 14)
825#define RT5677_DMIC_2_EN (0x1 << 14)
826#define RT5677_DMIC_L_STO1_LH_MASK (0x1 << 13)
827#define RT5677_DMIC_L_STO1_LH_SFT 13
828#define RT5677_DMIC_L_STO1_LH_FALLING (0x0 << 13)
829#define RT5677_DMIC_L_STO1_LH_RISING (0x1 << 13)
830#define RT5677_DMIC_R_STO1_LH_MASK (0x1 << 12)
831#define RT5677_DMIC_R_STO1_LH_SFT 12
832#define RT5677_DMIC_R_STO1_LH_FALLING (0x0 << 12)
833#define RT5677_DMIC_R_STO1_LH_RISING (0x1 << 12)
834#define RT5677_DMIC_L_STO3_LH_MASK (0x1 << 11)
835#define RT5677_DMIC_L_STO3_LH_SFT 11
836#define RT5677_DMIC_L_STO3_LH_FALLING (0x0 << 11)
837#define RT5677_DMIC_L_STO3_LH_RISING (0x1 << 11)
838#define RT5677_DMIC_R_STO3_LH_MASK (0x1 << 10)
839#define RT5677_DMIC_R_STO3_LH_SFT 10
840#define RT5677_DMIC_R_STO3_LH_FALLING (0x0 << 10)
841#define RT5677_DMIC_R_STO3_LH_RISING (0x1 << 10)
842#define RT5677_DMIC_L_STO2_LH_MASK (0x1 << 9)
843#define RT5677_DMIC_L_STO2_LH_SFT 9
844#define RT5677_DMIC_L_STO2_LH_FALLING (0x0 << 9)
845#define RT5677_DMIC_L_STO2_LH_RISING (0x1 << 9)
846#define RT5677_DMIC_R_STO2_LH_MASK (0x1 << 8)
847#define RT5677_DMIC_R_STO2_LH_SFT 8
848#define RT5677_DMIC_R_STO2_LH_FALLING (0x0 << 8)
849#define RT5677_DMIC_R_STO2_LH_RISING (0x1 << 8)
850#define RT5677_DMIC_CLK_MASK (0x7 << 5)
851#define RT5677_DMIC_CLK_SFT 5
852#define RT5677_DMIC_3_EN_MASK (0x1 << 4)
853#define RT5677_DMIC_3_EN_SFT 4
854#define RT5677_DMIC_3_DIS (0x0 << 4)
855#define RT5677_DMIC_3_EN (0x1 << 4)
856#define RT5677_DMIC_R_MONO_LH_MASK (0x1 << 2)
857#define RT5677_DMIC_R_MONO_LH_SFT 2
858#define RT5677_DMIC_R_MONO_LH_FALLING (0x0 << 2)
859#define RT5677_DMIC_R_MONO_LH_RISING (0x1 << 2)
860#define RT5677_DMIC_L_STO4_LH_MASK (0x1 << 1)
861#define RT5677_DMIC_L_STO4_LH_SFT 1
862#define RT5677_DMIC_L_STO4_LH_FALLING (0x0 << 1)
863#define RT5677_DMIC_L_STO4_LH_RISING (0x1 << 1)
864#define RT5677_DMIC_R_STO4_LH_MASK (0x1 << 0)
865#define RT5677_DMIC_R_STO4_LH_SFT 0
866#define RT5677_DMIC_R_STO4_LH_FALLING (0x0 << 0)
867#define RT5677_DMIC_R_STO4_LH_RISING (0x1 << 0)
868
869/* Digital Microphone Control 2 (0x51) */
870#define RT5677_DMIC_4_EN_MASK (0x1 << 15)
871#define RT5677_DMIC_4_EN_SFT 15
872#define RT5677_DMIC_4_DIS (0x0 << 15)
873#define RT5677_DMIC_4_EN (0x1 << 15)
874#define RT5677_DMIC_4L_LH_MASK (0x1 << 7)
875#define RT5677_DMIC_4L_LH_SFT 7
876#define RT5677_DMIC_4L_LH_FALLING (0x0 << 7)
877#define RT5677_DMIC_4L_LH_RISING (0x1 << 7)
878#define RT5677_DMIC_4R_LH_MASK (0x1 << 6)
879#define RT5677_DMIC_4R_LH_SFT 6
880#define RT5677_DMIC_4R_LH_FALLING (0x0 << 6)
881#define RT5677_DMIC_4R_LH_RISING (0x1 << 6)
882#define RT5677_DMIC_3L_LH_MASK (0x1 << 5)
883#define RT5677_DMIC_3L_LH_SFT 5
884#define RT5677_DMIC_3L_LH_FALLING (0x0 << 5)
885#define RT5677_DMIC_3L_LH_RISING (0x1 << 5)
886#define RT5677_DMIC_3R_LH_MASK (0x1 << 4)
887#define RT5677_DMIC_3R_LH_SFT 4
888#define RT5677_DMIC_3R_LH_FALLING (0x0 << 4)
889#define RT5677_DMIC_3R_LH_RISING (0x1 << 4)
890#define RT5677_DMIC_2L_LH_MASK (0x1 << 3)
891#define RT5677_DMIC_2L_LH_SFT 3
892#define RT5677_DMIC_2L_LH_FALLING (0x0 << 3)
893#define RT5677_DMIC_2L_LH_RISING (0x1 << 3)
894#define RT5677_DMIC_2R_LH_MASK (0x1 << 2)
895#define RT5677_DMIC_2R_LH_SFT 2
896#define RT5677_DMIC_2R_LH_FALLING (0x0 << 2)
897#define RT5677_DMIC_2R_LH_RISING (0x1 << 2)
898#define RT5677_DMIC_1L_LH_MASK (0x1 << 1)
899#define RT5677_DMIC_1L_LH_SFT 1
900#define RT5677_DMIC_1L_LH_FALLING (0x0 << 1)
901#define RT5677_DMIC_1L_LH_RISING (0x1 << 1)
902#define RT5677_DMIC_1R_LH_MASK (0x1 << 0)
903#define RT5677_DMIC_1R_LH_SFT 0
904#define RT5677_DMIC_1R_LH_FALLING (0x0 << 0)
905#define RT5677_DMIC_1R_LH_RISING (0x1 << 0)
906
907/* Power Management for Digital 1 (0x61) */
908#define RT5677_PWR_I2S1 (0x1 << 15)
909#define RT5677_PWR_I2S1_BIT 15
910#define RT5677_PWR_I2S2 (0x1 << 14)
911#define RT5677_PWR_I2S2_BIT 14
912#define RT5677_PWR_I2S3 (0x1 << 13)
913#define RT5677_PWR_I2S3_BIT 13
914#define RT5677_PWR_DAC1 (0x1 << 12)
915#define RT5677_PWR_DAC1_BIT 12
916#define RT5677_PWR_DAC2 (0x1 << 11)
917#define RT5677_PWR_DAC2_BIT 11
918#define RT5677_PWR_I2S4 (0x1 << 10)
919#define RT5677_PWR_I2S4_BIT 10
920#define RT5677_PWR_SLB (0x1 << 9)
921#define RT5677_PWR_SLB_BIT 9
922#define RT5677_PWR_DAC3 (0x1 << 7)
923#define RT5677_PWR_DAC3_BIT 7
924#define RT5677_PWR_ADCFED2 (0x1 << 4)
925#define RT5677_PWR_ADCFED2_BIT 4
926#define RT5677_PWR_ADCFED1 (0x1 << 3)
927#define RT5677_PWR_ADCFED1_BIT 3
928#define RT5677_PWR_ADC_L (0x1 << 2)
929#define RT5677_PWR_ADC_L_BIT 2
930#define RT5677_PWR_ADC_R (0x1 << 1)
931#define RT5677_PWR_ADC_R_BIT 1
932#define RT5677_PWR_I2C_MASTER (0x1 << 0)
933#define RT5677_PWR_I2C_MASTER_BIT 0
934
935/* Power Management for Digital 2 (0x62) */
936#define RT5677_PWR_ADC_S1F (0x1 << 15)
937#define RT5677_PWR_ADC_S1F_BIT 15
938#define RT5677_PWR_ADC_MF_L (0x1 << 14)
939#define RT5677_PWR_ADC_MF_L_BIT 14
940#define RT5677_PWR_ADC_MF_R (0x1 << 13)
941#define RT5677_PWR_ADC_MF_R_BIT 13
942#define RT5677_PWR_DAC_S1F (0x1 << 12)
943#define RT5677_PWR_DAC_S1F_BIT 12
944#define RT5677_PWR_DAC_M2F_L (0x1 << 11)
945#define RT5677_PWR_DAC_M2F_L_BIT 11
946#define RT5677_PWR_DAC_M2F_R (0x1 << 10)
947#define RT5677_PWR_DAC_M2F_R_BIT 10
948#define RT5677_PWR_DAC_M3F_L (0x1 << 9)
949#define RT5677_PWR_DAC_M3F_L_BIT 9
950#define RT5677_PWR_DAC_M3F_R (0x1 << 8)
951#define RT5677_PWR_DAC_M3F_R_BIT 8
952#define RT5677_PWR_DAC_M4F_L (0x1 << 7)
953#define RT5677_PWR_DAC_M4F_L_BIT 7
954#define RT5677_PWR_DAC_M4F_R (0x1 << 6)
955#define RT5677_PWR_DAC_M4F_R_BIT 6
956#define RT5677_PWR_ADC_S2F (0x1 << 5)
957#define RT5677_PWR_ADC_S2F_BIT 5
958#define RT5677_PWR_ADC_S3F (0x1 << 4)
959#define RT5677_PWR_ADC_S3F_BIT 4
960#define RT5677_PWR_ADC_S4F (0x1 << 3)
961#define RT5677_PWR_ADC_S4F_BIT 3
962#define RT5677_PWR_PDM1 (0x1 << 2)
963#define RT5677_PWR_PDM1_BIT 2
964#define RT5677_PWR_PDM2 (0x1 << 1)
965#define RT5677_PWR_PDM2_BIT 1
966
967/* Power Management for Analog 1 (0x63) */
968#define RT5677_PWR_VREF1 (0x1 << 15)
969#define RT5677_PWR_VREF1_BIT 15
970#define RT5677_PWR_FV1 (0x1 << 14)
971#define RT5677_PWR_FV1_BIT 14
972#define RT5677_PWR_MB (0x1 << 13)
973#define RT5677_PWR_MB_BIT 13
974#define RT5677_PWR_LO1 (0x1 << 12)
975#define RT5677_PWR_LO1_BIT 12
976#define RT5677_PWR_BG (0x1 << 11)
977#define RT5677_PWR_BG_BIT 11
978#define RT5677_PWR_LO2 (0x1 << 10)
979#define RT5677_PWR_LO2_BIT 10
980#define RT5677_PWR_LO3 (0x1 << 9)
981#define RT5677_PWR_LO3_BIT 9
982#define RT5677_PWR_VREF2 (0x1 << 8)
983#define RT5677_PWR_VREF2_BIT 8
984#define RT5677_PWR_FV2 (0x1 << 7)
985#define RT5677_PWR_FV2_BIT 7
986#define RT5677_LDO2_SEL_MASK (0x7 << 4)
987#define RT5677_LDO2_SEL_SFT 4
988#define RT5677_LDO1_SEL_MASK (0x7 << 0)
989#define RT5677_LDO1_SEL_SFT 0
990
991/* Power Management for Analog 2 (0x64) */
992#define RT5677_PWR_BST1 (0x1 << 15)
993#define RT5677_PWR_BST1_BIT 15
994#define RT5677_PWR_BST2 (0x1 << 14)
995#define RT5677_PWR_BST2_BIT 14
996#define RT5677_PWR_CLK_MB1 (0x1 << 13)
997#define RT5677_PWR_CLK_MB1_BIT 13
998#define RT5677_PWR_SLIM (0x1 << 12)
999#define RT5677_PWR_SLIM_BIT 12
1000#define RT5677_PWR_MB1 (0x1 << 11)
1001#define RT5677_PWR_MB1_BIT 11
1002#define RT5677_PWR_PP_MB1 (0x1 << 10)
1003#define RT5677_PWR_PP_MB1_BIT 10
1004#define RT5677_PWR_PLL1 (0x1 << 9)
1005#define RT5677_PWR_PLL1_BIT 9
1006#define RT5677_PWR_PLL2 (0x1 << 8)
1007#define RT5677_PWR_PLL2_BIT 8
1008#define RT5677_PWR_CORE (0x1 << 7)
1009#define RT5677_PWR_CORE_BIT 7
1010#define RT5677_PWR_CLK_MB (0x1 << 6)
1011#define RT5677_PWR_CLK_MB_BIT 6
1012#define RT5677_PWR_BST1_P (0x1 << 5)
1013#define RT5677_PWR_BST1_P_BIT 5
1014#define RT5677_PWR_BST2_P (0x1 << 4)
1015#define RT5677_PWR_BST2_P_BIT 4
1016#define RT5677_PWR_IPTV (0x1 << 3)
1017#define RT5677_PWR_IPTV_BIT 3
1018#define RT5677_PWR_25M_CLK (0x1 << 1)
1019#define RT5677_PWR_25M_CLK_BIT 1
1020#define RT5677_PWR_LDO1 (0x1 << 0)
1021#define RT5677_PWR_LDO1_BIT 0
1022
1023/* Power Management for DSP (0x65) */
1024#define RT5677_PWR_SR7 (0x1 << 10)
1025#define RT5677_PWR_SR7_BIT 10
1026#define RT5677_PWR_SR6 (0x1 << 9)
1027#define RT5677_PWR_SR6_BIT 9
1028#define RT5677_PWR_SR5 (0x1 << 8)
1029#define RT5677_PWR_SR5_BIT 8
1030#define RT5677_PWR_SR4 (0x1 << 7)
1031#define RT5677_PWR_SR4_BIT 7
1032#define RT5677_PWR_SR3 (0x1 << 6)
1033#define RT5677_PWR_SR3_BIT 6
1034#define RT5677_PWR_SR2 (0x1 << 5)
1035#define RT5677_PWR_SR2_BIT 5
1036#define RT5677_PWR_SR1 (0x1 << 4)
1037#define RT5677_PWR_SR1_BIT 4
1038#define RT5677_PWR_SR0 (0x1 << 3)
1039#define RT5677_PWR_SR0_BIT 3
1040#define RT5677_PWR_MLT (0x1 << 2)
1041#define RT5677_PWR_MLT_BIT 2
1042#define RT5677_PWR_DSP (0x1 << 1)
1043#define RT5677_PWR_DSP_BIT 1
1044#define RT5677_PWR_DSP_CPU (0x1 << 0)
1045#define RT5677_PWR_DSP_CPU_BIT 0
1046
1047/* Power Status for DSP (0x66) */
1048#define RT5677_PWR_SR7_RDY (0x1 << 9)
1049#define RT5677_PWR_SR7_RDY_BIT 9
1050#define RT5677_PWR_SR6_RDY (0x1 << 8)
1051#define RT5677_PWR_SR6_RDY_BIT 8
1052#define RT5677_PWR_SR5_RDY (0x1 << 7)
1053#define RT5677_PWR_SR5_RDY_BIT 7
1054#define RT5677_PWR_SR4_RDY (0x1 << 6)
1055#define RT5677_PWR_SR4_RDY_BIT 6
1056#define RT5677_PWR_SR3_RDY (0x1 << 5)
1057#define RT5677_PWR_SR3_RDY_BIT 5
1058#define RT5677_PWR_SR2_RDY (0x1 << 4)
1059#define RT5677_PWR_SR2_RDY_BIT 4
1060#define RT5677_PWR_SR1_RDY (0x1 << 3)
1061#define RT5677_PWR_SR1_RDY_BIT 3
1062#define RT5677_PWR_SR0_RDY (0x1 << 2)
1063#define RT5677_PWR_SR0_RDY_BIT 2
1064#define RT5677_PWR_MLT_RDY (0x1 << 1)
1065#define RT5677_PWR_MLT_RDY_BIT 1
1066#define RT5677_PWR_DSP_RDY (0x1 << 0)
1067#define RT5677_PWR_DSP_RDY_BIT 0
1068
1069/* Power Management for DSP (0x67) */
1070#define RT5677_PWR_SLIM_ISO (0x1 << 11)
1071#define RT5677_PWR_SLIM_ISO_BIT 11
1072#define RT5677_PWR_CORE_ISO (0x1 << 10)
1073#define RT5677_PWR_CORE_ISO_BIT 10
1074#define RT5677_PWR_DSP_ISO (0x1 << 9)
1075#define RT5677_PWR_DSP_ISO_BIT 9
1076#define RT5677_PWR_SR7_ISO (0x1 << 8)
1077#define RT5677_PWR_SR7_ISO_BIT 8
1078#define RT5677_PWR_SR6_ISO (0x1 << 7)
1079#define RT5677_PWR_SR6_ISO_BIT 7
1080#define RT5677_PWR_SR5_ISO (0x1 << 6)
1081#define RT5677_PWR_SR5_ISO_BIT 6
1082#define RT5677_PWR_SR4_ISO (0x1 << 5)
1083#define RT5677_PWR_SR4_ISO_BIT 5
1084#define RT5677_PWR_SR3_ISO (0x1 << 4)
1085#define RT5677_PWR_SR3_ISO_BIT 4
1086#define RT5677_PWR_SR2_ISO (0x1 << 3)
1087#define RT5677_PWR_SR2_ISO_BIT 3
1088#define RT5677_PWR_SR1_ISO (0x1 << 2)
1089#define RT5677_PWR_SR1_ISO_BIT 2
1090#define RT5677_PWR_SR0_ISO (0x1 << 1)
1091#define RT5677_PWR_SR0_ISO_BIT 1
1092#define RT5677_PWR_MLT_ISO (0x1 << 0)
1093#define RT5677_PWR_MLT_ISO_BIT 0
1094
1095/* I2S1/2/3/4 Audio Serial Data Port Control (0x6f 0x70 0x71 0x72) */
1096#define RT5677_I2S_MS_MASK (0x1 << 15)
1097#define RT5677_I2S_MS_SFT 15
1098#define RT5677_I2S_MS_M (0x0 << 15)
1099#define RT5677_I2S_MS_S (0x1 << 15)
1100#define RT5677_I2S_O_CP_MASK (0x3 << 10)
1101#define RT5677_I2S_O_CP_SFT 10
1102#define RT5677_I2S_O_CP_OFF (0x0 << 10)
1103#define RT5677_I2S_O_CP_U_LAW (0x1 << 10)
1104#define RT5677_I2S_O_CP_A_LAW (0x2 << 10)
1105#define RT5677_I2S_I_CP_MASK (0x3 << 8)
1106#define RT5677_I2S_I_CP_SFT 8
1107#define RT5677_I2S_I_CP_OFF (0x0 << 8)
1108#define RT5677_I2S_I_CP_U_LAW (0x1 << 8)
1109#define RT5677_I2S_I_CP_A_LAW (0x2 << 8)
1110#define RT5677_I2S_BP_MASK (0x1 << 7)
1111#define RT5677_I2S_BP_SFT 7
1112#define RT5677_I2S_BP_NOR (0x0 << 7)
1113#define RT5677_I2S_BP_INV (0x1 << 7)
1114#define RT5677_I2S_DL_MASK (0x3 << 2)
1115#define RT5677_I2S_DL_SFT 2
1116#define RT5677_I2S_DL_16 (0x0 << 2)
1117#define RT5677_I2S_DL_20 (0x1 << 2)
1118#define RT5677_I2S_DL_24 (0x2 << 2)
1119#define RT5677_I2S_DL_8 (0x3 << 2)
1120#define RT5677_I2S_DF_MASK (0x3 << 0)
1121#define RT5677_I2S_DF_SFT 0
1122#define RT5677_I2S_DF_I2S (0x0 << 0)
1123#define RT5677_I2S_DF_LEFT (0x1 << 0)
1124#define RT5677_I2S_DF_PCM_A (0x2 << 0)
1125#define RT5677_I2S_DF_PCM_B (0x3 << 0)
1126
1127/* Clock Tree Control 1 (0x73) */
1128#define RT5677_I2S_PD1_MASK (0x7 << 12)
1129#define RT5677_I2S_PD1_SFT 12
1130#define RT5677_I2S_PD1_1 (0x0 << 12)
1131#define RT5677_I2S_PD1_2 (0x1 << 12)
1132#define RT5677_I2S_PD1_3 (0x2 << 12)
1133#define RT5677_I2S_PD1_4 (0x3 << 12)
1134#define RT5677_I2S_PD1_6 (0x4 << 12)
1135#define RT5677_I2S_PD1_8 (0x5 << 12)
1136#define RT5677_I2S_PD1_12 (0x6 << 12)
1137#define RT5677_I2S_PD1_16 (0x7 << 12)
1138#define RT5677_I2S_BCLK_MS2_MASK (0x1 << 11)
1139#define RT5677_I2S_BCLK_MS2_SFT 11
1140#define RT5677_I2S_BCLK_MS2_32 (0x0 << 11)
1141#define RT5677_I2S_BCLK_MS2_64 (0x1 << 11)
1142#define RT5677_I2S_PD2_MASK (0x7 << 8)
1143#define RT5677_I2S_PD2_SFT 8
1144#define RT5677_I2S_PD2_1 (0x0 << 8)
1145#define RT5677_I2S_PD2_2 (0x1 << 8)
1146#define RT5677_I2S_PD2_3 (0x2 << 8)
1147#define RT5677_I2S_PD2_4 (0x3 << 8)
1148#define RT5677_I2S_PD2_6 (0x4 << 8)
1149#define RT5677_I2S_PD2_8 (0x5 << 8)
1150#define RT5677_I2S_PD2_12 (0x6 << 8)
1151#define RT5677_I2S_PD2_16 (0x7 << 8)
1152#define RT5677_I2S_BCLK_MS3_MASK (0x1 << 7)
1153#define RT5677_I2S_BCLK_MS3_SFT 7
1154#define RT5677_I2S_BCLK_MS3_32 (0x0 << 7)
1155#define RT5677_I2S_BCLK_MS3_64 (0x1 << 7)
1156#define RT5677_I2S_PD3_MASK (0x7 << 4)
1157#define RT5677_I2S_PD3_SFT 4
1158#define RT5677_I2S_PD3_1 (0x0 << 4)
1159#define RT5677_I2S_PD3_2 (0x1 << 4)
1160#define RT5677_I2S_PD3_3 (0x2 << 4)
1161#define RT5677_I2S_PD3_4 (0x3 << 4)
1162#define RT5677_I2S_PD3_6 (0x4 << 4)
1163#define RT5677_I2S_PD3_8 (0x5 << 4)
1164#define RT5677_I2S_PD3_12 (0x6 << 4)
1165#define RT5677_I2S_PD3_16 (0x7 << 4)
1166#define RT5677_I2S_BCLK_MS4_MASK (0x1 << 3)
1167#define RT5677_I2S_BCLK_MS4_SFT 3
1168#define RT5677_I2S_BCLK_MS4_32 (0x0 << 3)
1169#define RT5677_I2S_BCLK_MS4_64 (0x1 << 3)
1170#define RT5677_I2S_PD4_MASK (0x7 << 0)
1171#define RT5677_I2S_PD4_SFT 0
1172#define RT5677_I2S_PD4_1 (0x0 << 0)
1173#define RT5677_I2S_PD4_2 (0x1 << 0)
1174#define RT5677_I2S_PD4_3 (0x2 << 0)
1175#define RT5677_I2S_PD4_4 (0x3 << 0)
1176#define RT5677_I2S_PD4_6 (0x4 << 0)
1177#define RT5677_I2S_PD4_8 (0x5 << 0)
1178#define RT5677_I2S_PD4_12 (0x6 << 0)
1179#define RT5677_I2S_PD4_16 (0x7 << 0)
1180
1181/* Clock Tree Control 2 (0x74) */
1182#define RT5677_I2S_PD5_MASK (0x7 << 12)
1183#define RT5677_I2S_PD5_SFT 12
1184#define RT5677_I2S_PD5_1 (0x0 << 12)
1185#define RT5677_I2S_PD5_2 (0x1 << 12)
1186#define RT5677_I2S_PD5_3 (0x2 << 12)
1187#define RT5677_I2S_PD5_4 (0x3 << 12)
1188#define RT5677_I2S_PD5_6 (0x4 << 12)
1189#define RT5677_I2S_PD5_8 (0x5 << 12)
1190#define RT5677_I2S_PD5_12 (0x6 << 12)
1191#define RT5677_I2S_PD5_16 (0x7 << 12)
1192#define RT5677_I2S_PD6_MASK (0x7 << 8)
1193#define RT5677_I2S_PD6_SFT 8
1194#define RT5677_I2S_PD6_1 (0x0 << 8)
1195#define RT5677_I2S_PD6_2 (0x1 << 8)
1196#define RT5677_I2S_PD6_3 (0x2 << 8)
1197#define RT5677_I2S_PD6_4 (0x3 << 8)
1198#define RT5677_I2S_PD6_6 (0x4 << 8)
1199#define RT5677_I2S_PD6_8 (0x5 << 8)
1200#define RT5677_I2S_PD6_12 (0x6 << 8)
1201#define RT5677_I2S_PD6_16 (0x7 << 8)
1202#define RT5677_I2S_PD7_MASK (0x7 << 4)
1203#define RT5677_I2S_PD7_SFT 4
1204#define RT5677_I2S_PD7_1 (0x0 << 4)
1205#define RT5677_I2S_PD7_2 (0x1 << 4)
1206#define RT5677_I2S_PD7_3 (0x2 << 4)
1207#define RT5677_I2S_PD7_4 (0x3 << 4)
1208#define RT5677_I2S_PD7_6 (0x4 << 4)
1209#define RT5677_I2S_PD7_8 (0x5 << 4)
1210#define RT5677_I2S_PD7_12 (0x6 << 4)
1211#define RT5677_I2S_PD7_16 (0x7 << 4)
1212#define RT5677_I2S_PD8_MASK (0x7 << 0)
1213#define RT5677_I2S_PD8_SFT 0
1214#define RT5677_I2S_PD8_1 (0x0 << 0)
1215#define RT5677_I2S_PD8_2 (0x1 << 0)
1216#define RT5677_I2S_PD8_3 (0x2 << 0)
1217#define RT5677_I2S_PD8_4 (0x3 << 0)
1218#define RT5677_I2S_PD8_6 (0x4 << 0)
1219#define RT5677_I2S_PD8_8 (0x5 << 0)
1220#define RT5677_I2S_PD8_12 (0x6 << 0)
1221#define RT5677_I2S_PD8_16 (0x7 << 0)
1222
1223/* Clock Tree Control 3 (0x75) */
1224#define RT5677_DSP_ASRC_O_MASK (0x3 << 6)
1225#define RT5677_DSP_ASRC_O_SFT 6
1226#define RT5677_DSP_ASRC_O_1_0 (0x0 << 6)
1227#define RT5677_DSP_ASRC_O_1_5 (0x1 << 6)
1228#define RT5677_DSP_ASRC_O_2_0 (0x2 << 6)
1229#define RT5677_DSP_ASRC_O_3_0 (0x3 << 6)
1230#define RT5677_DSP_ASRC_I_MASK (0x3 << 4)
1231#define RT5677_DSP_ASRC_I_SFT 4
1232#define RT5677_DSP_ASRC_I_1_0 (0x0 << 4)
1233#define RT5677_DSP_ASRC_I_1_5 (0x1 << 4)
1234#define RT5677_DSP_ASRC_I_2_0 (0x2 << 4)
1235#define RT5677_DSP_ASRC_I_3_0 (0x3 << 4)
1236#define RT5677_DSP_BUS_PD_MASK (0x7 << 0)
1237#define RT5677_DSP_BUS_PD_SFT 0
1238#define RT5677_DSP_BUS_PD_1 (0x0 << 0)
1239#define RT5677_DSP_BUS_PD_2 (0x1 << 0)
1240#define RT5677_DSP_BUS_PD_3 (0x2 << 0)
1241#define RT5677_DSP_BUS_PD_4 (0x3 << 0)
1242#define RT5677_DSP_BUS_PD_6 (0x4 << 0)
1243#define RT5677_DSP_BUS_PD_8 (0x5 << 0)
1244#define RT5677_DSP_BUS_PD_12 (0x6 << 0)
1245#define RT5677_DSP_BUS_PD_16 (0x7 << 0)
1246
1247#define RT5677_PLL_INP_MAX 40000000
1248#define RT5677_PLL_INP_MIN 2048000
1249/* PLL M/N/K Code Control 1 (0x7a 0x7c) */
1250#define RT5677_PLL_N_MAX 0x1ff
1251#define RT5677_PLL_N_MASK (RT5677_PLL_N_MAX << 7)
1252#define RT5677_PLL_N_SFT 7
1253#define RT5677_PLL_K_BP (0x1 << 5)
1254#define RT5677_PLL_K_BP_SFT 5
1255#define RT5677_PLL_K_MAX 0x1f
1256#define RT5677_PLL_K_MASK (RT5677_PLL_K_MAX)
1257#define RT5677_PLL_K_SFT 0
1258
1259/* PLL M/N/K Code Control 2 (0x7b 0x7d) */
1260#define RT5677_PLL_M_MAX 0xf
1261#define RT5677_PLL_M_MASK (RT5677_PLL_M_MAX << 12)
1262#define RT5677_PLL_M_SFT 12
1263#define RT5677_PLL_M_BP (0x1 << 11)
1264#define RT5677_PLL_M_BP_SFT 11
1265
1266/* Global Clock Control 1 (0x80) */
1267#define RT5677_SCLK_SRC_MASK (0x3 << 14)
1268#define RT5677_SCLK_SRC_SFT 14
1269#define RT5677_SCLK_SRC_MCLK (0x0 << 14)
1270#define RT5677_SCLK_SRC_PLL1 (0x1 << 14)
1271#define RT5677_SCLK_SRC_RCCLK (0x2 << 14) /* 25MHz */
1272#define RT5677_SCLK_SRC_SLIM (0x3 << 14)
1273#define RT5677_PLL1_SRC_MASK (0x7 << 11)
1274#define RT5677_PLL1_SRC_SFT 11
1275#define RT5677_PLL1_SRC_MCLK (0x0 << 11)
1276#define RT5677_PLL1_SRC_BCLK1 (0x1 << 11)
1277#define RT5677_PLL1_SRC_BCLK2 (0x2 << 11)
1278#define RT5677_PLL1_SRC_BCLK3 (0x3 << 11)
1279#define RT5677_PLL1_SRC_BCLK4 (0x4 << 11)
1280#define RT5677_PLL1_SRC_RCCLK (0x5 << 11)
1281#define RT5677_PLL1_SRC_SLIM (0x6 << 11)
1282#define RT5677_MCLK_SRC_MASK (0x1 << 10)
1283#define RT5677_MCLK_SRC_SFT 10
1284#define RT5677_MCLK1_SRC (0x0 << 10)
1285#define RT5677_MCLK2_SRC (0x1 << 10)
1286#define RT5677_PLL1_PD_MASK (0x1 << 8)
1287#define RT5677_PLL1_PD_SFT 8
1288#define RT5677_PLL1_PD_1 (0x0 << 8)
1289#define RT5677_PLL1_PD_2 (0x1 << 8)
1290#define RT5671_DAC_OSR_MASK (0x3 << 6)
1291#define RT5671_DAC_OSR_SFT 6
1292#define RT5671_DAC_OSR_128 (0x0 << 6)
1293#define RT5671_DAC_OSR_64 (0x1 << 6)
1294#define RT5671_DAC_OSR_32 (0x2 << 6)
1295#define RT5671_ADC_OSR_MASK (0x3 << 4)
1296#define RT5671_ADC_OSR_SFT 4
1297#define RT5671_ADC_OSR_128 (0x0 << 4)
1298#define RT5671_ADC_OSR_64 (0x1 << 4)
1299#define RT5671_ADC_OSR_32 (0x2 << 4)
1300
1301/* Global Clock Control 2 (0x81) */
1302#define RT5677_PLL2_PR_SRC_MASK (0x1 << 15)
1303#define RT5677_PLL2_PR_SRC_SFT 15
1304#define RT5677_PLL2_PR_SRC_MCLK1 (0x0 << 15)
1305#define RT5677_PLL2_PR_SRC_MCLK2 (0x1 << 15)
1306#define RT5677_PLL2_SRC_MASK (0x7 << 12)
1307#define RT5677_PLL2_SRC_SFT 12
1308#define RT5677_PLL2_SRC_MCLK (0x0 << 12)
1309#define RT5677_PLL2_SRC_BCLK1 (0x1 << 12)
1310#define RT5677_PLL2_SRC_BCLK2 (0x2 << 12)
1311#define RT5677_PLL2_SRC_BCLK3 (0x3 << 12)
1312#define RT5677_PLL2_SRC_BCLK4 (0x4 << 12)
1313#define RT5677_PLL2_SRC_RCCLK (0x5 << 12)
1314#define RT5677_PLL2_SRC_SLIM (0x6 << 12)
1315#define RT5671_DSP_ASRC_O_SRC (0x3 << 10)
1316#define RT5671_DSP_ASRC_O_SRC_SFT 10
1317#define RT5671_DSP_ASRC_O_MCLK (0x0 << 10)
1318#define RT5671_DSP_ASRC_O_PLL1 (0x1 << 10)
1319#define RT5671_DSP_ASRC_O_SLIM (0x2 << 10)
1320#define RT5671_DSP_ASRC_O_RCCLK (0x3 << 10)
1321#define RT5671_DSP_ASRC_I_SRC (0x3 << 8)
1322#define RT5671_DSP_ASRC_I_SRC_SFT 8
1323#define RT5671_DSP_ASRC_I_MCLK (0x0 << 8)
1324#define RT5671_DSP_ASRC_I_PLL1 (0x1 << 8)
1325#define RT5671_DSP_ASRC_I_SLIM (0x2 << 8)
1326#define RT5671_DSP_ASRC_I_RCCLK (0x3 << 8)
1327#define RT5677_DSP_CLK_SRC_MASK (0x1 << 7)
1328#define RT5677_DSP_CLK_SRC_SFT 7
1329#define RT5677_DSP_CLK_SRC_PLL2 (0x0 << 7)
1330#define RT5677_DSP_CLK_SRC_BYPASS (0x1 << 7)
1331
1332/* VAD Function Control 4 (0x9f) */
1333#define RT5677_VAD_SRC_MASK (0x7 << 8)
1334#define RT5677_VAD_SRC_SFT 8
1335
1336/* DSP InBound Control (0xa3) */
1337#define RT5677_IB01_SRC_MASK (0x7 << 12)
1338#define RT5677_IB01_SRC_SFT 12
1339#define RT5677_IB23_SRC_MASK (0x7 << 8)
1340#define RT5677_IB23_SRC_SFT 8
1341#define RT5677_IB45_SRC_MASK (0x7 << 4)
1342#define RT5677_IB45_SRC_SFT 4
1343#define RT5677_IB6_SRC_MASK (0x7 << 0)
1344#define RT5677_IB6_SRC_SFT 0
1345
1346/* DSP InBound Control (0xa4) */
1347#define RT5677_IB7_SRC_MASK (0x7 << 12)
1348#define RT5677_IB7_SRC_SFT 12
1349#define RT5677_IB8_SRC_MASK (0x7 << 8)
1350#define RT5677_IB8_SRC_SFT 8
1351#define RT5677_IB9_SRC_MASK (0x7 << 4)
1352#define RT5677_IB9_SRC_SFT 4
1353
1354/* DSP In/OutBound Control (0xa5) */
1355#define RT5677_SEL_SRC_OB23 (0x1 << 4)
1356#define RT5677_SEL_SRC_OB23_SFT 4
1357#define RT5677_SEL_SRC_OB01 (0x1 << 3)
1358#define RT5677_SEL_SRC_OB01_SFT 3
1359#define RT5677_SEL_SRC_IB45 (0x1 << 2)
1360#define RT5677_SEL_SRC_IB45_SFT 2
1361#define RT5677_SEL_SRC_IB23 (0x1 << 1)
1362#define RT5677_SEL_SRC_IB23_SFT 1
1363#define RT5677_SEL_SRC_IB01 (0x1 << 0)
1364#define RT5677_SEL_SRC_IB01_SFT 0
1365
1366/* Virtual DSP Mixer Control (0xf7 0xf8 0xf9) */
1367#define RT5677_DSP_IB_01_H (0x1 << 15)
1368#define RT5677_DSP_IB_01_H_SFT 15
1369#define RT5677_DSP_IB_23_H (0x1 << 14)
1370#define RT5677_DSP_IB_23_H_SFT 14
1371#define RT5677_DSP_IB_45_H (0x1 << 13)
1372#define RT5677_DSP_IB_45_H_SFT 13
1373#define RT5677_DSP_IB_6_H (0x1 << 12)
1374#define RT5677_DSP_IB_6_H_SFT 12
1375#define RT5677_DSP_IB_7_H (0x1 << 11)
1376#define RT5677_DSP_IB_7_H_SFT 11
1377#define RT5677_DSP_IB_8_H (0x1 << 10)
1378#define RT5677_DSP_IB_8_H_SFT 10
1379#define RT5677_DSP_IB_9_H (0x1 << 9)
1380#define RT5677_DSP_IB_9_H_SFT 9
1381#define RT5677_DSP_IB_01_L (0x1 << 7)
1382#define RT5677_DSP_IB_01_L_SFT 7
1383#define RT5677_DSP_IB_23_L (0x1 << 6)
1384#define RT5677_DSP_IB_23_L_SFT 6
1385#define RT5677_DSP_IB_45_L (0x1 << 5)
1386#define RT5677_DSP_IB_45_L_SFT 5
1387#define RT5677_DSP_IB_6_L (0x1 << 4)
1388#define RT5677_DSP_IB_6_L_SFT 4
1389#define RT5677_DSP_IB_7_L (0x1 << 3)
1390#define RT5677_DSP_IB_7_L_SFT 3
1391#define RT5677_DSP_IB_8_L (0x1 << 2)
1392#define RT5677_DSP_IB_8_L_SFT 2
1393#define RT5677_DSP_IB_9_L (0x1 << 1)
1394#define RT5677_DSP_IB_9_L_SFT 1
1395
1396/* Debug String Length */
1397#define RT5677_REG_DISP_LEN 23
1398
1399#define RT5677_NO_JACK BIT(0)
1400#define RT5677_HEADSET_DET BIT(1)
1401#define RT5677_HEADPHO_DET BIT(2)
1402
1403/* System Clock Source */
1404enum {
1405 RT5677_SCLK_S_MCLK,
1406 RT5677_SCLK_S_PLL1,
1407 RT5677_SCLK_S_RCCLK,
1408};
1409
1410/* PLL1 Source */
1411enum {
1412 RT5677_PLL1_S_MCLK,
1413 RT5677_PLL1_S_BCLK1,
1414 RT5677_PLL1_S_BCLK2,
1415 RT5677_PLL1_S_BCLK3,
1416 RT5677_PLL1_S_BCLK4,
1417};
1418
1419enum {
1420 RT5677_AIF1,
1421 RT5677_AIF2,
1422 RT5677_AIF3,
1423 RT5677_AIF4,
1424 RT5677_AIF5,
1425 RT5677_AIFS,
1426};
1427
1428struct rt5677_pll_code {
1429 bool m_bp; /* Indicates bypass m code or not. */
1430 bool k_bp; /* Indicates bypass k code or not. */
1431 int m_code;
1432 int n_code;
1433 int k_code;
1434};
1435
1436struct rt5677_priv {
1437 struct snd_soc_codec *codec;
1438 struct rt5677_platform_data pdata;
1439 struct regmap *regmap;
1440
1441 int sysclk;
1442 int sysclk_src;
1443 int lrck[RT5677_AIFS];
1444 int bclk[RT5677_AIFS];
1445 int master[RT5677_AIFS];
1446 int pll_src;
1447 int pll_in;
1448 int pll_out;
1449};
1450
1451#endif /* __RT5677_H__ */
diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
index d3ed1be5a186..3d39f0b5b4a8 100644
--- a/sound/soc/codecs/sgtl5000.c
+++ b/sound/soc/codecs/sgtl5000.c
@@ -36,18 +36,32 @@
36 36
37/* default value of sgtl5000 registers */ 37/* default value of sgtl5000 registers */
38static const struct reg_default sgtl5000_reg_defaults[] = { 38static const struct reg_default sgtl5000_reg_defaults[] = {
39 { SGTL5000_CHIP_DIG_POWER, 0x0000 },
39 { SGTL5000_CHIP_CLK_CTRL, 0x0008 }, 40 { SGTL5000_CHIP_CLK_CTRL, 0x0008 },
40 { SGTL5000_CHIP_I2S_CTRL, 0x0010 }, 41 { SGTL5000_CHIP_I2S_CTRL, 0x0010 },
41 { SGTL5000_CHIP_SSS_CTRL, 0x0010 }, 42 { SGTL5000_CHIP_SSS_CTRL, 0x0010 },
43 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
42 { SGTL5000_CHIP_DAC_VOL, 0x3c3c }, 44 { SGTL5000_CHIP_DAC_VOL, 0x3c3c },
43 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f }, 45 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
46 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 },
44 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 }, 47 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
45 { SGTL5000_CHIP_ANA_CTRL, 0x0111 }, 48 { SGTL5000_CHIP_ANA_CTRL, 0x0111 },
49 { SGTL5000_CHIP_LINREG_CTRL, 0x0000 },
50 { SGTL5000_CHIP_REF_CTRL, 0x0000 },
51 { SGTL5000_CHIP_MIC_CTRL, 0x0000 },
52 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 },
46 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 }, 53 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
47 { SGTL5000_CHIP_ANA_POWER, 0x7060 }, 54 { SGTL5000_CHIP_ANA_POWER, 0x7060 },
48 { SGTL5000_CHIP_PLL_CTRL, 0x5000 }, 55 { SGTL5000_CHIP_PLL_CTRL, 0x5000 },
56 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 },
57 { SGTL5000_CHIP_ANA_STATUS, 0x0000 },
58 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 },
59 { SGTL5000_CHIP_ANA_TEST2, 0x0000 },
60 { SGTL5000_DAP_CTRL, 0x0000 },
61 { SGTL5000_DAP_PEQ, 0x0000 },
49 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 }, 62 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
50 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f }, 63 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
64 { SGTL5000_DAP_AUDIO_EQ, 0x0000 },
51 { SGTL5000_DAP_SURROUND, 0x0040 }, 65 { SGTL5000_DAP_SURROUND, 0x0040 },
52 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f }, 66 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
53 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f }, 67 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
@@ -55,6 +69,7 @@ static const struct reg_default sgtl5000_reg_defaults[] = {
55 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f }, 69 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
56 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f }, 70 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
57 { SGTL5000_DAP_MAIN_CHAN, 0x8000 }, 71 { SGTL5000_DAP_MAIN_CHAN, 0x8000 },
72 { SGTL5000_DAP_MIX_CHAN, 0x0000 },
58 { SGTL5000_DAP_AVC_CTRL, 0x0510 }, 73 { SGTL5000_DAP_AVC_CTRL, 0x0510 },
59 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 }, 74 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
60 { SGTL5000_DAP_AVC_ATTACK, 0x0028 }, 75 { SGTL5000_DAP_AVC_ATTACK, 0x0028 },
@@ -296,7 +311,7 @@ static int dac_info_volsw(struct snd_kcontrol *kcontrol,
296static int dac_get_volsw(struct snd_kcontrol *kcontrol, 311static int dac_get_volsw(struct snd_kcontrol *kcontrol,
297 struct snd_ctl_elem_value *ucontrol) 312 struct snd_ctl_elem_value *ucontrol)
298{ 313{
299 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 314 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
300 int reg; 315 int reg;
301 int l; 316 int l;
302 int r; 317 int r;
@@ -349,7 +364,7 @@ static int dac_get_volsw(struct snd_kcontrol *kcontrol,
349static int dac_put_volsw(struct snd_kcontrol *kcontrol, 364static int dac_put_volsw(struct snd_kcontrol *kcontrol,
350 struct snd_ctl_elem_value *ucontrol) 365 struct snd_ctl_elem_value *ucontrol)
351{ 366{
352 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 367 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
353 int reg; 368 int reg;
354 int l; 369 int l;
355 int r; 370 int r;
@@ -1068,71 +1083,11 @@ static int sgtl5000_suspend(struct snd_soc_codec *codec)
1068 return 0; 1083 return 0;
1069} 1084}
1070 1085
1071/*
1072 * restore all sgtl5000 registers,
1073 * since a big hole between dap and regular registers,
1074 * we will restore them respectively.
1075 */
1076static int sgtl5000_restore_regs(struct snd_soc_codec *codec)
1077{
1078 u16 *cache = codec->reg_cache;
1079 u16 reg;
1080
1081 /* restore regular registers */
1082 for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) {
1083
1084 /* These regs should restore in particular order */
1085 if (reg == SGTL5000_CHIP_ANA_POWER ||
1086 reg == SGTL5000_CHIP_CLK_CTRL ||
1087 reg == SGTL5000_CHIP_LINREG_CTRL ||
1088 reg == SGTL5000_CHIP_LINE_OUT_CTRL ||
1089 reg == SGTL5000_CHIP_REF_CTRL)
1090 continue;
1091
1092 snd_soc_write(codec, reg, cache[reg]);
1093 }
1094
1095 /* restore dap registers */
1096 for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2)
1097 snd_soc_write(codec, reg, cache[reg]);
1098
1099 /*
1100 * restore these regs according to the power setting sequence in
1101 * sgtl5000_set_power_regs() and clock setting sequence in
1102 * sgtl5000_set_clock().
1103 *
1104 * The order of restore is:
1105 * 1. SGTL5000_CHIP_CLK_CTRL MCLK_FREQ bits (1:0) should be restore after
1106 * SGTL5000_CHIP_ANA_POWER PLL bits set
1107 * 2. SGTL5000_CHIP_LINREG_CTRL should be set before
1108 * SGTL5000_CHIP_ANA_POWER LINREG_D restored
1109 * 3. SGTL5000_CHIP_REF_CTRL controls Analog Ground Voltage,
1110 * prefer to resotre it after SGTL5000_CHIP_ANA_POWER restored
1111 */
1112 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
1113 cache[SGTL5000_CHIP_LINREG_CTRL]);
1114
1115 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER,
1116 cache[SGTL5000_CHIP_ANA_POWER]);
1117
1118 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL,
1119 cache[SGTL5000_CHIP_CLK_CTRL]);
1120
1121 snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL,
1122 cache[SGTL5000_CHIP_REF_CTRL]);
1123
1124 snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
1125 cache[SGTL5000_CHIP_LINE_OUT_CTRL]);
1126 return 0;
1127}
1128
1129static int sgtl5000_resume(struct snd_soc_codec *codec) 1086static int sgtl5000_resume(struct snd_soc_codec *codec)
1130{ 1087{
1131 /* Bring the codec back up to standby to enable regulators */ 1088 /* Bring the codec back up to standby to enable regulators */
1132 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1089 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1133 1090
1134 /* Restore registers by cached in memory */
1135 sgtl5000_restore_regs(codec);
1136 return 0; 1091 return 0;
1137} 1092}
1138#else 1093#else
@@ -1322,7 +1277,7 @@ static int sgtl5000_enable_regulators(struct snd_soc_codec *codec)
1322 return ret; 1277 return ret;
1323 } 1278 }
1324 1279
1325 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies), 1280 ret = devm_regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
1326 sgtl5000->supplies); 1281 sgtl5000->supplies);
1327 if (ret) 1282 if (ret)
1328 goto err_ldo_remove; 1283 goto err_ldo_remove;
@@ -1330,16 +1285,13 @@ static int sgtl5000_enable_regulators(struct snd_soc_codec *codec)
1330 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies), 1285 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1331 sgtl5000->supplies); 1286 sgtl5000->supplies);
1332 if (ret) 1287 if (ret)
1333 goto err_regulator_free; 1288 goto err_ldo_remove;
1334 1289
1335 /* wait for all power rails bring up */ 1290 /* wait for all power rails bring up */
1336 udelay(10); 1291 udelay(10);
1337 1292
1338 return 0; 1293 return 0;
1339 1294
1340err_regulator_free:
1341 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1342 sgtl5000->supplies);
1343err_ldo_remove: 1295err_ldo_remove:
1344 if (!external_vddd) 1296 if (!external_vddd)
1345 ldo_regulator_remove(codec); 1297 ldo_regulator_remove(codec);
@@ -1409,8 +1361,6 @@ static int sgtl5000_probe(struct snd_soc_codec *codec)
1409err: 1361err:
1410 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1362 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1411 sgtl5000->supplies); 1363 sgtl5000->supplies);
1412 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1413 sgtl5000->supplies);
1414 ldo_regulator_remove(codec); 1364 ldo_regulator_remove(codec);
1415 1365
1416 return ret; 1366 return ret;
@@ -1424,8 +1374,6 @@ static int sgtl5000_remove(struct snd_soc_codec *codec)
1424 1374
1425 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies), 1375 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1426 sgtl5000->supplies); 1376 sgtl5000->supplies);
1427 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1428 sgtl5000->supplies);
1429 ldo_regulator_remove(codec); 1377 ldo_regulator_remove(codec);
1430 1378
1431 return 0; 1379 return 0;
diff --git a/sound/soc/codecs/si476x.c b/sound/soc/codecs/si476x.c
index 244c097cd905..f26befb0c297 100644
--- a/sound/soc/codecs/si476x.c
+++ b/sound/soc/codecs/si476x.c
@@ -208,13 +208,6 @@ out:
208 return err; 208 return err;
209} 209}
210 210
211static int si476x_codec_probe(struct snd_soc_codec *codec)
212{
213 struct regmap *regmap = dev_get_regmap(codec->dev->parent, NULL);
214
215 return snd_soc_codec_set_cache_io(codec, regmap);
216}
217
218static struct snd_soc_dai_ops si476x_dai_ops = { 211static struct snd_soc_dai_ops si476x_dai_ops = {
219 .hw_params = si476x_codec_hw_params, 212 .hw_params = si476x_codec_hw_params,
220 .set_fmt = si476x_codec_set_dai_fmt, 213 .set_fmt = si476x_codec_set_dai_fmt,
@@ -238,8 +231,13 @@ static struct snd_soc_dai_driver si476x_dai = {
238 .ops = &si476x_dai_ops, 231 .ops = &si476x_dai_ops,
239}; 232};
240 233
234static struct regmap *si476x_get_regmap(struct device *dev)
235{
236 return dev_get_regmap(dev->parent, NULL);
237}
238
241static struct snd_soc_codec_driver soc_codec_dev_si476x = { 239static struct snd_soc_codec_driver soc_codec_dev_si476x = {
242 .probe = si476x_codec_probe, 240 .get_regmap = si476x_get_regmap,
243 .dapm_widgets = si476x_dapm_widgets, 241 .dapm_widgets = si476x_dapm_widgets,
244 .num_dapm_widgets = ARRAY_SIZE(si476x_dapm_widgets), 242 .num_dapm_widgets = ARRAY_SIZE(si476x_dapm_widgets),
245 .dapm_routes = si476x_dapm_routes, 243 .dapm_routes = si476x_dapm_routes,
diff --git a/sound/soc/codecs/sirf-audio-codec.c b/sound/soc/codecs/sirf-audio-codec.c
index 58e7c1f23771..d90cb0fafcb2 100644
--- a/sound/soc/codecs/sirf-audio-codec.c
+++ b/sound/soc/codecs/sirf-audio-codec.c
@@ -109,7 +109,7 @@ static void enable_and_reset_codec(struct regmap *regmap,
109{ 109{
110 regmap_update_bits(regmap, AUDIO_IC_CODEC_CTRL1, 110 regmap_update_bits(regmap, AUDIO_IC_CODEC_CTRL1,
111 codec_enable_bits | codec_reset_bits, 111 codec_enable_bits | codec_reset_bits,
112 codec_enable_bits | ~codec_reset_bits); 112 codec_enable_bits);
113 msleep(20); 113 msleep(20);
114 regmap_update_bits(regmap, AUDIO_IC_CODEC_CTRL1, 114 regmap_update_bits(regmap, AUDIO_IC_CODEC_CTRL1,
115 codec_reset_bits, codec_reset_bits); 115 codec_reset_bits, codec_reset_bits);
@@ -128,8 +128,7 @@ static int atlas6_codec_enable_and_reset_event(struct snd_soc_dapm_widget *w,
128 break; 128 break;
129 case SND_SOC_DAPM_POST_PMD: 129 case SND_SOC_DAPM_POST_PMD:
130 regmap_update_bits(sirf_audio_codec->regmap, 130 regmap_update_bits(sirf_audio_codec->regmap,
131 AUDIO_IC_CODEC_CTRL1, ATLAS6_CODEC_ENABLE_BITS, 131 AUDIO_IC_CODEC_CTRL1, ATLAS6_CODEC_ENABLE_BITS, 0);
132 ~ATLAS6_CODEC_ENABLE_BITS);
133 break; 132 break;
134 default: 133 default:
135 break; 134 break;
@@ -151,8 +150,7 @@ static int prima2_codec_enable_and_reset_event(struct snd_soc_dapm_widget *w,
151 break; 150 break;
152 case SND_SOC_DAPM_POST_PMD: 151 case SND_SOC_DAPM_POST_PMD:
153 regmap_update_bits(sirf_audio_codec->regmap, 152 regmap_update_bits(sirf_audio_codec->regmap,
154 AUDIO_IC_CODEC_CTRL1, PRIMA2_CODEC_ENABLE_BITS, 153 AUDIO_IC_CODEC_CTRL1, PRIMA2_CODEC_ENABLE_BITS, 0);
155 ~PRIMA2_CODEC_ENABLE_BITS);
156 break; 154 break;
157 default: 155 default:
158 break; 156 break;
@@ -279,13 +277,63 @@ static const struct snd_soc_dapm_route sirf_audio_codec_map[] = {
279 {"Mic input mode mux", "Differential", "MICIN1"}, 277 {"Mic input mode mux", "Differential", "MICIN1"},
280}; 278};
281 279
280static void sirf_audio_codec_tx_enable(struct sirf_audio_codec *sirf_audio_codec)
281{
282 regmap_update_bits(sirf_audio_codec->regmap, AUDIO_PORT_IC_TXFIFO_OP,
283 AUDIO_FIFO_RESET, AUDIO_FIFO_RESET);
284 regmap_update_bits(sirf_audio_codec->regmap, AUDIO_PORT_IC_TXFIFO_OP,
285 AUDIO_FIFO_RESET, ~AUDIO_FIFO_RESET);
286 regmap_write(sirf_audio_codec->regmap, AUDIO_PORT_IC_TXFIFO_INT_MSK, 0);
287 regmap_write(sirf_audio_codec->regmap, AUDIO_PORT_IC_TXFIFO_OP, 0);
288 regmap_update_bits(sirf_audio_codec->regmap, AUDIO_PORT_IC_TXFIFO_OP,
289 AUDIO_FIFO_START, AUDIO_FIFO_START);
290 regmap_update_bits(sirf_audio_codec->regmap,
291 AUDIO_PORT_IC_CODEC_TX_CTRL, IC_TX_ENABLE, IC_TX_ENABLE);
292}
293
294static void sirf_audio_codec_tx_disable(struct sirf_audio_codec *sirf_audio_codec)
295{
296 regmap_write(sirf_audio_codec->regmap, AUDIO_PORT_IC_TXFIFO_OP, 0);
297 regmap_update_bits(sirf_audio_codec->regmap,
298 AUDIO_PORT_IC_CODEC_TX_CTRL, IC_TX_ENABLE, ~IC_TX_ENABLE);
299}
300
301static void sirf_audio_codec_rx_enable(struct sirf_audio_codec *sirf_audio_codec,
302 int channels)
303{
304 regmap_update_bits(sirf_audio_codec->regmap, AUDIO_PORT_IC_RXFIFO_OP,
305 AUDIO_FIFO_RESET, AUDIO_FIFO_RESET);
306 regmap_update_bits(sirf_audio_codec->regmap, AUDIO_PORT_IC_RXFIFO_OP,
307 AUDIO_FIFO_RESET, ~AUDIO_FIFO_RESET);
308 regmap_write(sirf_audio_codec->regmap,
309 AUDIO_PORT_IC_RXFIFO_INT_MSK, 0);
310 regmap_write(sirf_audio_codec->regmap, AUDIO_PORT_IC_RXFIFO_OP, 0);
311 regmap_update_bits(sirf_audio_codec->regmap, AUDIO_PORT_IC_RXFIFO_OP,
312 AUDIO_FIFO_START, AUDIO_FIFO_START);
313 if (channels == 1)
314 regmap_update_bits(sirf_audio_codec->regmap,
315 AUDIO_PORT_IC_CODEC_RX_CTRL,
316 IC_RX_ENABLE_MONO, IC_RX_ENABLE_MONO);
317 else
318 regmap_update_bits(sirf_audio_codec->regmap,
319 AUDIO_PORT_IC_CODEC_RX_CTRL,
320 IC_RX_ENABLE_STEREO, IC_RX_ENABLE_STEREO);
321}
322
323static void sirf_audio_codec_rx_disable(struct sirf_audio_codec *sirf_audio_codec)
324{
325 regmap_update_bits(sirf_audio_codec->regmap,
326 AUDIO_PORT_IC_CODEC_RX_CTRL,
327 IC_RX_ENABLE_STEREO, ~IC_RX_ENABLE_STEREO);
328}
329
282static int sirf_audio_codec_trigger(struct snd_pcm_substream *substream, 330static int sirf_audio_codec_trigger(struct snd_pcm_substream *substream,
283 int cmd, 331 int cmd,
284 struct snd_soc_dai *dai) 332 struct snd_soc_dai *dai)
285{ 333{
286 int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
287 struct snd_soc_codec *codec = dai->codec; 334 struct snd_soc_codec *codec = dai->codec;
288 u32 val = 0; 335 struct sirf_audio_codec *sirf_audio_codec = snd_soc_codec_get_drvdata(codec);
336 int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
289 337
290 /* 338 /*
291 * This is a workaround, When stop playback, 339 * This is a workaround, When stop playback,
@@ -295,20 +343,28 @@ static int sirf_audio_codec_trigger(struct snd_pcm_substream *substream,
295 case SNDRV_PCM_TRIGGER_STOP: 343 case SNDRV_PCM_TRIGGER_STOP:
296 case SNDRV_PCM_TRIGGER_SUSPEND: 344 case SNDRV_PCM_TRIGGER_SUSPEND:
297 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 345 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
346 if (playback) {
347 snd_soc_update_bits(codec, AUDIO_IC_CODEC_CTRL0,
348 IC_HSLEN | IC_HSREN, 0);
349 sirf_audio_codec_tx_disable(sirf_audio_codec);
350 } else
351 sirf_audio_codec_rx_disable(sirf_audio_codec);
298 break; 352 break;
299 case SNDRV_PCM_TRIGGER_START: 353 case SNDRV_PCM_TRIGGER_START:
300 case SNDRV_PCM_TRIGGER_RESUME: 354 case SNDRV_PCM_TRIGGER_RESUME:
301 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 355 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
302 if (playback) 356 if (playback) {
303 val = IC_HSLEN | IC_HSREN; 357 sirf_audio_codec_tx_enable(sirf_audio_codec);
358 snd_soc_update_bits(codec, AUDIO_IC_CODEC_CTRL0,
359 IC_HSLEN | IC_HSREN, IC_HSLEN | IC_HSREN);
360 } else
361 sirf_audio_codec_rx_enable(sirf_audio_codec,
362 substream->runtime->channels);
304 break; 363 break;
305 default: 364 default:
306 return -EINVAL; 365 return -EINVAL;
307 } 366 }
308 367
309 if (playback)
310 snd_soc_update_bits(codec, AUDIO_IC_CODEC_CTRL0,
311 IC_HSLEN | IC_HSREN, val);
312 return 0; 368 return 0;
313} 369}
314 370
@@ -392,7 +448,7 @@ static const struct regmap_config sirf_audio_codec_regmap_config = {
392 .reg_bits = 32, 448 .reg_bits = 32,
393 .reg_stride = 4, 449 .reg_stride = 4,
394 .val_bits = 32, 450 .val_bits = 32,
395 .max_register = AUDIO_IC_CODEC_CTRL3, 451 .max_register = AUDIO_PORT_IC_RXFIFO_INT_MSK,
396 .cache_type = REGCACHE_NONE, 452 .cache_type = REGCACHE_NONE,
397}; 453};
398 454
diff --git a/sound/soc/codecs/sirf-audio-codec.h b/sound/soc/codecs/sirf-audio-codec.h
index d4c187b8e54a..ba1adc03839f 100644
--- a/sound/soc/codecs/sirf-audio-codec.h
+++ b/sound/soc/codecs/sirf-audio-codec.h
@@ -72,4 +72,54 @@
72#define IC_RXPGAR 0x7B 72#define IC_RXPGAR 0x7B
73#define IC_RXPGAL 0x7B 73#define IC_RXPGAL 0x7B
74 74
75#define AUDIO_PORT_TX_FIFO_LEVEL_CHECK_MASK 0x3F
76#define AUDIO_PORT_TX_FIFO_SC_OFFSET 0
77#define AUDIO_PORT_TX_FIFO_LC_OFFSET 10
78#define AUDIO_PORT_TX_FIFO_HC_OFFSET 20
79
80#define TX_FIFO_SC(x) (((x) & AUDIO_PORT_TX_FIFO_LEVEL_CHECK_MASK) \
81 << AUDIO_PORT_TX_FIFO_SC_OFFSET)
82#define TX_FIFO_LC(x) (((x) & AUDIO_PORT_TX_FIFO_LEVEL_CHECK_MASK) \
83 << AUDIO_PORT_TX_FIFO_LC_OFFSET)
84#define TX_FIFO_HC(x) (((x) & AUDIO_PORT_TX_FIFO_LEVEL_CHECK_MASK) \
85 << AUDIO_PORT_TX_FIFO_HC_OFFSET)
86
87#define AUDIO_PORT_RX_FIFO_LEVEL_CHECK_MASK 0x0F
88#define AUDIO_PORT_RX_FIFO_SC_OFFSET 0
89#define AUDIO_PORT_RX_FIFO_LC_OFFSET 10
90#define AUDIO_PORT_RX_FIFO_HC_OFFSET 20
91
92#define RX_FIFO_SC(x) (((x) & AUDIO_PORT_RX_FIFO_LEVEL_CHECK_MASK) \
93 << AUDIO_PORT_RX_FIFO_SC_OFFSET)
94#define RX_FIFO_LC(x) (((x) & AUDIO_PORT_RX_FIFO_LEVEL_CHECK_MASK) \
95 << AUDIO_PORT_RX_FIFO_LC_OFFSET)
96#define RX_FIFO_HC(x) (((x) & AUDIO_PORT_RX_FIFO_LEVEL_CHECK_MASK) \
97 << AUDIO_PORT_RX_FIFO_HC_OFFSET)
98#define AUDIO_PORT_IC_CODEC_TX_CTRL (0x00F4)
99#define AUDIO_PORT_IC_CODEC_RX_CTRL (0x00F8)
100
101#define AUDIO_PORT_IC_TXFIFO_OP (0x00FC)
102#define AUDIO_PORT_IC_TXFIFO_LEV_CHK (0x0100)
103#define AUDIO_PORT_IC_TXFIFO_STS (0x0104)
104#define AUDIO_PORT_IC_TXFIFO_INT (0x0108)
105#define AUDIO_PORT_IC_TXFIFO_INT_MSK (0x010C)
106
107#define AUDIO_PORT_IC_RXFIFO_OP (0x0110)
108#define AUDIO_PORT_IC_RXFIFO_LEV_CHK (0x0114)
109#define AUDIO_PORT_IC_RXFIFO_STS (0x0118)
110#define AUDIO_PORT_IC_RXFIFO_INT (0x011C)
111#define AUDIO_PORT_IC_RXFIFO_INT_MSK (0x0120)
112
113#define AUDIO_FIFO_START (1 << 0)
114#define AUDIO_FIFO_RESET (1 << 1)
115
116#define AUDIO_FIFO_FULL (1 << 0)
117#define AUDIO_FIFO_EMPTY (1 << 1)
118#define AUDIO_FIFO_OFLOW (1 << 2)
119#define AUDIO_FIFO_UFLOW (1 << 3)
120
121#define IC_TX_ENABLE (0x03)
122#define IC_RX_ENABLE_MONO (0x01)
123#define IC_RX_ENABLE_STEREO (0x03)
124
75#endif /*__SIRF_AUDIO_CODEC_H*/ 125#endif /*__SIRF_AUDIO_CODEC_H*/
diff --git a/sound/soc/codecs/sta32x.c b/sound/soc/codecs/sta32x.c
index 12577749b17b..0579d187135b 100644
--- a/sound/soc/codecs/sta32x.c
+++ b/sound/soc/codecs/sta32x.c
@@ -243,7 +243,7 @@ static int sta32x_coefficient_info(struct snd_kcontrol *kcontrol,
243static int sta32x_coefficient_get(struct snd_kcontrol *kcontrol, 243static int sta32x_coefficient_get(struct snd_kcontrol *kcontrol,
244 struct snd_ctl_elem_value *ucontrol) 244 struct snd_ctl_elem_value *ucontrol)
245{ 245{
246 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 246 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
247 int numcoef = kcontrol->private_value >> 16; 247 int numcoef = kcontrol->private_value >> 16;
248 int index = kcontrol->private_value & 0xffff; 248 int index = kcontrol->private_value & 0xffff;
249 unsigned int cfud; 249 unsigned int cfud;
@@ -272,7 +272,7 @@ static int sta32x_coefficient_get(struct snd_kcontrol *kcontrol,
272static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol, 272static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol,
273 struct snd_ctl_elem_value *ucontrol) 273 struct snd_ctl_elem_value *ucontrol)
274{ 274{
275 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 275 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
276 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); 276 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
277 int numcoef = kcontrol->private_value >> 16; 277 int numcoef = kcontrol->private_value >> 16;
278 int index = kcontrol->private_value & 0xffff; 278 int index = kcontrol->private_value & 0xffff;
diff --git a/sound/soc/codecs/sta350.c b/sound/soc/codecs/sta350.c
new file mode 100644
index 000000000000..cc97dd52aa9c
--- /dev/null
+++ b/sound/soc/codecs/sta350.c
@@ -0,0 +1,1311 @@
1/*
2 * Codec driver for ST STA350 2.1-channel high-efficiency digital audio system
3 *
4 * Copyright: 2014 Raumfeld GmbH
5 * Author: Sven Brandau <info@brandau.biz>
6 *
7 * based on code from:
8 * Raumfeld GmbH
9 * Johannes Stezenbach <js@sig21.net>
10 * Wolfson Microelectronics PLC.
11 * Mark Brown <broonie@opensource.wolfsonmicro.com>
12 * Freescale Semiconductor, Inc.
13 * Timur Tabi <timur@freescale.com>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21#define pr_fmt(fmt) KBUILD_MODNAME ":%s:%d: " fmt, __func__, __LINE__
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/pm.h>
28#include <linux/i2c.h>
29#include <linux/of_device.h>
30#include <linux/of_gpio.h>
31#include <linux/regmap.h>
32#include <linux/regulator/consumer.h>
33#include <linux/gpio/consumer.h>
34#include <linux/slab.h>
35#include <sound/core.h>
36#include <sound/pcm.h>
37#include <sound/pcm_params.h>
38#include <sound/soc.h>
39#include <sound/soc-dapm.h>
40#include <sound/initval.h>
41#include <sound/tlv.h>
42
43#include <sound/sta350.h>
44#include "sta350.h"
45
46#define STA350_RATES (SNDRV_PCM_RATE_32000 | \
47 SNDRV_PCM_RATE_44100 | \
48 SNDRV_PCM_RATE_48000 | \
49 SNDRV_PCM_RATE_88200 | \
50 SNDRV_PCM_RATE_96000 | \
51 SNDRV_PCM_RATE_176400 | \
52 SNDRV_PCM_RATE_192000)
53
54#define STA350_FORMATS \
55 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \
56 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S18_3BE | \
57 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S20_3BE | \
58 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE | \
59 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE | \
60 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE)
61
62/* Power-up register defaults */
63static const struct reg_default sta350_regs[] = {
64 { 0x0, 0x63 },
65 { 0x1, 0x80 },
66 { 0x2, 0xdf },
67 { 0x3, 0x40 },
68 { 0x4, 0xc2 },
69 { 0x5, 0x5c },
70 { 0x6, 0x00 },
71 { 0x7, 0xff },
72 { 0x8, 0x60 },
73 { 0x9, 0x60 },
74 { 0xa, 0x60 },
75 { 0xb, 0x00 },
76 { 0xc, 0x00 },
77 { 0xd, 0x00 },
78 { 0xe, 0x00 },
79 { 0xf, 0x40 },
80 { 0x10, 0x80 },
81 { 0x11, 0x77 },
82 { 0x12, 0x6a },
83 { 0x13, 0x69 },
84 { 0x14, 0x6a },
85 { 0x15, 0x69 },
86 { 0x16, 0x00 },
87 { 0x17, 0x00 },
88 { 0x18, 0x00 },
89 { 0x19, 0x00 },
90 { 0x1a, 0x00 },
91 { 0x1b, 0x00 },
92 { 0x1c, 0x00 },
93 { 0x1d, 0x00 },
94 { 0x1e, 0x00 },
95 { 0x1f, 0x00 },
96 { 0x20, 0x00 },
97 { 0x21, 0x00 },
98 { 0x22, 0x00 },
99 { 0x23, 0x00 },
100 { 0x24, 0x00 },
101 { 0x25, 0x00 },
102 { 0x26, 0x00 },
103 { 0x27, 0x2a },
104 { 0x28, 0xc0 },
105 { 0x29, 0xf3 },
106 { 0x2a, 0x33 },
107 { 0x2b, 0x00 },
108 { 0x2c, 0x0c },
109 { 0x31, 0x00 },
110 { 0x36, 0x00 },
111 { 0x37, 0x00 },
112 { 0x38, 0x00 },
113 { 0x39, 0x01 },
114 { 0x3a, 0xee },
115 { 0x3b, 0xff },
116 { 0x3c, 0x7e },
117 { 0x3d, 0xc0 },
118 { 0x3e, 0x26 },
119 { 0x3f, 0x00 },
120 { 0x48, 0x00 },
121 { 0x49, 0x00 },
122 { 0x4a, 0x00 },
123 { 0x4b, 0x04 },
124 { 0x4c, 0x00 },
125};
126
127static const struct regmap_range sta350_write_regs_range[] = {
128 regmap_reg_range(STA350_CONFA, STA350_AUTO2),
129 regmap_reg_range(STA350_C1CFG, STA350_FDRC2),
130 regmap_reg_range(STA350_EQCFG, STA350_EVOLRES),
131 regmap_reg_range(STA350_NSHAPE, STA350_MISC2),
132};
133
134static const struct regmap_range sta350_read_regs_range[] = {
135 regmap_reg_range(STA350_CONFA, STA350_AUTO2),
136 regmap_reg_range(STA350_C1CFG, STA350_STATUS),
137 regmap_reg_range(STA350_EQCFG, STA350_EVOLRES),
138 regmap_reg_range(STA350_NSHAPE, STA350_MISC2),
139};
140
141static const struct regmap_range sta350_volatile_regs_range[] = {
142 regmap_reg_range(STA350_CFADDR2, STA350_CFUD),
143 regmap_reg_range(STA350_STATUS, STA350_STATUS),
144};
145
146static const struct regmap_access_table sta350_write_regs = {
147 .yes_ranges = sta350_write_regs_range,
148 .n_yes_ranges = ARRAY_SIZE(sta350_write_regs_range),
149};
150
151static const struct regmap_access_table sta350_read_regs = {
152 .yes_ranges = sta350_read_regs_range,
153 .n_yes_ranges = ARRAY_SIZE(sta350_read_regs_range),
154};
155
156static const struct regmap_access_table sta350_volatile_regs = {
157 .yes_ranges = sta350_volatile_regs_range,
158 .n_yes_ranges = ARRAY_SIZE(sta350_volatile_regs_range),
159};
160
161/* regulator power supply names */
162static const char * const sta350_supply_names[] = {
163 "vdd-dig", /* digital supply, 3.3V */
164 "vdd-pll", /* pll supply, 3.3V */
165 "vcc" /* power amp supply, 5V - 26V */
166};
167
168/* codec private data */
169struct sta350_priv {
170 struct regmap *regmap;
171 struct regulator_bulk_data supplies[ARRAY_SIZE(sta350_supply_names)];
172 struct sta350_platform_data *pdata;
173
174 unsigned int mclk;
175 unsigned int format;
176
177 u32 coef_shadow[STA350_COEF_COUNT];
178 int shutdown;
179
180 struct gpio_desc *gpiod_nreset;
181 struct gpio_desc *gpiod_power_down;
182
183 struct mutex coeff_lock;
184};
185
186static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12750, 50, 1);
187static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1);
188static const DECLARE_TLV_DB_SCALE(tone_tlv, -1200, 200, 0);
189
190static const char * const sta350_drc_ac[] = {
191 "Anti-Clipping", "Dynamic Range Compression"
192};
193static const char * const sta350_auto_gc_mode[] = {
194 "User", "AC no clipping", "AC limited clipping (10%)",
195 "DRC nighttime listening mode"
196};
197static const char * const sta350_auto_xo_mode[] = {
198 "User", "80Hz", "100Hz", "120Hz", "140Hz", "160Hz", "180Hz",
199 "200Hz", "220Hz", "240Hz", "260Hz", "280Hz", "300Hz", "320Hz",
200 "340Hz", "360Hz"
201};
202static const char * const sta350_binary_output[] = {
203 "FFX 3-state output - normal operation", "Binary output"
204};
205static const char * const sta350_limiter_select[] = {
206 "Limiter Disabled", "Limiter #1", "Limiter #2"
207};
208static const char * const sta350_limiter_attack_rate[] = {
209 "3.1584", "2.7072", "2.2560", "1.8048", "1.3536", "0.9024",
210 "0.4512", "0.2256", "0.1504", "0.1123", "0.0902", "0.0752",
211 "0.0645", "0.0564", "0.0501", "0.0451"
212};
213static const char * const sta350_limiter_release_rate[] = {
214 "0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299",
215 "0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137",
216 "0.0134", "0.0117", "0.0110", "0.0104"
217};
218static const char * const sta350_noise_shaper_type[] = {
219 "Third order", "Fourth order"
220};
221
222static DECLARE_TLV_DB_RANGE(sta350_limiter_ac_attack_tlv,
223 0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0),
224 8, 16, TLV_DB_SCALE_ITEM(300, 100, 0),
225);
226
227static DECLARE_TLV_DB_RANGE(sta350_limiter_ac_release_tlv,
228 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
229 1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0),
230 2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0),
231 3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0),
232 8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0),
233);
234
235static DECLARE_TLV_DB_RANGE(sta350_limiter_drc_attack_tlv,
236 0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0),
237 8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0),
238 14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0),
239);
240
241static DECLARE_TLV_DB_RANGE(sta350_limiter_drc_release_tlv,
242 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
243 1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0),
244 3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0),
245 5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0),
246 13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0),
247);
248
249static SOC_ENUM_SINGLE_DECL(sta350_drc_ac_enum,
250 STA350_CONFD, STA350_CONFD_DRC_SHIFT,
251 sta350_drc_ac);
252static SOC_ENUM_SINGLE_DECL(sta350_noise_shaper_enum,
253 STA350_CONFE, STA350_CONFE_NSBW_SHIFT,
254 sta350_noise_shaper_type);
255static SOC_ENUM_SINGLE_DECL(sta350_auto_gc_enum,
256 STA350_AUTO1, STA350_AUTO1_AMGC_SHIFT,
257 sta350_auto_gc_mode);
258static SOC_ENUM_SINGLE_DECL(sta350_auto_xo_enum,
259 STA350_AUTO2, STA350_AUTO2_XO_SHIFT,
260 sta350_auto_xo_mode);
261static SOC_ENUM_SINGLE_DECL(sta350_binary_output_ch1_enum,
262 STA350_C1CFG, STA350_CxCFG_BO_SHIFT,
263 sta350_binary_output);
264static SOC_ENUM_SINGLE_DECL(sta350_binary_output_ch2_enum,
265 STA350_C2CFG, STA350_CxCFG_BO_SHIFT,
266 sta350_binary_output);
267static SOC_ENUM_SINGLE_DECL(sta350_binary_output_ch3_enum,
268 STA350_C3CFG, STA350_CxCFG_BO_SHIFT,
269 sta350_binary_output);
270static SOC_ENUM_SINGLE_DECL(sta350_limiter_ch1_enum,
271 STA350_C1CFG, STA350_CxCFG_LS_SHIFT,
272 sta350_limiter_select);
273static SOC_ENUM_SINGLE_DECL(sta350_limiter_ch2_enum,
274 STA350_C2CFG, STA350_CxCFG_LS_SHIFT,
275 sta350_limiter_select);
276static SOC_ENUM_SINGLE_DECL(sta350_limiter_ch3_enum,
277 STA350_C3CFG, STA350_CxCFG_LS_SHIFT,
278 sta350_limiter_select);
279static SOC_ENUM_SINGLE_DECL(sta350_limiter1_attack_rate_enum,
280 STA350_L1AR, STA350_LxA_SHIFT,
281 sta350_limiter_attack_rate);
282static SOC_ENUM_SINGLE_DECL(sta350_limiter2_attack_rate_enum,
283 STA350_L2AR, STA350_LxA_SHIFT,
284 sta350_limiter_attack_rate);
285static SOC_ENUM_SINGLE_DECL(sta350_limiter1_release_rate_enum,
286 STA350_L1AR, STA350_LxR_SHIFT,
287 sta350_limiter_release_rate);
288static SOC_ENUM_SINGLE_DECL(sta350_limiter2_release_rate_enum,
289 STA350_L2AR, STA350_LxR_SHIFT,
290 sta350_limiter_release_rate);
291
292/*
293 * byte array controls for setting biquad, mixer, scaling coefficients;
294 * for biquads all five coefficients need to be set in one go,
295 * mixer and pre/postscale coefs can be set individually;
296 * each coef is 24bit, the bytes are ordered in the same way
297 * as given in the STA350 data sheet (big endian; b1, b2, a1, a2, b0)
298 */
299
300static int sta350_coefficient_info(struct snd_kcontrol *kcontrol,
301 struct snd_ctl_elem_info *uinfo)
302{
303 int numcoef = kcontrol->private_value >> 16;
304 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
305 uinfo->count = 3 * numcoef;
306 return 0;
307}
308
309static int sta350_coefficient_get(struct snd_kcontrol *kcontrol,
310 struct snd_ctl_elem_value *ucontrol)
311{
312 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
313 struct sta350_priv *sta350 = snd_soc_codec_get_drvdata(codec);
314 int numcoef = kcontrol->private_value >> 16;
315 int index = kcontrol->private_value & 0xffff;
316 unsigned int cfud, val;
317 int i, ret = 0;
318
319 mutex_lock(&sta350->coeff_lock);
320
321 /* preserve reserved bits in STA350_CFUD */
322 regmap_read(sta350->regmap, STA350_CFUD, &cfud);
323 cfud &= 0xf0;
324 /*
325 * chip documentation does not say if the bits are self clearing,
326 * so do it explicitly
327 */
328 regmap_write(sta350->regmap, STA350_CFUD, cfud);
329
330 regmap_write(sta350->regmap, STA350_CFADDR2, index);
331 if (numcoef == 1) {
332 regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x04);
333 } else if (numcoef == 5) {
334 regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x08);
335 } else {
336 ret = -EINVAL;
337 goto exit_unlock;
338 }
339
340 for (i = 0; i < 3 * numcoef; i++) {
341 regmap_read(sta350->regmap, STA350_B1CF1 + i, &val);
342 ucontrol->value.bytes.data[i] = val;
343 }
344
345exit_unlock:
346 mutex_unlock(&sta350->coeff_lock);
347
348 return ret;
349}
350
351static int sta350_coefficient_put(struct snd_kcontrol *kcontrol,
352 struct snd_ctl_elem_value *ucontrol)
353{
354 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
355 struct sta350_priv *sta350 = snd_soc_codec_get_drvdata(codec);
356 int numcoef = kcontrol->private_value >> 16;
357 int index = kcontrol->private_value & 0xffff;
358 unsigned int cfud;
359 int i;
360
361 /* preserve reserved bits in STA350_CFUD */
362 regmap_read(sta350->regmap, STA350_CFUD, &cfud);
363 cfud &= 0xf0;
364 /*
365 * chip documentation does not say if the bits are self clearing,
366 * so do it explicitly
367 */
368 regmap_write(sta350->regmap, STA350_CFUD, cfud);
369
370 regmap_write(sta350->regmap, STA350_CFADDR2, index);
371 for (i = 0; i < numcoef && (index + i < STA350_COEF_COUNT); i++)
372 sta350->coef_shadow[index + i] =
373 (ucontrol->value.bytes.data[3 * i] << 16)
374 | (ucontrol->value.bytes.data[3 * i + 1] << 8)
375 | (ucontrol->value.bytes.data[3 * i + 2]);
376 for (i = 0; i < 3 * numcoef; i++)
377 regmap_write(sta350->regmap, STA350_B1CF1 + i,
378 ucontrol->value.bytes.data[i]);
379 if (numcoef == 1)
380 regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x01);
381 else if (numcoef == 5)
382 regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x02);
383 else
384 return -EINVAL;
385
386 return 0;
387}
388
389static int sta350_sync_coef_shadow(struct snd_soc_codec *codec)
390{
391 struct sta350_priv *sta350 = snd_soc_codec_get_drvdata(codec);
392 unsigned int cfud;
393 int i;
394
395 /* preserve reserved bits in STA350_CFUD */
396 regmap_read(sta350->regmap, STA350_CFUD, &cfud);
397 cfud &= 0xf0;
398
399 for (i = 0; i < STA350_COEF_COUNT; i++) {
400 regmap_write(sta350->regmap, STA350_CFADDR2, i);
401 regmap_write(sta350->regmap, STA350_B1CF1,
402 (sta350->coef_shadow[i] >> 16) & 0xff);
403 regmap_write(sta350->regmap, STA350_B1CF2,
404 (sta350->coef_shadow[i] >> 8) & 0xff);
405 regmap_write(sta350->regmap, STA350_B1CF3,
406 (sta350->coef_shadow[i]) & 0xff);
407 /*
408 * chip documentation does not say if the bits are
409 * self-clearing, so do it explicitly
410 */
411 regmap_write(sta350->regmap, STA350_CFUD, cfud);
412 regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x01);
413 }
414 return 0;
415}
416
417static int sta350_cache_sync(struct snd_soc_codec *codec)
418{
419 struct sta350_priv *sta350 = snd_soc_codec_get_drvdata(codec);
420 unsigned int mute;
421 int rc;
422
423 /* mute during register sync */
424 regmap_read(sta350->regmap, STA350_CFUD, &mute);
425 regmap_write(sta350->regmap, STA350_MMUTE, mute | STA350_MMUTE_MMUTE);
426 sta350_sync_coef_shadow(codec);
427 rc = regcache_sync(sta350->regmap);
428 regmap_write(sta350->regmap, STA350_MMUTE, mute);
429 return rc;
430}
431
432#define SINGLE_COEF(xname, index) \
433{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
434 .info = sta350_coefficient_info, \
435 .get = sta350_coefficient_get,\
436 .put = sta350_coefficient_put, \
437 .private_value = index | (1 << 16) }
438
439#define BIQUAD_COEFS(xname, index) \
440{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
441 .info = sta350_coefficient_info, \
442 .get = sta350_coefficient_get,\
443 .put = sta350_coefficient_put, \
444 .private_value = index | (5 << 16) }
445
446static const struct snd_kcontrol_new sta350_snd_controls[] = {
447SOC_SINGLE_TLV("Master Volume", STA350_MVOL, 0, 0xff, 1, mvol_tlv),
448/* VOL */
449SOC_SINGLE_TLV("Ch1 Volume", STA350_C1VOL, 0, 0xff, 1, chvol_tlv),
450SOC_SINGLE_TLV("Ch2 Volume", STA350_C2VOL, 0, 0xff, 1, chvol_tlv),
451SOC_SINGLE_TLV("Ch3 Volume", STA350_C3VOL, 0, 0xff, 1, chvol_tlv),
452/* CONFD */
453SOC_SINGLE("High Pass Filter Bypass Switch",
454 STA350_CONFD, STA350_CONFD_HPB_SHIFT, 1, 1),
455SOC_SINGLE("De-emphasis Filter Switch",
456 STA350_CONFD, STA350_CONFD_DEMP_SHIFT, 1, 0),
457SOC_SINGLE("DSP Bypass Switch",
458 STA350_CONFD, STA350_CONFD_DSPB_SHIFT, 1, 0),
459SOC_SINGLE("Post-scale Link Switch",
460 STA350_CONFD, STA350_CONFD_PSL_SHIFT, 1, 0),
461SOC_SINGLE("Biquad Coefficient Link Switch",
462 STA350_CONFD, STA350_CONFD_BQL_SHIFT, 1, 0),
463SOC_ENUM("Compressor/Limiter Switch", sta350_drc_ac_enum),
464SOC_ENUM("Noise Shaper Bandwidth", sta350_noise_shaper_enum),
465SOC_SINGLE("Zero-detect Mute Enable Switch",
466 STA350_CONFD, STA350_CONFD_ZDE_SHIFT, 1, 0),
467SOC_SINGLE("Submix Mode Switch",
468 STA350_CONFD, STA350_CONFD_SME_SHIFT, 1, 0),
469/* CONFE */
470SOC_SINGLE("Zero Cross Switch", STA350_CONFE, STA350_CONFE_ZCE_SHIFT, 1, 0),
471SOC_SINGLE("Soft Ramp Switch", STA350_CONFE, STA350_CONFE_SVE_SHIFT, 1, 0),
472/* MUTE */
473SOC_SINGLE("Master Switch", STA350_MMUTE, STA350_MMUTE_MMUTE_SHIFT, 1, 1),
474SOC_SINGLE("Ch1 Switch", STA350_MMUTE, STA350_MMUTE_C1M_SHIFT, 1, 1),
475SOC_SINGLE("Ch2 Switch", STA350_MMUTE, STA350_MMUTE_C2M_SHIFT, 1, 1),
476SOC_SINGLE("Ch3 Switch", STA350_MMUTE, STA350_MMUTE_C3M_SHIFT, 1, 1),
477/* AUTOx */
478SOC_ENUM("Automode GC", sta350_auto_gc_enum),
479SOC_ENUM("Automode XO", sta350_auto_xo_enum),
480/* CxCFG */
481SOC_SINGLE("Ch1 Tone Control Bypass Switch",
482 STA350_C1CFG, STA350_CxCFG_TCB_SHIFT, 1, 0),
483SOC_SINGLE("Ch2 Tone Control Bypass Switch",
484 STA350_C2CFG, STA350_CxCFG_TCB_SHIFT, 1, 0),
485SOC_SINGLE("Ch1 EQ Bypass Switch",
486 STA350_C1CFG, STA350_CxCFG_EQBP_SHIFT, 1, 0),
487SOC_SINGLE("Ch2 EQ Bypass Switch",
488 STA350_C2CFG, STA350_CxCFG_EQBP_SHIFT, 1, 0),
489SOC_SINGLE("Ch1 Master Volume Bypass Switch",
490 STA350_C1CFG, STA350_CxCFG_VBP_SHIFT, 1, 0),
491SOC_SINGLE("Ch2 Master Volume Bypass Switch",
492 STA350_C1CFG, STA350_CxCFG_VBP_SHIFT, 1, 0),
493SOC_SINGLE("Ch3 Master Volume Bypass Switch",
494 STA350_C1CFG, STA350_CxCFG_VBP_SHIFT, 1, 0),
495SOC_ENUM("Ch1 Binary Output Select", sta350_binary_output_ch1_enum),
496SOC_ENUM("Ch2 Binary Output Select", sta350_binary_output_ch2_enum),
497SOC_ENUM("Ch3 Binary Output Select", sta350_binary_output_ch3_enum),
498SOC_ENUM("Ch1 Limiter Select", sta350_limiter_ch1_enum),
499SOC_ENUM("Ch2 Limiter Select", sta350_limiter_ch2_enum),
500SOC_ENUM("Ch3 Limiter Select", sta350_limiter_ch3_enum),
501/* TONE */
502SOC_SINGLE_RANGE_TLV("Bass Tone Control Volume",
503 STA350_TONE, STA350_TONE_BTC_SHIFT, 1, 13, 0, tone_tlv),
504SOC_SINGLE_RANGE_TLV("Treble Tone Control Volume",
505 STA350_TONE, STA350_TONE_TTC_SHIFT, 1, 13, 0, tone_tlv),
506SOC_ENUM("Limiter1 Attack Rate (dB/ms)", sta350_limiter1_attack_rate_enum),
507SOC_ENUM("Limiter2 Attack Rate (dB/ms)", sta350_limiter2_attack_rate_enum),
508SOC_ENUM("Limiter1 Release Rate (dB/ms)", sta350_limiter1_release_rate_enum),
509SOC_ENUM("Limiter2 Release Rate (dB/ms)", sta350_limiter2_release_rate_enum),
510
511/*
512 * depending on mode, the attack/release thresholds have
513 * two different enum definitions; provide both
514 */
515SOC_SINGLE_TLV("Limiter1 Attack Threshold (AC Mode)",
516 STA350_L1ATRT, STA350_LxA_SHIFT,
517 16, 0, sta350_limiter_ac_attack_tlv),
518SOC_SINGLE_TLV("Limiter2 Attack Threshold (AC Mode)",
519 STA350_L2ATRT, STA350_LxA_SHIFT,
520 16, 0, sta350_limiter_ac_attack_tlv),
521SOC_SINGLE_TLV("Limiter1 Release Threshold (AC Mode)",
522 STA350_L1ATRT, STA350_LxR_SHIFT,
523 16, 0, sta350_limiter_ac_release_tlv),
524SOC_SINGLE_TLV("Limiter2 Release Threshold (AC Mode)",
525 STA350_L2ATRT, STA350_LxR_SHIFT,
526 16, 0, sta350_limiter_ac_release_tlv),
527SOC_SINGLE_TLV("Limiter1 Attack Threshold (DRC Mode)",
528 STA350_L1ATRT, STA350_LxA_SHIFT,
529 16, 0, sta350_limiter_drc_attack_tlv),
530SOC_SINGLE_TLV("Limiter2 Attack Threshold (DRC Mode)",
531 STA350_L2ATRT, STA350_LxA_SHIFT,
532 16, 0, sta350_limiter_drc_attack_tlv),
533SOC_SINGLE_TLV("Limiter1 Release Threshold (DRC Mode)",
534 STA350_L1ATRT, STA350_LxR_SHIFT,
535 16, 0, sta350_limiter_drc_release_tlv),
536SOC_SINGLE_TLV("Limiter2 Release Threshold (DRC Mode)",
537 STA350_L2ATRT, STA350_LxR_SHIFT,
538 16, 0, sta350_limiter_drc_release_tlv),
539
540BIQUAD_COEFS("Ch1 - Biquad 1", 0),
541BIQUAD_COEFS("Ch1 - Biquad 2", 5),
542BIQUAD_COEFS("Ch1 - Biquad 3", 10),
543BIQUAD_COEFS("Ch1 - Biquad 4", 15),
544BIQUAD_COEFS("Ch2 - Biquad 1", 20),
545BIQUAD_COEFS("Ch2 - Biquad 2", 25),
546BIQUAD_COEFS("Ch2 - Biquad 3", 30),
547BIQUAD_COEFS("Ch2 - Biquad 4", 35),
548BIQUAD_COEFS("High-pass", 40),
549BIQUAD_COEFS("Low-pass", 45),
550SINGLE_COEF("Ch1 - Prescale", 50),
551SINGLE_COEF("Ch2 - Prescale", 51),
552SINGLE_COEF("Ch1 - Postscale", 52),
553SINGLE_COEF("Ch2 - Postscale", 53),
554SINGLE_COEF("Ch3 - Postscale", 54),
555SINGLE_COEF("Thermal warning - Postscale", 55),
556SINGLE_COEF("Ch1 - Mix 1", 56),
557SINGLE_COEF("Ch1 - Mix 2", 57),
558SINGLE_COEF("Ch2 - Mix 1", 58),
559SINGLE_COEF("Ch2 - Mix 2", 59),
560SINGLE_COEF("Ch3 - Mix 1", 60),
561SINGLE_COEF("Ch3 - Mix 2", 61),
562};
563
564static const struct snd_soc_dapm_widget sta350_dapm_widgets[] = {
565SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
566SND_SOC_DAPM_OUTPUT("LEFT"),
567SND_SOC_DAPM_OUTPUT("RIGHT"),
568SND_SOC_DAPM_OUTPUT("SUB"),
569};
570
571static const struct snd_soc_dapm_route sta350_dapm_routes[] = {
572 { "LEFT", NULL, "DAC" },
573 { "RIGHT", NULL, "DAC" },
574 { "SUB", NULL, "DAC" },
575 { "DAC", NULL, "Playback" },
576};
577
578/* MCLK interpolation ratio per fs */
579static struct {
580 int fs;
581 int ir;
582} interpolation_ratios[] = {
583 { 32000, 0 },
584 { 44100, 0 },
585 { 48000, 0 },
586 { 88200, 1 },
587 { 96000, 1 },
588 { 176400, 2 },
589 { 192000, 2 },
590};
591
592/* MCLK to fs clock ratios */
593static int mcs_ratio_table[3][6] = {
594 { 768, 512, 384, 256, 128, 576 },
595 { 384, 256, 192, 128, 64, 0 },
596 { 192, 128, 96, 64, 32, 0 },
597};
598
599/**
600 * sta350_set_dai_sysclk - configure MCLK
601 * @codec_dai: the codec DAI
602 * @clk_id: the clock ID (ignored)
603 * @freq: the MCLK input frequency
604 * @dir: the clock direction (ignored)
605 *
606 * The value of MCLK is used to determine which sample rates are supported
607 * by the STA350, based on the mcs_ratio_table.
608 *
609 * This function must be called by the machine driver's 'startup' function,
610 * otherwise the list of supported sample rates will not be available in
611 * time for ALSA.
612 */
613static int sta350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
614 int clk_id, unsigned int freq, int dir)
615{
616 struct snd_soc_codec *codec = codec_dai->codec;
617 struct sta350_priv *sta350 = snd_soc_codec_get_drvdata(codec);
618
619 dev_dbg(codec->dev, "mclk=%u\n", freq);
620 sta350->mclk = freq;
621
622 return 0;
623}
624
625/**
626 * sta350_set_dai_fmt - configure the codec for the selected audio format
627 * @codec_dai: the codec DAI
628 * @fmt: a SND_SOC_DAIFMT_x value indicating the data format
629 *
630 * This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the
631 * codec accordingly.
632 */
633static int sta350_set_dai_fmt(struct snd_soc_dai *codec_dai,
634 unsigned int fmt)
635{
636 struct snd_soc_codec *codec = codec_dai->codec;
637 struct sta350_priv *sta350 = snd_soc_codec_get_drvdata(codec);
638 unsigned int confb = 0;
639
640 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
641 case SND_SOC_DAIFMT_CBS_CFS:
642 break;
643 default:
644 return -EINVAL;
645 }
646
647 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
648 case SND_SOC_DAIFMT_I2S:
649 case SND_SOC_DAIFMT_RIGHT_J:
650 case SND_SOC_DAIFMT_LEFT_J:
651 sta350->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
652 break;
653 default:
654 return -EINVAL;
655 }
656
657 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
658 case SND_SOC_DAIFMT_NB_NF:
659 confb |= STA350_CONFB_C2IM;
660 break;
661 case SND_SOC_DAIFMT_NB_IF:
662 confb |= STA350_CONFB_C1IM;
663 break;
664 default:
665 return -EINVAL;
666 }
667
668 return regmap_update_bits(sta350->regmap, STA350_CONFB,
669 STA350_CONFB_C1IM | STA350_CONFB_C2IM, confb);
670}
671
672/**
673 * sta350_hw_params - program the STA350 with the given hardware parameters.
674 * @substream: the audio stream
675 * @params: the hardware parameters to set
676 * @dai: the SOC DAI (ignored)
677 *
678 * This function programs the hardware with the values provided.
679 * Specifically, the sample rate and the data format.
680 */
681static int sta350_hw_params(struct snd_pcm_substream *substream,
682 struct snd_pcm_hw_params *params,
683 struct snd_soc_dai *dai)
684{
685 struct snd_soc_codec *codec = dai->codec;
686 struct sta350_priv *sta350 = snd_soc_codec_get_drvdata(codec);
687 int i, mcs = -EINVAL, ir = -EINVAL;
688 unsigned int confa, confb;
689 unsigned int rate, ratio;
690 int ret;
691
692 if (!sta350->mclk) {
693 dev_err(codec->dev,
694 "sta350->mclk is unset. Unable to determine ratio\n");
695 return -EIO;
696 }
697
698 rate = params_rate(params);
699 ratio = sta350->mclk / rate;
700 dev_dbg(codec->dev, "rate: %u, ratio: %u\n", rate, ratio);
701
702 for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) {
703 if (interpolation_ratios[i].fs == rate) {
704 ir = interpolation_ratios[i].ir;
705 break;
706 }
707 }
708
709 if (ir < 0) {
710 dev_err(codec->dev, "Unsupported samplerate: %u\n", rate);
711 return -EINVAL;
712 }
713
714 for (i = 0; i < 6; i++) {
715 if (mcs_ratio_table[ir][i] == ratio) {
716 mcs = i;
717 break;
718 }
719 }
720
721 if (mcs < 0) {
722 dev_err(codec->dev, "Unresolvable ratio: %u\n", ratio);
723 return -EINVAL;
724 }
725
726 confa = (ir << STA350_CONFA_IR_SHIFT) |
727 (mcs << STA350_CONFA_MCS_SHIFT);
728 confb = 0;
729
730 switch (params_width(params)) {
731 case 24:
732 dev_dbg(codec->dev, "24bit\n");
733 /* fall through */
734 case 32:
735 dev_dbg(codec->dev, "24bit or 32bit\n");
736 switch (sta350->format) {
737 case SND_SOC_DAIFMT_I2S:
738 confb |= 0x0;
739 break;
740 case SND_SOC_DAIFMT_LEFT_J:
741 confb |= 0x1;
742 break;
743 case SND_SOC_DAIFMT_RIGHT_J:
744 confb |= 0x2;
745 break;
746 }
747
748 break;
749 case 20:
750 dev_dbg(codec->dev, "20bit\n");
751 switch (sta350->format) {
752 case SND_SOC_DAIFMT_I2S:
753 confb |= 0x4;
754 break;
755 case SND_SOC_DAIFMT_LEFT_J:
756 confb |= 0x5;
757 break;
758 case SND_SOC_DAIFMT_RIGHT_J:
759 confb |= 0x6;
760 break;
761 }
762
763 break;
764 case 18:
765 dev_dbg(codec->dev, "18bit\n");
766 switch (sta350->format) {
767 case SND_SOC_DAIFMT_I2S:
768 confb |= 0x8;
769 break;
770 case SND_SOC_DAIFMT_LEFT_J:
771 confb |= 0x9;
772 break;
773 case SND_SOC_DAIFMT_RIGHT_J:
774 confb |= 0xa;
775 break;
776 }
777
778 break;
779 case 16:
780 dev_dbg(codec->dev, "16bit\n");
781 switch (sta350->format) {
782 case SND_SOC_DAIFMT_I2S:
783 confb |= 0x0;
784 break;
785 case SND_SOC_DAIFMT_LEFT_J:
786 confb |= 0xd;
787 break;
788 case SND_SOC_DAIFMT_RIGHT_J:
789 confb |= 0xe;
790 break;
791 }
792
793 break;
794 default:
795 return -EINVAL;
796 }
797
798 ret = regmap_update_bits(sta350->regmap, STA350_CONFA,
799 STA350_CONFA_MCS_MASK | STA350_CONFA_IR_MASK,
800 confa);
801 if (ret < 0)
802 return ret;
803
804 ret = regmap_update_bits(sta350->regmap, STA350_CONFB,
805 STA350_CONFB_SAI_MASK | STA350_CONFB_SAIFB,
806 confb);
807 if (ret < 0)
808 return ret;
809
810 return 0;
811}
812
813static int sta350_startup_sequence(struct sta350_priv *sta350)
814{
815 if (sta350->gpiod_power_down)
816 gpiod_set_value(sta350->gpiod_power_down, 1);
817
818 if (sta350->gpiod_nreset) {
819 gpiod_set_value(sta350->gpiod_nreset, 0);
820 mdelay(1);
821 gpiod_set_value(sta350->gpiod_nreset, 1);
822 mdelay(1);
823 }
824
825 return 0;
826}
827
828/**
829 * sta350_set_bias_level - DAPM callback
830 * @codec: the codec device
831 * @level: DAPM power level
832 *
833 * This is called by ALSA to put the codec into low power mode
834 * or to wake it up. If the codec is powered off completely
835 * all registers must be restored after power on.
836 */
837static int sta350_set_bias_level(struct snd_soc_codec *codec,
838 enum snd_soc_bias_level level)
839{
840 struct sta350_priv *sta350 = snd_soc_codec_get_drvdata(codec);
841 int ret;
842
843 dev_dbg(codec->dev, "level = %d\n", level);
844 switch (level) {
845 case SND_SOC_BIAS_ON:
846 break;
847
848 case SND_SOC_BIAS_PREPARE:
849 /* Full power on */
850 regmap_update_bits(sta350->regmap, STA350_CONFF,
851 STA350_CONFF_PWDN | STA350_CONFF_EAPD,
852 STA350_CONFF_PWDN | STA350_CONFF_EAPD);
853 break;
854
855 case SND_SOC_BIAS_STANDBY:
856 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
857 ret = regulator_bulk_enable(
858 ARRAY_SIZE(sta350->supplies),
859 sta350->supplies);
860 if (ret < 0) {
861 dev_err(codec->dev,
862 "Failed to enable supplies: %d\n",
863 ret);
864 return ret;
865 }
866 sta350_startup_sequence(sta350);
867 sta350_cache_sync(codec);
868 }
869
870 /* Power down */
871 regmap_update_bits(sta350->regmap, STA350_CONFF,
872 STA350_CONFF_PWDN | STA350_CONFF_EAPD,
873 0);
874
875 break;
876
877 case SND_SOC_BIAS_OFF:
878 /* The chip runs through the power down sequence for us */
879 regmap_update_bits(sta350->regmap, STA350_CONFF,
880 STA350_CONFF_PWDN | STA350_CONFF_EAPD, 0);
881
882 /* power down: low */
883 if (sta350->gpiod_power_down)
884 gpiod_set_value(sta350->gpiod_power_down, 0);
885
886 if (sta350->gpiod_nreset)
887 gpiod_set_value(sta350->gpiod_nreset, 0);
888
889 regulator_bulk_disable(ARRAY_SIZE(sta350->supplies),
890 sta350->supplies);
891 break;
892 }
893 codec->dapm.bias_level = level;
894 return 0;
895}
896
897static const struct snd_soc_dai_ops sta350_dai_ops = {
898 .hw_params = sta350_hw_params,
899 .set_sysclk = sta350_set_dai_sysclk,
900 .set_fmt = sta350_set_dai_fmt,
901};
902
903static struct snd_soc_dai_driver sta350_dai = {
904 .name = "sta350-hifi",
905 .playback = {
906 .stream_name = "Playback",
907 .channels_min = 2,
908 .channels_max = 2,
909 .rates = STA350_RATES,
910 .formats = STA350_FORMATS,
911 },
912 .ops = &sta350_dai_ops,
913};
914
915#ifdef CONFIG_PM
916static int sta350_suspend(struct snd_soc_codec *codec)
917{
918 sta350_set_bias_level(codec, SND_SOC_BIAS_OFF);
919 return 0;
920}
921
922static int sta350_resume(struct snd_soc_codec *codec)
923{
924 sta350_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
925 return 0;
926}
927#else
928#define sta350_suspend NULL
929#define sta350_resume NULL
930#endif
931
932static int sta350_probe(struct snd_soc_codec *codec)
933{
934 struct sta350_priv *sta350 = snd_soc_codec_get_drvdata(codec);
935 struct sta350_platform_data *pdata = sta350->pdata;
936 int i, ret = 0, thermal = 0;
937
938 ret = regulator_bulk_enable(ARRAY_SIZE(sta350->supplies),
939 sta350->supplies);
940 if (ret < 0) {
941 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
942 return ret;
943 }
944
945 ret = sta350_startup_sequence(sta350);
946 if (ret < 0) {
947 dev_err(codec->dev, "Failed to startup device\n");
948 return ret;
949 }
950
951 /* CONFA */
952 if (!pdata->thermal_warning_recovery)
953 thermal |= STA350_CONFA_TWAB;
954 if (!pdata->thermal_warning_adjustment)
955 thermal |= STA350_CONFA_TWRB;
956 if (!pdata->fault_detect_recovery)
957 thermal |= STA350_CONFA_FDRB;
958 regmap_update_bits(sta350->regmap, STA350_CONFA,
959 STA350_CONFA_TWAB | STA350_CONFA_TWRB |
960 STA350_CONFA_FDRB,
961 thermal);
962
963 /* CONFC */
964 regmap_update_bits(sta350->regmap, STA350_CONFC,
965 STA350_CONFC_OM_MASK,
966 pdata->ffx_power_output_mode
967 << STA350_CONFC_OM_SHIFT);
968 regmap_update_bits(sta350->regmap, STA350_CONFC,
969 STA350_CONFC_CSZ_MASK,
970 pdata->drop_compensation_ns
971 << STA350_CONFC_CSZ_SHIFT);
972 regmap_update_bits(sta350->regmap,
973 STA350_CONFC,
974 STA350_CONFC_OCRB,
975 pdata->oc_warning_adjustment ?
976 STA350_CONFC_OCRB : 0);
977
978 /* CONFE */
979 regmap_update_bits(sta350->regmap, STA350_CONFE,
980 STA350_CONFE_MPCV,
981 pdata->max_power_use_mpcc ?
982 STA350_CONFE_MPCV : 0);
983 regmap_update_bits(sta350->regmap, STA350_CONFE,
984 STA350_CONFE_MPC,
985 pdata->max_power_correction ?
986 STA350_CONFE_MPC : 0);
987 regmap_update_bits(sta350->regmap, STA350_CONFE,
988 STA350_CONFE_AME,
989 pdata->am_reduction_mode ?
990 STA350_CONFE_AME : 0);
991 regmap_update_bits(sta350->regmap, STA350_CONFE,
992 STA350_CONFE_PWMS,
993 pdata->odd_pwm_speed_mode ?
994 STA350_CONFE_PWMS : 0);
995 regmap_update_bits(sta350->regmap, STA350_CONFE,
996 STA350_CONFE_DCCV,
997 pdata->distortion_compensation ?
998 STA350_CONFE_DCCV : 0);
999 /* CONFF */
1000 regmap_update_bits(sta350->regmap, STA350_CONFF,
1001 STA350_CONFF_IDE,
1002 pdata->invalid_input_detect_mute ?
1003 STA350_CONFF_IDE : 0);
1004 regmap_update_bits(sta350->regmap, STA350_CONFF,
1005 STA350_CONFF_OCFG_MASK,
1006 pdata->output_conf
1007 << STA350_CONFF_OCFG_SHIFT);
1008
1009 /* channel to output mapping */
1010 regmap_update_bits(sta350->regmap, STA350_C1CFG,
1011 STA350_CxCFG_OM_MASK,
1012 pdata->ch1_output_mapping
1013 << STA350_CxCFG_OM_SHIFT);
1014 regmap_update_bits(sta350->regmap, STA350_C2CFG,
1015 STA350_CxCFG_OM_MASK,
1016 pdata->ch2_output_mapping
1017 << STA350_CxCFG_OM_SHIFT);
1018 regmap_update_bits(sta350->regmap, STA350_C3CFG,
1019 STA350_CxCFG_OM_MASK,
1020 pdata->ch3_output_mapping
1021 << STA350_CxCFG_OM_SHIFT);
1022
1023 /* miscellaneous registers */
1024 regmap_update_bits(sta350->regmap, STA350_MISC1,
1025 STA350_MISC1_CPWMEN,
1026 pdata->activate_mute_output ?
1027 STA350_MISC1_CPWMEN : 0);
1028 regmap_update_bits(sta350->regmap, STA350_MISC1,
1029 STA350_MISC1_BRIDGOFF,
1030 pdata->bridge_immediate_off ?
1031 STA350_MISC1_BRIDGOFF : 0);
1032 regmap_update_bits(sta350->regmap, STA350_MISC1,
1033 STA350_MISC1_NSHHPEN,
1034 pdata->noise_shape_dc_cut ?
1035 STA350_MISC1_NSHHPEN : 0);
1036 regmap_update_bits(sta350->regmap, STA350_MISC1,
1037 STA350_MISC1_RPDNEN,
1038 pdata->powerdown_master_vol ?
1039 STA350_MISC1_RPDNEN: 0);
1040
1041 regmap_update_bits(sta350->regmap, STA350_MISC2,
1042 STA350_MISC2_PNDLSL_MASK,
1043 pdata->powerdown_delay_divider
1044 << STA350_MISC2_PNDLSL_SHIFT);
1045
1046 /* initialize coefficient shadow RAM with reset values */
1047 for (i = 4; i <= 49; i += 5)
1048 sta350->coef_shadow[i] = 0x400000;
1049 for (i = 50; i <= 54; i++)
1050 sta350->coef_shadow[i] = 0x7fffff;
1051 sta350->coef_shadow[55] = 0x5a9df7;
1052 sta350->coef_shadow[56] = 0x7fffff;
1053 sta350->coef_shadow[59] = 0x7fffff;
1054 sta350->coef_shadow[60] = 0x400000;
1055 sta350->coef_shadow[61] = 0x400000;
1056
1057 sta350_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1058 /* Bias level configuration will have done an extra enable */
1059 regulator_bulk_disable(ARRAY_SIZE(sta350->supplies), sta350->supplies);
1060
1061 return 0;
1062}
1063
1064static int sta350_remove(struct snd_soc_codec *codec)
1065{
1066 struct sta350_priv *sta350 = snd_soc_codec_get_drvdata(codec);
1067
1068 sta350_set_bias_level(codec, SND_SOC_BIAS_OFF);
1069 regulator_bulk_disable(ARRAY_SIZE(sta350->supplies), sta350->supplies);
1070
1071 return 0;
1072}
1073
1074static const struct snd_soc_codec_driver sta350_codec = {
1075 .probe = sta350_probe,
1076 .remove = sta350_remove,
1077 .suspend = sta350_suspend,
1078 .resume = sta350_resume,
1079 .set_bias_level = sta350_set_bias_level,
1080 .controls = sta350_snd_controls,
1081 .num_controls = ARRAY_SIZE(sta350_snd_controls),
1082 .dapm_widgets = sta350_dapm_widgets,
1083 .num_dapm_widgets = ARRAY_SIZE(sta350_dapm_widgets),
1084 .dapm_routes = sta350_dapm_routes,
1085 .num_dapm_routes = ARRAY_SIZE(sta350_dapm_routes),
1086};
1087
1088static const struct regmap_config sta350_regmap = {
1089 .reg_bits = 8,
1090 .val_bits = 8,
1091 .max_register = STA350_MISC2,
1092 .reg_defaults = sta350_regs,
1093 .num_reg_defaults = ARRAY_SIZE(sta350_regs),
1094 .cache_type = REGCACHE_RBTREE,
1095 .wr_table = &sta350_write_regs,
1096 .rd_table = &sta350_read_regs,
1097 .volatile_table = &sta350_volatile_regs,
1098};
1099
1100#ifdef CONFIG_OF
1101static const struct of_device_id st350_dt_ids[] = {
1102 { .compatible = "st,sta350", },
1103 { }
1104};
1105MODULE_DEVICE_TABLE(of, st350_dt_ids);
1106
1107static const char * const sta350_ffx_modes[] = {
1108 [STA350_FFX_PM_DROP_COMP] = "drop-compensation",
1109 [STA350_FFX_PM_TAPERED_COMP] = "tapered-compensation",
1110 [STA350_FFX_PM_FULL_POWER] = "full-power-mode",
1111 [STA350_FFX_PM_VARIABLE_DROP_COMP] = "variable-drop-compensation",
1112};
1113
1114static int sta350_probe_dt(struct device *dev, struct sta350_priv *sta350)
1115{
1116 struct device_node *np = dev->of_node;
1117 struct sta350_platform_data *pdata;
1118 const char *ffx_power_mode;
1119 u16 tmp;
1120 u8 tmp8;
1121
1122 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1123 if (!pdata)
1124 return -ENOMEM;
1125
1126 of_property_read_u8(np, "st,output-conf",
1127 &pdata->output_conf);
1128 of_property_read_u8(np, "st,ch1-output-mapping",
1129 &pdata->ch1_output_mapping);
1130 of_property_read_u8(np, "st,ch2-output-mapping",
1131 &pdata->ch2_output_mapping);
1132 of_property_read_u8(np, "st,ch3-output-mapping",
1133 &pdata->ch3_output_mapping);
1134
1135 if (of_get_property(np, "st,thermal-warning-recovery", NULL))
1136 pdata->thermal_warning_recovery = 1;
1137 if (of_get_property(np, "st,thermal-warning-adjustment", NULL))
1138 pdata->thermal_warning_adjustment = 1;
1139 if (of_get_property(np, "st,fault-detect-recovery", NULL))
1140 pdata->fault_detect_recovery = 1;
1141
1142 pdata->ffx_power_output_mode = STA350_FFX_PM_VARIABLE_DROP_COMP;
1143 if (!of_property_read_string(np, "st,ffx-power-output-mode",
1144 &ffx_power_mode)) {
1145 int i, mode = -EINVAL;
1146
1147 for (i = 0; i < ARRAY_SIZE(sta350_ffx_modes); i++)
1148 if (!strcasecmp(ffx_power_mode, sta350_ffx_modes[i]))
1149 mode = i;
1150
1151 if (mode < 0)
1152 dev_warn(dev, "Unsupported ffx output mode: %s\n",
1153 ffx_power_mode);
1154 else
1155 pdata->ffx_power_output_mode = mode;
1156 }
1157
1158 tmp = 140;
1159 of_property_read_u16(np, "st,drop-compensation-ns", &tmp);
1160 pdata->drop_compensation_ns = clamp_t(u16, tmp, 0, 300) / 20;
1161
1162 if (of_get_property(np, "st,overcurrent-warning-adjustment", NULL))
1163 pdata->oc_warning_adjustment = 1;
1164
1165 /* CONFE */
1166 if (of_get_property(np, "st,max-power-use-mpcc", NULL))
1167 pdata->max_power_use_mpcc = 1;
1168
1169 if (of_get_property(np, "st,max-power-correction", NULL))
1170 pdata->max_power_correction = 1;
1171
1172 if (of_get_property(np, "st,am-reduction-mode", NULL))
1173 pdata->am_reduction_mode = 1;
1174
1175 if (of_get_property(np, "st,odd-pwm-speed-mode", NULL))
1176 pdata->odd_pwm_speed_mode = 1;
1177
1178 if (of_get_property(np, "st,distortion-compensation", NULL))
1179 pdata->distortion_compensation = 1;
1180
1181 /* CONFF */
1182 if (of_get_property(np, "st,invalid-input-detect-mute", NULL))
1183 pdata->invalid_input_detect_mute = 1;
1184
1185 /* MISC */
1186 if (of_get_property(np, "st,activate-mute-output", NULL))
1187 pdata->activate_mute_output = 1;
1188
1189 if (of_get_property(np, "st,bridge-immediate-off", NULL))
1190 pdata->bridge_immediate_off = 1;
1191
1192 if (of_get_property(np, "st,noise-shape-dc-cut", NULL))
1193 pdata->noise_shape_dc_cut = 1;
1194
1195 if (of_get_property(np, "st,powerdown-master-volume", NULL))
1196 pdata->powerdown_master_vol = 1;
1197
1198 if (!of_property_read_u8(np, "st,powerdown-delay-divider", &tmp8)) {
1199 if (is_power_of_2(tmp8) && tmp8 >= 1 && tmp8 <= 128)
1200 pdata->powerdown_delay_divider = ilog2(tmp8);
1201 else
1202 dev_warn(dev, "Unsupported powerdown delay divider %d\n",
1203 tmp8);
1204 }
1205
1206 sta350->pdata = pdata;
1207
1208 return 0;
1209}
1210#endif
1211
1212static int sta350_i2c_probe(struct i2c_client *i2c,
1213 const struct i2c_device_id *id)
1214{
1215 struct device *dev = &i2c->dev;
1216 struct sta350_priv *sta350;
1217 int ret, i;
1218
1219 sta350 = devm_kzalloc(dev, sizeof(struct sta350_priv), GFP_KERNEL);
1220 if (!sta350)
1221 return -ENOMEM;
1222
1223 mutex_init(&sta350->coeff_lock);
1224 sta350->pdata = dev_get_platdata(dev);
1225
1226#ifdef CONFIG_OF
1227 if (dev->of_node) {
1228 ret = sta350_probe_dt(dev, sta350);
1229 if (ret < 0)
1230 return ret;
1231 }
1232#endif
1233
1234 /* GPIOs */
1235 sta350->gpiod_nreset = devm_gpiod_get(dev, "reset");
1236 if (IS_ERR(sta350->gpiod_nreset)) {
1237 ret = PTR_ERR(sta350->gpiod_nreset);
1238 if (ret != -ENOENT && ret != -ENOSYS)
1239 return ret;
1240
1241 sta350->gpiod_nreset = NULL;
1242 } else {
1243 gpiod_direction_output(sta350->gpiod_nreset, 0);
1244 }
1245
1246 sta350->gpiod_power_down = devm_gpiod_get(dev, "power-down");
1247 if (IS_ERR(sta350->gpiod_power_down)) {
1248 ret = PTR_ERR(sta350->gpiod_power_down);
1249 if (ret != -ENOENT && ret != -ENOSYS)
1250 return ret;
1251
1252 sta350->gpiod_power_down = NULL;
1253 } else {
1254 gpiod_direction_output(sta350->gpiod_power_down, 0);
1255 }
1256
1257 /* regulators */
1258 for (i = 0; i < ARRAY_SIZE(sta350->supplies); i++)
1259 sta350->supplies[i].supply = sta350_supply_names[i];
1260
1261 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(sta350->supplies),
1262 sta350->supplies);
1263 if (ret < 0) {
1264 dev_err(dev, "Failed to request supplies: %d\n", ret);
1265 return ret;
1266 }
1267
1268 sta350->regmap = devm_regmap_init_i2c(i2c, &sta350_regmap);
1269 if (IS_ERR(sta350->regmap)) {
1270 ret = PTR_ERR(sta350->regmap);
1271 dev_err(dev, "Failed to init regmap: %d\n", ret);
1272 return ret;
1273 }
1274
1275 i2c_set_clientdata(i2c, sta350);
1276
1277 ret = snd_soc_register_codec(dev, &sta350_codec, &sta350_dai, 1);
1278 if (ret < 0)
1279 dev_err(dev, "Failed to register codec (%d)\n", ret);
1280
1281 return ret;
1282}
1283
1284static int sta350_i2c_remove(struct i2c_client *client)
1285{
1286 snd_soc_unregister_codec(&client->dev);
1287 return 0;
1288}
1289
1290static const struct i2c_device_id sta350_i2c_id[] = {
1291 { "sta350", 0 },
1292 { }
1293};
1294MODULE_DEVICE_TABLE(i2c, sta350_i2c_id);
1295
1296static struct i2c_driver sta350_i2c_driver = {
1297 .driver = {
1298 .name = "sta350",
1299 .owner = THIS_MODULE,
1300 .of_match_table = of_match_ptr(st350_dt_ids),
1301 },
1302 .probe = sta350_i2c_probe,
1303 .remove = sta350_i2c_remove,
1304 .id_table = sta350_i2c_id,
1305};
1306
1307module_i2c_driver(sta350_i2c_driver);
1308
1309MODULE_DESCRIPTION("ASoC STA350 driver");
1310MODULE_AUTHOR("Sven Brandau <info@brandau.biz>");
1311MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/sta350.h b/sound/soc/codecs/sta350.h
new file mode 100644
index 000000000000..fb7285290779
--- /dev/null
+++ b/sound/soc/codecs/sta350.h
@@ -0,0 +1,238 @@
1/*
2 * Codec driver for ST STA350 2.1-channel high-efficiency digital audio system
3 *
4 * Copyright: 2011 Raumfeld GmbH
5 * Author: Sven Brandau <info@brandau.biz>
6 *
7 * based on code from:
8 * Raumfeld GmbH
9 * Johannes Stezenbach <js@sig21.net>
10 * Wolfson Microelectronics PLC.
11 * Mark Brown <broonie@opensource.wolfsonmicro.com>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18#ifndef _ASOC_STA_350_H
19#define _ASOC_STA_350_H
20
21/* STA50 register addresses */
22
23#define STA350_REGISTER_COUNT 0x4D
24#define STA350_COEF_COUNT 62
25
26#define STA350_CONFA 0x00
27#define STA350_CONFB 0x01
28#define STA350_CONFC 0x02
29#define STA350_CONFD 0x03
30#define STA350_CONFE 0x04
31#define STA350_CONFF 0x05
32#define STA350_MMUTE 0x06
33#define STA350_MVOL 0x07
34#define STA350_C1VOL 0x08
35#define STA350_C2VOL 0x09
36#define STA350_C3VOL 0x0a
37#define STA350_AUTO1 0x0b
38#define STA350_AUTO2 0x0c
39#define STA350_AUTO3 0x0d
40#define STA350_C1CFG 0x0e
41#define STA350_C2CFG 0x0f
42#define STA350_C3CFG 0x10
43#define STA350_TONE 0x11
44#define STA350_L1AR 0x12
45#define STA350_L1ATRT 0x13
46#define STA350_L2AR 0x14
47#define STA350_L2ATRT 0x15
48#define STA350_CFADDR2 0x16
49#define STA350_B1CF1 0x17
50#define STA350_B1CF2 0x18
51#define STA350_B1CF3 0x19
52#define STA350_B2CF1 0x1a
53#define STA350_B2CF2 0x1b
54#define STA350_B2CF3 0x1c
55#define STA350_A1CF1 0x1d
56#define STA350_A1CF2 0x1e
57#define STA350_A1CF3 0x1f
58#define STA350_A2CF1 0x20
59#define STA350_A2CF2 0x21
60#define STA350_A2CF3 0x22
61#define STA350_B0CF1 0x23
62#define STA350_B0CF2 0x24
63#define STA350_B0CF3 0x25
64#define STA350_CFUD 0x26
65#define STA350_MPCC1 0x27
66#define STA350_MPCC2 0x28
67#define STA350_DCC1 0x29
68#define STA350_DCC2 0x2a
69#define STA350_FDRC1 0x2b
70#define STA350_FDRC2 0x2c
71#define STA350_STATUS 0x2d
72/* reserved: 0x2d - 0x30 */
73#define STA350_EQCFG 0x31
74#define STA350_EATH1 0x32
75#define STA350_ERTH1 0x33
76#define STA350_EATH2 0x34
77#define STA350_ERTH2 0x35
78#define STA350_CONFX 0x36
79#define STA350_SVCA 0x37
80#define STA350_SVCB 0x38
81#define STA350_RMS0A 0x39
82#define STA350_RMS0B 0x3a
83#define STA350_RMS0C 0x3b
84#define STA350_RMS1A 0x3c
85#define STA350_RMS1B 0x3d
86#define STA350_RMS1C 0x3e
87#define STA350_EVOLRES 0x3f
88/* reserved: 0x40 - 0x47 */
89#define STA350_NSHAPE 0x48
90#define STA350_CTXB4B1 0x49
91#define STA350_CTXB7B5 0x4a
92#define STA350_MISC1 0x4b
93#define STA350_MISC2 0x4c
94
95/* 0x00 CONFA */
96#define STA350_CONFA_MCS_MASK 0x03
97#define STA350_CONFA_MCS_SHIFT 0
98#define STA350_CONFA_IR_MASK 0x18
99#define STA350_CONFA_IR_SHIFT 3
100#define STA350_CONFA_TWRB BIT(5)
101#define STA350_CONFA_TWAB BIT(6)
102#define STA350_CONFA_FDRB BIT(7)
103
104/* 0x01 CONFB */
105#define STA350_CONFB_SAI_MASK 0x0f
106#define STA350_CONFB_SAI_SHIFT 0
107#define STA350_CONFB_SAIFB BIT(4)
108#define STA350_CONFB_DSCKE BIT(5)
109#define STA350_CONFB_C1IM BIT(6)
110#define STA350_CONFB_C2IM BIT(7)
111
112/* 0x02 CONFC */
113#define STA350_CONFC_OM_MASK 0x03
114#define STA350_CONFC_OM_SHIFT 0
115#define STA350_CONFC_CSZ_MASK 0x3c
116#define STA350_CONFC_CSZ_SHIFT 2
117#define STA350_CONFC_OCRB BIT(7)
118
119/* 0x03 CONFD */
120#define STA350_CONFD_HPB_SHIFT 0
121#define STA350_CONFD_DEMP_SHIFT 1
122#define STA350_CONFD_DSPB_SHIFT 2
123#define STA350_CONFD_PSL_SHIFT 3
124#define STA350_CONFD_BQL_SHIFT 4
125#define STA350_CONFD_DRC_SHIFT 5
126#define STA350_CONFD_ZDE_SHIFT 6
127#define STA350_CONFD_SME_SHIFT 7
128
129/* 0x04 CONFE */
130#define STA350_CONFE_MPCV BIT(0)
131#define STA350_CONFE_MPCV_SHIFT 0
132#define STA350_CONFE_MPC BIT(1)
133#define STA350_CONFE_MPC_SHIFT 1
134#define STA350_CONFE_NSBW BIT(2)
135#define STA350_CONFE_NSBW_SHIFT 2
136#define STA350_CONFE_AME BIT(3)
137#define STA350_CONFE_AME_SHIFT 3
138#define STA350_CONFE_PWMS BIT(4)
139#define STA350_CONFE_PWMS_SHIFT 4
140#define STA350_CONFE_DCCV BIT(5)
141#define STA350_CONFE_DCCV_SHIFT 5
142#define STA350_CONFE_ZCE BIT(6)
143#define STA350_CONFE_ZCE_SHIFT 6
144#define STA350_CONFE_SVE BIT(7)
145#define STA350_CONFE_SVE_SHIFT 7
146
147/* 0x05 CONFF */
148#define STA350_CONFF_OCFG_MASK 0x03
149#define STA350_CONFF_OCFG_SHIFT 0
150#define STA350_CONFF_IDE BIT(2)
151#define STA350_CONFF_BCLE BIT(3)
152#define STA350_CONFF_LDTE BIT(4)
153#define STA350_CONFF_ECLE BIT(5)
154#define STA350_CONFF_PWDN BIT(6)
155#define STA350_CONFF_EAPD BIT(7)
156
157/* 0x06 MMUTE */
158#define STA350_MMUTE_MMUTE 0x01
159#define STA350_MMUTE_MMUTE_SHIFT 0
160#define STA350_MMUTE_C1M 0x02
161#define STA350_MMUTE_C1M_SHIFT 1
162#define STA350_MMUTE_C2M 0x04
163#define STA350_MMUTE_C2M_SHIFT 2
164#define STA350_MMUTE_C3M 0x08
165#define STA350_MMUTE_C3M_SHIFT 3
166#define STA350_MMUTE_LOC_MASK 0xC0
167#define STA350_MMUTE_LOC_SHIFT 6
168
169/* 0x0b AUTO1 */
170#define STA350_AUTO1_AMGC_MASK 0x30
171#define STA350_AUTO1_AMGC_SHIFT 4
172
173/* 0x0c AUTO2 */
174#define STA350_AUTO2_AMAME 0x01
175#define STA350_AUTO2_AMAM_MASK 0x0e
176#define STA350_AUTO2_AMAM_SHIFT 1
177#define STA350_AUTO2_XO_MASK 0xf0
178#define STA350_AUTO2_XO_SHIFT 4
179
180/* 0x0d AUTO3 */
181#define STA350_AUTO3_PEQ_MASK 0x1f
182#define STA350_AUTO3_PEQ_SHIFT 0
183
184/* 0x0e 0x0f 0x10 CxCFG */
185#define STA350_CxCFG_TCB_SHIFT 0
186#define STA350_CxCFG_EQBP_SHIFT 1
187#define STA350_CxCFG_VBP_SHIFT 2
188#define STA350_CxCFG_BO_SHIFT 3
189#define STA350_CxCFG_LS_SHIFT 4
190#define STA350_CxCFG_OM_MASK 0xc0
191#define STA350_CxCFG_OM_SHIFT 6
192
193/* 0x11 TONE */
194#define STA350_TONE_BTC_SHIFT 0
195#define STA350_TONE_TTC_SHIFT 4
196
197/* 0x12 0x13 0x14 0x15 limiter attack/release */
198#define STA350_LxA_SHIFT 0
199#define STA350_LxR_SHIFT 4
200
201/* 0x26 CFUD */
202#define STA350_CFUD_W1 0x01
203#define STA350_CFUD_WA 0x02
204#define STA350_CFUD_R1 0x04
205#define STA350_CFUD_RA 0x08
206
207
208/* biquad filter coefficient table offsets */
209#define STA350_C1_BQ_BASE 0
210#define STA350_C2_BQ_BASE 20
211#define STA350_CH_BQ_NUM 4
212#define STA350_BQ_NUM_COEF 5
213#define STA350_XO_HP_BQ_BASE 40
214#define STA350_XO_LP_BQ_BASE 45
215#define STA350_C1_PRESCALE 50
216#define STA350_C2_PRESCALE 51
217#define STA350_C1_POSTSCALE 52
218#define STA350_C2_POSTSCALE 53
219#define STA350_C3_POSTSCALE 54
220#define STA350_TW_POSTSCALE 55
221#define STA350_C1_MIX1 56
222#define STA350_C1_MIX2 57
223#define STA350_C2_MIX1 58
224#define STA350_C2_MIX2 59
225#define STA350_C3_MIX1 60
226#define STA350_C3_MIX2 61
227
228/* miscellaneous register 1 */
229#define STA350_MISC1_CPWMEN BIT(2)
230#define STA350_MISC1_BRIDGOFF BIT(5)
231#define STA350_MISC1_NSHHPEN BIT(6)
232#define STA350_MISC1_RPDNEN BIT(7)
233
234/* miscellaneous register 2 */
235#define STA350_MISC2_PNDLSL_MASK 0x1c
236#define STA350_MISC2_PNDLSL_SHIFT 2
237
238#endif /* _ASOC_STA_350_H */
diff --git a/sound/soc/codecs/tas5086.c b/sound/soc/codecs/tas5086.c
index a895a5e4bdf2..d48491a4a19d 100644
--- a/sound/soc/codecs/tas5086.c
+++ b/sound/soc/codecs/tas5086.c
@@ -272,7 +272,7 @@ static int tas5086_set_deemph(struct snd_soc_codec *codec)
272static int tas5086_get_deemph(struct snd_kcontrol *kcontrol, 272static int tas5086_get_deemph(struct snd_kcontrol *kcontrol,
273 struct snd_ctl_elem_value *ucontrol) 273 struct snd_ctl_elem_value *ucontrol)
274{ 274{
275 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 275 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
276 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); 276 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
277 277
278 ucontrol->value.enumerated.item[0] = priv->deemph; 278 ucontrol->value.enumerated.item[0] = priv->deemph;
@@ -283,7 +283,7 @@ static int tas5086_get_deemph(struct snd_kcontrol *kcontrol,
283static int tas5086_put_deemph(struct snd_kcontrol *kcontrol, 283static int tas5086_put_deemph(struct snd_kcontrol *kcontrol,
284 struct snd_ctl_elem_value *ucontrol) 284 struct snd_ctl_elem_value *ucontrol)
285{ 285{
286 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 286 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
287 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); 287 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
288 288
289 priv->deemph = ucontrol->value.enumerated.item[0]; 289 priv->deemph = ucontrol->value.enumerated.item[0];
diff --git a/sound/soc/codecs/tlv320aic23-i2c.c b/sound/soc/codecs/tlv320aic23-i2c.c
index b73c94ebcc2a..f13701995482 100644
--- a/sound/soc/codecs/tlv320aic23-i2c.c
+++ b/sound/soc/codecs/tlv320aic23-i2c.c
@@ -13,6 +13,7 @@
13 13
14#include <linux/i2c.h> 14#include <linux/i2c.h>
15#include <linux/module.h> 15#include <linux/module.h>
16#include <linux/of.h>
16#include <linux/regmap.h> 17#include <linux/regmap.h>
17#include <sound/soc.h> 18#include <sound/soc.h>
18 19
diff --git a/sound/soc/codecs/tlv320aic23.c b/sound/soc/codecs/tlv320aic23.c
index 20864ee8793b..686b8b85b956 100644
--- a/sound/soc/codecs/tlv320aic23.c
+++ b/sound/soc/codecs/tlv320aic23.c
@@ -82,7 +82,7 @@ static const DECLARE_TLV_DB_SCALE(sidetone_vol_tlv, -1800, 300, 0);
82static int snd_soc_tlv320aic23_put_volsw(struct snd_kcontrol *kcontrol, 82static int snd_soc_tlv320aic23_put_volsw(struct snd_kcontrol *kcontrol,
83 struct snd_ctl_elem_value *ucontrol) 83 struct snd_ctl_elem_value *ucontrol)
84{ 84{
85 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 85 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
86 u16 val, reg; 86 u16 val, reg;
87 87
88 val = (ucontrol->value.integer.value[0] & 0x07); 88 val = (ucontrol->value.integer.value[0] & 0x07);
@@ -105,7 +105,7 @@ static int snd_soc_tlv320aic23_put_volsw(struct snd_kcontrol *kcontrol,
105static int snd_soc_tlv320aic23_get_volsw(struct snd_kcontrol *kcontrol, 105static int snd_soc_tlv320aic23_get_volsw(struct snd_kcontrol *kcontrol,
106 struct snd_ctl_elem_value *ucontrol) 106 struct snd_ctl_elem_value *ucontrol)
107{ 107{
108 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 108 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
109 u16 val; 109 u16 val;
110 110
111 val = snd_soc_read(codec, TLV320AIC23_ANLG) & (0x1C0); 111 val = snd_soc_read(codec, TLV320AIC23_ANLG) & (0x1C0);
diff --git a/sound/soc/codecs/tlv320aic31xx.c b/sound/soc/codecs/tlv320aic31xx.c
index fa158cfe9b32..23419109ecac 100644
--- a/sound/soc/codecs/tlv320aic31xx.c
+++ b/sound/soc/codecs/tlv320aic31xx.c
@@ -28,6 +28,7 @@
28#include <linux/i2c.h> 28#include <linux/i2c.h>
29#include <linux/gpio.h> 29#include <linux/gpio.h>
30#include <linux/regulator/consumer.h> 30#include <linux/regulator/consumer.h>
31#include <linux/of.h>
31#include <linux/of_gpio.h> 32#include <linux/of_gpio.h>
32#include <linux/slab.h> 33#include <linux/slab.h>
33#include <sound/core.h> 34#include <sound/core.h>
@@ -376,7 +377,7 @@ static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w,
376 reg = AIC31XX_ADCFLAG; 377 reg = AIC31XX_ADCFLAG;
377 break; 378 break;
378 default: 379 default:
379 dev_err(w->codec->dev, "Unknown widget '%s' calling %s/n", 380 dev_err(w->codec->dev, "Unknown widget '%s' calling %s\n",
380 w->name, __func__); 381 w->name, __func__);
381 return -EINVAL; 382 return -EINVAL;
382 } 383 }
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
index b1835103e9b4..e12fafbb1e09 100644
--- a/sound/soc/codecs/tlv320aic3x.c
+++ b/sound/soc/codecs/tlv320aic3x.c
@@ -169,7 +169,7 @@ static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
169 mask <<= shift; 169 mask <<= shift;
170 val <<= shift; 170 val <<= shift;
171 171
172 change = snd_soc_test_bits(codec, val, mask, reg); 172 change = snd_soc_test_bits(codec, reg, mask, val);
173 if (change) { 173 if (change) {
174 update.kcontrol = kcontrol; 174 update.kcontrol = kcontrol;
175 update.reg = reg; 175 update.reg = reg;
@@ -1399,7 +1399,6 @@ static int aic3x_probe(struct snd_soc_codec *codec)
1399 } 1399 }
1400 1400
1401 aic3x_add_widgets(codec); 1401 aic3x_add_widgets(codec);
1402 list_add(&aic3x->list, &reset_list);
1403 1402
1404 return 0; 1403 return 0;
1405 1404
@@ -1569,7 +1568,13 @@ static int aic3x_i2c_probe(struct i2c_client *i2c,
1569 1568
1570 ret = snd_soc_register_codec(&i2c->dev, 1569 ret = snd_soc_register_codec(&i2c->dev,
1571 &soc_codec_dev_aic3x, &aic3x_dai, 1); 1570 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1572 return ret; 1571
1572 if (ret != 0)
1573 goto err_gpio;
1574
1575 list_add(&aic3x->list, &reset_list);
1576
1577 return 0;
1573 1578
1574err_gpio: 1579err_gpio:
1575 if (gpio_is_valid(aic3x->gpio_reset) && 1580 if (gpio_is_valid(aic3x->gpio_reset) &&
diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c
index 6bfc8a17331b..df3a7506c023 100644
--- a/sound/soc/codecs/tlv320dac33.c
+++ b/sound/soc/codecs/tlv320dac33.c
@@ -442,7 +442,7 @@ static int dac33_playback_event(struct snd_soc_dapm_widget *w,
442static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol, 442static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
443 struct snd_ctl_elem_value *ucontrol) 443 struct snd_ctl_elem_value *ucontrol)
444{ 444{
445 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 445 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
446 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 446 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
447 447
448 ucontrol->value.integer.value[0] = dac33->fifo_mode; 448 ucontrol->value.integer.value[0] = dac33->fifo_mode;
@@ -453,7 +453,7 @@ static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
453static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol, 453static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
454 struct snd_ctl_elem_value *ucontrol) 454 struct snd_ctl_elem_value *ucontrol)
455{ 455{
456 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 456 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
457 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 457 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
458 int ret = 0; 458 int ret = 0;
459 459
@@ -1540,7 +1540,7 @@ static int dac33_i2c_probe(struct i2c_client *client,
1540 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++) 1540 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1541 dac33->supplies[i].supply = dac33_supply_names[i]; 1541 dac33->supplies[i].supply = dac33_supply_names[i];
1542 1542
1543 ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies), 1543 ret = devm_regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
1544 dac33->supplies); 1544 dac33->supplies);
1545 1545
1546 if (ret != 0) { 1546 if (ret != 0) {
@@ -1551,11 +1551,9 @@ static int dac33_i2c_probe(struct i2c_client *client,
1551 ret = snd_soc_register_codec(&client->dev, 1551 ret = snd_soc_register_codec(&client->dev,
1552 &soc_codec_dev_tlv320dac33, &dac33_dai, 1); 1552 &soc_codec_dev_tlv320dac33, &dac33_dai, 1);
1553 if (ret < 0) 1553 if (ret < 0)
1554 goto err_register; 1554 goto err_get;
1555 1555
1556 return ret; 1556 return ret;
1557err_register:
1558 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1559err_get: 1557err_get:
1560 if (dac33->power_gpio >= 0) 1558 if (dac33->power_gpio >= 0)
1561 gpio_free(dac33->power_gpio); 1559 gpio_free(dac33->power_gpio);
@@ -1573,8 +1571,6 @@ static int dac33_i2c_remove(struct i2c_client *client)
1573 if (dac33->power_gpio >= 0) 1571 if (dac33->power_gpio >= 0)
1574 gpio_free(dac33->power_gpio); 1572 gpio_free(dac33->power_gpio);
1575 1573
1576 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1577
1578 snd_soc_unregister_codec(&client->dev); 1574 snd_soc_unregister_codec(&client->dev);
1579 return 0; 1575 return 0;
1580} 1576}
diff --git a/sound/soc/codecs/tpa6130a2.c b/sound/soc/codecs/tpa6130a2.c
index b27c396037d4..8fc5a647453b 100644
--- a/sound/soc/codecs/tpa6130a2.c
+++ b/sound/soc/codecs/tpa6130a2.c
@@ -30,6 +30,7 @@
30#include <sound/tpa6130a2-plat.h> 30#include <sound/tpa6130a2-plat.h>
31#include <sound/soc.h> 31#include <sound/soc.h>
32#include <sound/tlv.h> 32#include <sound/tlv.h>
33#include <linux/of.h>
33#include <linux/of_gpio.h> 34#include <linux/of_gpio.h>
34 35
35#include "tpa6130a2.h" 36#include "tpa6130a2.h"
diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index 975e0f760ac1..69e12a311ba2 100644
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -830,7 +830,7 @@ static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
830{ 830{
831 struct soc_mixer_control *mc = 831 struct soc_mixer_control *mc =
832 (struct soc_mixer_control *)kcontrol->private_value; 832 (struct soc_mixer_control *)kcontrol->private_value;
833 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 833 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
834 unsigned int reg = mc->reg; 834 unsigned int reg = mc->reg;
835 unsigned int shift = mc->shift; 835 unsigned int shift = mc->shift;
836 unsigned int rshift = mc->rshift; 836 unsigned int rshift = mc->rshift;
@@ -859,7 +859,7 @@ static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
859{ 859{
860 struct soc_mixer_control *mc = 860 struct soc_mixer_control *mc =
861 (struct soc_mixer_control *)kcontrol->private_value; 861 (struct soc_mixer_control *)kcontrol->private_value;
862 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 862 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
863 unsigned int reg = mc->reg; 863 unsigned int reg = mc->reg;
864 unsigned int shift = mc->shift; 864 unsigned int shift = mc->shift;
865 unsigned int rshift = mc->rshift; 865 unsigned int rshift = mc->rshift;
@@ -888,7 +888,7 @@ static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
888{ 888{
889 struct soc_mixer_control *mc = 889 struct soc_mixer_control *mc =
890 (struct soc_mixer_control *)kcontrol->private_value; 890 (struct soc_mixer_control *)kcontrol->private_value;
891 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 891 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
892 unsigned int reg = mc->reg; 892 unsigned int reg = mc->reg;
893 unsigned int reg2 = mc->rreg; 893 unsigned int reg2 = mc->rreg;
894 unsigned int shift = mc->shift; 894 unsigned int shift = mc->shift;
@@ -915,7 +915,7 @@ static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
915{ 915{
916 struct soc_mixer_control *mc = 916 struct soc_mixer_control *mc =
917 (struct soc_mixer_control *)kcontrol->private_value; 917 (struct soc_mixer_control *)kcontrol->private_value;
918 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 918 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
919 unsigned int reg = mc->reg; 919 unsigned int reg = mc->reg;
920 unsigned int reg2 = mc->rreg; 920 unsigned int reg2 = mc->rreg;
921 unsigned int shift = mc->shift; 921 unsigned int shift = mc->shift;
@@ -956,7 +956,7 @@ static SOC_ENUM_SINGLE_DECL(twl4030_op_modes_enum,
956static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol, 956static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
957 struct snd_ctl_elem_value *ucontrol) 957 struct snd_ctl_elem_value *ucontrol)
958{ 958{
959 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 959 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
960 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); 960 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
961 961
962 if (twl4030->configured) { 962 if (twl4030->configured) {
diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c
index bd3a20647fdf..0f6067f04e29 100644
--- a/sound/soc/codecs/twl6040.c
+++ b/sound/soc/codecs/twl6040.c
@@ -484,7 +484,7 @@ static SOC_ENUM_SINGLE_EXT_DECL(twl6040_power_mode_enum,
484static int twl6040_headset_power_get_enum(struct snd_kcontrol *kcontrol, 484static int twl6040_headset_power_get_enum(struct snd_kcontrol *kcontrol,
485 struct snd_ctl_elem_value *ucontrol) 485 struct snd_ctl_elem_value *ucontrol)
486{ 486{
487 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 487 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
488 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); 488 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
489 489
490 ucontrol->value.enumerated.item[0] = priv->hs_power_mode; 490 ucontrol->value.enumerated.item[0] = priv->hs_power_mode;
@@ -495,7 +495,7 @@ static int twl6040_headset_power_get_enum(struct snd_kcontrol *kcontrol,
495static int twl6040_headset_power_put_enum(struct snd_kcontrol *kcontrol, 495static int twl6040_headset_power_put_enum(struct snd_kcontrol *kcontrol,
496 struct snd_ctl_elem_value *ucontrol) 496 struct snd_ctl_elem_value *ucontrol)
497{ 497{
498 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 498 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
499 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); 499 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
500 int high_perf = ucontrol->value.enumerated.item[0]; 500 int high_perf = ucontrol->value.enumerated.item[0];
501 int ret = 0; 501 int ret = 0;
@@ -512,7 +512,7 @@ static int twl6040_headset_power_put_enum(struct snd_kcontrol *kcontrol,
512static int twl6040_pll_get_enum(struct snd_kcontrol *kcontrol, 512static int twl6040_pll_get_enum(struct snd_kcontrol *kcontrol,
513 struct snd_ctl_elem_value *ucontrol) 513 struct snd_ctl_elem_value *ucontrol)
514{ 514{
515 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 515 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
516 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); 516 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
517 517
518 ucontrol->value.enumerated.item[0] = priv->pll_power_mode; 518 ucontrol->value.enumerated.item[0] = priv->pll_power_mode;
@@ -523,7 +523,7 @@ static int twl6040_pll_get_enum(struct snd_kcontrol *kcontrol,
523static int twl6040_pll_put_enum(struct snd_kcontrol *kcontrol, 523static int twl6040_pll_put_enum(struct snd_kcontrol *kcontrol,
524 struct snd_ctl_elem_value *ucontrol) 524 struct snd_ctl_elem_value *ucontrol)
525{ 525{
526 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 526 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
527 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); 527 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
528 528
529 priv->pll_power_mode = ucontrol->value.enumerated.item[0]; 529 priv->pll_power_mode = ucontrol->value.enumerated.item[0];
diff --git a/sound/soc/codecs/wl1273.c b/sound/soc/codecs/wl1273.c
index 6be5f80b65f1..4ead0dc02b87 100644
--- a/sound/soc/codecs/wl1273.c
+++ b/sound/soc/codecs/wl1273.c
@@ -172,7 +172,7 @@ out:
172static int snd_wl1273_get_audio_route(struct snd_kcontrol *kcontrol, 172static int snd_wl1273_get_audio_route(struct snd_kcontrol *kcontrol,
173 struct snd_ctl_elem_value *ucontrol) 173 struct snd_ctl_elem_value *ucontrol)
174{ 174{
175 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 175 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
176 struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec); 176 struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec);
177 177
178 ucontrol->value.integer.value[0] = wl1273->mode; 178 ucontrol->value.integer.value[0] = wl1273->mode;
@@ -190,7 +190,7 @@ static const char * const wl1273_audio_route[] = { "Bt", "FmRx", "FmTx" };
190static int snd_wl1273_set_audio_route(struct snd_kcontrol *kcontrol, 190static int snd_wl1273_set_audio_route(struct snd_kcontrol *kcontrol,
191 struct snd_ctl_elem_value *ucontrol) 191 struct snd_ctl_elem_value *ucontrol)
192{ 192{
193 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 193 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
194 struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec); 194 struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec);
195 195
196 if (wl1273->mode == ucontrol->value.integer.value[0]) 196 if (wl1273->mode == ucontrol->value.integer.value[0])
@@ -214,7 +214,7 @@ static SOC_ENUM_SINGLE_EXT_DECL(wl1273_enum, wl1273_audio_route);
214static int snd_wl1273_fm_audio_get(struct snd_kcontrol *kcontrol, 214static int snd_wl1273_fm_audio_get(struct snd_kcontrol *kcontrol,
215 struct snd_ctl_elem_value *ucontrol) 215 struct snd_ctl_elem_value *ucontrol)
216{ 216{
217 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 217 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
218 struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec); 218 struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec);
219 219
220 dev_dbg(codec->dev, "%s: enter.\n", __func__); 220 dev_dbg(codec->dev, "%s: enter.\n", __func__);
@@ -227,7 +227,7 @@ static int snd_wl1273_fm_audio_get(struct snd_kcontrol *kcontrol,
227static int snd_wl1273_fm_audio_put(struct snd_kcontrol *kcontrol, 227static int snd_wl1273_fm_audio_put(struct snd_kcontrol *kcontrol,
228 struct snd_ctl_elem_value *ucontrol) 228 struct snd_ctl_elem_value *ucontrol)
229{ 229{
230 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 230 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
231 struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec); 231 struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec);
232 int val, r = 0; 232 int val, r = 0;
233 233
@@ -251,7 +251,7 @@ static SOC_ENUM_SINGLE_EXT_DECL(wl1273_audio_enum, wl1273_audio_strings);
251static int snd_wl1273_fm_volume_get(struct snd_kcontrol *kcontrol, 251static int snd_wl1273_fm_volume_get(struct snd_kcontrol *kcontrol,
252 struct snd_ctl_elem_value *ucontrol) 252 struct snd_ctl_elem_value *ucontrol)
253{ 253{
254 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 254 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
255 struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec); 255 struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec);
256 256
257 dev_dbg(codec->dev, "%s: enter.\n", __func__); 257 dev_dbg(codec->dev, "%s: enter.\n", __func__);
@@ -264,7 +264,7 @@ static int snd_wl1273_fm_volume_get(struct snd_kcontrol *kcontrol,
264static int snd_wl1273_fm_volume_put(struct snd_kcontrol *kcontrol, 264static int snd_wl1273_fm_volume_put(struct snd_kcontrol *kcontrol,
265 struct snd_ctl_elem_value *ucontrol) 265 struct snd_ctl_elem_value *ucontrol)
266{ 266{
267 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 267 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
268 struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec); 268 struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec);
269 int r; 269 int r;
270 270
diff --git a/sound/soc/codecs/wm2000.c b/sound/soc/codecs/wm2000.c
index 83a2c872925c..a4c352cc3464 100644
--- a/sound/soc/codecs/wm2000.c
+++ b/sound/soc/codecs/wm2000.c
@@ -607,7 +607,7 @@ static int wm2000_anc_set_mode(struct wm2000_priv *wm2000)
607static int wm2000_anc_mode_get(struct snd_kcontrol *kcontrol, 607static int wm2000_anc_mode_get(struct snd_kcontrol *kcontrol,
608 struct snd_ctl_elem_value *ucontrol) 608 struct snd_ctl_elem_value *ucontrol)
609{ 609{
610 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 610 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
611 struct wm2000_priv *wm2000 = dev_get_drvdata(codec->dev); 611 struct wm2000_priv *wm2000 = dev_get_drvdata(codec->dev);
612 612
613 ucontrol->value.enumerated.item[0] = wm2000->anc_active; 613 ucontrol->value.enumerated.item[0] = wm2000->anc_active;
@@ -618,7 +618,7 @@ static int wm2000_anc_mode_get(struct snd_kcontrol *kcontrol,
618static int wm2000_anc_mode_put(struct snd_kcontrol *kcontrol, 618static int wm2000_anc_mode_put(struct snd_kcontrol *kcontrol,
619 struct snd_ctl_elem_value *ucontrol) 619 struct snd_ctl_elem_value *ucontrol)
620{ 620{
621 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 621 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
622 struct wm2000_priv *wm2000 = dev_get_drvdata(codec->dev); 622 struct wm2000_priv *wm2000 = dev_get_drvdata(codec->dev);
623 int anc_active = ucontrol->value.enumerated.item[0]; 623 int anc_active = ucontrol->value.enumerated.item[0];
624 int ret; 624 int ret;
@@ -640,7 +640,7 @@ static int wm2000_anc_mode_put(struct snd_kcontrol *kcontrol,
640static int wm2000_speaker_get(struct snd_kcontrol *kcontrol, 640static int wm2000_speaker_get(struct snd_kcontrol *kcontrol,
641 struct snd_ctl_elem_value *ucontrol) 641 struct snd_ctl_elem_value *ucontrol)
642{ 642{
643 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 643 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
644 struct wm2000_priv *wm2000 = dev_get_drvdata(codec->dev); 644 struct wm2000_priv *wm2000 = dev_get_drvdata(codec->dev);
645 645
646 ucontrol->value.enumerated.item[0] = wm2000->spk_ena; 646 ucontrol->value.enumerated.item[0] = wm2000->spk_ena;
@@ -651,7 +651,7 @@ static int wm2000_speaker_get(struct snd_kcontrol *kcontrol,
651static int wm2000_speaker_put(struct snd_kcontrol *kcontrol, 651static int wm2000_speaker_put(struct snd_kcontrol *kcontrol,
652 struct snd_ctl_elem_value *ucontrol) 652 struct snd_ctl_elem_value *ucontrol)
653{ 653{
654 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 654 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
655 struct wm2000_priv *wm2000 = dev_get_drvdata(codec->dev); 655 struct wm2000_priv *wm2000 = dev_get_drvdata(codec->dev);
656 int val = ucontrol->value.enumerated.item[0]; 656 int val = ucontrol->value.enumerated.item[0];
657 int ret; 657 int ret;
diff --git a/sound/soc/codecs/wm2200.c b/sound/soc/codecs/wm2200.c
index 2e721e06671b..cdea9d9c1631 100644
--- a/sound/soc/codecs/wm2200.c
+++ b/sound/soc/codecs/wm2200.c
@@ -1083,7 +1083,7 @@ static int wm2200_mixer_values[] = {
1083 1083
1084#define WM2200_MUX_CTL_DECL(name) \ 1084#define WM2200_MUX_CTL_DECL(name) \
1085 const struct snd_kcontrol_new name##_mux = \ 1085 const struct snd_kcontrol_new name##_mux = \
1086 SOC_DAPM_VALUE_ENUM("Route", name##_enum) 1086 SOC_DAPM_ENUM("Route", name##_enum)
1087 1087
1088#define WM2200_MIXER_ENUMS(name, base_reg) \ 1088#define WM2200_MIXER_ENUMS(name, base_reg) \
1089 static WM2200_MUX_ENUM_DECL(name##_in1_enum, base_reg); \ 1089 static WM2200_MUX_ENUM_DECL(name##_in1_enum, base_reg); \
@@ -1207,7 +1207,7 @@ WM2200_MIXER_ENUMS(LHPF1, WM2200_LHPF1MIX_INPUT_1_SOURCE);
1207WM2200_MIXER_ENUMS(LHPF2, WM2200_LHPF2MIX_INPUT_1_SOURCE); 1207WM2200_MIXER_ENUMS(LHPF2, WM2200_LHPF2MIX_INPUT_1_SOURCE);
1208 1208
1209#define WM2200_MUX(name, ctrl) \ 1209#define WM2200_MUX(name, ctrl) \
1210 SND_SOC_DAPM_VALUE_MUX(name, SND_SOC_NOPM, 0, 0, ctrl) 1210 SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
1211 1211
1212#define WM2200_MIXER_WIDGETS(name, name_str) \ 1212#define WM2200_MIXER_WIDGETS(name, name_str) \
1213 WM2200_MUX(name_str " Input 1", &name##_in1_mux), \ 1213 WM2200_MUX(name_str " Input 1", &name##_in1_mux), \
diff --git a/sound/soc/codecs/wm5100.c b/sound/soc/codecs/wm5100.c
index eca983fad891..91a9ea2a2056 100644
--- a/sound/soc/codecs/wm5100.c
+++ b/sound/soc/codecs/wm5100.c
@@ -390,7 +390,7 @@ static int wm5100_mixer_values[] = {
390 390
391#define WM5100_MUX_CTL_DECL(name) \ 391#define WM5100_MUX_CTL_DECL(name) \
392 const struct snd_kcontrol_new name##_mux = \ 392 const struct snd_kcontrol_new name##_mux = \
393 SOC_DAPM_VALUE_ENUM("Route", name##_enum) 393 SOC_DAPM_ENUM("Route", name##_enum)
394 394
395#define WM5100_MIXER_ENUMS(name, base_reg) \ 395#define WM5100_MIXER_ENUMS(name, base_reg) \
396 static WM5100_MUX_ENUM_DECL(name##_in1_enum, base_reg); \ 396 static WM5100_MUX_ENUM_DECL(name##_in1_enum, base_reg); \
@@ -448,7 +448,7 @@ WM5100_MIXER_ENUMS(LHPF3, WM5100_HPLP3MIX_INPUT_1_SOURCE);
448WM5100_MIXER_ENUMS(LHPF4, WM5100_HPLP4MIX_INPUT_1_SOURCE); 448WM5100_MIXER_ENUMS(LHPF4, WM5100_HPLP4MIX_INPUT_1_SOURCE);
449 449
450#define WM5100_MUX(name, ctrl) \ 450#define WM5100_MUX(name, ctrl) \
451 SND_SOC_DAPM_VALUE_MUX(name, SND_SOC_NOPM, 0, 0, ctrl) 451 SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
452 452
453#define WM5100_MIXER_WIDGETS(name, name_str) \ 453#define WM5100_MIXER_WIDGETS(name, name_str) \
454 WM5100_MUX(name_str " Input 1", &name##_in1_mux), \ 454 WM5100_MUX(name_str " Input 1", &name##_in1_mux), \
diff --git a/sound/soc/codecs/wm5102.c b/sound/soc/codecs/wm5102.c
index dcf1d12cfef8..289b64d89abd 100644
--- a/sound/soc/codecs/wm5102.c
+++ b/sound/soc/codecs/wm5102.c
@@ -764,8 +764,8 @@ SOC_ENUM("LHPF2 Mode", arizona_lhpf2_mode),
764SOC_ENUM("LHPF3 Mode", arizona_lhpf3_mode), 764SOC_ENUM("LHPF3 Mode", arizona_lhpf3_mode),
765SOC_ENUM("LHPF4 Mode", arizona_lhpf4_mode), 765SOC_ENUM("LHPF4 Mode", arizona_lhpf4_mode),
766 766
767SOC_VALUE_ENUM("ISRC1 FSL", arizona_isrc_fsl[0]), 767SOC_ENUM("ISRC1 FSL", arizona_isrc_fsl[0]),
768SOC_VALUE_ENUM("ISRC2 FSL", arizona_isrc_fsl[1]), 768SOC_ENUM("ISRC2 FSL", arizona_isrc_fsl[1]),
769 769
770ARIZONA_MIXER_CONTROLS("Mic", ARIZONA_MICMIX_INPUT_1_SOURCE), 770ARIZONA_MIXER_CONTROLS("Mic", ARIZONA_MICMIX_INPUT_1_SOURCE),
771ARIZONA_MIXER_CONTROLS("Noise", ARIZONA_NOISEMIX_INPUT_1_SOURCE), 771ARIZONA_MIXER_CONTROLS("Noise", ARIZONA_NOISEMIX_INPUT_1_SOURCE),
@@ -814,9 +814,9 @@ SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_5L,
814 ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_VOL_SHIFT, 814 ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_VOL_SHIFT,
815 0xbf, 0, digital_tlv), 815 0xbf, 0, digital_tlv),
816 816
817SOC_VALUE_ENUM("HPOUT1 OSR", wm5102_hpout_osr[0]), 817SOC_ENUM("HPOUT1 OSR", wm5102_hpout_osr[0]),
818SOC_VALUE_ENUM("HPOUT2 OSR", wm5102_hpout_osr[1]), 818SOC_ENUM("HPOUT2 OSR", wm5102_hpout_osr[1]),
819SOC_VALUE_ENUM("EPOUT OSR", wm5102_hpout_osr[2]), 819SOC_ENUM("EPOUT OSR", wm5102_hpout_osr[2]),
820 820
821SOC_DOUBLE("HPOUT1 DRE Switch", ARIZONA_DRE_ENABLE, 821SOC_DOUBLE("HPOUT1 DRE Switch", ARIZONA_DRE_ENABLE,
822 ARIZONA_DRE1L_ENA_SHIFT, ARIZONA_DRE1R_ENA_SHIFT, 1, 0), 822 ARIZONA_DRE1L_ENA_SHIFT, ARIZONA_DRE1R_ENA_SHIFT, 1, 0),
@@ -970,7 +970,7 @@ static const struct soc_enum wm5102_aec_loopback =
970 wm5102_aec_loopback_values); 970 wm5102_aec_loopback_values);
971 971
972static const struct snd_kcontrol_new wm5102_aec_loopback_mux = 972static const struct snd_kcontrol_new wm5102_aec_loopback_mux =
973 SOC_DAPM_VALUE_ENUM("AEC Loopback", wm5102_aec_loopback); 973 SOC_DAPM_ENUM("AEC Loopback", wm5102_aec_loopback);
974 974
975static const struct snd_soc_dapm_widget wm5102_dapm_widgets[] = { 975static const struct snd_soc_dapm_widget wm5102_dapm_widgets[] = {
976SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1, ARIZONA_SYSCLK_ENA_SHIFT, 976SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1, ARIZONA_SYSCLK_ENA_SHIFT,
@@ -1204,7 +1204,7 @@ SND_SOC_DAPM_AIF_IN("SLIMRX8", NULL, 0,
1204 1204
1205ARIZONA_DSP_WIDGETS(DSP1, "DSP1"), 1205ARIZONA_DSP_WIDGETS(DSP1, "DSP1"),
1206 1206
1207SND_SOC_DAPM_VALUE_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1, 1207SND_SOC_DAPM_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1,
1208 ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0, 1208 ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0,
1209 &wm5102_aec_loopback_mux), 1209 &wm5102_aec_loopback_mux),
1210 1210
@@ -1760,10 +1760,6 @@ static int wm5102_codec_probe(struct snd_soc_codec *codec)
1760 struct wm5102_priv *priv = snd_soc_codec_get_drvdata(codec); 1760 struct wm5102_priv *priv = snd_soc_codec_get_drvdata(codec);
1761 int ret; 1761 int ret;
1762 1762
1763 ret = snd_soc_codec_set_cache_io(codec, priv->core.arizona->regmap);
1764 if (ret != 0)
1765 return ret;
1766
1767 ret = snd_soc_add_codec_controls(codec, wm_adsp2_fw_controls, 2); 1763 ret = snd_soc_add_codec_controls(codec, wm_adsp2_fw_controls, 2);
1768 if (ret != 0) 1764 if (ret != 0)
1769 return ret; 1765 return ret;
@@ -1802,9 +1798,17 @@ static unsigned int wm5102_digital_vu[] = {
1802 ARIZONA_DAC_DIGITAL_VOLUME_5R, 1798 ARIZONA_DAC_DIGITAL_VOLUME_5R,
1803}; 1799};
1804 1800
1801static struct regmap *wm5102_get_regmap(struct device *dev)
1802{
1803 struct wm5102_priv *priv = dev_get_drvdata(dev);
1804
1805 return priv->core.arizona->regmap;
1806}
1807
1805static struct snd_soc_codec_driver soc_codec_dev_wm5102 = { 1808static struct snd_soc_codec_driver soc_codec_dev_wm5102 = {
1806 .probe = wm5102_codec_probe, 1809 .probe = wm5102_codec_probe,
1807 .remove = wm5102_codec_remove, 1810 .remove = wm5102_codec_remove,
1811 .get_regmap = wm5102_get_regmap,
1808 1812
1809 .idle_bias_off = true, 1813 .idle_bias_off = true,
1810 1814
diff --git a/sound/soc/codecs/wm5110.c b/sound/soc/codecs/wm5110.c
index df5a38dd8328..2e5fcb559e90 100644
--- a/sound/soc/codecs/wm5110.c
+++ b/sound/soc/codecs/wm5110.c
@@ -324,13 +324,13 @@ SOC_ENUM("LHPF2 Mode", arizona_lhpf2_mode),
324SOC_ENUM("LHPF3 Mode", arizona_lhpf3_mode), 324SOC_ENUM("LHPF3 Mode", arizona_lhpf3_mode),
325SOC_ENUM("LHPF4 Mode", arizona_lhpf4_mode), 325SOC_ENUM("LHPF4 Mode", arizona_lhpf4_mode),
326 326
327SOC_VALUE_ENUM("ISRC1 FSL", arizona_isrc_fsl[0]), 327SOC_ENUM("ISRC1 FSL", arizona_isrc_fsl[0]),
328SOC_VALUE_ENUM("ISRC2 FSL", arizona_isrc_fsl[1]), 328SOC_ENUM("ISRC2 FSL", arizona_isrc_fsl[1]),
329SOC_VALUE_ENUM("ISRC3 FSL", arizona_isrc_fsl[2]), 329SOC_ENUM("ISRC3 FSL", arizona_isrc_fsl[2]),
330SOC_VALUE_ENUM("ISRC1 FSH", arizona_isrc_fsh[0]), 330SOC_ENUM("ISRC1 FSH", arizona_isrc_fsh[0]),
331SOC_VALUE_ENUM("ISRC2 FSH", arizona_isrc_fsh[1]), 331SOC_ENUM("ISRC2 FSH", arizona_isrc_fsh[1]),
332SOC_VALUE_ENUM("ISRC3 FSH", arizona_isrc_fsh[2]), 332SOC_ENUM("ISRC3 FSH", arizona_isrc_fsh[2]),
333SOC_VALUE_ENUM("ASRC RATE 1", arizona_asrc_rate1), 333SOC_ENUM("ASRC RATE 1", arizona_asrc_rate1),
334 334
335ARIZONA_MIXER_CONTROLS("DSP1L", ARIZONA_DSP1LMIX_INPUT_1_SOURCE), 335ARIZONA_MIXER_CONTROLS("DSP1L", ARIZONA_DSP1LMIX_INPUT_1_SOURCE),
336ARIZONA_MIXER_CONTROLS("DSP1R", ARIZONA_DSP1RMIX_INPUT_1_SOURCE), 336ARIZONA_MIXER_CONTROLS("DSP1R", ARIZONA_DSP1RMIX_INPUT_1_SOURCE),
@@ -367,6 +367,11 @@ SOC_SINGLE("HPOUT2 SC Protect Switch", ARIZONA_HP2_SHORT_CIRCUIT_CTRL,
367SOC_SINGLE("HPOUT3 SC Protect Switch", ARIZONA_HP3_SHORT_CIRCUIT_CTRL, 367SOC_SINGLE("HPOUT3 SC Protect Switch", ARIZONA_HP3_SHORT_CIRCUIT_CTRL,
368 ARIZONA_HP3_SC_ENA_SHIFT, 1, 0), 368 ARIZONA_HP3_SC_ENA_SHIFT, 1, 0),
369 369
370SOC_SINGLE("SPKDAT1 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_5L,
371 ARIZONA_OUT5_OSR_SHIFT, 1, 0),
372SOC_SINGLE("SPKDAT2 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_6L,
373 ARIZONA_OUT6_OSR_SHIFT, 1, 0),
374
370SOC_DOUBLE_R("HPOUT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_1L, 375SOC_DOUBLE_R("HPOUT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_1L,
371 ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_MUTE_SHIFT, 1, 1), 376 ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_MUTE_SHIFT, 1, 1),
372SOC_DOUBLE_R("HPOUT2 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_2L, 377SOC_DOUBLE_R("HPOUT2 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_2L,
@@ -592,7 +597,7 @@ static const struct soc_enum wm5110_aec_loopback =
592 wm5110_aec_loopback_values); 597 wm5110_aec_loopback_values);
593 598
594static const struct snd_kcontrol_new wm5110_aec_loopback_mux = 599static const struct snd_kcontrol_new wm5110_aec_loopback_mux =
595 SOC_DAPM_VALUE_ENUM("AEC Loopback", wm5110_aec_loopback); 600 SOC_DAPM_ENUM("AEC Loopback", wm5110_aec_loopback);
596 601
597static const struct snd_soc_dapm_widget wm5110_dapm_widgets[] = { 602static const struct snd_soc_dapm_widget wm5110_dapm_widgets[] = {
598SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1, ARIZONA_SYSCLK_ENA_SHIFT, 603SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1, ARIZONA_SYSCLK_ENA_SHIFT,
@@ -774,7 +779,7 @@ SND_SOC_DAPM_PGA("ISRC3DEC3", ARIZONA_ISRC_3_CTRL_3,
774SND_SOC_DAPM_PGA("ISRC3DEC4", ARIZONA_ISRC_3_CTRL_3, 779SND_SOC_DAPM_PGA("ISRC3DEC4", ARIZONA_ISRC_3_CTRL_3,
775 ARIZONA_ISRC3_DEC3_ENA_SHIFT, 0, NULL, 0), 780 ARIZONA_ISRC3_DEC3_ENA_SHIFT, 0, NULL, 0),
776 781
777SND_SOC_DAPM_VALUE_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1, 782SND_SOC_DAPM_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1,
778 ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0, 783 ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0,
779 &wm5110_aec_loopback_mux), 784 &wm5110_aec_loopback_mux),
780 785
@@ -1589,10 +1594,6 @@ static int wm5110_codec_probe(struct snd_soc_codec *codec)
1589 1594
1590 priv->core.arizona->dapm = &codec->dapm; 1595 priv->core.arizona->dapm = &codec->dapm;
1591 1596
1592 ret = snd_soc_codec_set_cache_io(codec, priv->core.arizona->regmap);
1593 if (ret != 0)
1594 return ret;
1595
1596 arizona_init_spk(codec); 1597 arizona_init_spk(codec);
1597 arizona_init_gpio(codec); 1598 arizona_init_gpio(codec);
1598 1599
@@ -1633,9 +1634,17 @@ static unsigned int wm5110_digital_vu[] = {
1633 ARIZONA_DAC_DIGITAL_VOLUME_6R, 1634 ARIZONA_DAC_DIGITAL_VOLUME_6R,
1634}; 1635};
1635 1636
1637static struct regmap *wm5110_get_regmap(struct device *dev)
1638{
1639 struct wm5110_priv *priv = dev_get_drvdata(dev);
1640
1641 return priv->core.arizona->regmap;
1642}
1643
1636static struct snd_soc_codec_driver soc_codec_dev_wm5110 = { 1644static struct snd_soc_codec_driver soc_codec_dev_wm5110 = {
1637 .probe = wm5110_codec_probe, 1645 .probe = wm5110_codec_probe,
1638 .remove = wm5110_codec_remove, 1646 .remove = wm5110_codec_remove,
1647 .get_regmap = wm5110_get_regmap,
1639 1648
1640 .idle_bias_off = true, 1649 .idle_bias_off = true,
1641 1650
diff --git a/sound/soc/codecs/wm8350.c b/sound/soc/codecs/wm8350.c
index 757256bf7672..392285edb595 100644
--- a/sound/soc/codecs/wm8350.c
+++ b/sound/soc/codecs/wm8350.c
@@ -302,7 +302,7 @@ static int pga_event(struct snd_soc_dapm_widget *w,
302static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol, 302static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,
303 struct snd_ctl_elem_value *ucontrol) 303 struct snd_ctl_elem_value *ucontrol)
304{ 304{
305 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 305 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
306 struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec); 306 struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec);
307 struct wm8350_output *out = NULL; 307 struct wm8350_output *out = NULL;
308 struct soc_mixer_control *mc = 308 struct soc_mixer_control *mc =
@@ -345,7 +345,7 @@ static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,
345static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol, 345static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol,
346 struct snd_ctl_elem_value *ucontrol) 346 struct snd_ctl_elem_value *ucontrol)
347{ 347{
348 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 348 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
349 struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec); 349 struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec);
350 struct wm8350_output *out1 = &wm8350_priv->out1; 350 struct wm8350_output *out1 = &wm8350_priv->out1;
351 struct wm8350_output *out2 = &wm8350_priv->out2; 351 struct wm8350_output *out2 = &wm8350_priv->out2;
@@ -1505,8 +1505,6 @@ static int wm8350_codec_probe(struct snd_soc_codec *codec)
1505 if (ret != 0) 1505 if (ret != 0)
1506 return ret; 1506 return ret;
1507 1507
1508 snd_soc_codec_set_cache_io(codec, wm8350->regmap);
1509
1510 /* Put the codec into reset if it wasn't already */ 1508 /* Put the codec into reset if it wasn't already */
1511 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); 1509 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1512 1510
@@ -1608,11 +1606,19 @@ static int wm8350_codec_remove(struct snd_soc_codec *codec)
1608 return 0; 1606 return 0;
1609} 1607}
1610 1608
1609static struct regmap *wm8350_get_regmap(struct device *dev)
1610{
1611 struct wm8350 *wm8350 = dev_get_platdata(dev);
1612
1613 return wm8350->regmap;
1614}
1615
1611static struct snd_soc_codec_driver soc_codec_dev_wm8350 = { 1616static struct snd_soc_codec_driver soc_codec_dev_wm8350 = {
1612 .probe = wm8350_codec_probe, 1617 .probe = wm8350_codec_probe,
1613 .remove = wm8350_codec_remove, 1618 .remove = wm8350_codec_remove,
1614 .suspend = wm8350_suspend, 1619 .suspend = wm8350_suspend,
1615 .resume = wm8350_resume, 1620 .resume = wm8350_resume,
1621 .get_regmap = wm8350_get_regmap,
1616 .set_bias_level = wm8350_set_bias_level, 1622 .set_bias_level = wm8350_set_bias_level,
1617 1623
1618 .controls = wm8350_snd_controls, 1624 .controls = wm8350_snd_controls,
diff --git a/sound/soc/codecs/wm8400.c b/sound/soc/codecs/wm8400.c
index 146564feaea0..06e913d3fea1 100644
--- a/sound/soc/codecs/wm8400.c
+++ b/sound/soc/codecs/wm8400.c
@@ -93,7 +93,7 @@ static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
93static int wm8400_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, 93static int wm8400_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
94 struct snd_ctl_elem_value *ucontrol) 94 struct snd_ctl_elem_value *ucontrol)
95{ 95{
96 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 96 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
97 struct soc_mixer_control *mc = 97 struct soc_mixer_control *mc =
98 (struct soc_mixer_control *)kcontrol->private_value; 98 (struct soc_mixer_control *)kcontrol->private_value;
99 int reg = mc->reg; 99 int reg = mc->reg;
@@ -1318,8 +1318,6 @@ static int wm8400_codec_probe(struct snd_soc_codec *codec)
1318 priv->wm8400 = wm8400; 1318 priv->wm8400 = wm8400;
1319 priv->codec = codec; 1319 priv->codec = codec;
1320 1320
1321 snd_soc_codec_set_cache_io(codec, wm8400->regmap);
1322
1323 ret = devm_regulator_bulk_get(wm8400->dev, 1321 ret = devm_regulator_bulk_get(wm8400->dev,
1324 ARRAY_SIZE(power), &power[0]); 1322 ARRAY_SIZE(power), &power[0]);
1325 if (ret != 0) { 1323 if (ret != 0) {
@@ -1361,11 +1359,19 @@ static int wm8400_codec_remove(struct snd_soc_codec *codec)
1361 return 0; 1359 return 0;
1362} 1360}
1363 1361
1362static struct regmap *wm8400_get_regmap(struct device *dev)
1363{
1364 struct wm8400 *wm8400 = dev_get_platdata(dev);
1365
1366 return wm8400->regmap;
1367}
1368
1364static struct snd_soc_codec_driver soc_codec_dev_wm8400 = { 1369static struct snd_soc_codec_driver soc_codec_dev_wm8400 = {
1365 .probe = wm8400_codec_probe, 1370 .probe = wm8400_codec_probe,
1366 .remove = wm8400_codec_remove, 1371 .remove = wm8400_codec_remove,
1367 .suspend = wm8400_suspend, 1372 .suspend = wm8400_suspend,
1368 .resume = wm8400_resume, 1373 .resume = wm8400_resume,
1374 .get_regmap = wm8400_get_regmap,
1369 .set_bias_level = wm8400_set_bias_level, 1375 .set_bias_level = wm8400_set_bias_level,
1370 1376
1371 .controls = wm8400_snd_controls, 1377 .controls = wm8400_snd_controls,
diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c
index af7ed8b5d4e1..7665ff6aea6d 100644
--- a/sound/soc/codecs/wm8580.c
+++ b/sound/soc/codecs/wm8580.c
@@ -252,7 +252,7 @@ static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
252{ 252{
253 struct soc_mixer_control *mc = 253 struct soc_mixer_control *mc =
254 (struct soc_mixer_control *)kcontrol->private_value; 254 (struct soc_mixer_control *)kcontrol->private_value;
255 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 255 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
256 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec); 256 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
257 unsigned int reg = mc->reg; 257 unsigned int reg = mc->reg;
258 unsigned int reg2 = mc->rreg; 258 unsigned int reg2 = mc->rreg;
diff --git a/sound/soc/codecs/wm8731.c b/sound/soc/codecs/wm8731.c
index d74f43975b90..5ada61611324 100644
--- a/sound/soc/codecs/wm8731.c
+++ b/sound/soc/codecs/wm8731.c
@@ -119,7 +119,7 @@ static int wm8731_set_deemph(struct snd_soc_codec *codec)
119static int wm8731_get_deemph(struct snd_kcontrol *kcontrol, 119static int wm8731_get_deemph(struct snd_kcontrol *kcontrol,
120 struct snd_ctl_elem_value *ucontrol) 120 struct snd_ctl_elem_value *ucontrol)
121{ 121{
122 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 122 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
123 struct wm8731_priv *wm8731 = snd_soc_codec_get_drvdata(codec); 123 struct wm8731_priv *wm8731 = snd_soc_codec_get_drvdata(codec);
124 124
125 ucontrol->value.enumerated.item[0] = wm8731->deemph; 125 ucontrol->value.enumerated.item[0] = wm8731->deemph;
@@ -130,7 +130,7 @@ static int wm8731_get_deemph(struct snd_kcontrol *kcontrol,
130static int wm8731_put_deemph(struct snd_kcontrol *kcontrol, 130static int wm8731_put_deemph(struct snd_kcontrol *kcontrol,
131 struct snd_ctl_elem_value *ucontrol) 131 struct snd_ctl_elem_value *ucontrol)
132{ 132{
133 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 133 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
134 struct wm8731_priv *wm8731 = snd_soc_codec_get_drvdata(codec); 134 struct wm8731_priv *wm8731 = snd_soc_codec_get_drvdata(codec);
135 int deemph = ucontrol->value.enumerated.item[0]; 135 int deemph = ucontrol->value.enumerated.item[0];
136 int ret = 0; 136 int ret = 0;
@@ -586,7 +586,7 @@ static int wm8731_probe(struct snd_soc_codec *codec)
586 for (i = 0; i < ARRAY_SIZE(wm8731->supplies); i++) 586 for (i = 0; i < ARRAY_SIZE(wm8731->supplies); i++)
587 wm8731->supplies[i].supply = wm8731_supply_names[i]; 587 wm8731->supplies[i].supply = wm8731_supply_names[i];
588 588
589 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8731->supplies), 589 ret = devm_regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8731->supplies),
590 wm8731->supplies); 590 wm8731->supplies);
591 if (ret != 0) { 591 if (ret != 0) {
592 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 592 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
@@ -597,7 +597,7 @@ static int wm8731_probe(struct snd_soc_codec *codec)
597 wm8731->supplies); 597 wm8731->supplies);
598 if (ret != 0) { 598 if (ret != 0) {
599 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); 599 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
600 goto err_regulator_get; 600 return ret;
601 } 601 }
602 602
603 ret = wm8731_reset(codec); 603 ret = wm8731_reset(codec);
@@ -624,8 +624,6 @@ static int wm8731_probe(struct snd_soc_codec *codec)
624 624
625err_regulator_enable: 625err_regulator_enable:
626 regulator_bulk_disable(ARRAY_SIZE(wm8731->supplies), wm8731->supplies); 626 regulator_bulk_disable(ARRAY_SIZE(wm8731->supplies), wm8731->supplies);
627err_regulator_get:
628 regulator_bulk_free(ARRAY_SIZE(wm8731->supplies), wm8731->supplies);
629 627
630 return ret; 628 return ret;
631} 629}
@@ -638,7 +636,6 @@ static int wm8731_remove(struct snd_soc_codec *codec)
638 wm8731_set_bias_level(codec, SND_SOC_BIAS_OFF); 636 wm8731_set_bias_level(codec, SND_SOC_BIAS_OFF);
639 637
640 regulator_bulk_disable(ARRAY_SIZE(wm8731->supplies), wm8731->supplies); 638 regulator_bulk_disable(ARRAY_SIZE(wm8731->supplies), wm8731->supplies);
641 regulator_bulk_free(ARRAY_SIZE(wm8731->supplies), wm8731->supplies);
642 639
643 return 0; 640 return 0;
644} 641}
diff --git a/sound/soc/codecs/wm8753.c b/sound/soc/codecs/wm8753.c
index cbb8d55052a4..53e57b4049a8 100644
--- a/sound/soc/codecs/wm8753.c
+++ b/sound/soc/codecs/wm8753.c
@@ -234,7 +234,7 @@ SOC_ENUM_SINGLE(WM8753_OUTCTL, 2, 2, wm8753_rout2_phase),
234static int wm8753_get_dai(struct snd_kcontrol *kcontrol, 234static int wm8753_get_dai(struct snd_kcontrol *kcontrol,
235 struct snd_ctl_elem_value *ucontrol) 235 struct snd_ctl_elem_value *ucontrol)
236{ 236{
237 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 237 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
238 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec); 238 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
239 239
240 ucontrol->value.integer.value[0] = wm8753->dai_func; 240 ucontrol->value.integer.value[0] = wm8753->dai_func;
@@ -244,7 +244,7 @@ static int wm8753_get_dai(struct snd_kcontrol *kcontrol,
244static int wm8753_set_dai(struct snd_kcontrol *kcontrol, 244static int wm8753_set_dai(struct snd_kcontrol *kcontrol,
245 struct snd_ctl_elem_value *ucontrol) 245 struct snd_ctl_elem_value *ucontrol)
246{ 246{
247 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 247 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
248 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec); 248 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
249 u16 ioctl; 249 u16 ioctl;
250 250
diff --git a/sound/soc/codecs/wm8804.c b/sound/soc/codecs/wm8804.c
index ee76f0fb4299..bbcad9ff3c98 100644
--- a/sound/soc/codecs/wm8804.c
+++ b/sound/soc/codecs/wm8804.c
@@ -106,7 +106,7 @@ static int txsrc_get(struct snd_kcontrol *kcontrol,
106 struct snd_soc_codec *codec; 106 struct snd_soc_codec *codec;
107 unsigned int src; 107 unsigned int src;
108 108
109 codec = snd_kcontrol_chip(kcontrol); 109 codec = snd_soc_kcontrol_codec(kcontrol);
110 src = snd_soc_read(codec, WM8804_SPDTX4); 110 src = snd_soc_read(codec, WM8804_SPDTX4);
111 if (src & 0x40) 111 if (src & 0x40)
112 ucontrol->value.integer.value[0] = 1; 112 ucontrol->value.integer.value[0] = 1;
@@ -122,7 +122,7 @@ static int txsrc_put(struct snd_kcontrol *kcontrol,
122 struct snd_soc_codec *codec; 122 struct snd_soc_codec *codec;
123 unsigned int src, txpwr; 123 unsigned int src, txpwr;
124 124
125 codec = snd_kcontrol_chip(kcontrol); 125 codec = snd_soc_kcontrol_codec(kcontrol);
126 126
127 if (ucontrol->value.integer.value[0] != 0 127 if (ucontrol->value.integer.value[0] != 0
128 && ucontrol->value.integer.value[0] != 1) 128 && ucontrol->value.integer.value[0] != 1)
@@ -535,7 +535,6 @@ static int wm8804_remove(struct snd_soc_codec *codec)
535 for (i = 0; i < ARRAY_SIZE(wm8804->supplies); ++i) 535 for (i = 0; i < ARRAY_SIZE(wm8804->supplies); ++i)
536 regulator_unregister_notifier(wm8804->supplies[i].consumer, 536 regulator_unregister_notifier(wm8804->supplies[i].consumer,
537 &wm8804->disable_nb[i]); 537 &wm8804->disable_nb[i]);
538 regulator_bulk_free(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
539 return 0; 538 return 0;
540} 539}
541 540
@@ -549,7 +548,7 @@ static int wm8804_probe(struct snd_soc_codec *codec)
549 for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++) 548 for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++)
550 wm8804->supplies[i].supply = wm8804_supply_names[i]; 549 wm8804->supplies[i].supply = wm8804_supply_names[i];
551 550
552 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8804->supplies), 551 ret = devm_regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8804->supplies),
553 wm8804->supplies); 552 wm8804->supplies);
554 if (ret) { 553 if (ret) {
555 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 554 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
@@ -574,7 +573,7 @@ static int wm8804_probe(struct snd_soc_codec *codec)
574 wm8804->supplies); 573 wm8804->supplies);
575 if (ret) { 574 if (ret) {
576 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); 575 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
577 goto err_reg_get; 576 return ret;
578 } 577 }
579 578
580 id1 = snd_soc_read(codec, WM8804_RST_DEVID1); 579 id1 = snd_soc_read(codec, WM8804_RST_DEVID1);
@@ -619,8 +618,6 @@ static int wm8804_probe(struct snd_soc_codec *codec)
619 618
620err_reg_enable: 619err_reg_enable:
621 regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies), wm8804->supplies); 620 regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
622err_reg_get:
623 regulator_bulk_free(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
624 return ret; 621 return ret;
625} 622}
626 623
diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c
index b0084a127d18..b84940c359a1 100644
--- a/sound/soc/codecs/wm8903.c
+++ b/sound/soc/codecs/wm8903.c
@@ -439,7 +439,7 @@ static int wm8903_set_deemph(struct snd_soc_codec *codec)
439static int wm8903_get_deemph(struct snd_kcontrol *kcontrol, 439static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
440 struct snd_ctl_elem_value *ucontrol) 440 struct snd_ctl_elem_value *ucontrol)
441{ 441{
442 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 442 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
443 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 443 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
444 444
445 ucontrol->value.enumerated.item[0] = wm8903->deemph; 445 ucontrol->value.enumerated.item[0] = wm8903->deemph;
@@ -450,7 +450,7 @@ static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
450static int wm8903_put_deemph(struct snd_kcontrol *kcontrol, 450static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
451 struct snd_ctl_elem_value *ucontrol) 451 struct snd_ctl_elem_value *ucontrol)
452{ 452{
453 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 453 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
454 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 454 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
455 int deemph = ucontrol->value.enumerated.item[0]; 455 int deemph = ucontrol->value.enumerated.item[0];
456 int ret = 0; 456 int ret = 0;
diff --git a/sound/soc/codecs/wm8904.c b/sound/soc/codecs/wm8904.c
index 49c35c36935e..f7c549949c54 100644
--- a/sound/soc/codecs/wm8904.c
+++ b/sound/soc/codecs/wm8904.c
@@ -391,7 +391,7 @@ static void wm8904_set_drc(struct snd_soc_codec *codec)
391static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol, 391static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol,
392 struct snd_ctl_elem_value *ucontrol) 392 struct snd_ctl_elem_value *ucontrol)
393{ 393{
394 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 394 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
395 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 395 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
396 struct wm8904_pdata *pdata = wm8904->pdata; 396 struct wm8904_pdata *pdata = wm8904->pdata;
397 int value = ucontrol->value.integer.value[0]; 397 int value = ucontrol->value.integer.value[0];
@@ -409,7 +409,7 @@ static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol,
409static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol, 409static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol,
410 struct snd_ctl_elem_value *ucontrol) 410 struct snd_ctl_elem_value *ucontrol)
411{ 411{
412 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 412 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
413 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 413 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
414 414
415 ucontrol->value.enumerated.item[0] = wm8904->drc_cfg; 415 ucontrol->value.enumerated.item[0] = wm8904->drc_cfg;
@@ -462,7 +462,7 @@ static void wm8904_set_retune_mobile(struct snd_soc_codec *codec)
462static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 462static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
463 struct snd_ctl_elem_value *ucontrol) 463 struct snd_ctl_elem_value *ucontrol)
464{ 464{
465 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 465 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
466 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 466 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
467 struct wm8904_pdata *pdata = wm8904->pdata; 467 struct wm8904_pdata *pdata = wm8904->pdata;
468 int value = ucontrol->value.integer.value[0]; 468 int value = ucontrol->value.integer.value[0];
@@ -480,7 +480,7 @@ static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
480static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 480static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
481 struct snd_ctl_elem_value *ucontrol) 481 struct snd_ctl_elem_value *ucontrol)
482{ 482{
483 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 483 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
484 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 484 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
485 485
486 ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg; 486 ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg;
@@ -520,7 +520,7 @@ static int wm8904_set_deemph(struct snd_soc_codec *codec)
520static int wm8904_get_deemph(struct snd_kcontrol *kcontrol, 520static int wm8904_get_deemph(struct snd_kcontrol *kcontrol,
521 struct snd_ctl_elem_value *ucontrol) 521 struct snd_ctl_elem_value *ucontrol)
522{ 522{
523 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 523 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
524 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 524 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
525 525
526 ucontrol->value.enumerated.item[0] = wm8904->deemph; 526 ucontrol->value.enumerated.item[0] = wm8904->deemph;
@@ -530,7 +530,7 @@ static int wm8904_get_deemph(struct snd_kcontrol *kcontrol,
530static int wm8904_put_deemph(struct snd_kcontrol *kcontrol, 530static int wm8904_put_deemph(struct snd_kcontrol *kcontrol,
531 struct snd_ctl_elem_value *ucontrol) 531 struct snd_ctl_elem_value *ucontrol)
532{ 532{
533 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 533 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
534 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 534 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
535 int deemph = ucontrol->value.enumerated.item[0]; 535 int deemph = ucontrol->value.enumerated.item[0];
536 536
@@ -570,7 +570,7 @@ static SOC_ENUM_SINGLE_DECL(hpf_mode, WM8904_ADC_DIGITAL_0, 5,
570static int wm8904_adc_osr_put(struct snd_kcontrol *kcontrol, 570static int wm8904_adc_osr_put(struct snd_kcontrol *kcontrol,
571 struct snd_ctl_elem_value *ucontrol) 571 struct snd_ctl_elem_value *ucontrol)
572{ 572{
573 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 573 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
574 unsigned int val; 574 unsigned int val;
575 int ret; 575 int ret;
576 576
diff --git a/sound/soc/codecs/wm8955.c b/sound/soc/codecs/wm8955.c
index fecd4e4f4c57..2a35108f233d 100644
--- a/sound/soc/codecs/wm8955.c
+++ b/sound/soc/codecs/wm8955.c
@@ -390,7 +390,7 @@ static int wm8955_set_deemph(struct snd_soc_codec *codec)
390static int wm8955_get_deemph(struct snd_kcontrol *kcontrol, 390static int wm8955_get_deemph(struct snd_kcontrol *kcontrol,
391 struct snd_ctl_elem_value *ucontrol) 391 struct snd_ctl_elem_value *ucontrol)
392{ 392{
393 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 393 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
394 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec); 394 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
395 395
396 ucontrol->value.enumerated.item[0] = wm8955->deemph; 396 ucontrol->value.enumerated.item[0] = wm8955->deemph;
@@ -400,7 +400,7 @@ static int wm8955_get_deemph(struct snd_kcontrol *kcontrol,
400static int wm8955_put_deemph(struct snd_kcontrol *kcontrol, 400static int wm8955_put_deemph(struct snd_kcontrol *kcontrol,
401 struct snd_ctl_elem_value *ucontrol) 401 struct snd_ctl_elem_value *ucontrol)
402{ 402{
403 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 403 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
404 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec); 404 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
405 int deemph = ucontrol->value.enumerated.item[0]; 405 int deemph = ucontrol->value.enumerated.item[0];
406 406
@@ -898,7 +898,7 @@ static int wm8955_probe(struct snd_soc_codec *codec)
898 for (i = 0; i < ARRAY_SIZE(wm8955->supplies); i++) 898 for (i = 0; i < ARRAY_SIZE(wm8955->supplies); i++)
899 wm8955->supplies[i].supply = wm8955_supply_names[i]; 899 wm8955->supplies[i].supply = wm8955_supply_names[i];
900 900
901 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8955->supplies), 901 ret = devm_regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8955->supplies),
902 wm8955->supplies); 902 wm8955->supplies);
903 if (ret != 0) { 903 if (ret != 0) {
904 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 904 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
@@ -909,7 +909,7 @@ static int wm8955_probe(struct snd_soc_codec *codec)
909 wm8955->supplies); 909 wm8955->supplies);
910 if (ret != 0) { 910 if (ret != 0) {
911 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); 911 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
912 goto err_get; 912 return ret;
913 } 913 }
914 914
915 ret = wm8955_reset(codec); 915 ret = wm8955_reset(codec);
@@ -961,17 +961,12 @@ static int wm8955_probe(struct snd_soc_codec *codec)
961 961
962err_enable: 962err_enable:
963 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies); 963 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
964err_get:
965 regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
966 return ret; 964 return ret;
967} 965}
968 966
969static int wm8955_remove(struct snd_soc_codec *codec) 967static int wm8955_remove(struct snd_soc_codec *codec)
970{ 968{
971 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
972
973 wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF); 969 wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF);
974 regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
975 return 0; 970 return 0;
976} 971}
977 972
diff --git a/sound/soc/codecs/wm8958-dsp2.c b/sound/soc/codecs/wm8958-dsp2.c
index 7ac2e511403c..b2ebb104d879 100644
--- a/sound/soc/codecs/wm8958-dsp2.c
+++ b/sound/soc/codecs/wm8958-dsp2.c
@@ -456,7 +456,7 @@ static int wm8958_dsp2_busy(struct wm8994_priv *wm8994, int aif)
456static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol, 456static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
457 struct snd_ctl_elem_value *ucontrol) 457 struct snd_ctl_elem_value *ucontrol)
458{ 458{
459 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 459 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
460 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 460 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
461 struct wm8994 *control = wm8994->wm8994; 461 struct wm8994 *control = wm8994->wm8994;
462 int value = ucontrol->value.integer.value[0]; 462 int value = ucontrol->value.integer.value[0];
@@ -478,7 +478,7 @@ static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
478static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol, 478static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
479 struct snd_ctl_elem_value *ucontrol) 479 struct snd_ctl_elem_value *ucontrol)
480{ 480{
481 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 481 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
482 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 482 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
483 483
484 ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg; 484 ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
@@ -500,7 +500,7 @@ static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
500 struct snd_ctl_elem_value *ucontrol) 500 struct snd_ctl_elem_value *ucontrol)
501{ 501{
502 int mbc = kcontrol->private_value; 502 int mbc = kcontrol->private_value;
503 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 503 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
504 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 504 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
505 505
506 ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc]; 506 ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
@@ -512,7 +512,7 @@ static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
512 struct snd_ctl_elem_value *ucontrol) 512 struct snd_ctl_elem_value *ucontrol)
513{ 513{
514 int mbc = kcontrol->private_value; 514 int mbc = kcontrol->private_value;
515 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 515 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
516 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 516 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
517 517
518 if (wm8994->mbc_ena[mbc] == ucontrol->value.integer.value[0]) 518 if (wm8994->mbc_ena[mbc] == ucontrol->value.integer.value[0])
@@ -546,7 +546,7 @@ static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
546static int wm8958_put_vss_enum(struct snd_kcontrol *kcontrol, 546static int wm8958_put_vss_enum(struct snd_kcontrol *kcontrol,
547 struct snd_ctl_elem_value *ucontrol) 547 struct snd_ctl_elem_value *ucontrol)
548{ 548{
549 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 549 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
550 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 550 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
551 struct wm8994 *control = wm8994->wm8994; 551 struct wm8994 *control = wm8994->wm8994;
552 int value = ucontrol->value.integer.value[0]; 552 int value = ucontrol->value.integer.value[0];
@@ -568,7 +568,7 @@ static int wm8958_put_vss_enum(struct snd_kcontrol *kcontrol,
568static int wm8958_get_vss_enum(struct snd_kcontrol *kcontrol, 568static int wm8958_get_vss_enum(struct snd_kcontrol *kcontrol,
569 struct snd_ctl_elem_value *ucontrol) 569 struct snd_ctl_elem_value *ucontrol)
570{ 570{
571 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 571 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
572 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 572 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
573 573
574 ucontrol->value.enumerated.item[0] = wm8994->vss_cfg; 574 ucontrol->value.enumerated.item[0] = wm8994->vss_cfg;
@@ -579,7 +579,7 @@ static int wm8958_get_vss_enum(struct snd_kcontrol *kcontrol,
579static int wm8958_put_vss_hpf_enum(struct snd_kcontrol *kcontrol, 579static int wm8958_put_vss_hpf_enum(struct snd_kcontrol *kcontrol,
580 struct snd_ctl_elem_value *ucontrol) 580 struct snd_ctl_elem_value *ucontrol)
581{ 581{
582 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 582 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
583 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 583 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
584 struct wm8994 *control = wm8994->wm8994; 584 struct wm8994 *control = wm8994->wm8994;
585 int value = ucontrol->value.integer.value[0]; 585 int value = ucontrol->value.integer.value[0];
@@ -601,7 +601,7 @@ static int wm8958_put_vss_hpf_enum(struct snd_kcontrol *kcontrol,
601static int wm8958_get_vss_hpf_enum(struct snd_kcontrol *kcontrol, 601static int wm8958_get_vss_hpf_enum(struct snd_kcontrol *kcontrol,
602 struct snd_ctl_elem_value *ucontrol) 602 struct snd_ctl_elem_value *ucontrol)
603{ 603{
604 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 604 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
605 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 605 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
606 606
607 ucontrol->value.enumerated.item[0] = wm8994->vss_hpf_cfg; 607 ucontrol->value.enumerated.item[0] = wm8994->vss_hpf_cfg;
@@ -623,7 +623,7 @@ static int wm8958_vss_get(struct snd_kcontrol *kcontrol,
623 struct snd_ctl_elem_value *ucontrol) 623 struct snd_ctl_elem_value *ucontrol)
624{ 624{
625 int vss = kcontrol->private_value; 625 int vss = kcontrol->private_value;
626 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 626 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
627 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 627 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
628 628
629 ucontrol->value.integer.value[0] = wm8994->vss_ena[vss]; 629 ucontrol->value.integer.value[0] = wm8994->vss_ena[vss];
@@ -635,7 +635,7 @@ static int wm8958_vss_put(struct snd_kcontrol *kcontrol,
635 struct snd_ctl_elem_value *ucontrol) 635 struct snd_ctl_elem_value *ucontrol)
636{ 636{
637 int vss = kcontrol->private_value; 637 int vss = kcontrol->private_value;
638 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 638 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
639 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 639 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
640 640
641 if (wm8994->vss_ena[vss] == ucontrol->value.integer.value[0]) 641 if (wm8994->vss_ena[vss] == ucontrol->value.integer.value[0])
@@ -684,7 +684,7 @@ static int wm8958_hpf_get(struct snd_kcontrol *kcontrol,
684 struct snd_ctl_elem_value *ucontrol) 684 struct snd_ctl_elem_value *ucontrol)
685{ 685{
686 int hpf = kcontrol->private_value; 686 int hpf = kcontrol->private_value;
687 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 687 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
688 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 688 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
689 689
690 if (hpf < 3) 690 if (hpf < 3)
@@ -699,7 +699,7 @@ static int wm8958_hpf_put(struct snd_kcontrol *kcontrol,
699 struct snd_ctl_elem_value *ucontrol) 699 struct snd_ctl_elem_value *ucontrol)
700{ 700{
701 int hpf = kcontrol->private_value; 701 int hpf = kcontrol->private_value;
702 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 702 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
703 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 703 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
704 704
705 if (hpf < 3) { 705 if (hpf < 3) {
@@ -746,7 +746,7 @@ static int wm8958_hpf_put(struct snd_kcontrol *kcontrol,
746static int wm8958_put_enh_eq_enum(struct snd_kcontrol *kcontrol, 746static int wm8958_put_enh_eq_enum(struct snd_kcontrol *kcontrol,
747 struct snd_ctl_elem_value *ucontrol) 747 struct snd_ctl_elem_value *ucontrol)
748{ 748{
749 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 749 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
750 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 750 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
751 struct wm8994 *control = wm8994->wm8994; 751 struct wm8994 *control = wm8994->wm8994;
752 int value = ucontrol->value.integer.value[0]; 752 int value = ucontrol->value.integer.value[0];
@@ -768,7 +768,7 @@ static int wm8958_put_enh_eq_enum(struct snd_kcontrol *kcontrol,
768static int wm8958_get_enh_eq_enum(struct snd_kcontrol *kcontrol, 768static int wm8958_get_enh_eq_enum(struct snd_kcontrol *kcontrol,
769 struct snd_ctl_elem_value *ucontrol) 769 struct snd_ctl_elem_value *ucontrol)
770{ 770{
771 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 771 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
772 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 772 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
773 773
774 ucontrol->value.enumerated.item[0] = wm8994->enh_eq_cfg; 774 ucontrol->value.enumerated.item[0] = wm8994->enh_eq_cfg;
@@ -790,7 +790,7 @@ static int wm8958_enh_eq_get(struct snd_kcontrol *kcontrol,
790 struct snd_ctl_elem_value *ucontrol) 790 struct snd_ctl_elem_value *ucontrol)
791{ 791{
792 int eq = kcontrol->private_value; 792 int eq = kcontrol->private_value;
793 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 793 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
794 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 794 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
795 795
796 ucontrol->value.integer.value[0] = wm8994->enh_eq_ena[eq]; 796 ucontrol->value.integer.value[0] = wm8994->enh_eq_ena[eq];
@@ -802,7 +802,7 @@ static int wm8958_enh_eq_put(struct snd_kcontrol *kcontrol,
802 struct snd_ctl_elem_value *ucontrol) 802 struct snd_ctl_elem_value *ucontrol)
803{ 803{
804 int eq = kcontrol->private_value; 804 int eq = kcontrol->private_value;
805 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 805 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
806 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 806 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
807 807
808 if (wm8994->enh_eq_ena[eq] == ucontrol->value.integer.value[0]) 808 if (wm8994->enh_eq_ena[eq] == ucontrol->value.integer.value[0])
diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c
index d04e9cad445c..a145d0431b63 100644
--- a/sound/soc/codecs/wm8960.c
+++ b/sound/soc/codecs/wm8960.c
@@ -178,7 +178,7 @@ static int wm8960_set_deemph(struct snd_soc_codec *codec)
178static int wm8960_get_deemph(struct snd_kcontrol *kcontrol, 178static int wm8960_get_deemph(struct snd_kcontrol *kcontrol,
179 struct snd_ctl_elem_value *ucontrol) 179 struct snd_ctl_elem_value *ucontrol)
180{ 180{
181 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 181 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
182 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); 182 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
183 183
184 ucontrol->value.enumerated.item[0] = wm8960->deemph; 184 ucontrol->value.enumerated.item[0] = wm8960->deemph;
@@ -188,7 +188,7 @@ static int wm8960_get_deemph(struct snd_kcontrol *kcontrol,
188static int wm8960_put_deemph(struct snd_kcontrol *kcontrol, 188static int wm8960_put_deemph(struct snd_kcontrol *kcontrol,
189 struct snd_ctl_elem_value *ucontrol) 189 struct snd_ctl_elem_value *ucontrol)
190{ 190{
191 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 191 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
192 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); 192 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
193 int deemph = ucontrol->value.enumerated.item[0]; 193 int deemph = ucontrol->value.enumerated.item[0];
194 194
diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c
index 5522d2566c67..ca2fda9d72be 100644
--- a/sound/soc/codecs/wm8962.c
+++ b/sound/soc/codecs/wm8962.c
@@ -74,11 +74,9 @@ struct wm8962_priv {
74 struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES]; 74 struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
75 struct notifier_block disable_nb[WM8962_NUM_SUPPLIES]; 75 struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
76 76
77#if IS_ENABLED(CONFIG_INPUT)
78 struct input_dev *beep; 77 struct input_dev *beep;
79 struct work_struct beep_work; 78 struct work_struct beep_work;
80 int beep_rate; 79 int beep_rate;
81#endif
82 80
83#ifdef CONFIG_GPIOLIB 81#ifdef CONFIG_GPIOLIB
84 struct gpio_chip gpio_chip; 82 struct gpio_chip gpio_chip;
@@ -154,6 +152,7 @@ static struct reg_default wm8962_reg[] = {
154 { 40, 0x0000 }, /* R40 - SPKOUTL volume */ 152 { 40, 0x0000 }, /* R40 - SPKOUTL volume */
155 { 41, 0x0000 }, /* R41 - SPKOUTR volume */ 153 { 41, 0x0000 }, /* R41 - SPKOUTR volume */
156 154
155 { 49, 0x0010 }, /* R49 - Class D Control 1 */
157 { 51, 0x0003 }, /* R51 - Class D Control 2 */ 156 { 51, 0x0003 }, /* R51 - Class D Control 2 */
158 157
159 { 56, 0x0506 }, /* R56 - Clocking 4 */ 158 { 56, 0x0506 }, /* R56 - Clocking 4 */
@@ -795,7 +794,6 @@ static bool wm8962_volatile_register(struct device *dev, unsigned int reg)
795 case WM8962_ALC2: 794 case WM8962_ALC2:
796 case WM8962_THERMAL_SHUTDOWN_STATUS: 795 case WM8962_THERMAL_SHUTDOWN_STATUS:
797 case WM8962_ADDITIONAL_CONTROL_4: 796 case WM8962_ADDITIONAL_CONTROL_4:
798 case WM8962_CLASS_D_CONTROL_1:
799 case WM8962_DC_SERVO_6: 797 case WM8962_DC_SERVO_6:
800 case WM8962_INTERRUPT_STATUS_1: 798 case WM8962_INTERRUPT_STATUS_1:
801 case WM8962_INTERRUPT_STATUS_2: 799 case WM8962_INTERRUPT_STATUS_2:
@@ -1552,7 +1550,7 @@ static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol,
1552 struct snd_ctl_elem_value *ucontrol) 1550 struct snd_ctl_elem_value *ucontrol)
1553{ 1551{
1554 int shift = kcontrol->private_value; 1552 int shift = kcontrol->private_value;
1555 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1553 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1556 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 1554 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1557 1555
1558 ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift); 1556 ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift);
@@ -1564,7 +1562,7 @@ static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol,
1564 struct snd_ctl_elem_value *ucontrol) 1562 struct snd_ctl_elem_value *ucontrol)
1565{ 1563{
1566 int shift = kcontrol->private_value; 1564 int shift = kcontrol->private_value;
1567 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1565 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1568 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 1566 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1569 int old = wm8962->dsp2_ena; 1567 int old = wm8962->dsp2_ena;
1570 int ret = 0; 1568 int ret = 0;
@@ -1602,7 +1600,7 @@ out:
1602static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol, 1600static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
1603 struct snd_ctl_elem_value *ucontrol) 1601 struct snd_ctl_elem_value *ucontrol)
1604{ 1602{
1605 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1603 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1606 int ret; 1604 int ret;
1607 1605
1608 /* Apply the update (if any) */ 1606 /* Apply the update (if any) */
@@ -1632,7 +1630,7 @@ static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
1632static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol, 1630static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
1633 struct snd_ctl_elem_value *ucontrol) 1631 struct snd_ctl_elem_value *ucontrol)
1634{ 1632{
1635 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1633 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1636 int ret; 1634 int ret;
1637 1635
1638 /* Apply the update (if any) */ 1636 /* Apply the update (if any) */
@@ -2929,13 +2927,22 @@ static int wm8962_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2929static int wm8962_mute(struct snd_soc_dai *dai, int mute) 2927static int wm8962_mute(struct snd_soc_dai *dai, int mute)
2930{ 2928{
2931 struct snd_soc_codec *codec = dai->codec; 2929 struct snd_soc_codec *codec = dai->codec;
2932 int val; 2930 int val, ret;
2933 2931
2934 if (mute) 2932 if (mute)
2935 val = WM8962_DAC_MUTE; 2933 val = WM8962_DAC_MUTE | WM8962_DAC_MUTE_ALT;
2936 else 2934 else
2937 val = 0; 2935 val = 0;
2938 2936
2937 /**
2938 * The DAC mute bit is mirrored in two registers, update both to keep
2939 * the register cache consistent.
2940 */
2941 ret = snd_soc_update_bits(codec, WM8962_CLASS_D_CONTROL_1,
2942 WM8962_DAC_MUTE_ALT, val);
2943 if (ret < 0)
2944 return ret;
2945
2939 return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1, 2946 return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
2940 WM8962_DAC_MUTE, val); 2947 WM8962_DAC_MUTE, val);
2941} 2948}
@@ -3145,7 +3152,6 @@ int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
3145} 3152}
3146EXPORT_SYMBOL_GPL(wm8962_mic_detect); 3153EXPORT_SYMBOL_GPL(wm8962_mic_detect);
3147 3154
3148#if IS_ENABLED(CONFIG_INPUT)
3149static int beep_rates[] = { 3155static int beep_rates[] = {
3150 500, 1000, 2000, 4000, 3156 500, 1000, 2000, 4000,
3151}; 3157};
@@ -3277,15 +3283,6 @@ static void wm8962_free_beep(struct snd_soc_codec *codec)
3277 3283
3278 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0); 3284 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
3279} 3285}
3280#else
3281static void wm8962_init_beep(struct snd_soc_codec *codec)
3282{
3283}
3284
3285static void wm8962_free_beep(struct snd_soc_codec *codec)
3286{
3287}
3288#endif
3289 3286
3290static void wm8962_set_gpio_mode(struct wm8962_priv *wm8962, int gpio) 3287static void wm8962_set_gpio_mode(struct wm8962_priv *wm8962, int gpio)
3291{ 3288{
diff --git a/sound/soc/codecs/wm8962.h b/sound/soc/codecs/wm8962.h
index a1a5d5294c19..910aafd09d21 100644
--- a/sound/soc/codecs/wm8962.h
+++ b/sound/soc/codecs/wm8962.h
@@ -1954,6 +1954,10 @@
1954#define WM8962_SPKOUTL_ENA_MASK 0x0040 /* SPKOUTL_ENA */ 1954#define WM8962_SPKOUTL_ENA_MASK 0x0040 /* SPKOUTL_ENA */
1955#define WM8962_SPKOUTL_ENA_SHIFT 6 /* SPKOUTL_ENA */ 1955#define WM8962_SPKOUTL_ENA_SHIFT 6 /* SPKOUTL_ENA */
1956#define WM8962_SPKOUTL_ENA_WIDTH 1 /* SPKOUTL_ENA */ 1956#define WM8962_SPKOUTL_ENA_WIDTH 1 /* SPKOUTL_ENA */
1957#define WM8962_DAC_MUTE_ALT 0x0010 /* DAC_MUTE */
1958#define WM8962_DAC_MUTE_ALT_MASK 0x0010 /* DAC_MUTE */
1959#define WM8962_DAC_MUTE_ALT_SHIFT 4 /* DAC_MUTE */
1960#define WM8962_DAC_MUTE_ALT_WIDTH 1 /* DAC_MUTE */
1957#define WM8962_SPKOUTL_PGA_MUTE 0x0002 /* SPKOUTL_PGA_MUTE */ 1961#define WM8962_SPKOUTL_PGA_MUTE 0x0002 /* SPKOUTL_PGA_MUTE */
1958#define WM8962_SPKOUTL_PGA_MUTE_MASK 0x0002 /* SPKOUTL_PGA_MUTE */ 1962#define WM8962_SPKOUTL_PGA_MUTE_MASK 0x0002 /* SPKOUTL_PGA_MUTE */
1959#define WM8962_SPKOUTL_PGA_MUTE_SHIFT 1 /* SPKOUTL_PGA_MUTE */ 1963#define WM8962_SPKOUTL_PGA_MUTE_SHIFT 1 /* SPKOUTL_PGA_MUTE */
diff --git a/sound/soc/codecs/wm8983.c b/sound/soc/codecs/wm8983.c
index 2b9bfa53efbf..19d5baa38f5c 100644
--- a/sound/soc/codecs/wm8983.c
+++ b/sound/soc/codecs/wm8983.c
@@ -552,7 +552,7 @@ static const struct snd_soc_dapm_route wm8983_audio_map[] = {
552static int eqmode_get(struct snd_kcontrol *kcontrol, 552static int eqmode_get(struct snd_kcontrol *kcontrol,
553 struct snd_ctl_elem_value *ucontrol) 553 struct snd_ctl_elem_value *ucontrol)
554{ 554{
555 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 555 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
556 unsigned int reg; 556 unsigned int reg;
557 557
558 reg = snd_soc_read(codec, WM8983_EQ1_LOW_SHELF); 558 reg = snd_soc_read(codec, WM8983_EQ1_LOW_SHELF);
@@ -567,7 +567,7 @@ static int eqmode_get(struct snd_kcontrol *kcontrol,
567static int eqmode_put(struct snd_kcontrol *kcontrol, 567static int eqmode_put(struct snd_kcontrol *kcontrol,
568 struct snd_ctl_elem_value *ucontrol) 568 struct snd_ctl_elem_value *ucontrol)
569{ 569{
570 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 570 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
571 unsigned int regpwr2, regpwr3; 571 unsigned int regpwr2, regpwr3;
572 unsigned int reg_eq; 572 unsigned int reg_eq;
573 573
diff --git a/sound/soc/codecs/wm8985.c b/sound/soc/codecs/wm8985.c
index 5473dc969585..0f5780c09f3a 100644
--- a/sound/soc/codecs/wm8985.c
+++ b/sound/soc/codecs/wm8985.c
@@ -526,7 +526,7 @@ static const struct snd_soc_dapm_route wm8985_dapm_routes[] = {
526static int eqmode_get(struct snd_kcontrol *kcontrol, 526static int eqmode_get(struct snd_kcontrol *kcontrol,
527 struct snd_ctl_elem_value *ucontrol) 527 struct snd_ctl_elem_value *ucontrol)
528{ 528{
529 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 529 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
530 unsigned int reg; 530 unsigned int reg;
531 531
532 reg = snd_soc_read(codec, WM8985_EQ1_LOW_SHELF); 532 reg = snd_soc_read(codec, WM8985_EQ1_LOW_SHELF);
@@ -541,7 +541,7 @@ static int eqmode_get(struct snd_kcontrol *kcontrol,
541static int eqmode_put(struct snd_kcontrol *kcontrol, 541static int eqmode_put(struct snd_kcontrol *kcontrol,
542 struct snd_ctl_elem_value *ucontrol) 542 struct snd_ctl_elem_value *ucontrol)
543{ 543{
544 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 544 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
545 unsigned int regpwr2, regpwr3; 545 unsigned int regpwr2, regpwr3;
546 unsigned int reg_eq; 546 unsigned int reg_eq;
547 547
@@ -984,7 +984,6 @@ static int wm8985_remove(struct snd_soc_codec *codec)
984 984
985 wm8985 = snd_soc_codec_get_drvdata(codec); 985 wm8985 = snd_soc_codec_get_drvdata(codec);
986 wm8985_set_bias_level(codec, SND_SOC_BIAS_OFF); 986 wm8985_set_bias_level(codec, SND_SOC_BIAS_OFF);
987 regulator_bulk_free(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
988 return 0; 987 return 0;
989} 988}
990 989
@@ -999,7 +998,7 @@ static int wm8985_probe(struct snd_soc_codec *codec)
999 for (i = 0; i < ARRAY_SIZE(wm8985->supplies); i++) 998 for (i = 0; i < ARRAY_SIZE(wm8985->supplies); i++)
1000 wm8985->supplies[i].supply = wm8985_supply_names[i]; 999 wm8985->supplies[i].supply = wm8985_supply_names[i];
1001 1000
1002 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8985->supplies), 1001 ret = devm_regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8985->supplies),
1003 wm8985->supplies); 1002 wm8985->supplies);
1004 if (ret) { 1003 if (ret) {
1005 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 1004 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
@@ -1010,7 +1009,7 @@ static int wm8985_probe(struct snd_soc_codec *codec)
1010 wm8985->supplies); 1009 wm8985->supplies);
1011 if (ret) { 1010 if (ret) {
1012 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); 1011 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1013 goto err_reg_get; 1012 return ret;
1014 } 1013 }
1015 1014
1016 ret = wm8985_reset(codec); 1015 ret = wm8985_reset(codec);
@@ -1032,8 +1031,6 @@ static int wm8985_probe(struct snd_soc_codec *codec)
1032 1031
1033err_reg_enable: 1032err_reg_enable:
1034 regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies), wm8985->supplies); 1033 regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
1035err_reg_get:
1036 regulator_bulk_free(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
1037 return ret; 1034 return ret;
1038} 1035}
1039 1036
diff --git a/sound/soc/codecs/wm8988.c b/sound/soc/codecs/wm8988.c
index 3a1ae4f5164d..d3fea46d58e8 100644
--- a/sound/soc/codecs/wm8988.c
+++ b/sound/soc/codecs/wm8988.c
@@ -268,7 +268,7 @@ static const struct soc_enum wm8988_lline_enum =
268 wm8988_line_texts, 268 wm8988_line_texts,
269 wm8988_line_values); 269 wm8988_line_values);
270static const struct snd_kcontrol_new wm8988_left_line_controls = 270static const struct snd_kcontrol_new wm8988_left_line_controls =
271 SOC_DAPM_VALUE_ENUM("Route", wm8988_lline_enum); 271 SOC_DAPM_ENUM("Route", wm8988_lline_enum);
272 272
273static const struct soc_enum wm8988_rline_enum = 273static const struct soc_enum wm8988_rline_enum =
274 SOC_VALUE_ENUM_SINGLE(WM8988_ROUTM1, 0, 7, 274 SOC_VALUE_ENUM_SINGLE(WM8988_ROUTM1, 0, 7,
@@ -276,7 +276,7 @@ static const struct soc_enum wm8988_rline_enum =
276 wm8988_line_texts, 276 wm8988_line_texts,
277 wm8988_line_values); 277 wm8988_line_values);
278static const struct snd_kcontrol_new wm8988_right_line_controls = 278static const struct snd_kcontrol_new wm8988_right_line_controls =
279 SOC_DAPM_VALUE_ENUM("Route", wm8988_lline_enum); 279 SOC_DAPM_ENUM("Route", wm8988_lline_enum);
280 280
281/* Left Mixer */ 281/* Left Mixer */
282static const struct snd_kcontrol_new wm8988_left_mixer_controls[] = { 282static const struct snd_kcontrol_new wm8988_left_mixer_controls[] = {
@@ -304,7 +304,7 @@ static const struct soc_enum wm8988_lpga_enum =
304 wm8988_pga_sel, 304 wm8988_pga_sel,
305 wm8988_pga_val); 305 wm8988_pga_val);
306static const struct snd_kcontrol_new wm8988_left_pga_controls = 306static const struct snd_kcontrol_new wm8988_left_pga_controls =
307 SOC_DAPM_VALUE_ENUM("Route", wm8988_lpga_enum); 307 SOC_DAPM_ENUM("Route", wm8988_lpga_enum);
308 308
309/* Right PGA Mux */ 309/* Right PGA Mux */
310static const struct soc_enum wm8988_rpga_enum = 310static const struct soc_enum wm8988_rpga_enum =
@@ -313,7 +313,7 @@ static const struct soc_enum wm8988_rpga_enum =
313 wm8988_pga_sel, 313 wm8988_pga_sel,
314 wm8988_pga_val); 314 wm8988_pga_val);
315static const struct snd_kcontrol_new wm8988_right_pga_controls = 315static const struct snd_kcontrol_new wm8988_right_pga_controls =
316 SOC_DAPM_VALUE_ENUM("Route", wm8988_rpga_enum); 316 SOC_DAPM_ENUM("Route", wm8988_rpga_enum);
317 317
318/* Differential Mux */ 318/* Differential Mux */
319static const char *wm8988_diff_sel[] = {"Line 1", "Line 2"}; 319static const char *wm8988_diff_sel[] = {"Line 1", "Line 2"};
diff --git a/sound/soc/codecs/wm8990.c b/sound/soc/codecs/wm8990.c
index c413c1991453..b5c1f0f07058 100644
--- a/sound/soc/codecs/wm8990.c
+++ b/sound/soc/codecs/wm8990.c
@@ -132,7 +132,7 @@ static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
132static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, 132static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
133 struct snd_ctl_elem_value *ucontrol) 133 struct snd_ctl_elem_value *ucontrol)
134{ 134{
135 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 135 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
136 struct soc_mixer_control *mc = 136 struct soc_mixer_control *mc =
137 (struct soc_mixer_control *)kcontrol->private_value; 137 (struct soc_mixer_control *)kcontrol->private_value;
138 int reg = mc->reg; 138 int reg = mc->reg;
diff --git a/sound/soc/codecs/wm8991.c b/sound/soc/codecs/wm8991.c
index 844cc4a60d66..b8fd284fc0c0 100644
--- a/sound/soc/codecs/wm8991.c
+++ b/sound/soc/codecs/wm8991.c
@@ -154,7 +154,7 @@ static const unsigned int out_sidetone_tlv[] = {
154static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, 154static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
155 struct snd_ctl_elem_value *ucontrol) 155 struct snd_ctl_elem_value *ucontrol)
156{ 156{
157 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 157 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
158 int reg = kcontrol->private_value & 0xff; 158 int reg = kcontrol->private_value & 0xff;
159 int ret; 159 int ret;
160 u16 val; 160 u16 val;
diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index 6303537f54c6..247b39013fba 100644
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -298,7 +298,7 @@ static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
298{ 298{
299 struct soc_mixer_control *mc = 299 struct soc_mixer_control *mc =
300 (struct soc_mixer_control *)kcontrol->private_value; 300 (struct soc_mixer_control *)kcontrol->private_value;
301 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 301 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
302 int mask, ret; 302 int mask, ret;
303 303
304 /* Can't enable both ADC and DAC paths simultaneously */ 304 /* Can't enable both ADC and DAC paths simultaneously */
@@ -355,7 +355,7 @@ static int wm8994_get_drc(const char *name)
355static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol, 355static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
356 struct snd_ctl_elem_value *ucontrol) 356 struct snd_ctl_elem_value *ucontrol)
357{ 357{
358 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 358 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
359 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 359 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
360 struct wm8994 *control = wm8994->wm8994; 360 struct wm8994 *control = wm8994->wm8994;
361 struct wm8994_pdata *pdata = &control->pdata; 361 struct wm8994_pdata *pdata = &control->pdata;
@@ -378,7 +378,7 @@ static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
378static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol, 378static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
379 struct snd_ctl_elem_value *ucontrol) 379 struct snd_ctl_elem_value *ucontrol)
380{ 380{
381 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 381 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
382 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 382 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
383 int drc = wm8994_get_drc(kcontrol->id.name); 383 int drc = wm8994_get_drc(kcontrol->id.name);
384 384
@@ -462,7 +462,7 @@ static int wm8994_get_retune_mobile_block(const char *name)
462static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 462static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
463 struct snd_ctl_elem_value *ucontrol) 463 struct snd_ctl_elem_value *ucontrol)
464{ 464{
465 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 465 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
466 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 466 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
467 struct wm8994 *control = wm8994->wm8994; 467 struct wm8994 *control = wm8994->wm8994;
468 struct wm8994_pdata *pdata = &control->pdata; 468 struct wm8994_pdata *pdata = &control->pdata;
@@ -485,7 +485,7 @@ static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
485static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 485static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_value *ucontrol) 486 struct snd_ctl_elem_value *ucontrol)
487{ 487{
488 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 488 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
489 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 489 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
490 int block = wm8994_get_retune_mobile_block(kcontrol->id.name); 490 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
491 491
@@ -1347,10 +1347,10 @@ static const char *adc_mux_text[] = {
1347static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text); 1347static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text);
1348 1348
1349static const struct snd_kcontrol_new adcl_mux = 1349static const struct snd_kcontrol_new adcl_mux =
1350 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum); 1350 SOC_DAPM_ENUM("ADCL Mux", adc_enum);
1351 1351
1352static const struct snd_kcontrol_new adcr_mux = 1352static const struct snd_kcontrol_new adcr_mux =
1353 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum); 1353 SOC_DAPM_ENUM("ADCR Mux", adc_enum);
1354 1354
1355static const struct snd_kcontrol_new left_speaker_mixer[] = { 1355static const struct snd_kcontrol_new left_speaker_mixer[] = {
1356SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0), 1356SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
@@ -1651,15 +1651,15 @@ SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1651}; 1651};
1652 1652
1653static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = { 1653static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1654SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux, 1654SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1655 adc_mux_ev, SND_SOC_DAPM_PRE_PMU), 1655 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1656SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux, 1656SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1657 adc_mux_ev, SND_SOC_DAPM_PRE_PMU), 1657 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1658}; 1658};
1659 1659
1660static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = { 1660static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1661SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux), 1661SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1662SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux), 1662SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1663}; 1663};
1664 1664
1665static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = { 1665static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
@@ -3999,8 +3999,6 @@ static int wm8994_codec_probe(struct snd_soc_codec *codec)
3999 3999
4000 wm8994->hubs.codec = codec; 4000 wm8994->hubs.codec = codec;
4001 4001
4002 snd_soc_codec_set_cache_io(codec, control->regmap);
4003
4004 mutex_init(&wm8994->accdet_lock); 4002 mutex_init(&wm8994->accdet_lock);
4005 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap, 4003 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
4006 wm1811_jackdet_bootstrap); 4004 wm1811_jackdet_bootstrap);
@@ -4434,11 +4432,19 @@ static int wm8994_codec_remove(struct snd_soc_codec *codec)
4434 return 0; 4432 return 0;
4435} 4433}
4436 4434
4435static struct regmap *wm8994_get_regmap(struct device *dev)
4436{
4437 struct wm8994 *control = dev_get_drvdata(dev->parent);
4438
4439 return control->regmap;
4440}
4441
4437static struct snd_soc_codec_driver soc_codec_dev_wm8994 = { 4442static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4438 .probe = wm8994_codec_probe, 4443 .probe = wm8994_codec_probe,
4439 .remove = wm8994_codec_remove, 4444 .remove = wm8994_codec_remove,
4440 .suspend = wm8994_codec_suspend, 4445 .suspend = wm8994_codec_suspend,
4441 .resume = wm8994_codec_resume, 4446 .resume = wm8994_codec_resume,
4447 .get_regmap = wm8994_get_regmap,
4442 .set_bias_level = wm8994_set_bias_level, 4448 .set_bias_level = wm8994_set_bias_level,
4443}; 4449};
4444 4450
diff --git a/sound/soc/codecs/wm8995.c b/sound/soc/codecs/wm8995.c
index d3152cf5bd56..863a2c38bcb5 100644
--- a/sound/soc/codecs/wm8995.c
+++ b/sound/soc/codecs/wm8995.c
@@ -885,10 +885,10 @@ static const char *adc_mux_text[] = {
885static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text); 885static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text);
886 886
887static const struct snd_kcontrol_new adcl_mux = 887static const struct snd_kcontrol_new adcl_mux =
888 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum); 888 SOC_DAPM_ENUM("ADCL Mux", adc_enum);
889 889
890static const struct snd_kcontrol_new adcr_mux = 890static const struct snd_kcontrol_new adcr_mux =
891 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum); 891 SOC_DAPM_ENUM("ADCR Mux", adc_enum);
892 892
893static const char *spk_src_text[] = { 893static const char *spk_src_text[] = {
894 "DAC1L", "DAC1R", "DAC2L", "DAC2R" 894 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
@@ -948,10 +948,8 @@ static const struct snd_soc_dapm_widget wm8995_dapm_widgets[] = {
948 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture", 948 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
949 0, WM8995_POWER_MANAGEMENT_3, 10, 0), 949 0, WM8995_POWER_MANAGEMENT_3, 10, 0),
950 950
951 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", SND_SOC_NOPM, 1, 0, 951 SND_SOC_DAPM_MUX("ADCL Mux", SND_SOC_NOPM, 1, 0, &adcl_mux),
952 &adcl_mux), 952 SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0, &adcr_mux),
953 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0,
954 &adcr_mux),
955 953
956 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8995_POWER_MANAGEMENT_3, 5, 0), 954 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8995_POWER_MANAGEMENT_3, 5, 0),
957 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8995_POWER_MANAGEMENT_3, 4, 0), 955 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8995_POWER_MANAGEMENT_3, 4, 0),
diff --git a/sound/soc/codecs/wm8996.c b/sound/soc/codecs/wm8996.c
index c6cbb3b8ace9..69266332760e 100644
--- a/sound/soc/codecs/wm8996.c
+++ b/sound/soc/codecs/wm8996.c
@@ -412,7 +412,7 @@ static int wm8996_get_retune_mobile_block(const char *name)
412static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 412static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
413 struct snd_ctl_elem_value *ucontrol) 413 struct snd_ctl_elem_value *ucontrol)
414{ 414{
415 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 415 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
416 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 416 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
417 struct wm8996_pdata *pdata = &wm8996->pdata; 417 struct wm8996_pdata *pdata = &wm8996->pdata;
418 int block = wm8996_get_retune_mobile_block(kcontrol->id.name); 418 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
@@ -434,7 +434,7 @@ static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
434static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 434static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
435 struct snd_ctl_elem_value *ucontrol) 435 struct snd_ctl_elem_value *ucontrol)
436{ 436{
437 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 437 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
438 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 438 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
439 int block = wm8996_get_retune_mobile_block(kcontrol->id.name); 439 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
440 440
diff --git a/sound/soc/codecs/wm8997.c b/sound/soc/codecs/wm8997.c
index 004186b6bd48..bb9b47b956aa 100644
--- a/sound/soc/codecs/wm8997.c
+++ b/sound/soc/codecs/wm8997.c
@@ -245,8 +245,8 @@ SND_SOC_BYTES("LHPF2 Coefficients", ARIZONA_HPLPF2_2, 1),
245SND_SOC_BYTES("LHPF3 Coefficients", ARIZONA_HPLPF3_2, 1), 245SND_SOC_BYTES("LHPF3 Coefficients", ARIZONA_HPLPF3_2, 1),
246SND_SOC_BYTES("LHPF4 Coefficients", ARIZONA_HPLPF4_2, 1), 246SND_SOC_BYTES("LHPF4 Coefficients", ARIZONA_HPLPF4_2, 1),
247 247
248SOC_VALUE_ENUM("ISRC1 FSL", arizona_isrc_fsl[0]), 248SOC_ENUM("ISRC1 FSL", arizona_isrc_fsl[0]),
249SOC_VALUE_ENUM("ISRC2 FSL", arizona_isrc_fsl[1]), 249SOC_ENUM("ISRC2 FSL", arizona_isrc_fsl[1]),
250 250
251ARIZONA_MIXER_CONTROLS("Mic", ARIZONA_MICMIX_INPUT_1_SOURCE), 251ARIZONA_MIXER_CONTROLS("Mic", ARIZONA_MICMIX_INPUT_1_SOURCE),
252ARIZONA_MIXER_CONTROLS("Noise", ARIZONA_NOISEMIX_INPUT_1_SOURCE), 252ARIZONA_MIXER_CONTROLS("Noise", ARIZONA_NOISEMIX_INPUT_1_SOURCE),
@@ -286,8 +286,8 @@ SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_5L,
286 ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_VOL_SHIFT, 286 ARIZONA_DAC_DIGITAL_VOLUME_5R, ARIZONA_OUT5L_VOL_SHIFT,
287 0xbf, 0, digital_tlv), 287 0xbf, 0, digital_tlv),
288 288
289SOC_VALUE_ENUM("HPOUT1 OSR", wm8997_hpout_osr[0]), 289SOC_ENUM("HPOUT1 OSR", wm8997_hpout_osr[0]),
290SOC_VALUE_ENUM("EPOUT OSR", wm8997_hpout_osr[1]), 290SOC_ENUM("EPOUT OSR", wm8997_hpout_osr[1]),
291 291
292SOC_ENUM("Output Ramp Up", arizona_out_vi_ramp), 292SOC_ENUM("Output Ramp Up", arizona_out_vi_ramp),
293SOC_ENUM("Output Ramp Down", arizona_out_vd_ramp), 293SOC_ENUM("Output Ramp Down", arizona_out_vd_ramp),
@@ -405,7 +405,7 @@ static const struct soc_enum wm8997_aec_loopback =
405 wm8997_aec_loopback_values); 405 wm8997_aec_loopback_values);
406 406
407static const struct snd_kcontrol_new wm8997_aec_loopback_mux = 407static const struct snd_kcontrol_new wm8997_aec_loopback_mux =
408 SOC_DAPM_VALUE_ENUM("AEC Loopback", wm8997_aec_loopback); 408 SOC_DAPM_ENUM("AEC Loopback", wm8997_aec_loopback);
409 409
410static const struct snd_soc_dapm_widget wm8997_dapm_widgets[] = { 410static const struct snd_soc_dapm_widget wm8997_dapm_widgets[] = {
411SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1, ARIZONA_SYSCLK_ENA_SHIFT, 411SND_SOC_DAPM_SUPPLY("SYSCLK", ARIZONA_SYSTEM_CLOCK_1, ARIZONA_SYSCLK_ENA_SHIFT,
@@ -604,7 +604,7 @@ SND_SOC_DAPM_AIF_IN("SLIMRX8", NULL, 0,
604 ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE, 604 ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE,
605 ARIZONA_SLIMRX8_ENA_SHIFT, 0), 605 ARIZONA_SLIMRX8_ENA_SHIFT, 0),
606 606
607SND_SOC_DAPM_VALUE_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1, 607SND_SOC_DAPM_MUX("AEC Loopback", ARIZONA_DAC_AEC_CONTROL_1,
608 ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0, 608 ARIZONA_AEC_LOOPBACK_ENA_SHIFT, 0,
609 &wm8997_aec_loopback_mux), 609 &wm8997_aec_loopback_mux),
610 610
@@ -1051,11 +1051,6 @@ static struct snd_soc_dai_driver wm8997_dai[] = {
1051static int wm8997_codec_probe(struct snd_soc_codec *codec) 1051static int wm8997_codec_probe(struct snd_soc_codec *codec)
1052{ 1052{
1053 struct wm8997_priv *priv = snd_soc_codec_get_drvdata(codec); 1053 struct wm8997_priv *priv = snd_soc_codec_get_drvdata(codec);
1054 int ret;
1055
1056 ret = snd_soc_codec_set_cache_io(codec, priv->core.arizona->regmap);
1057 if (ret != 0)
1058 return ret;
1059 1054
1060 arizona_init_spk(codec); 1055 arizona_init_spk(codec);
1061 1056
@@ -1086,9 +1081,17 @@ static unsigned int wm8997_digital_vu[] = {
1086 ARIZONA_DAC_DIGITAL_VOLUME_5R, 1081 ARIZONA_DAC_DIGITAL_VOLUME_5R,
1087}; 1082};
1088 1083
1084static struct regmap *wm8997_get_regmap(struct device *dev)
1085{
1086 struct wm8997_priv *priv = dev_get_drvdata(dev);
1087
1088 return priv->core.arizona->regmap;
1089}
1090
1089static struct snd_soc_codec_driver soc_codec_dev_wm8997 = { 1091static struct snd_soc_codec_driver soc_codec_dev_wm8997 = {
1090 .probe = wm8997_codec_probe, 1092 .probe = wm8997_codec_probe,
1091 .remove = wm8997_codec_remove, 1093 .remove = wm8997_codec_remove,
1094 .get_regmap = wm8997_get_regmap,
1092 1095
1093 .idle_bias_off = true, 1096 .idle_bias_off = true,
1094 1097
diff --git a/sound/soc/codecs/wm9081.c b/sound/soc/codecs/wm9081.c
index d18eff31fbbc..185eb97769e7 100644
--- a/sound/soc/codecs/wm9081.c
+++ b/sound/soc/codecs/wm9081.c
@@ -340,7 +340,7 @@ static SOC_ENUM_SINGLE_DECL(speaker_mode, WM9081_ANALOGUE_SPEAKER_2, 6,
340static int speaker_mode_get(struct snd_kcontrol *kcontrol, 340static int speaker_mode_get(struct snd_kcontrol *kcontrol,
341 struct snd_ctl_elem_value *ucontrol) 341 struct snd_ctl_elem_value *ucontrol)
342{ 342{
343 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 343 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
344 unsigned int reg; 344 unsigned int reg;
345 345
346 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2); 346 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
@@ -361,7 +361,7 @@ static int speaker_mode_get(struct snd_kcontrol *kcontrol,
361static int speaker_mode_put(struct snd_kcontrol *kcontrol, 361static int speaker_mode_put(struct snd_kcontrol *kcontrol,
362 struct snd_ctl_elem_value *ucontrol) 362 struct snd_ctl_elem_value *ucontrol)
363{ 363{
364 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 364 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
365 unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT); 365 unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
366 unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2); 366 unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
367 367
diff --git a/sound/soc/codecs/wm_adsp.c b/sound/soc/codecs/wm_adsp.c
index bb5f7b4e3ebb..060027182dcb 100644
--- a/sound/soc/codecs/wm_adsp.c
+++ b/sound/soc/codecs/wm_adsp.c
@@ -242,7 +242,7 @@ struct wm_coeff_ctl {
242static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol, 242static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
243 struct snd_ctl_elem_value *ucontrol) 243 struct snd_ctl_elem_value *ucontrol)
244{ 244{
245 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 245 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
246 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 246 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
247 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec); 247 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
248 248
@@ -254,7 +254,7 @@ static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
254static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol, 254static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
255 struct snd_ctl_elem_value *ucontrol) 255 struct snd_ctl_elem_value *ucontrol)
256{ 256{
257 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 257 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
258 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 258 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
259 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec); 259 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
260 260
@@ -1543,16 +1543,16 @@ static void wm_adsp2_boot_work(struct work_struct *work)
1543 ret = regmap_read(dsp->regmap, 1543 ret = regmap_read(dsp->regmap,
1544 dsp->base + ADSP2_CLOCKING, &val); 1544 dsp->base + ADSP2_CLOCKING, &val);
1545 if (ret != 0) { 1545 if (ret != 0) {
1546 dev_err(dsp->dev, "Failed to read clocking: %d\n", ret); 1546 adsp_err(dsp, "Failed to read clocking: %d\n", ret);
1547 return; 1547 return;
1548 } 1548 }
1549 1549
1550 if ((val & ADSP2_CLK_SEL_MASK) >= 3) { 1550 if ((val & ADSP2_CLK_SEL_MASK) >= 3) {
1551 ret = regulator_enable(dsp->dvfs); 1551 ret = regulator_enable(dsp->dvfs);
1552 if (ret != 0) { 1552 if (ret != 0) {
1553 dev_err(dsp->dev, 1553 adsp_err(dsp,
1554 "Failed to enable supply: %d\n", 1554 "Failed to enable supply: %d\n",
1555 ret); 1555 ret);
1556 return; 1556 return;
1557 } 1557 }
1558 1558
@@ -1560,9 +1560,9 @@ static void wm_adsp2_boot_work(struct work_struct *work)
1560 1800000, 1560 1800000,
1561 1800000); 1561 1800000);
1562 if (ret != 0) { 1562 if (ret != 0) {
1563 dev_err(dsp->dev, 1563 adsp_err(dsp,
1564 "Failed to raise supply: %d\n", 1564 "Failed to raise supply: %d\n",
1565 ret); 1565 ret);
1566 return; 1566 return;
1567 } 1567 }
1568 } 1568 }
@@ -1625,7 +1625,7 @@ int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
1625 break; 1625 break;
1626 default: 1626 default:
1627 break; 1627 break;
1628 }; 1628 }
1629 1629
1630 return 0; 1630 return 0;
1631} 1631}
@@ -1672,15 +1672,15 @@ int wm_adsp2_event(struct snd_soc_dapm_widget *w,
1672 ret = regulator_set_voltage(dsp->dvfs, 1200000, 1672 ret = regulator_set_voltage(dsp->dvfs, 1200000,
1673 1800000); 1673 1800000);
1674 if (ret != 0) 1674 if (ret != 0)
1675 dev_warn(dsp->dev, 1675 adsp_warn(dsp,
1676 "Failed to lower supply: %d\n", 1676 "Failed to lower supply: %d\n",
1677 ret); 1677 ret);
1678 1678
1679 ret = regulator_disable(dsp->dvfs); 1679 ret = regulator_disable(dsp->dvfs);
1680 if (ret != 0) 1680 if (ret != 0)
1681 dev_err(dsp->dev, 1681 adsp_err(dsp,
1682 "Failed to enable supply: %d\n", 1682 "Failed to enable supply: %d\n",
1683 ret); 1683 ret);
1684 } 1684 }
1685 1685
1686 list_for_each_entry(ctl, &dsp->ctl_list, list) 1686 list_for_each_entry(ctl, &dsp->ctl_list, list)
@@ -1732,28 +1732,25 @@ int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs)
1732 adsp->dvfs = devm_regulator_get(adsp->dev, "DCVDD"); 1732 adsp->dvfs = devm_regulator_get(adsp->dev, "DCVDD");
1733 if (IS_ERR(adsp->dvfs)) { 1733 if (IS_ERR(adsp->dvfs)) {
1734 ret = PTR_ERR(adsp->dvfs); 1734 ret = PTR_ERR(adsp->dvfs);
1735 dev_err(adsp->dev, "Failed to get DCVDD: %d\n", ret); 1735 adsp_err(adsp, "Failed to get DCVDD: %d\n", ret);
1736 return ret; 1736 return ret;
1737 } 1737 }
1738 1738
1739 ret = regulator_enable(adsp->dvfs); 1739 ret = regulator_enable(adsp->dvfs);
1740 if (ret != 0) { 1740 if (ret != 0) {
1741 dev_err(adsp->dev, "Failed to enable DCVDD: %d\n", 1741 adsp_err(adsp, "Failed to enable DCVDD: %d\n", ret);
1742 ret);
1743 return ret; 1742 return ret;
1744 } 1743 }
1745 1744
1746 ret = regulator_set_voltage(adsp->dvfs, 1200000, 1800000); 1745 ret = regulator_set_voltage(adsp->dvfs, 1200000, 1800000);
1747 if (ret != 0) { 1746 if (ret != 0) {
1748 dev_err(adsp->dev, "Failed to initialise DVFS: %d\n", 1747 adsp_err(adsp, "Failed to initialise DVFS: %d\n", ret);
1749 ret);
1750 return ret; 1748 return ret;
1751 } 1749 }
1752 1750
1753 ret = regulator_disable(adsp->dvfs); 1751 ret = regulator_disable(adsp->dvfs);
1754 if (ret != 0) { 1752 if (ret != 0) {
1755 dev_err(adsp->dev, "Failed to disable DCVDD: %d\n", 1753 adsp_err(adsp, "Failed to disable DCVDD: %d\n", ret);
1756 ret);
1757 return ret; 1754 return ret;
1758 } 1755 }
1759 } 1756 }
diff --git a/sound/soc/codecs/wm_hubs.c b/sound/soc/codecs/wm_hubs.c
index b6209662ab13..916817fe6632 100644
--- a/sound/soc/codecs/wm_hubs.c
+++ b/sound/soc/codecs/wm_hubs.c
@@ -337,7 +337,7 @@ static void enable_dc_servo(struct snd_soc_codec *codec)
337static int wm8993_put_dc_servo(struct snd_kcontrol *kcontrol, 337static int wm8993_put_dc_servo(struct snd_kcontrol *kcontrol,
338 struct snd_ctl_elem_value *ucontrol) 338 struct snd_ctl_elem_value *ucontrol)
339{ 339{
340 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 340 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
341 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec); 341 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
342 int ret; 342 int ret;
343 343
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 10:29:19 -0500