11 files changed, 328 insertions, 16 deletions

diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
index 941ac70e7f30..555937a25504 100644
--- a/include/dt-bindings/clock/axg-clkc.h
+++ b/include/dt-bindings/clock/axg-clkc.h
@@ -67,5 +67,6 @@
 #define CLKID_AO_I2C                            58
 #define CLKID_SD_EMMC_B_CLK0                    59
 #define CLKID_SD_EMMC_C_CLK0                    60
+#define CLKID_HIFI_PLL                          69
 
 #endif /* __AXG_CLKC_H */
diff --git a/include/dt-bindings/clock/mt2712-clk.h b/include/dt-bindings/clock/mt2712-clk.h
index 48a8e797a617..76265836a1e1 100644
--- a/include/dt-bindings/clock/mt2712-clk.h
+++ b/include/dt-bindings/clock/mt2712-clk.h
@@ -222,7 +222,13 @@
 #define CLK_TOP_APLL_DIV_PDN5           183
 #define CLK_TOP_APLL_DIV_PDN6           184
 #define CLK_TOP_APLL_DIV_PDN7           185
-#define CLK_TOP_NR_CLK                  186
+#define CLK_TOP_APLL1_D3                186
+#define CLK_TOP_APLL1_REF_SEL           187
+#define CLK_TOP_APLL2_REF_SEL           188
+#define CLK_TOP_NFI2X_EN                189
+#define CLK_TOP_NFIECC_EN               190
+#define CLK_TOP_NFI1X_CK_EN             191
+#define CLK_TOP_NR_CLK                  192
 
 /* INFRACFG */
 
@@ -281,7 +287,9 @@
 #define CLK_PERI_MSDC30_3_EN            41
 #define CLK_PERI_MSDC50_0_HCLK_EN       42
 #define CLK_PERI_MSDC50_3_HCLK_EN       43
-#define CLK_PERI_NR_CLK                 44
+#define CLK_PERI_MSDC30_0_QTR_EN        44
+#define CLK_PERI_MSDC30_3_QTR_EN        45
+#define CLK_PERI_NR_CLK                 46
 
 /* MCUCFG */
 
diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h
index b8337a5fa347..c585b82b9c05 100644
--- a/include/dt-bindings/clock/qcom,rpmcc.h
+++ b/include/dt-bindings/clock/qcom,rpmcc.h
@@ -40,6 +40,11 @@
 #define RPM_SMI_CLK                             22
 #define RPM_SMI_A_CLK                           23
 #define RPM_PLL4_CLK                            24
+#define RPM_XO_D0                               25
+#define RPM_XO_D1                               26
+#define RPM_XO_A0                               27
+#define RPM_XO_A1                               28
+#define RPM_XO_A2                               29
 
 /* SMD RPM clocks */
 #define RPM_SMD_XO_CLK_SRC                              0
diff --git a/include/dt-bindings/clock/sprd,sc9860-clk.h b/include/dt-bindings/clock/sprd,sc9860-clk.h
index 4cb202f090c2..f2ab4631df0d 100644
--- a/include/dt-bindings/clock/sprd,sc9860-clk.h
+++ b/include/dt-bindings/clock/sprd,sc9860-clk.h
@@ -229,7 +229,26 @@
 #define CLK_SDIO1_2X_EN         65
 #define CLK_SDIO2_2X_EN         66
 #define CLK_EMMC_2X_EN          67
-#define CLK_AON_GATE_NUM        (CLK_EMMC_2X_EN + 1)
+#define CLK_ARCH_RTC_EB         68
+#define CLK_KPB_RTC_EB          69
+#define CLK_AON_SYST_RTC_EB     70
+#define CLK_AP_SYST_RTC_EB      71
+#define CLK_AON_TMR_RTC_EB      72
+#define CLK_AP_TMR0_RTC_EB      73
+#define CLK_EIC_RTC_EB          74
+#define CLK_EIC_RTCDV5_EB       75
+#define CLK_AP_WDG_RTC_EB       76
+#define CLK_AP_TMR1_RTC_EB      77
+#define CLK_AP_TMR2_RTC_EB      78
+#define CLK_DCXO_TMR_RTC_EB     79
+#define CLK_BB_CAL_RTC_EB       80
+#define CLK_AVS_BIG_RTC_EB      81
+#define CLK_AVS_LIT_RTC_EB      82
+#define CLK_AVS_GPU0_RTC_EB     83
+#define CLK_AVS_GPU1_RTC_EB     84
+#define CLK_GPU_TS_EB           85
+#define CLK_RTCDV10_EB          86
+#define CLK_AON_GATE_NUM        (CLK_RTCDV10_EB + 1)
 
 #define CLK_LIT_MCU             0
 #define CLK_BIG_MCU             1
diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
index 49bb3c203e5c..58d8b515be55 100644
--- a/include/dt-bindings/clock/stm32fx-clock.h
+++ b/include/dt-bindings/clock/stm32fx-clock.h
@@ -33,11 +33,12 @@
 #define CLK_SAI2                11
 #define CLK_I2SQ_PDIV           12
 #define CLK_SAIQ_PDIV           13
-
-#define END_PRIMARY_CLK         14
-
 #define CLK_HSI                 14
 #define CLK_SYSCLK              15
+#define CLK_F469_DSI            16
+
+#define END_PRIMARY_CLK         17
+
 #define CLK_HDMI_CEC            16
 #define CLK_SPDIF               17
 #define CLK_USART1              18
diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h
new file mode 100644
index 000000000000..86e3ec662ef4
--- /dev/null
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -0,0 +1,254 @@
+/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
+ */
+
+#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_
+#define _DT_BINDINGS_STM32MP1_CLKS_H_
+
+/* OSCILLATOR clocks */
+#define CK_HSE          0
+#define CK_CSI          1
+#define CK_LSI          2
+#define CK_LSE          3
+#define CK_HSI          4
+#define CK_HSE_DIV2     5
+
+/* Bus clocks */
+#define TIM2            6
+#define TIM3            7
+#define TIM4            8
+#define TIM5            9
+#define TIM6            10
+#define TIM7            11
+#define TIM12           12
+#define TIM13           13
+#define TIM14           14
+#define LPTIM1          15
+#define SPI2            16
+#define SPI3            17
+#define USART2          18
+#define USART3          19
+#define UART4           20
+#define UART5           21
+#define UART7           22
+#define UART8           23
+#define I2C1            24
+#define I2C2            25
+#define I2C3            26
+#define I2C5            27
+#define SPDIF           28
+#define CEC             29
+#define DAC12           30
+#define MDIO            31
+#define TIM1            32
+#define TIM8            33
+#define TIM15           34
+#define TIM16           35
+#define TIM17           36
+#define SPI1            37
+#define SPI4            38
+#define SPI5            39
+#define USART6          40
+#define SAI1            41
+#define SAI2            42
+#define SAI3            43
+#define DFSDM           44
+#define FDCAN           45
+#define LPTIM2          46
+#define LPTIM3          47
+#define LPTIM4          48
+#define LPTIM5          49
+#define SAI4            50
+#define SYSCFG          51
+#define VREF            52
+#define TMPSENS         53
+#define PMBCTRL         54
+#define HDP             55
+#define LTDC            56
+#define DSI             57
+#define IWDG2           58
+#define USBPHY          59
+#define STGENRO         60
+#define SPI6            61
+#define I2C4            62
+#define I2C6            63
+#define USART1          64
+#define RTCAPB          65
+#define TZC             66
+#define TZPC            67
+#define IWDG1           68
+#define BSEC            69
+#define STGEN           70
+#define DMA1            71
+#define DMA2            72
+#define DMAMUX          73
+#define ADC12           74
+#define USBO            75
+#define SDMMC3          76
+#define DCMI            77
+#define CRYP2           78
+#define HASH2           79
+#define RNG2            80
+#define CRC2            81
+#define HSEM            82
+#define IPCC            83
+#define GPIOA           84
+#define GPIOB           85
+#define GPIOC           86
+#define GPIOD           87
+#define GPIOE           88
+#define GPIOF           89
+#define GPIOG           90
+#define GPIOH           91
+#define GPIOI           92
+#define GPIOJ           93
+#define GPIOK           94
+#define GPIOZ           95
+#define CRYP1           96
+#define HASH1           97
+#define RNG1            98
+#define BKPSRAM         99
+#define MDMA            100
+#define GPU             101
+#define ETHCK           102
+#define ETHTX           103
+#define ETHRX           104
+#define ETHMAC          105
+#define FMC             106
+#define QSPI            107
+#define SDMMC1          108
+#define SDMMC2          109
+#define CRC1            110
+#define USBH            111
+#define ETHSTP          112
+
+/* Kernel clocks */
+#define SDMMC1_K        118
+#define SDMMC2_K        119
+#define SDMMC3_K        120
+#define FMC_K           121
+#define QSPI_K          122
+#define ETHCK_K         123
+#define RNG1_K          124
+#define RNG2_K          125
+#define GPU_K           126
+#define USBPHY_K        127
+#define STGEN_K         128
+#define SPDIF_K         129
+#define SPI1_K          130
+#define SPI2_K          131
+#define SPI3_K          132
+#define SPI4_K          133
+#define SPI5_K          134
+#define SPI6_K          135
+#define CEC_K           136
+#define I2C1_K          137
+#define I2C2_K          138
+#define I2C3_K          139
+#define I2C4_K          140
+#define I2C5_K          141
+#define I2C6_K          142
+#define LPTIM1_K        143
+#define LPTIM2_K        144
+#define LPTIM3_K        145
+#define LPTIM4_K        146
+#define LPTIM5_K        147
+#define USART1_K        148
+#define USART2_K        149
+#define USART3_K        150
+#define UART4_K         151
+#define UART5_K         152
+#define USART6_K        153
+#define UART7_K         154
+#define UART8_K         155
+#define DFSDM_K         156
+#define FDCAN_K         157
+#define SAI1_K          158
+#define SAI2_K          159
+#define SAI3_K          160
+#define SAI4_K          161
+#define ADC12_K         162
+#define DSI_K           163
+#define DSI_PX          164
+#define ADFSDM_K        165
+#define USBO_K          166
+#define LTDC_PX         167
+#define DAC12_K         168
+#define ETHPTP_K        169
+
+/* PLL */
+#define PLL1            176
+#define PLL2            177
+#define PLL3            178
+#define PLL4            179
+
+/* ODF */
+#define PLL1_P          180
+#define PLL1_Q          181
+#define PLL1_R          182
+#define PLL2_P          183
+#define PLL2_Q          184
+#define PLL2_R          185
+#define PLL3_P          186
+#define PLL3_Q          187
+#define PLL3_R          188
+#define PLL4_P          189
+#define PLL4_Q          190
+#define PLL4_R          191
+
+/* AUX */
+#define RTC             192
+
+/* MCLK */
+#define CK_PER          193
+#define CK_MPU          194
+#define CK_AXI          195
+#define CK_MCU          196
+
+/* Time base */
+#define TIM2_K          197
+#define TIM3_K          198
+#define TIM4_K          199
+#define TIM5_K          200
+#define TIM6_K          201
+#define TIM7_K          202
+#define TIM12_K         203
+#define TIM13_K         204
+#define TIM14_K         205
+#define TIM1_K          206
+#define TIM8_K          207
+#define TIM15_K         208
+#define TIM16_K         209
+#define TIM17_K         210
+
+/* MCO clocks */
+#define CK_MCO1         211
+#define CK_MCO2         212
+
+/* TRACE & DEBUG clocks */
+#define DBG             213
+#define CK_DBG          214
+#define CK_TRACE        215
+
+/* DDR */
+#define DDRC1           220
+#define DDRC1LP         221
+#define DDRC2           222
+#define DDRC2LP         223
+#define DDRPHYC         224
+#define DDRPHYCLP       225
+#define DDRCAPB         226
+#define DDRCAPBLP       227
+#define AXIDCG          228
+#define DDRPHYCAPB      229
+#define DDRPHYCAPBLP    230
+#define DDRPERFM        231
+
+#define STM32MP1_LAST_CLK 232
+
+#define LTDC_K          LTDC_PX
+#define ETHMAC_K        ETHCK_K
+
+#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index 6422314e46eb..6b77e721f6b1 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -95,7 +95,7 @@
 #define TEGRA210_CLK_CSITE 73
 /* 74 */
 /* 75 */
-/* 76 */
+#define TEGRA210_CLK_LA 76
 /* 77 */
 #define TEGRA210_CLK_SOC_THERM 78
 #define TEGRA210_CLK_DTV 79
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index f711be6e8c44..210a890008f9 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -399,6 +399,7 @@ struct clk_divider {
         spinlock_t      *lock;
 };
 
+#define clk_div_mask(width)     ((1 << (width)) - 1)
 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
 
 #define CLK_DIVIDER_ONE_BASED           BIT(0)
@@ -419,6 +420,10 @@ long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
                                unsigned long rate, unsigned long *prate,
                                const struct clk_div_table *table,
                                u8 width, unsigned long flags);
+long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
+                                  unsigned long rate, unsigned long *prate,
+                                  const struct clk_div_table *table, u8 width,
+                                  unsigned long flags, unsigned int val);
 int divider_get_val(unsigned long rate, unsigned long parent_rate,
                 const struct clk_div_table *table, u8 width,
                 unsigned long flags);
@@ -449,8 +454,9 @@ void clk_hw_unregister_divider(struct clk_hw *hw);
  *
  * @hw:         handle between common and hardware-specific interfaces
  * @reg:        register controlling multiplexer
+ * @table:      array of register values corresponding to the parent index
  * @shift:      shift to multiplexer bit field
- * @width:      width of mutliplexer bit field
+ * @mask:       mask of mutliplexer bit field
  * @flags:      hardware-specific flags
  * @lock:       register lock
  *
@@ -510,6 +516,10 @@ struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
                 void __iomem *reg, u8 shift, u32 mask,
                 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
 
+int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
+                         unsigned int val);
+unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
+
 void clk_unregister_mux(struct clk *clk);
 void clk_hw_unregister_mux(struct clk_hw *hw);
 
@@ -774,6 +784,17 @@ static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
                                          rate, prate, table, width, flags);
 }
 
+static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
+                                         unsigned long *prate,
+                                         const struct clk_div_table *table,
+                                         u8 width, unsigned long flags,
+                                         unsigned int val)
+{
+        return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
+                                            rate, prate, table, width, flags,
+                                            val);
+}
+
 /*
  * FIXME clock api without lock protection
  */
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 4c4ef9f34db3..0dbd0885b2c2 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -209,7 +209,7 @@ static inline int clk_prepare(struct clk *clk)
         return 0;
 }
 
-static inline int clk_bulk_prepare(int num_clks, struct clk_bulk_data *clks)
+static inline int __must_check clk_bulk_prepare(int num_clks, struct clk_bulk_data *clks)
 {
         might_sleep();
         return 0;
@@ -603,8 +603,8 @@ static inline struct clk *clk_get(struct device *dev, const char *id)
         return NULL;
 }
 
-static inline int clk_bulk_get(struct device *dev, int num_clks,
-                               struct clk_bulk_data *clks)
+static inline int __must_check clk_bulk_get(struct device *dev, int num_clks,
+                                            struct clk_bulk_data *clks)
 {
         return 0;
 }
@@ -614,8 +614,8 @@ static inline struct clk *devm_clk_get(struct device *dev, const char *id)
         return NULL;
 }
 
-static inline int devm_clk_bulk_get(struct device *dev, int num_clks,
-                                    struct clk_bulk_data *clks)
+static inline int __must_check devm_clk_bulk_get(struct device *dev, int num_clks,
+                                                 struct clk_bulk_data *clks)
 {
         return 0;
 }
@@ -645,7 +645,7 @@ static inline int clk_enable(struct clk *clk)
         return 0;
 }
 
-static inline int clk_bulk_enable(int num_clks, struct clk_bulk_data *clks)
+static inline int __must_check clk_bulk_enable(int num_clks, struct clk_bulk_data *clks)
 {
         return 0;
 }
@@ -719,8 +719,8 @@ static inline void clk_disable_unprepare(struct clk *clk)
         clk_unprepare(clk);
 }
 
-static inline int clk_bulk_prepare_enable(int num_clks,
-                                          struct clk_bulk_data *clks)
+static inline int __must_check clk_bulk_prepare_enable(int num_clks,
+                                        struct clk_bulk_data *clks)
 {
         int ret;
 
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index d23c9cf26993..afb9edfa5d58 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -128,5 +128,6 @@ extern void tegra210_sata_pll_hw_sequence_start(void);
 extern void tegra210_set_sata_pll_seq_sw(bool state);
 extern void tegra210_put_utmipll_in_iddq(void);
 extern void tegra210_put_utmipll_out_iddq(void);
+extern int tegra210_clk_handle_mbist_war(unsigned int id);
 
 #endif /* __LINUX_CLK_TEGRA_H_ */
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index d18da839b810..9e8611470187 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -211,6 +211,7 @@ enum {
  * struct ti_clk_ll_ops - low-level ops for clocks
  * @clk_readl: pointer to register read function
  * @clk_writel: pointer to register write function
+ * @clk_rmw: pointer to register read-modify-write function
  * @clkdm_clk_enable: pointer to clockdomain enable function
  * @clkdm_clk_disable: pointer to clockdomain disable function
  * @clkdm_lookup: pointer to clockdomain lookup function
@@ -226,6 +227,7 @@ enum {
 struct ti_clk_ll_ops {
         u32     (*clk_readl)(const struct clk_omap_reg *reg);
         void    (*clk_writel)(u32 val, const struct clk_omap_reg *reg);
+        void    (*clk_rmw)(u32 val, u32 mask, const struct clk_omap_reg *reg);
         int     (*clkdm_clk_enable)(struct clockdomain *clkdm, struct clk *clk);
         int     (*clkdm_clk_disable)(struct clockdomain *clkdm,
                                      struct clk *clk);