2 files changed, 14 insertions, 0 deletions

diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 370e9a5536ef..be84e43c1e19 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -326,6 +326,12 @@ struct drm_amdgpu_gem_userptr {
 /* GFX9 and later: */
 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT                0
 #define AMDGPU_TILING_SWIZZLE_MODE_MASK                 0x1f
+#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT             5
+#define AMDGPU_TILING_DCC_OFFSET_256B_MASK              0xFFFFFF
+#define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT               29
+#define AMDGPU_TILING_DCC_PITCH_MAX_MASK                0x3FFF
+#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT         43
+#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK          0x1
 
 /* Set/Get helpers for tiling flags. */
 #define AMDGPU_TILING_SET(field, value) \
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index a4446f452040..298b2e197744 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -412,6 +412,14 @@ typedef struct drm_i915_irq_wait {
         int irq_seq;
 } drm_i915_irq_wait_t;
 
+/*
+ * Different modes of per-process Graphics Translation Table,
+ * see I915_PARAM_HAS_ALIASING_PPGTT
+ */
+#define I915_GEM_PPGTT_NONE     0
+#define I915_GEM_PPGTT_ALIASING 1
+#define I915_GEM_PPGTT_FULL     2
+
 /* Ioctl to query kernel params:
  */
 #define I915_PARAM_IRQ_ACTIVE            1