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-rw-r--r--include/linux/qed/eth_common.h396
1 files changed, 213 insertions, 183 deletions
diff --git a/include/linux/qed/eth_common.h b/include/linux/qed/eth_common.h
index cb06e6e368e1..9db02856623b 100644
--- a/include/linux/qed/eth_common.h
+++ b/include/linux/qed/eth_common.h
@@ -36,150 +36,168 @@
36/********************/ 36/********************/
37/* ETH FW CONSTANTS */ 37/* ETH FW CONSTANTS */
38/********************/ 38/********************/
39#define ETH_HSI_VER_MAJOR 3 39
40#define ETH_HSI_VER_MINOR 10 40#define ETH_HSI_VER_MAJOR 3
41#define ETH_HSI_VER_MINOR 10
41 42
42#define ETH_HSI_VER_NO_PKT_LEN_TUNN 5 43#define ETH_HSI_VER_NO_PKT_LEN_TUNN 5
43 44
44#define ETH_CACHE_LINE_SIZE 64 45#define ETH_CACHE_LINE_SIZE 64
45#define ETH_RX_CQE_GAP 32 46#define ETH_RX_CQE_GAP 32
46#define ETH_MAX_RAMROD_PER_CON 8 47#define ETH_MAX_RAMROD_PER_CON 8
47#define ETH_TX_BD_PAGE_SIZE_BYTES 4096 48#define ETH_TX_BD_PAGE_SIZE_BYTES 4096
48#define ETH_RX_BD_PAGE_SIZE_BYTES 4096 49#define ETH_RX_BD_PAGE_SIZE_BYTES 4096
49#define ETH_RX_CQE_PAGE_SIZE_BYTES 4096 50#define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
50#define ETH_RX_NUM_NEXT_PAGE_BDS 2 51#define ETH_RX_NUM_NEXT_PAGE_BDS 2
51 52
52#define ETH_MAX_TUNN_LSO_INNER_IPV4_OFFSET 253 53#define ETH_MAX_TUNN_LSO_INNER_IPV4_OFFSET 253
53#define ETH_MAX_TUNN_LSO_INNER_IPV6_OFFSET 251 54#define ETH_MAX_TUNN_LSO_INNER_IPV6_OFFSET 251
54 55
55#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1 56#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
56#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18 57#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
57#define ETH_TX_MAX_BDS_PER_LSO_PACKET 255 58#define ETH_TX_MAX_BDS_PER_LSO_PACKET 255
58#define ETH_TX_MAX_LSO_HDR_NBD 4 59#define ETH_TX_MAX_LSO_HDR_NBD 4
59#define ETH_TX_MIN_BDS_PER_LSO_PKT 3 60#define ETH_TX_MIN_BDS_PER_LSO_PKT 3
60#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3 61#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
61#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2 62#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
62#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2 63#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
63#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8)) 64#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8))
64#define ETH_TX_MAX_LSO_HDR_BYTES 510 65#define ETH_TX_MAX_LSO_HDR_BYTES 510
65#define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1) 66#define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1)
66#define ETH_TX_LSO_WINDOW_MIN_LEN 9700 67#define ETH_TX_LSO_WINDOW_MIN_LEN 9700
67#define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000 68#define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000
68#define ETH_TX_NUM_SAME_AS_LAST_ENTRIES 320 69#define ETH_TX_NUM_SAME_AS_LAST_ENTRIES 320
69#define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF 70#define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF
70 71
71#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS 72#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
72#define ETH_NUM_STATISTIC_COUNTERS_DOUBLE_VF_ZONE \ 73#define ETH_NUM_STATISTIC_COUNTERS_DOUBLE_VF_ZONE \
73 (ETH_NUM_STATISTIC_COUNTERS - MAX_NUM_VFS / 2) 74 (ETH_NUM_STATISTIC_COUNTERS - MAX_NUM_VFS / 2)
74#define ETH_NUM_STATISTIC_COUNTERS_QUAD_VF_ZONE \ 75#define ETH_NUM_STATISTIC_COUNTERS_QUAD_VF_ZONE \
75 (ETH_NUM_STATISTIC_COUNTERS - 3 * MAX_NUM_VFS / 4) 76 (ETH_NUM_STATISTIC_COUNTERS - 3 * MAX_NUM_VFS / 4)
76 77
77/* Maximum number of buffers, used for RX packet placement */ 78/* Maximum number of buffers, used for RX packet placement */
78#define ETH_RX_MAX_BUFF_PER_PKT 5 79#define ETH_RX_MAX_BUFF_PER_PKT 5
79#define ETH_RX_BD_THRESHOLD 12 80#define ETH_RX_BD_THRESHOLD 12
80 81
81/* num of MAC/VLAN filters */ 82/* Num of MAC/VLAN filters */
82#define ETH_NUM_MAC_FILTERS 512 83#define ETH_NUM_MAC_FILTERS 512
83#define ETH_NUM_VLAN_FILTERS 512 84#define ETH_NUM_VLAN_FILTERS 512
84 85
85/* approx. multicast constants */ 86/* Approx. multicast constants */
86#define ETH_MULTICAST_BIN_FROM_MAC_SEED 0 87#define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
87#define ETH_MULTICAST_MAC_BINS 256 88#define ETH_MULTICAST_MAC_BINS 256
88#define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32) 89#define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
89 90
90/* ethernet vport update constants */ 91/* Ethernet vport update constants */
91#define ETH_FILTER_RULES_COUNT 10 92#define ETH_FILTER_RULES_COUNT 10
92#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128 93#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
93#define ETH_RSS_KEY_SIZE_REGS 10 94#define ETH_RSS_KEY_SIZE_REGS 10
94#define ETH_RSS_ENGINE_NUM_K2 207 95#define ETH_RSS_ENGINE_NUM_K2 207
95#define ETH_RSS_ENGINE_NUM_BB 127 96#define ETH_RSS_ENGINE_NUM_BB 127
96 97
97/* TPA constants */ 98/* TPA constants */
98#define ETH_TPA_MAX_AGGS_NUM 64 99#define ETH_TPA_MAX_AGGS_NUM 64
99#define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT 100#define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT
100#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6 101#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
101#define ETH_TPA_CQE_END_LEN_LIST_SIZE 4 102#define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
102 103
103/* Control frame check constants */ 104/* Control frame check constants */
104#define ETH_CTL_FRAME_ETH_TYPE_NUM 4 105#define ETH_CTL_FRAME_ETH_TYPE_NUM 4
105 106
107/* GFS constants */
108#define ETH_GFT_TRASH_CAN_VPORT 0x1FF
109
110/* Destination port mode */
111enum dest_port_mode {
112 DEST_PORT_PHY,
113 DEST_PORT_LOOPBACK,
114 DEST_PORT_PHY_LOOPBACK,
115 DEST_PORT_DROP,
116 MAX_DEST_PORT_MODE
117};
118
119/* Ethernet address type */
120enum eth_addr_type {
121 BROADCAST_ADDRESS,
122 MULTICAST_ADDRESS,
123 UNICAST_ADDRESS,
124 UNKNOWN_ADDRESS,
125 MAX_ETH_ADDR_TYPE
126};
127
106struct eth_tx_1st_bd_flags { 128struct eth_tx_1st_bd_flags {
107 u8 bitfields; 129 u8 bitfields;
108#define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1 130#define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
109#define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0 131#define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0
110#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1 132#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
111#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1 133#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
112#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1 134#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
113#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2 135#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2
114#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1 136#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
115#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3 137#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3
116#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1 138#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
117#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4 139#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4
118#define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1 140#define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
119#define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5 141#define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5
120#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1 142#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
121#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6 143#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6
122#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1 144#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
123#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7 145#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
124}; 146};
125 147
126/* The parsing information data fo rthe first tx bd of a given packet. */ 148/* The parsing information data fo rthe first tx bd of a given packet */
127struct eth_tx_data_1st_bd { 149struct eth_tx_data_1st_bd {
128 __le16 vlan; 150 __le16 vlan;
129 u8 nbds; 151 u8 nbds;
130 struct eth_tx_1st_bd_flags bd_flags; 152 struct eth_tx_1st_bd_flags bd_flags;
131 __le16 bitfields; 153 __le16 bitfields;
132#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1 154#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1
133#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0 155#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0
134#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1 156#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
135#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1 157#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1
136#define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK 0x3FFF 158#define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK 0x3FFF
137#define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2 159#define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2
138}; 160};
139 161
140/* The parsing information data for the second tx bd of a given packet. */ 162/* The parsing information data for the second tx bd of a given packet */
141struct eth_tx_data_2nd_bd { 163struct eth_tx_data_2nd_bd {
142 __le16 tunn_ip_size; 164 __le16 tunn_ip_size;
143 __le16 bitfields1; 165 __le16 bitfields1;
144#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF 166#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
145#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0 167#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
146#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3 168#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
147#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4 169#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
148#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3 170#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3
149#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6 171#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6
150#define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1 172#define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1
151#define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8 173#define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8
152#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3 174#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
153#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9 175#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9
154#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1 176#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1
155#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11 177#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11
156#define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1 178#define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1
157#define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12 179#define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12
158#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1 180#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1
159#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13 181#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13
160#define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1 182#define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1
161#define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14 183#define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14
162#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1 184#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1
163#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15 185#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15
164 __le16 bitfields2; 186 __le16 bitfields2;
165#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF 187#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF
166#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0 188#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0
167#define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7 189#define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7
168#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13 190#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
169}; 191};
170 192
171/* Firmware data for L2-EDPM packet. */ 193/* Firmware data for L2-EDPM packet */
172struct eth_edpm_fw_data { 194struct eth_edpm_fw_data {
173 struct eth_tx_data_1st_bd data_1st_bd; 195 struct eth_tx_data_1st_bd data_1st_bd;
174 struct eth_tx_data_2nd_bd data_2nd_bd; 196 struct eth_tx_data_2nd_bd data_2nd_bd;
175 __le32 reserved; 197 __le32 reserved;
176}; 198};
177 199
178struct eth_fast_path_cqe_fw_debug { 200/* Tunneling parsing flags */
179 __le16 reserved2;
180};
181
182/* tunneling parsing flags */
183struct eth_tunnel_parsing_flags { 201struct eth_tunnel_parsing_flags {
184 u8 flags; 202 u8 flags;
185#define ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3 203#define ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3
@@ -199,24 +217,24 @@ struct eth_tunnel_parsing_flags {
199/* PMD flow control bits */ 217/* PMD flow control bits */
200struct eth_pmd_flow_flags { 218struct eth_pmd_flow_flags {
201 u8 flags; 219 u8 flags;
202#define ETH_PMD_FLOW_FLAGS_VALID_MASK 0x1 220#define ETH_PMD_FLOW_FLAGS_VALID_MASK 0x1
203#define ETH_PMD_FLOW_FLAGS_VALID_SHIFT 0 221#define ETH_PMD_FLOW_FLAGS_VALID_SHIFT 0
204#define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK 0x1 222#define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK 0x1
205#define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT 1 223#define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT 1
206#define ETH_PMD_FLOW_FLAGS_RESERVED_MASK 0x3F 224#define ETH_PMD_FLOW_FLAGS_RESERVED_MASK 0x3F
207#define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2 225#define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2
208}; 226};
209 227
210/* Regular ETH Rx FP CQE. */ 228/* Regular ETH Rx FP CQE */
211struct eth_fast_path_rx_reg_cqe { 229struct eth_fast_path_rx_reg_cqe {
212 u8 type; 230 u8 type;
213 u8 bitfields; 231 u8 bitfields;
214#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7 232#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7
215#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0 233#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
216#define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF 234#define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF
217#define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3 235#define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3
218#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1 236#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
219#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7 237#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
220 __le16 pkt_len; 238 __le16 pkt_len;
221 struct parsing_and_err_flags pars_flags; 239 struct parsing_and_err_flags pars_flags;
222 __le16 vlan_tag; 240 __le16 vlan_tag;
@@ -225,13 +243,13 @@ struct eth_fast_path_rx_reg_cqe {
225 u8 placement_offset; 243 u8 placement_offset;
226 struct eth_tunnel_parsing_flags tunnel_pars_flags; 244 struct eth_tunnel_parsing_flags tunnel_pars_flags;
227 u8 bd_num; 245 u8 bd_num;
228 u8 reserved[9]; 246 u8 reserved;
229 struct eth_fast_path_cqe_fw_debug fw_debug; 247 __le16 flow_id;
230 u8 reserved1[3]; 248 u8 reserved1[11];
231 struct eth_pmd_flow_flags pmd_flags; 249 struct eth_pmd_flow_flags pmd_flags;
232}; 250};
233 251
234/* TPA-continue ETH Rx FP CQE. */ 252/* TPA-continue ETH Rx FP CQE */
235struct eth_fast_path_rx_tpa_cont_cqe { 253struct eth_fast_path_rx_tpa_cont_cqe {
236 u8 type; 254 u8 type;
237 u8 tpa_agg_index; 255 u8 tpa_agg_index;
@@ -243,7 +261,7 @@ struct eth_fast_path_rx_tpa_cont_cqe {
243 struct eth_pmd_flow_flags pmd_flags; 261 struct eth_pmd_flow_flags pmd_flags;
244}; 262};
245 263
246/* TPA-end ETH Rx FP CQE. */ 264/* TPA-end ETH Rx FP CQE */
247struct eth_fast_path_rx_tpa_end_cqe { 265struct eth_fast_path_rx_tpa_end_cqe {
248 u8 type; 266 u8 type;
249 u8 tpa_agg_index; 267 u8 tpa_agg_index;
@@ -259,16 +277,16 @@ struct eth_fast_path_rx_tpa_end_cqe {
259 struct eth_pmd_flow_flags pmd_flags; 277 struct eth_pmd_flow_flags pmd_flags;
260}; 278};
261 279
262/* TPA-start ETH Rx FP CQE. */ 280/* TPA-start ETH Rx FP CQE */
263struct eth_fast_path_rx_tpa_start_cqe { 281struct eth_fast_path_rx_tpa_start_cqe {
264 u8 type; 282 u8 type;
265 u8 bitfields; 283 u8 bitfields;
266#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7 284#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7
267#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0 285#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
268#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF 286#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF
269#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3 287#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3
270#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1 288#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1
271#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7 289#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7
272 __le16 seg_len; 290 __le16 seg_len;
273 struct parsing_and_err_flags pars_flags; 291 struct parsing_and_err_flags pars_flags;
274 __le16 vlan_tag; 292 __le16 vlan_tag;
@@ -279,7 +297,7 @@ struct eth_fast_path_rx_tpa_start_cqe {
279 u8 tpa_agg_index; 297 u8 tpa_agg_index;
280 u8 header_len; 298 u8 header_len;
281 __le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE]; 299 __le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE];
282 struct eth_fast_path_cqe_fw_debug fw_debug; 300 __le16 flow_id;
283 u8 reserved; 301 u8 reserved;
284 struct eth_pmd_flow_flags pmd_flags; 302 struct eth_pmd_flow_flags pmd_flags;
285}; 303};
@@ -295,24 +313,24 @@ struct eth_rx_bd {
295 struct regpair addr; 313 struct regpair addr;
296}; 314};
297 315
298/* regular ETH Rx SP CQE */ 316/* Regular ETH Rx SP CQE */
299struct eth_slow_path_rx_cqe { 317struct eth_slow_path_rx_cqe {
300 u8 type; 318 u8 type;
301 u8 ramrod_cmd_id; 319 u8 ramrod_cmd_id;
302 u8 error_flag; 320 u8 error_flag;
303 u8 reserved[25]; 321 u8 reserved[25];
304 __le16 echo; 322 __le16 echo;
305 u8 reserved1; 323 u8 reserved1;
306 struct eth_pmd_flow_flags pmd_flags; 324 struct eth_pmd_flow_flags pmd_flags;
307}; 325};
308 326
309/* union for all ETH Rx CQE types */ 327/* Union for all ETH Rx CQE types */
310union eth_rx_cqe { 328union eth_rx_cqe {
311 struct eth_fast_path_rx_reg_cqe fast_path_regular; 329 struct eth_fast_path_rx_reg_cqe fast_path_regular;
312 struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start; 330 struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start;
313 struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont; 331 struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont;
314 struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end; 332 struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end;
315 struct eth_slow_path_rx_cqe slow_path; 333 struct eth_slow_path_rx_cqe slow_path;
316}; 334};
317 335
318/* ETH Rx CQE type */ 336/* ETH Rx CQE type */
@@ -339,7 +357,7 @@ enum eth_rx_tunn_type {
339 MAX_ETH_RX_TUNN_TYPE 357 MAX_ETH_RX_TUNN_TYPE
340}; 358};
341 359
342/* Aggregation end reason. */ 360/* Aggregation end reason. */
343enum eth_tpa_end_reason { 361enum eth_tpa_end_reason {
344 ETH_AGG_END_UNUSED, 362 ETH_AGG_END_UNUSED,
345 ETH_AGG_END_SP_UPDATE, 363 ETH_AGG_END_SP_UPDATE,
@@ -354,59 +372,59 @@ enum eth_tpa_end_reason {
354 372
355/* The first tx bd of a given packet */ 373/* The first tx bd of a given packet */
356struct eth_tx_1st_bd { 374struct eth_tx_1st_bd {
357 struct regpair addr; 375 struct regpair addr;
358 __le16 nbytes; 376 __le16 nbytes;
359 struct eth_tx_data_1st_bd data; 377 struct eth_tx_data_1st_bd data;
360}; 378};
361 379
362/* The second tx bd of a given packet */ 380/* The second tx bd of a given packet */
363struct eth_tx_2nd_bd { 381struct eth_tx_2nd_bd {
364 struct regpair addr; 382 struct regpair addr;
365 __le16 nbytes; 383 __le16 nbytes;
366 struct eth_tx_data_2nd_bd data; 384 struct eth_tx_data_2nd_bd data;
367}; 385};
368 386
369/* The parsing information data for the third tx bd of a given packet. */ 387/* The parsing information data for the third tx bd of a given packet */
370struct eth_tx_data_3rd_bd { 388struct eth_tx_data_3rd_bd {
371 __le16 lso_mss; 389 __le16 lso_mss;
372 __le16 bitfields; 390 __le16 bitfields;
373#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF 391#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
374#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0 392#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
375#define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF 393#define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
376#define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4 394#define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4
377#define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1 395#define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1
378#define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8 396#define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8
379#define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F 397#define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F
380#define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9 398#define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9
381 u8 tunn_l4_hdr_start_offset_w; 399 u8 tunn_l4_hdr_start_offset_w;
382 u8 tunn_hdr_size_w; 400 u8 tunn_hdr_size_w;
383}; 401};
384 402
385/* The third tx bd of a given packet */ 403/* The third tx bd of a given packet */
386struct eth_tx_3rd_bd { 404struct eth_tx_3rd_bd {
387 struct regpair addr; 405 struct regpair addr;
388 __le16 nbytes; 406 __le16 nbytes;
389 struct eth_tx_data_3rd_bd data; 407 struct eth_tx_data_3rd_bd data;
390}; 408};
391 409
392/* Complementary information for the regular tx bd of a given packet. */ 410/* Complementary information for the regular tx bd of a given packet */
393struct eth_tx_data_bd { 411struct eth_tx_data_bd {
394 __le16 reserved0; 412 __le16 reserved0;
395 __le16 bitfields; 413 __le16 bitfields;
396#define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF 414#define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF
397#define ETH_TX_DATA_BD_RESERVED1_SHIFT 0 415#define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
398#define ETH_TX_DATA_BD_START_BD_MASK 0x1 416#define ETH_TX_DATA_BD_START_BD_MASK 0x1
399#define ETH_TX_DATA_BD_START_BD_SHIFT 8 417#define ETH_TX_DATA_BD_START_BD_SHIFT 8
400#define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F 418#define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F
401#define ETH_TX_DATA_BD_RESERVED2_SHIFT 9 419#define ETH_TX_DATA_BD_RESERVED2_SHIFT 9
402 __le16 reserved3; 420 __le16 reserved3;
403}; 421};
404 422
405/* The common non-special TX BD ring element */ 423/* The common non-special TX BD ring element */
406struct eth_tx_bd { 424struct eth_tx_bd {
407 struct regpair addr; 425 struct regpair addr;
408 __le16 nbytes; 426 __le16 nbytes;
409 struct eth_tx_data_bd data; 427 struct eth_tx_data_bd data;
410}; 428};
411 429
412union eth_tx_bd_types { 430union eth_tx_bd_types {
@@ -434,18 +452,30 @@ struct xstorm_eth_queue_zone {
434/* ETH doorbell data */ 452/* ETH doorbell data */
435struct eth_db_data { 453struct eth_db_data {
436 u8 params; 454 u8 params;
437#define ETH_DB_DATA_DEST_MASK 0x3 455#define ETH_DB_DATA_DEST_MASK 0x3
438#define ETH_DB_DATA_DEST_SHIFT 0 456#define ETH_DB_DATA_DEST_SHIFT 0
439#define ETH_DB_DATA_AGG_CMD_MASK 0x3 457#define ETH_DB_DATA_AGG_CMD_MASK 0x3
440#define ETH_DB_DATA_AGG_CMD_SHIFT 2 458#define ETH_DB_DATA_AGG_CMD_SHIFT 2
441#define ETH_DB_DATA_BYPASS_EN_MASK 0x1 459#define ETH_DB_DATA_BYPASS_EN_MASK 0x1
442#define ETH_DB_DATA_BYPASS_EN_SHIFT 4 460#define ETH_DB_DATA_BYPASS_EN_SHIFT 4
443#define ETH_DB_DATA_RESERVED_MASK 0x1 461#define ETH_DB_DATA_RESERVED_MASK 0x1
444#define ETH_DB_DATA_RESERVED_SHIFT 5 462#define ETH_DB_DATA_RESERVED_SHIFT 5
445#define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3 463#define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
446#define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6 464#define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
447 u8 agg_flags; 465 u8 agg_flags;
448 __le16 bd_prod; 466 __le16 bd_prod;
449}; 467};
450 468
469/* RSS hash type */
470enum rss_hash_type {
471 RSS_HASH_TYPE_DEFAULT = 0,
472 RSS_HASH_TYPE_IPV4 = 1,
473 RSS_HASH_TYPE_TCP_IPV4 = 2,
474 RSS_HASH_TYPE_IPV6 = 3,
475 RSS_HASH_TYPE_TCP_IPV6 = 4,
476 RSS_HASH_TYPE_UDP_IPV4 = 5,
477 RSS_HASH_TYPE_UDP_IPV6 = 6,
478 MAX_RSS_HASH_TYPE
479};
480
451#endif /* __ETH_COMMON__ */ 481#endif /* __ETH_COMMON__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-27 10:14:58 -0400