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-rw-r--r--include/linux/qed/common_hsi.h1264
1 files changed, 629 insertions, 635 deletions
diff --git a/include/linux/qed/common_hsi.h b/include/linux/qed/common_hsi.h
index 39e2a2ac2471..2b3b350e07b7 100644
--- a/include/linux/qed/common_hsi.h
+++ b/include/linux/qed/common_hsi.h
@@ -32,14 +32,15 @@
32 32
33#ifndef _COMMON_HSI_H 33#ifndef _COMMON_HSI_H
34#define _COMMON_HSI_H 34#define _COMMON_HSI_H
35
35#include <linux/types.h> 36#include <linux/types.h>
36#include <asm/byteorder.h> 37#include <asm/byteorder.h>
37#include <linux/bitops.h> 38#include <linux/bitops.h>
38#include <linux/slab.h> 39#include <linux/slab.h>
39 40
40/* dma_addr_t manip */ 41/* dma_addr_t manip */
41#define PTR_LO(x) ((u32)(((uintptr_t)(x)) & 0xffffffff)) 42#define PTR_LO(x) ((u32)(((uintptr_t)(x)) & 0xffffffff))
42#define PTR_HI(x) ((u32)((((uintptr_t)(x)) >> 16) >> 16)) 43#define PTR_HI(x) ((u32)((((uintptr_t)(x)) >> 16) >> 16))
43#define DMA_LO_LE(x) cpu_to_le32(lower_32_bits(x)) 44#define DMA_LO_LE(x) cpu_to_le32(lower_32_bits(x))
44#define DMA_HI_LE(x) cpu_to_le32(upper_32_bits(x)) 45#define DMA_HI_LE(x) cpu_to_le32(upper_32_bits(x))
45#define DMA_REGPAIR_LE(x, val) do { \ 46#define DMA_REGPAIR_LE(x, val) do { \
@@ -47,39 +48,45 @@
47 (x).lo = DMA_LO_LE((val)); \ 48 (x).lo = DMA_LO_LE((val)); \
48 } while (0) 49 } while (0)
49 50
50#define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo)) 51#define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo))
51#define HILO_64(hi, lo) HILO_GEN((le32_to_cpu(hi)), (le32_to_cpu(lo)), u64) 52#define HILO_64(hi, lo) \
52#define HILO_64_REGPAIR(regpair) (HILO_64(regpair.hi, regpair.lo)) 53 HILO_GEN(le32_to_cpu(hi), le32_to_cpu(lo), u64)
54#define HILO_64_REGPAIR(regpair) ({ \
55 typeof(regpair) __regpair = (regpair); \
56 HILO_64(__regpair.hi, __regpair.lo); })
53#define HILO_DMA_REGPAIR(regpair) ((dma_addr_t)HILO_64_REGPAIR(regpair)) 57#define HILO_DMA_REGPAIR(regpair) ((dma_addr_t)HILO_64_REGPAIR(regpair))
54 58
55#ifndef __COMMON_HSI__ 59#ifndef __COMMON_HSI__
56#define __COMMON_HSI__ 60#define __COMMON_HSI__
57 61
62/********************************/
63/* PROTOCOL COMMON FW CONSTANTS */
64/********************************/
58 65
59#define X_FINAL_CLEANUP_AGG_INT 1 66#define X_FINAL_CLEANUP_AGG_INT 1
60 67
61#define EVENT_RING_PAGE_SIZE_BYTES 4096 68#define EVENT_RING_PAGE_SIZE_BYTES 4096
62 69
63#define NUM_OF_GLOBAL_QUEUES 128 70#define NUM_OF_GLOBAL_QUEUES 128
64#define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64 71#define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64
65 72
66#define ISCSI_CDU_TASK_SEG_TYPE 0 73#define ISCSI_CDU_TASK_SEG_TYPE 0
67#define FCOE_CDU_TASK_SEG_TYPE 0 74#define FCOE_CDU_TASK_SEG_TYPE 0
68#define RDMA_CDU_TASK_SEG_TYPE 1 75#define RDMA_CDU_TASK_SEG_TYPE 1
69 76
70#define FW_ASSERT_GENERAL_ATTN_IDX 32 77#define FW_ASSERT_GENERAL_ATTN_IDX 32
71 78
72#define MAX_PINNED_CCFC 32 79#define MAX_PINNED_CCFC 32
73 80
74/* Queue Zone sizes in bytes */ 81/* Queue Zone sizes in bytes */
75#define TSTORM_QZONE_SIZE 8 82#define TSTORM_QZONE_SIZE 8
76#define MSTORM_QZONE_SIZE 16 83#define MSTORM_QZONE_SIZE 16
77#define USTORM_QZONE_SIZE 8 84#define USTORM_QZONE_SIZE 8
78#define XSTORM_QZONE_SIZE 8 85#define XSTORM_QZONE_SIZE 8
79#define YSTORM_QZONE_SIZE 0 86#define YSTORM_QZONE_SIZE 0
80#define PSTORM_QZONE_SIZE 0 87#define PSTORM_QZONE_SIZE 0
81 88
82#define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7 89#define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7
83#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16 90#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16
84#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48 91#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48
85#define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112 92#define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112
@@ -102,8 +109,8 @@
102#define MAX_NUM_LL2_TX_STATS_COUNTERS 48 109#define MAX_NUM_LL2_TX_STATS_COUNTERS 48
103 110
104#define FW_MAJOR_VERSION 8 111#define FW_MAJOR_VERSION 8
105#define FW_MINOR_VERSION 20 112#define FW_MINOR_VERSION 33
106#define FW_REVISION_VERSION 0 113#define FW_REVISION_VERSION 1
107#define FW_ENGINEERING_VERSION 0 114#define FW_ENGINEERING_VERSION 0
108 115
109/***********************/ 116/***********************/
@@ -115,10 +122,10 @@
115#define MAX_NUM_PORTS_BB (2) 122#define MAX_NUM_PORTS_BB (2)
116#define MAX_NUM_PORTS (MAX_NUM_PORTS_K2) 123#define MAX_NUM_PORTS (MAX_NUM_PORTS_K2)
117 124
118#define MAX_NUM_PFS_K2 (16) 125#define MAX_NUM_PFS_K2 (16)
119#define MAX_NUM_PFS_BB (8) 126#define MAX_NUM_PFS_BB (8)
120#define MAX_NUM_PFS (MAX_NUM_PFS_K2) 127#define MAX_NUM_PFS (MAX_NUM_PFS_K2)
121#define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ 128#define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */
122 129
123#define MAX_NUM_VFS_K2 (192) 130#define MAX_NUM_VFS_K2 (192)
124#define MAX_NUM_VFS_BB (120) 131#define MAX_NUM_VFS_BB (120)
@@ -141,29 +148,14 @@
141/* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ 148/* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */
142#define NUM_PHYS_TCS_4PORT_K2 (4) 149#define NUM_PHYS_TCS_4PORT_K2 (4)
143#define NUM_OF_PHYS_TCS (8) 150#define NUM_OF_PHYS_TCS (8)
144 151#define PURE_LB_TC NUM_OF_PHYS_TCS
145#define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) 152#define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1)
146#define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) 153#define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1)
147 154
148#define LB_TC (NUM_OF_PHYS_TCS)
149
150/* Num of possible traffic priority values */
151#define NUM_OF_PRIO (8)
152
153#define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2)
154#define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB)
155#define MAX_NUM_VOQS (MAX_NUM_VOQS_K2)
156#define MAX_PHYS_VOQS (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB)
157
158/* CIDs */ 155/* CIDs */
159#define NUM_OF_CONNECTION_TYPES (8) 156#define NUM_OF_CONNECTION_TYPES_E4 (8)
160#define NUM_OF_LCIDS (320) 157#define NUM_OF_LCIDS (320)
161#define NUM_OF_LTIDS (320) 158#define NUM_OF_LTIDS (320)
162
163/* Clock values */
164#define MASTER_CLK_FREQ_E4 (375e6)
165#define STORM_CLK_FREQ_E4 (1000e6)
166#define CLK25M_CLK_FREQ_E4 (25e6)
167 159
168/* Global PXP windows (GTT) */ 160/* Global PXP windows (GTT) */
169#define NUM_OF_GTT 19 161#define NUM_OF_GTT 19
@@ -172,17 +164,17 @@
172#define GTT_DWORD_SIZE BIT(GTT_DWORD_SIZE_BITS) 164#define GTT_DWORD_SIZE BIT(GTT_DWORD_SIZE_BITS)
173 165
174/* Tools Version */ 166/* Tools Version */
175#define TOOLS_VERSION 10 167#define TOOLS_VERSION 10
176 168
177/*****************/ 169/*****************/
178/* CDU CONSTANTS */ 170/* CDU CONSTANTS */
179/*****************/ 171/*****************/
180 172
181#define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17) 173#define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17)
182#define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff) 174#define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
183 175
184#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12) 176#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12)
185#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff) 177#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
186 178
187#define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0) 179#define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0)
188#define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT (1) 180#define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT (1)
@@ -201,45 +193,45 @@
201#define DQ_DEMS_TOE_LOCAL_ADV_WND 4 193#define DQ_DEMS_TOE_LOCAL_ADV_WND 4
202#define DQ_DEMS_ROCE_CQ_CONS 7 194#define DQ_DEMS_ROCE_CQ_CONS 7
203 195
204/* XCM agg val selection */ 196/* XCM agg val selection (HW) */
205#define DQ_XCM_AGG_VAL_SEL_WORD2 0 197#define DQ_XCM_AGG_VAL_SEL_WORD2 0
206#define DQ_XCM_AGG_VAL_SEL_WORD3 1 198#define DQ_XCM_AGG_VAL_SEL_WORD3 1
207#define DQ_XCM_AGG_VAL_SEL_WORD4 2 199#define DQ_XCM_AGG_VAL_SEL_WORD4 2
208#define DQ_XCM_AGG_VAL_SEL_WORD5 3 200#define DQ_XCM_AGG_VAL_SEL_WORD5 3
209#define DQ_XCM_AGG_VAL_SEL_REG3 4 201#define DQ_XCM_AGG_VAL_SEL_REG3 4
210#define DQ_XCM_AGG_VAL_SEL_REG4 5 202#define DQ_XCM_AGG_VAL_SEL_REG4 5
211#define DQ_XCM_AGG_VAL_SEL_REG5 6 203#define DQ_XCM_AGG_VAL_SEL_REG5 6
212#define DQ_XCM_AGG_VAL_SEL_REG6 7 204#define DQ_XCM_AGG_VAL_SEL_REG6 7
213 205
214/* XCM agg val selection */ 206/* XCM agg val selection (FW) */
215#define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 207#define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
216#define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 208#define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
217#define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 209#define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
218#define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2 210#define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2
219#define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 211#define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
220#define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 212#define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
221#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5 213#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5
222#define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 214#define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
223#define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 215#define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
224#define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5 216#define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5
225#define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 217#define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
226#define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 218#define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
227#define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 219#define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
228#define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6 220#define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6
229#define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 221#define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
230#define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 222#define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
231#define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 223#define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
232#define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4 224#define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4
233 225
234/* UCM agg val selection (HW) */ 226/* UCM agg val selection (HW) */
235#define DQ_UCM_AGG_VAL_SEL_WORD0 0 227#define DQ_UCM_AGG_VAL_SEL_WORD0 0
236#define DQ_UCM_AGG_VAL_SEL_WORD1 1 228#define DQ_UCM_AGG_VAL_SEL_WORD1 1
237#define DQ_UCM_AGG_VAL_SEL_WORD2 2 229#define DQ_UCM_AGG_VAL_SEL_WORD2 2
238#define DQ_UCM_AGG_VAL_SEL_WORD3 3 230#define DQ_UCM_AGG_VAL_SEL_WORD3 3
239#define DQ_UCM_AGG_VAL_SEL_REG0 4 231#define DQ_UCM_AGG_VAL_SEL_REG0 4
240#define DQ_UCM_AGG_VAL_SEL_REG1 5 232#define DQ_UCM_AGG_VAL_SEL_REG1 5
241#define DQ_UCM_AGG_VAL_SEL_REG2 6 233#define DQ_UCM_AGG_VAL_SEL_REG2 6
242#define DQ_UCM_AGG_VAL_SEL_REG3 7 234#define DQ_UCM_AGG_VAL_SEL_REG3 7
243 235
244/* UCM agg val selection (FW) */ 236/* UCM agg val selection (FW) */
245#define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2 237#define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2
@@ -263,7 +255,7 @@
263#define DQ_TCM_ROCE_RQ_PROD_CMD \ 255#define DQ_TCM_ROCE_RQ_PROD_CMD \
264 DQ_TCM_AGG_VAL_SEL_WORD0 256 DQ_TCM_AGG_VAL_SEL_WORD0
265 257
266/* XCM agg counter flag selection */ 258/* XCM agg counter flag selection (HW) */
267#define DQ_XCM_AGG_FLG_SHIFT_BIT14 0 259#define DQ_XCM_AGG_FLG_SHIFT_BIT14 0
268#define DQ_XCM_AGG_FLG_SHIFT_BIT15 1 260#define DQ_XCM_AGG_FLG_SHIFT_BIT15 1
269#define DQ_XCM_AGG_FLG_SHIFT_CF12 2 261#define DQ_XCM_AGG_FLG_SHIFT_CF12 2
@@ -273,20 +265,20 @@
273#define DQ_XCM_AGG_FLG_SHIFT_CF22 6 265#define DQ_XCM_AGG_FLG_SHIFT_CF22 6
274#define DQ_XCM_AGG_FLG_SHIFT_CF23 7 266#define DQ_XCM_AGG_FLG_SHIFT_CF23 7
275 267
276/* XCM agg counter flag selection */ 268/* XCM agg counter flag selection (FW) */
277#define DQ_XCM_CORE_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18) 269#define DQ_XCM_CORE_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
278#define DQ_XCM_CORE_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 270#define DQ_XCM_CORE_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
279#define DQ_XCM_CORE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 271#define DQ_XCM_CORE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
280#define DQ_XCM_ETH_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18) 272#define DQ_XCM_ETH_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
281#define DQ_XCM_ETH_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 273#define DQ_XCM_ETH_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
282#define DQ_XCM_ETH_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 274#define DQ_XCM_ETH_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
283#define DQ_XCM_ETH_TPH_EN_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23) 275#define DQ_XCM_ETH_TPH_EN_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
284#define DQ_XCM_FCOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 276#define DQ_XCM_FCOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
285#define DQ_XCM_ISCSI_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 277#define DQ_XCM_ISCSI_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
286#define DQ_XCM_ISCSI_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 278#define DQ_XCM_ISCSI_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
287#define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23) 279#define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
288#define DQ_XCM_TOE_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19) 280#define DQ_XCM_TOE_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
289#define DQ_XCM_TOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22) 281#define DQ_XCM_TOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
290 282
291/* UCM agg counter flag selection (HW) */ 283/* UCM agg counter flag selection (HW) */
292#define DQ_UCM_AGG_FLG_SHIFT_CF0 0 284#define DQ_UCM_AGG_FLG_SHIFT_CF0 0
@@ -317,9 +309,9 @@
317#define DQ_TCM_AGG_FLG_SHIFT_CF6 6 309#define DQ_TCM_AGG_FLG_SHIFT_CF6 6
318#define DQ_TCM_AGG_FLG_SHIFT_CF7 7 310#define DQ_TCM_AGG_FLG_SHIFT_CF7 7
319/* TCM agg counter flag selection (FW) */ 311/* TCM agg counter flag selection (FW) */
320#define DQ_TCM_FCOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) 312#define DQ_TCM_FCOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
321#define DQ_TCM_FCOE_DUMMY_TIMER_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF2) 313#define DQ_TCM_FCOE_DUMMY_TIMER_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF2)
322#define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3) 314#define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
323#define DQ_TCM_ISCSI_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) 315#define DQ_TCM_ISCSI_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
324#define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3) 316#define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
325#define DQ_TCM_TOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) 317#define DQ_TCM_TOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
@@ -327,18 +319,18 @@
327#define DQ_TCM_IWARP_POST_RQ_CF_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1) 319#define DQ_TCM_IWARP_POST_RQ_CF_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
328 320
329/* PWM address mapping */ 321/* PWM address mapping */
330#define DQ_PWM_OFFSET_DPM_BASE 0x0 322#define DQ_PWM_OFFSET_DPM_BASE 0x0
331#define DQ_PWM_OFFSET_DPM_END 0x27 323#define DQ_PWM_OFFSET_DPM_END 0x27
332#define DQ_PWM_OFFSET_XCM16_BASE 0x40 324#define DQ_PWM_OFFSET_XCM16_BASE 0x40
333#define DQ_PWM_OFFSET_XCM32_BASE 0x44 325#define DQ_PWM_OFFSET_XCM32_BASE 0x44
334#define DQ_PWM_OFFSET_UCM16_BASE 0x48 326#define DQ_PWM_OFFSET_UCM16_BASE 0x48
335#define DQ_PWM_OFFSET_UCM32_BASE 0x4C 327#define DQ_PWM_OFFSET_UCM32_BASE 0x4C
336#define DQ_PWM_OFFSET_UCM16_4 0x50 328#define DQ_PWM_OFFSET_UCM16_4 0x50
337#define DQ_PWM_OFFSET_TCM16_BASE 0x58 329#define DQ_PWM_OFFSET_TCM16_BASE 0x58
338#define DQ_PWM_OFFSET_TCM32_BASE 0x5C 330#define DQ_PWM_OFFSET_TCM32_BASE 0x5C
339#define DQ_PWM_OFFSET_XCM_FLAGS 0x68 331#define DQ_PWM_OFFSET_XCM_FLAGS 0x68
340#define DQ_PWM_OFFSET_UCM_FLAGS 0x69 332#define DQ_PWM_OFFSET_UCM_FLAGS 0x69
341#define DQ_PWM_OFFSET_TCM_FLAGS 0x6B 333#define DQ_PWM_OFFSET_TCM_FLAGS 0x6B
342 334
343#define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2) 335#define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2)
344#define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE) 336#define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE)
@@ -347,10 +339,11 @@
347#define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS) 339#define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS)
348#define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1) 340#define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1)
349#define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3) 341#define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3)
350#define DQ_REGION_SHIFT (12) 342
343#define DQ_REGION_SHIFT (12)
351 344
352/* DPM */ 345/* DPM */
353#define DQ_DPM_WQE_BUFF_SIZE (320) 346#define DQ_DPM_WQE_BUFF_SIZE (320)
354 347
355/* Conn type ranges */ 348/* Conn type ranges */
356#define DQ_CONN_TYPE_RANGE_SHIFT (4) 349#define DQ_CONN_TYPE_RANGE_SHIFT (4)
@@ -359,29 +352,30 @@
359/* QM CONSTANTS */ 352/* QM CONSTANTS */
360/*****************/ 353/*****************/
361 354
362/* number of TX queues in the QM */ 355/* Number of TX queues in the QM */
363#define MAX_QM_TX_QUEUES_K2 512 356#define MAX_QM_TX_QUEUES_K2 512
364#define MAX_QM_TX_QUEUES_BB 448 357#define MAX_QM_TX_QUEUES_BB 448
365#define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2 358#define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2
366 359
367/* number of Other queues in the QM */ 360/* Number of Other queues in the QM */
368#define MAX_QM_OTHER_QUEUES_BB 64 361#define MAX_QM_OTHER_QUEUES_BB 64
369#define MAX_QM_OTHER_QUEUES_K2 128 362#define MAX_QM_OTHER_QUEUES_K2 128
370#define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2 363#define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2
371 364
372/* number of queues in a PF queue group */ 365/* Number of queues in a PF queue group */
373#define QM_PF_QUEUE_GROUP_SIZE 8 366#define QM_PF_QUEUE_GROUP_SIZE 8
374 367
375/* the size of a single queue element in bytes */ 368/* The size of a single queue element in bytes */
376#define QM_PQ_ELEMENT_SIZE 4 369#define QM_PQ_ELEMENT_SIZE 4
377 370
378/* base number of Tx PQs in the CM PQ representation. 371/* Base number of Tx PQs in the CM PQ representation.
379 * should be used when storing PQ IDs in CM PQ registers and context 372 * Should be used when storing PQ IDs in CM PQ registers and context.
380 */ 373 */
381#define CM_TX_PQ_BASE 0x200 374#define CM_TX_PQ_BASE 0x200
382 375
383/* number of global Vport/QCN rate limiters */ 376/* Number of global Vport/QCN rate limiters */
384#define MAX_QM_GLOBAL_RLS 256 377#define MAX_QM_GLOBAL_RLS 256
378
385/* QM registers data */ 379/* QM registers data */
386#define QM_LINE_CRD_REG_WIDTH 16 380#define QM_LINE_CRD_REG_WIDTH 16
387#define QM_LINE_CRD_REG_SIGN_BIT BIT((QM_LINE_CRD_REG_WIDTH - 1)) 381#define QM_LINE_CRD_REG_SIGN_BIT BIT((QM_LINE_CRD_REG_WIDTH - 1))
@@ -400,7 +394,7 @@
400#define CAU_FSM_ETH_TX 1 394#define CAU_FSM_ETH_TX 1
401 395
402/* Number of Protocol Indices per Status Block */ 396/* Number of Protocol Indices per Status Block */
403#define PIS_PER_SB 12 397#define PIS_PER_SB_E4 12
404 398
405#define CAU_HC_STOPPED_STATE 3 399#define CAU_HC_STOPPED_STATE 3
406#define CAU_HC_DISABLE_STATE 4 400#define CAU_HC_DISABLE_STATE 4
@@ -432,8 +426,7 @@
432 426
433#define IGU_CMD_INT_ACK_BASE 0x0400 427#define IGU_CMD_INT_ACK_BASE 0x0400
434#define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \ 428#define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \
435 MAX_TOT_SB_PER_PATH - \ 429 MAX_TOT_SB_PER_PATH - 1)
436 1)
437#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff 430#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff
438 431
439#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0 432#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0
@@ -447,8 +440,7 @@
447 440
448#define IGU_CMD_PROD_UPD_BASE 0x0600 441#define IGU_CMD_PROD_UPD_BASE 0x0600
449#define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE +\ 442#define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE +\
450 MAX_TOT_SB_PER_PATH - \ 443 MAX_TOT_SB_PER_PATH - 1)
451 1)
452#define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff 444#define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff
453 445
454/*****************/ 446/*****************/
@@ -514,129 +506,126 @@
514 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1) 506 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1)
515 507
516/* PF BAR */ 508/* PF BAR */
517#define PXP_BAR0_START_GRC 0x0000 509#define PXP_BAR0_START_GRC 0x0000
518#define PXP_BAR0_GRC_LENGTH 0x1C00000 510#define PXP_BAR0_GRC_LENGTH 0x1C00000
519#define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + \ 511#define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + \
520 PXP_BAR0_GRC_LENGTH - 1) 512 PXP_BAR0_GRC_LENGTH - 1)
521 513
522#define PXP_BAR0_START_IGU 0x1C00000 514#define PXP_BAR0_START_IGU 0x1C00000
523#define PXP_BAR0_IGU_LENGTH 0x10000 515#define PXP_BAR0_IGU_LENGTH 0x10000
524#define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + \ 516#define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + \
525 PXP_BAR0_IGU_LENGTH - 1) 517 PXP_BAR0_IGU_LENGTH - 1)
526 518
527#define PXP_BAR0_START_TSDM 0x1C80000 519#define PXP_BAR0_START_TSDM 0x1C80000
528#define PXP_BAR0_SDM_LENGTH 0x40000 520#define PXP_BAR0_SDM_LENGTH 0x40000
529#define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000 521#define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000
530#define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + \ 522#define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + \
531 PXP_BAR0_SDM_LENGTH - 1) 523 PXP_BAR0_SDM_LENGTH - 1)
532 524
533#define PXP_BAR0_START_MSDM 0x1D00000 525#define PXP_BAR0_START_MSDM 0x1D00000
534#define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + \ 526#define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + \
535 PXP_BAR0_SDM_LENGTH - 1) 527 PXP_BAR0_SDM_LENGTH - 1)
536 528
537#define PXP_BAR0_START_USDM 0x1D80000 529#define PXP_BAR0_START_USDM 0x1D80000
538#define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + \ 530#define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + \
539 PXP_BAR0_SDM_LENGTH - 1) 531 PXP_BAR0_SDM_LENGTH - 1)
540 532
541#define PXP_BAR0_START_XSDM 0x1E00000 533#define PXP_BAR0_START_XSDM 0x1E00000
542#define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + \ 534#define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + \
543 PXP_BAR0_SDM_LENGTH - 1) 535 PXP_BAR0_SDM_LENGTH - 1)
544 536
545#define PXP_BAR0_START_YSDM 0x1E80000 537#define PXP_BAR0_START_YSDM 0x1E80000
546#define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + \ 538#define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + \
547 PXP_BAR0_SDM_LENGTH - 1) 539 PXP_BAR0_SDM_LENGTH - 1)
548 540
549#define PXP_BAR0_START_PSDM 0x1F00000 541#define PXP_BAR0_START_PSDM 0x1F00000
550#define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + \ 542#define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + \
551 PXP_BAR0_SDM_LENGTH - 1) 543 PXP_BAR0_SDM_LENGTH - 1)
552 544
553#define PXP_BAR0_FIRST_INVALID_ADDRESS (PXP_BAR0_END_PSDM + 1) 545#define PXP_BAR0_FIRST_INVALID_ADDRESS (PXP_BAR0_END_PSDM + 1)
554 546
555/* VF BAR */ 547/* VF BAR */
556#define PXP_VF_BAR0 0 548#define PXP_VF_BAR0 0
557 549
558#define PXP_VF_BAR0_START_GRC 0x3E00 550#define PXP_VF_BAR0_START_IGU 0
559#define PXP_VF_BAR0_GRC_LENGTH 0x200 551#define PXP_VF_BAR0_IGU_LENGTH 0x3000
560#define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + \ 552#define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + \
561 PXP_VF_BAR0_GRC_LENGTH - 1) 553 PXP_VF_BAR0_IGU_LENGTH - 1)
562 554
563#define PXP_VF_BAR0_START_IGU 0 555#define PXP_VF_BAR0_START_DQ 0x3000
564#define PXP_VF_BAR0_IGU_LENGTH 0x3000 556#define PXP_VF_BAR0_DQ_LENGTH 0x200
565#define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + \ 557#define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0
566 PXP_VF_BAR0_IGU_LENGTH - 1) 558#define PXP_VF_BAR0_ME_OPAQUE_ADDRESS (PXP_VF_BAR0_START_DQ + \
567 559 PXP_VF_BAR0_DQ_OPAQUE_OFFSET)
568#define PXP_VF_BAR0_START_DQ 0x3000 560#define PXP_VF_BAR0_ME_CONCRETE_ADDRESS (PXP_VF_BAR0_ME_OPAQUE_ADDRESS \
569#define PXP_VF_BAR0_DQ_LENGTH 0x200 561 + 4)
570#define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0 562#define PXP_VF_BAR0_END_DQ (PXP_VF_BAR0_START_DQ + \
571#define PXP_VF_BAR0_ME_OPAQUE_ADDRESS (PXP_VF_BAR0_START_DQ + \ 563 PXP_VF_BAR0_DQ_LENGTH - 1)
572 PXP_VF_BAR0_DQ_OPAQUE_OFFSET) 564
573#define PXP_VF_BAR0_ME_CONCRETE_ADDRESS (PXP_VF_BAR0_ME_OPAQUE_ADDRESS \ 565#define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200
574 + 4) 566#define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200
575#define PXP_VF_BAR0_END_DQ (PXP_VF_BAR0_START_DQ + \ 567#define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B + \
576 PXP_VF_BAR0_DQ_LENGTH - 1) 568 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
577 569
578#define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200 570#define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400
579#define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200 571#define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B + \
580#define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B \ 572 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
581 + \ 573
582 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 574#define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600
583 - 1) 575#define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B + \
584 576 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
585#define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400 577
586#define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B \ 578#define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800
587 + \ 579#define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B + \
588 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 580 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
589 - 1) 581
590 582#define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00
591#define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600 583#define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B + \
592#define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B \ 584 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
593 + \ 585
594 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 586#define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00
595 - 1) 587#define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B + \
596 588 PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
597#define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800 589
598#define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B \ 590#define PXP_VF_BAR0_START_GRC 0x3E00
599 + \ 591#define PXP_VF_BAR0_GRC_LENGTH 0x200
600 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 592#define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + \
601 - 1) 593 PXP_VF_BAR0_GRC_LENGTH - 1)
602 594
603#define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00 595#define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000
604#define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B \ 596#define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000
605 + \ 597
606 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 598#define PXP_VF_BAR0_START_IGU2 0x10000
607 - 1) 599#define PXP_VF_BAR0_IGU2_LENGTH 0xD000
608 600#define PXP_VF_BAR0_END_IGU2 (PXP_VF_BAR0_START_IGU2 + \
609#define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00 601 PXP_VF_BAR0_IGU2_LENGTH - 1)
610#define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B \ 602
611 + \ 603#define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32
612 PXP_VF_BAR0_SDM_LENGTH_ZONE_B \ 604
613 - 1) 605#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12
614 606#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024
615#define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000
616#define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000
617
618#define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32
619
620#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12
621#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024
622 607
623/* ILT Records */ 608/* ILT Records */
624#define PXP_NUM_ILT_RECORDS_BB 7600 609#define PXP_NUM_ILT_RECORDS_BB 7600
625#define PXP_NUM_ILT_RECORDS_K2 11000 610#define PXP_NUM_ILT_RECORDS_K2 11000
626#define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2) 611#define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)
627#define PXP_QUEUES_ZONE_MAX_NUM 320 612
613/* Host Interface */
614#define PXP_QUEUES_ZONE_MAX_NUM 320
615
628/*****************/ 616/*****************/
629/* PRM CONSTANTS */ 617/* PRM CONSTANTS */
630/*****************/ 618/*****************/
631#define PRM_DMA_PAD_BYTES_NUM 2 619#define PRM_DMA_PAD_BYTES_NUM 2
620
632/*****************/ 621/*****************/
633/* SDMs CONSTANTS */ 622/* SDMs CONSTANTS */
634/*****************/ 623/*****************/
635 624
636#define SDM_OP_GEN_TRIG_NONE 0 625#define SDM_OP_GEN_TRIG_NONE 0
637#define SDM_OP_GEN_TRIG_WAKE_THREAD 1 626#define SDM_OP_GEN_TRIG_WAKE_THREAD 1
638#define SDM_OP_GEN_TRIG_AGG_INT 2 627#define SDM_OP_GEN_TRIG_AGG_INT 2
639#define SDM_OP_GEN_TRIG_LOADER 4 628#define SDM_OP_GEN_TRIG_LOADER 4
640#define SDM_OP_GEN_TRIG_INDICATE_ERROR 6 629#define SDM_OP_GEN_TRIG_INDICATE_ERROR 6
641#define SDM_OP_GEN_TRIG_INC_ORDER_CNT 9 630#define SDM_OP_GEN_TRIG_INC_ORDER_CNT 9
642 631
@@ -644,26 +633,26 @@
644/* Completion types */ 633/* Completion types */
645/********************/ 634/********************/
646 635
647#define SDM_COMP_TYPE_NONE 0 636#define SDM_COMP_TYPE_NONE 0
648#define SDM_COMP_TYPE_WAKE_THREAD 1 637#define SDM_COMP_TYPE_WAKE_THREAD 1
649#define SDM_COMP_TYPE_AGG_INT 2 638#define SDM_COMP_TYPE_AGG_INT 2
650#define SDM_COMP_TYPE_CM 3 639#define SDM_COMP_TYPE_CM 3
651#define SDM_COMP_TYPE_LOADER 4 640#define SDM_COMP_TYPE_LOADER 4
652#define SDM_COMP_TYPE_PXP 5 641#define SDM_COMP_TYPE_PXP 5
653#define SDM_COMP_TYPE_INDICATE_ERROR 6 642#define SDM_COMP_TYPE_INDICATE_ERROR 6
654#define SDM_COMP_TYPE_RELEASE_THREAD 7 643#define SDM_COMP_TYPE_RELEASE_THREAD 7
655#define SDM_COMP_TYPE_RAM 8 644#define SDM_COMP_TYPE_RAM 8
656#define SDM_COMP_TYPE_INC_ORDER_CNT 9 645#define SDM_COMP_TYPE_INC_ORDER_CNT 9
657 646
658/*****************/ 647/*****************/
659/* PBF Constants */ 648/* PBF CONSTANTS */
660/*****************/ 649/*****************/
661 650
662/* Number of PBF command queue lines. Each line is 32B. */ 651/* Number of PBF command queue lines. Each line is 32B. */
663#define PBF_MAX_CMD_LINES 3328 652#define PBF_MAX_CMD_LINES 3328
664 653
665/* Number of BTB blocks. Each block is 256B. */ 654/* Number of BTB blocks. Each block is 256B. */
666#define BTB_MAX_BLOCKS 1440 655#define BTB_MAX_BLOCKS 1440
667 656
668/*****************/ 657/*****************/
669/* PRS CONSTANTS */ 658/* PRS CONSTANTS */
@@ -671,14 +660,7 @@
671 660
672#define PRS_GFT_CAM_LINES_NO_MATCH 31 661#define PRS_GFT_CAM_LINES_NO_MATCH 31
673 662
674/* Async data KCQ CQE */ 663/* Interrupt coalescing TimeSet */
675struct async_data {
676 __le32 cid;
677 __le16 itid;
678 u8 error_code;
679 u8 fw_debug_param;
680};
681
682struct coalescing_timeset { 664struct coalescing_timeset {
683 u8 value; 665 u8 value;
684#define COALESCING_TIMESET_TIMESET_MASK 0x7F 666#define COALESCING_TIMESET_TIMESET_MASK 0x7F
@@ -692,23 +674,32 @@ struct common_queue_zone {
692 __le16 reserved; 674 __le16 reserved;
693}; 675};
694 676
677/* ETH Rx producers data */
695struct eth_rx_prod_data { 678struct eth_rx_prod_data {
696 __le16 bd_prod; 679 __le16 bd_prod;
697 __le16 cqe_prod; 680 __le16 cqe_prod;
698}; 681};
699 682
700struct regpair { 683struct tcp_ulp_connect_done_params {
701 __le32 lo; 684 __le16 mss;
702 __le32 hi; 685 u8 snd_wnd_scale;
686 u8 flags;
687#define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_MASK 0x1
688#define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_SHIFT 0
689#define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_MASK 0x7F
690#define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_SHIFT 1
703}; 691};
704 692
705struct vf_pf_channel_eqe_data { 693struct iscsi_connect_done_results {
706 struct regpair msg_addr; 694 __le16 icid;
695 __le16 conn_id;
696 struct tcp_ulp_connect_done_params params;
707}; 697};
708 698
709struct iscsi_eqe_data { 699struct iscsi_eqe_data {
710 __le32 cid; 700 __le16 icid;
711 __le16 conn_id; 701 __le16 conn_id;
702 __le16 reserved;
712 u8 error_code; 703 u8 error_code;
713 u8 error_pdu_opcode_reserved; 704 u8 error_pdu_opcode_reserved;
714#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F 705#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F
@@ -719,52 +710,6 @@ struct iscsi_eqe_data {
719#define ISCSI_EQE_DATA_RESERVED0_SHIFT 7 710#define ISCSI_EQE_DATA_RESERVED0_SHIFT 7
720}; 711};
721 712
722struct rdma_eqe_destroy_qp {
723 __le32 cid;
724 u8 reserved[4];
725};
726
727union rdma_eqe_data {
728 struct regpair async_handle;
729 struct rdma_eqe_destroy_qp rdma_destroy_qp_data;
730};
731
732struct malicious_vf_eqe_data {
733 u8 vf_id;
734 u8 err_id;
735 __le16 reserved[3];
736};
737
738struct initial_cleanup_eqe_data {
739 u8 vf_id;
740 u8 reserved[7];
741};
742
743/* Event Data Union */
744union event_ring_data {
745 u8 bytes[8];
746 struct vf_pf_channel_eqe_data vf_pf_channel;
747 struct iscsi_eqe_data iscsi_info;
748 union rdma_eqe_data rdma_data;
749 struct malicious_vf_eqe_data malicious_vf;
750 struct initial_cleanup_eqe_data vf_init_cleanup;
751};
752
753/* Event Ring Entry */
754struct event_ring_entry {
755 u8 protocol_id;
756 u8 opcode;
757 __le16 reserved0;
758 __le16 echo;
759 u8 fw_return_code;
760 u8 flags;
761#define EVENT_RING_ENTRY_ASYNC_MASK 0x1
762#define EVENT_RING_ENTRY_ASYNC_SHIFT 0
763#define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
764#define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
765 union event_ring_data data;
766};
767
768/* Multi function mode */ 713/* Multi function mode */
769enum mf_mode { 714enum mf_mode {
770 ERROR_MODE /* Unsupported mode */, 715 ERROR_MODE /* Unsupported mode */,
@@ -781,13 +726,31 @@ enum protocol_type {
781 PROTOCOLID_CORE, 726 PROTOCOLID_CORE,
782 PROTOCOLID_ETH, 727 PROTOCOLID_ETH,
783 PROTOCOLID_IWARP, 728 PROTOCOLID_IWARP,
784 PROTOCOLID_RESERVED5, 729 PROTOCOLID_RESERVED0,
785 PROTOCOLID_PREROCE, 730 PROTOCOLID_PREROCE,
786 PROTOCOLID_COMMON, 731 PROTOCOLID_COMMON,
787 PROTOCOLID_RESERVED6, 732 PROTOCOLID_RESERVED1,
788 MAX_PROTOCOL_TYPE 733 MAX_PROTOCOL_TYPE
789}; 734};
790 735
736struct regpair {
737 __le32 lo;
738 __le32 hi;
739};
740
741/* RoCE Destroy Event Data */
742struct rdma_eqe_destroy_qp {
743 __le32 cid;
744 u8 reserved[4];
745};
746
747/* RDMA Event Data Union */
748union rdma_eqe_data {
749 struct regpair async_handle;
750 struct rdma_eqe_destroy_qp rdma_destroy_qp_data;
751};
752
753/* Ustorm Queue Zone */
791struct ustorm_eth_queue_zone { 754struct ustorm_eth_queue_zone {
792 struct coalescing_timeset int_coalescing_timeset; 755 struct coalescing_timeset int_coalescing_timeset;
793 u8 reserved[3]; 756 u8 reserved[3];
@@ -798,62 +761,71 @@ struct ustorm_queue_zone {
798 struct common_queue_zone common; 761 struct common_queue_zone common;
799}; 762};
800 763
801/* status block structure */ 764/* Status block structure */
802struct cau_pi_entry { 765struct cau_pi_entry {
803 u32 prod; 766 __le32 prod;
804#define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF 767#define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF
805#define CAU_PI_ENTRY_PROD_VAL_SHIFT 0 768#define CAU_PI_ENTRY_PROD_VAL_SHIFT 0
806#define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F 769#define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F
807#define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16 770#define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16
808#define CAU_PI_ENTRY_FSM_SEL_MASK 0x1 771#define CAU_PI_ENTRY_FSM_SEL_MASK 0x1
809#define CAU_PI_ENTRY_FSM_SEL_SHIFT 23 772#define CAU_PI_ENTRY_FSM_SEL_SHIFT 23
810#define CAU_PI_ENTRY_RESERVED_MASK 0xFF 773#define CAU_PI_ENTRY_RESERVED_MASK 0xFF
811#define CAU_PI_ENTRY_RESERVED_SHIFT 24 774#define CAU_PI_ENTRY_RESERVED_SHIFT 24
812}; 775};
813 776
814/* status block structure */ 777/* Status block structure */
815struct cau_sb_entry { 778struct cau_sb_entry {
816 u32 data; 779 __le32 data;
817#define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF 780#define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF
818#define CAU_SB_ENTRY_SB_PROD_SHIFT 0 781#define CAU_SB_ENTRY_SB_PROD_SHIFT 0
819#define CAU_SB_ENTRY_STATE0_MASK 0xF 782#define CAU_SB_ENTRY_STATE0_MASK 0xF
820#define CAU_SB_ENTRY_STATE0_SHIFT 24 783#define CAU_SB_ENTRY_STATE0_SHIFT 24
821#define CAU_SB_ENTRY_STATE1_MASK 0xF 784#define CAU_SB_ENTRY_STATE1_MASK 0xF
822#define CAU_SB_ENTRY_STATE1_SHIFT 28 785#define CAU_SB_ENTRY_STATE1_SHIFT 28
823 u32 params; 786 __le32 params;
824#define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F 787#define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F
825#define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0 788#define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0
826#define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F 789#define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F
827#define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7 790#define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7
828#define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3 791#define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3
829#define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14 792#define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14
830#define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3 793#define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3
831#define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16 794#define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16
832#define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF 795#define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF
833#define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18 796#define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18
834#define CAU_SB_ENTRY_VF_VALID_MASK 0x1 797#define CAU_SB_ENTRY_VF_VALID_MASK 0x1
835#define CAU_SB_ENTRY_VF_VALID_SHIFT 26 798#define CAU_SB_ENTRY_VF_VALID_SHIFT 26
836#define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF 799#define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF
837#define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27 800#define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27
838#define CAU_SB_ENTRY_TPH_MASK 0x1 801#define CAU_SB_ENTRY_TPH_MASK 0x1
839#define CAU_SB_ENTRY_TPH_SHIFT 31 802#define CAU_SB_ENTRY_TPH_SHIFT 31
840}; 803};
841 804
842/* core doorbell data */ 805/* Igu cleanup bit values to distinguish between clean or producer consumer
806 * update.
807 */
808enum command_type_bit {
809 IGU_COMMAND_TYPE_NOP = 0,
810 IGU_COMMAND_TYPE_SET = 1,
811 MAX_COMMAND_TYPE_BIT
812};
813
814/* Core doorbell data */
843struct core_db_data { 815struct core_db_data {
844 u8 params; 816 u8 params;
845#define CORE_DB_DATA_DEST_MASK 0x3 817#define CORE_DB_DATA_DEST_MASK 0x3
846#define CORE_DB_DATA_DEST_SHIFT 0 818#define CORE_DB_DATA_DEST_SHIFT 0
847#define CORE_DB_DATA_AGG_CMD_MASK 0x3 819#define CORE_DB_DATA_AGG_CMD_MASK 0x3
848#define CORE_DB_DATA_AGG_CMD_SHIFT 2 820#define CORE_DB_DATA_AGG_CMD_SHIFT 2
849#define CORE_DB_DATA_BYPASS_EN_MASK 0x1 821#define CORE_DB_DATA_BYPASS_EN_MASK 0x1
850#define CORE_DB_DATA_BYPASS_EN_SHIFT 4 822#define CORE_DB_DATA_BYPASS_EN_SHIFT 4
851#define CORE_DB_DATA_RESERVED_MASK 0x1 823#define CORE_DB_DATA_RESERVED_MASK 0x1
852#define CORE_DB_DATA_RESERVED_SHIFT 5 824#define CORE_DB_DATA_RESERVED_SHIFT 5
853#define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3 825#define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3
854#define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6 826#define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6
855 u8 agg_flags; 827 u8 agg_flags;
856 __le16 spq_prod; 828 __le16 spq_prod;
857}; 829};
858 830
859/* Enum of doorbell aggregative command selection */ 831/* Enum of doorbell aggregative command selection */
@@ -909,67 +881,69 @@ struct db_l2_dpm_sge {
909 struct regpair addr; 881 struct regpair addr;
910 __le16 nbytes; 882 __le16 nbytes;
911 __le16 bitfields; 883 __le16 bitfields;
912#define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF 884#define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF
913#define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0 885#define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0
914#define DB_L2_DPM_SGE_RESERVED0_MASK 0x3 886#define DB_L2_DPM_SGE_RESERVED0_MASK 0x3
915#define DB_L2_DPM_SGE_RESERVED0_SHIFT 9 887#define DB_L2_DPM_SGE_RESERVED0_SHIFT 9
916#define DB_L2_DPM_SGE_ST_VALID_MASK 0x1 888#define DB_L2_DPM_SGE_ST_VALID_MASK 0x1
917#define DB_L2_DPM_SGE_ST_VALID_SHIFT 11 889#define DB_L2_DPM_SGE_ST_VALID_SHIFT 11
918#define DB_L2_DPM_SGE_RESERVED1_MASK 0xF 890#define DB_L2_DPM_SGE_RESERVED1_MASK 0xF
919#define DB_L2_DPM_SGE_RESERVED1_SHIFT 12 891#define DB_L2_DPM_SGE_RESERVED1_SHIFT 12
920 __le32 reserved2; 892 __le32 reserved2;
921}; 893};
922 894
923/* Structure for doorbell address, in legacy mode */ 895/* Structure for doorbell address, in legacy mode */
924struct db_legacy_addr { 896struct db_legacy_addr {
925 __le32 addr; 897 __le32 addr;
926#define DB_LEGACY_ADDR_RESERVED0_MASK 0x3 898#define DB_LEGACY_ADDR_RESERVED0_MASK 0x3
927#define DB_LEGACY_ADDR_RESERVED0_SHIFT 0 899#define DB_LEGACY_ADDR_RESERVED0_SHIFT 0
928#define DB_LEGACY_ADDR_DEMS_MASK 0x7 900#define DB_LEGACY_ADDR_DEMS_MASK 0x7
929#define DB_LEGACY_ADDR_DEMS_SHIFT 2 901#define DB_LEGACY_ADDR_DEMS_SHIFT 2
930#define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF 902#define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF
931#define DB_LEGACY_ADDR_ICID_SHIFT 5 903#define DB_LEGACY_ADDR_ICID_SHIFT 5
932}; 904};
933 905
934/* Structure for doorbell address, in PWM mode */ 906/* Structure for doorbell address, in PWM mode */
935struct db_pwm_addr { 907struct db_pwm_addr {
936 __le32 addr; 908 __le32 addr;
937#define DB_PWM_ADDR_RESERVED0_MASK 0x7 909#define DB_PWM_ADDR_RESERVED0_MASK 0x7
938#define DB_PWM_ADDR_RESERVED0_SHIFT 0 910#define DB_PWM_ADDR_RESERVED0_SHIFT 0
939#define DB_PWM_ADDR_OFFSET_MASK 0x7F 911#define DB_PWM_ADDR_OFFSET_MASK 0x7F
940#define DB_PWM_ADDR_OFFSET_SHIFT 3 912#define DB_PWM_ADDR_OFFSET_SHIFT 3
941#define DB_PWM_ADDR_WID_MASK 0x3 913#define DB_PWM_ADDR_WID_MASK 0x3
942#define DB_PWM_ADDR_WID_SHIFT 10 914#define DB_PWM_ADDR_WID_SHIFT 10
943#define DB_PWM_ADDR_DPI_MASK 0xFFFF 915#define DB_PWM_ADDR_DPI_MASK 0xFFFF
944#define DB_PWM_ADDR_DPI_SHIFT 12 916#define DB_PWM_ADDR_DPI_SHIFT 12
945#define DB_PWM_ADDR_RESERVED1_MASK 0xF 917#define DB_PWM_ADDR_RESERVED1_MASK 0xF
946#define DB_PWM_ADDR_RESERVED1_SHIFT 28 918#define DB_PWM_ADDR_RESERVED1_SHIFT 28
947}; 919};
948 920
949/* Parameters to RoCE firmware, passed in EDPM doorbell */ 921/* Parameters to RDMA firmware, passed in EDPM doorbell */
950struct db_rdma_dpm_params { 922struct db_rdma_dpm_params {
951 __le32 params; 923 __le32 params;
952#define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F 924#define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F
953#define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0 925#define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0
954#define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3 926#define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3
955#define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6 927#define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6
956#define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF 928#define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF
957#define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8 929#define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8
958#define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF 930#define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF
959#define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16 931#define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16
960#define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1 932#define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1
961#define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27 933#define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27
962#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 934#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1
963#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28 935#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28
964#define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1 936#define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1
965#define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29 937#define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29
966#define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x1 938#define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x1
967#define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30 939#define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30
968#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1 940#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1
969#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31 941#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31
970}; 942};
971 943
972/* Structure for doorbell data, in ROCE DPM mode, for 1st db in a DPM burst */ 944/* Structure for doorbell data, in RDMA DPM mode, for the first doorbell in a
945 * DPM burst.
946 */
973struct db_rdma_dpm_data { 947struct db_rdma_dpm_data {
974 __le16 icid; 948 __le16 icid;
975 __le16 prod_val; 949 __le16 prod_val;
@@ -987,22 +961,22 @@ enum igu_int_cmd {
987 961
988/* IGU producer or consumer update command */ 962/* IGU producer or consumer update command */
989struct igu_prod_cons_update { 963struct igu_prod_cons_update {
990 u32 sb_id_and_flags; 964 __le32 sb_id_and_flags;
991#define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF 965#define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF
992#define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0 966#define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0
993#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1 967#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1
994#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24 968#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24
995#define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3 969#define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3
996#define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25 970#define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25
997#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1 971#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1
998#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27 972#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27
999#define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1 973#define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1
1000#define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28 974#define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28
1001#define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3 975#define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3
1002#define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29 976#define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29
1003#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1 977#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1
1004#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31 978#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31
1005 u32 reserved1; 979 __le32 reserved1;
1006}; 980};
1007 981
1008/* Igu segments access for default status block only */ 982/* Igu segments access for default status block only */
@@ -1012,38 +986,63 @@ enum igu_seg_access {
1012 MAX_IGU_SEG_ACCESS 986 MAX_IGU_SEG_ACCESS
1013}; 987};
1014 988
989/* Enumeration for L3 type field of parsing_and_err_flags.
990 * L3Type: 0 - unknown (not ip), 1 - Ipv4, 2 - Ipv6
991 * (This field can be filled according to the last-ethertype)
992 */
993enum l3_type {
994 e_l3_type_unknown,
995 e_l3_type_ipv4,
996 e_l3_type_ipv6,
997 MAX_L3_TYPE
998};
999
1000/* Enumeration for l4Protocol field of parsing_and_err_flags.
1001 * L4-protocol: 0 - none, 1 - TCP, 2 - UDP.
1002 * If the packet is IPv4 fragment, and its not the first fragment, the
1003 * protocol-type should be set to none.
1004 */
1005enum l4_protocol {
1006 e_l4_protocol_none,
1007 e_l4_protocol_tcp,
1008 e_l4_protocol_udp,
1009 MAX_L4_PROTOCOL
1010};
1011
1012/* Parsing and error flags field */
1015struct parsing_and_err_flags { 1013struct parsing_and_err_flags {
1016 __le16 flags; 1014 __le16 flags;
1017#define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3 1015#define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3
1018#define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0 1016#define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0
1019#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3 1017#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3
1020#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2 1018#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2
1021#define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1 1019#define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1
1022#define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4 1020#define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4
1023#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1 1021#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1
1024#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5 1022#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5
1025#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1 1023#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1
1026#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6 1024#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6
1027#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1 1025#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1
1028#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7 1026#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7
1029#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1 1027#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1
1030#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8 1028#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8
1031#define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1 1029#define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1
1032#define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9 1030#define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9
1033#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1 1031#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1
1034#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10 1032#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10
1035#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1 1033#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1
1036#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11 1034#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11
1037#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1 1035#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1
1038#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12 1036#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12
1039#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1 1037#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1
1040#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13 1038#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13
1041#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1 1039#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1
1042#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14 1040#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14
1043#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1 1041#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1
1044#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15 1042#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15
1045}; 1043};
1046 1044
1045/* Parsing error flags bitmap */
1047struct parsing_err_flags { 1046struct parsing_err_flags {
1048 __le16 flags; 1047 __le16 flags;
1049#define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1 1048#define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1
@@ -1080,266 +1079,260 @@ struct parsing_err_flags {
1080#define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT 15 1079#define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT 15
1081}; 1080};
1082 1081
1082/* Pb context */
1083struct pb_context { 1083struct pb_context {
1084 __le32 crc[4]; 1084 __le32 crc[4];
1085}; 1085};
1086 1086
1087/* Concrete Function ID */
1087struct pxp_concrete_fid { 1088struct pxp_concrete_fid {
1088 __le16 fid; 1089 __le16 fid;
1089#define PXP_CONCRETE_FID_PFID_MASK 0xF 1090#define PXP_CONCRETE_FID_PFID_MASK 0xF
1090#define PXP_CONCRETE_FID_PFID_SHIFT 0 1091#define PXP_CONCRETE_FID_PFID_SHIFT 0
1091#define PXP_CONCRETE_FID_PORT_MASK 0x3 1092#define PXP_CONCRETE_FID_PORT_MASK 0x3
1092#define PXP_CONCRETE_FID_PORT_SHIFT 4 1093#define PXP_CONCRETE_FID_PORT_SHIFT 4
1093#define PXP_CONCRETE_FID_PATH_MASK 0x1 1094#define PXP_CONCRETE_FID_PATH_MASK 0x1
1094#define PXP_CONCRETE_FID_PATH_SHIFT 6 1095#define PXP_CONCRETE_FID_PATH_SHIFT 6
1095#define PXP_CONCRETE_FID_VFVALID_MASK 0x1 1096#define PXP_CONCRETE_FID_VFVALID_MASK 0x1
1096#define PXP_CONCRETE_FID_VFVALID_SHIFT 7 1097#define PXP_CONCRETE_FID_VFVALID_SHIFT 7
1097#define PXP_CONCRETE_FID_VFID_MASK 0xFF 1098#define PXP_CONCRETE_FID_VFID_MASK 0xFF
1098#define PXP_CONCRETE_FID_VFID_SHIFT 8 1099#define PXP_CONCRETE_FID_VFID_SHIFT 8
1099}; 1100};
1100 1101
1102/* Concrete Function ID */
1101struct pxp_pretend_concrete_fid { 1103struct pxp_pretend_concrete_fid {
1102 __le16 fid; 1104 __le16 fid;
1103#define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF 1105#define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF
1104#define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0 1106#define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0
1105#define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7 1107#define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7
1106#define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4 1108#define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4
1107#define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1 1109#define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1
1108#define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7 1110#define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7
1109#define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF 1111#define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF
1110#define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8 1112#define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8
1111}; 1113};
1112 1114
1115/* Function ID */
1113union pxp_pretend_fid { 1116union pxp_pretend_fid {
1114 struct pxp_pretend_concrete_fid concrete_fid; 1117 struct pxp_pretend_concrete_fid concrete_fid;
1115 __le16 opaque_fid; 1118 __le16 opaque_fid;
1116}; 1119};
1117 1120
1118/* Pxp Pretend Command Register. */ 1121/* Pxp Pretend Command Register */
1119struct pxp_pretend_cmd { 1122struct pxp_pretend_cmd {
1120 union pxp_pretend_fid fid; 1123 union pxp_pretend_fid fid;
1121 __le16 control; 1124 __le16 control;
1122#define PXP_PRETEND_CMD_PATH_MASK 0x1 1125#define PXP_PRETEND_CMD_PATH_MASK 0x1
1123#define PXP_PRETEND_CMD_PATH_SHIFT 0 1126#define PXP_PRETEND_CMD_PATH_SHIFT 0
1124#define PXP_PRETEND_CMD_USE_PORT_MASK 0x1 1127#define PXP_PRETEND_CMD_USE_PORT_MASK 0x1
1125#define PXP_PRETEND_CMD_USE_PORT_SHIFT 1 1128#define PXP_PRETEND_CMD_USE_PORT_SHIFT 1
1126#define PXP_PRETEND_CMD_PORT_MASK 0x3 1129#define PXP_PRETEND_CMD_PORT_MASK 0x3
1127#define PXP_PRETEND_CMD_PORT_SHIFT 2 1130#define PXP_PRETEND_CMD_PORT_SHIFT 2
1128#define PXP_PRETEND_CMD_RESERVED0_MASK 0xF 1131#define PXP_PRETEND_CMD_RESERVED0_MASK 0xF
1129#define PXP_PRETEND_CMD_RESERVED0_SHIFT 4 1132#define PXP_PRETEND_CMD_RESERVED0_SHIFT 4
1130#define PXP_PRETEND_CMD_RESERVED1_MASK 0xF 1133#define PXP_PRETEND_CMD_RESERVED1_MASK 0xF
1131#define PXP_PRETEND_CMD_RESERVED1_SHIFT 8 1134#define PXP_PRETEND_CMD_RESERVED1_SHIFT 8
1132#define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1 1135#define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1
1133#define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12 1136#define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12
1134#define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1 1137#define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1
1135#define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13 1138#define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13
1136#define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1 1139#define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1
1137#define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14 1140#define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14
1138#define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1 1141#define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1
1139#define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15 1142#define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15
1140}; 1143};
1141 1144
1142/* PTT Record in PXP Admin Window. */ 1145/* PTT Record in PXP Admin Window */
1143struct pxp_ptt_entry { 1146struct pxp_ptt_entry {
1144 __le32 offset; 1147 __le32 offset;
1145#define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF 1148#define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF
1146#define PXP_PTT_ENTRY_OFFSET_SHIFT 0 1149#define PXP_PTT_ENTRY_OFFSET_SHIFT 0
1147#define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF 1150#define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF
1148#define PXP_PTT_ENTRY_RESERVED0_SHIFT 23 1151#define PXP_PTT_ENTRY_RESERVED0_SHIFT 23
1149 struct pxp_pretend_cmd pretend; 1152 struct pxp_pretend_cmd pretend;
1150}; 1153};
1151 1154
1152/* VF Zone A Permission Register. */ 1155/* VF Zone A Permission Register */
1153struct pxp_vf_zone_a_permission { 1156struct pxp_vf_zone_a_permission {
1154 __le32 control; 1157 __le32 control;
1155#define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF 1158#define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF
1156#define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0 1159#define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0
1157#define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1 1160#define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1
1158#define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8 1161#define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8
1159#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F 1162#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F
1160#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9 1163#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9
1161#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF 1164#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF
1162#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16 1165#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16
1163}; 1166};
1164 1167
1165/* RSS hash type */ 1168/* Rdif context */
1166struct rdif_task_context { 1169struct rdif_task_context {
1167 __le32 initial_ref_tag; 1170 __le32 initial_ref_tag;
1168 __le16 app_tag_value; 1171 __le16 app_tag_value;
1169 __le16 app_tag_mask; 1172 __le16 app_tag_mask;
1170 u8 flags0; 1173 u8 flags0;
1171#define RDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1 1174#define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
1172#define RDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0 1175#define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
1173#define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1 1176#define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
1174#define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1 1177#define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1
1175#define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1 1178#define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1
1176#define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2 1179#define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2
1177#define RDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1 1180#define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
1178#define RDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3 1181#define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3
1179#define RDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3 1182#define RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3
1180#define RDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4 1183#define RDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4
1181#define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 1184#define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
1182#define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1185#define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
1183#define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1 1186#define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1
1184#define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 7 1187#define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 7
1185 u8 partial_dif_data[7]; 1188 u8 partial_dif_data[7];
1186 __le16 partial_crc_value; 1189 __le16 partial_crc_value;
1187 __le16 partial_checksum_value; 1190 __le16 partial_checksum_value;
1188 __le32 offset_in_io; 1191 __le32 offset_in_io;
1189 __le16 flags1; 1192 __le16 flags1;
1190#define RDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1 1193#define RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
1191#define RDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0 1194#define RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
1192#define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1 1195#define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
1193#define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1 1196#define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1
1194#define RDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1 1197#define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
1195#define RDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2 1198#define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2
1196#define RDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1 1199#define RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
1197#define RDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3 1200#define RDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3
1198#define RDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1 1201#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
1199#define RDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4 1202#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4
1200#define RDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1 1203#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
1201#define RDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5 1204#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5
1202#define RDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7 1205#define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7
1203#define RDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6 1206#define RDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6
1204#define RDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3 1207#define RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3
1205#define RDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9 1208#define RDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9
1206#define RDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1 1209#define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1
1207#define RDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11 1210#define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11
1208#define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1 1211#define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1
1209#define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12 1212#define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12
1210#define RDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1 1213#define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1
1211#define RDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13 1214#define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13
1212#define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1 1215#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1
1213#define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 14 1216#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 14
1214#define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1 1217#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1
1215#define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 15 1218#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 15
1216 __le16 state; 1219 __le16 state;
1217#define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_MASK 0xF 1220#define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK 0xF
1218#define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_SHIFT 0 1221#define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT 0
1219#define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_MASK 0xF 1222#define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK 0xF
1220#define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_SHIFT 4 1223#define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_SHIFT 4
1221#define RDIF_TASK_CONTEXT_ERRORINIO_MASK 0x1 1224#define RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK 0x1
1222#define RDIF_TASK_CONTEXT_ERRORINIO_SHIFT 8 1225#define RDIF_TASK_CONTEXT_ERROR_IN_IO_SHIFT 8
1223#define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1 1226#define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK 0x1
1224#define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9 1227#define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_SHIFT 9
1225#define RDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF 1228#define RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF
1226#define RDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 10 1229#define RDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 10
1227#define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3 1230#define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3
1228#define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14 1231#define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14
1229 __le32 reserved2; 1232 __le32 reserved2;
1230}; 1233};
1231 1234
1232/* RSS hash type */ 1235/* Status block structure */
1233enum rss_hash_type { 1236struct status_block_e4 {
1234 RSS_HASH_TYPE_DEFAULT = 0, 1237 __le16 pi_array[PIS_PER_SB_E4];
1235 RSS_HASH_TYPE_IPV4 = 1,
1236 RSS_HASH_TYPE_TCP_IPV4 = 2,
1237 RSS_HASH_TYPE_IPV6 = 3,
1238 RSS_HASH_TYPE_TCP_IPV6 = 4,
1239 RSS_HASH_TYPE_UDP_IPV4 = 5,
1240 RSS_HASH_TYPE_UDP_IPV6 = 6,
1241 MAX_RSS_HASH_TYPE
1242};
1243
1244/* status block structure */
1245struct status_block {
1246 __le16 pi_array[PIS_PER_SB];
1247 __le32 sb_num; 1238 __le32 sb_num;
1248#define STATUS_BLOCK_SB_NUM_MASK 0x1FF 1239#define STATUS_BLOCK_E4_SB_NUM_MASK 0x1FF
1249#define STATUS_BLOCK_SB_NUM_SHIFT 0 1240#define STATUS_BLOCK_E4_SB_NUM_SHIFT 0
1250#define STATUS_BLOCK_ZERO_PAD_MASK 0x7F 1241#define STATUS_BLOCK_E4_ZERO_PAD_MASK 0x7F
1251#define STATUS_BLOCK_ZERO_PAD_SHIFT 9 1242#define STATUS_BLOCK_E4_ZERO_PAD_SHIFT 9
1252#define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF 1243#define STATUS_BLOCK_E4_ZERO_PAD2_MASK 0xFFFF
1253#define STATUS_BLOCK_ZERO_PAD2_SHIFT 16 1244#define STATUS_BLOCK_E4_ZERO_PAD2_SHIFT 16
1254 __le32 prod_index; 1245 __le32 prod_index;
1255#define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF 1246#define STATUS_BLOCK_E4_PROD_INDEX_MASK 0xFFFFFF
1256#define STATUS_BLOCK_PROD_INDEX_SHIFT 0 1247#define STATUS_BLOCK_E4_PROD_INDEX_SHIFT 0
1257#define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF 1248#define STATUS_BLOCK_E4_ZERO_PAD3_MASK 0xFF
1258#define STATUS_BLOCK_ZERO_PAD3_SHIFT 24 1249#define STATUS_BLOCK_E4_ZERO_PAD3_SHIFT 24
1259}; 1250};
1260 1251
1252/* Tdif context */
1261struct tdif_task_context { 1253struct tdif_task_context {
1262 __le32 initial_ref_tag; 1254 __le32 initial_ref_tag;
1263 __le16 app_tag_value; 1255 __le16 app_tag_value;
1264 __le16 app_tag_mask; 1256 __le16 app_tag_mask;
1265 __le16 partial_crc_valueB; 1257 __le16 partial_crc_value_b;
1266 __le16 partial_checksum_valueB; 1258 __le16 partial_checksum_value_b;
1267 __le16 stateB; 1259 __le16 stateB;
1268#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_MASK 0xF 1260#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK 0xF
1269#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_SHIFT 0 1261#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT 0
1270#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_MASK 0xF 1262#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK 0xF
1271#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_SHIFT 4 1263#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_SHIFT 4
1272#define TDIF_TASK_CONTEXT_ERRORINIOB_MASK 0x1 1264#define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK 0x1
1273#define TDIF_TASK_CONTEXT_ERRORINIOB_SHIFT 8 1265#define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_SHIFT 8
1274#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1 1266#define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK 0x1
1275#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9 1267#define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_SHIFT 9
1276#define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F 1268#define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F
1277#define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10 1269#define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10
1278 u8 reserved1; 1270 u8 reserved1;
1279 u8 flags0; 1271 u8 flags0;
1280#define TDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1 1272#define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
1281#define TDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0 1273#define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
1282#define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1 1274#define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
1283#define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1 1275#define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1
1284#define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1 1276#define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1
1285#define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2 1277#define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2
1286#define TDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1 1278#define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
1287#define TDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3 1279#define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3
1288#define TDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3 1280#define TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3
1289#define TDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4 1281#define TDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4
1290#define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 1282#define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
1291#define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1283#define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
1292#define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1 1284#define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1
1293#define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7 1285#define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7
1294 __le32 flags1; 1286 __le32 flags1;
1295#define TDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1 1287#define TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
1296#define TDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0 1288#define TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
1297#define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1 1289#define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
1298#define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1 1290#define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1
1299#define TDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1 1291#define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
1300#define TDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2 1292#define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2
1301#define TDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1 1293#define TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
1302#define TDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3 1294#define TDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3
1303#define TDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1 1295#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
1304#define TDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4 1296#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4
1305#define TDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1 1297#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
1306#define TDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5 1298#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5
1307#define TDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7 1299#define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7
1308#define TDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6 1300#define TDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6
1309#define TDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3 1301#define TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3
1310#define TDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9 1302#define TDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9
1311#define TDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1 1303#define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1
1312#define TDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11 1304#define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11
1313#define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1 1305#define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1
1314#define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12 1306#define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12
1315#define TDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1 1307#define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1
1316#define TDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13 1308#define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13
1317#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_MASK 0xF 1309#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK 0xF
1318#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_SHIFT 14 1310#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_SHIFT 14
1319#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_MASK 0xF 1311#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK 0xF
1320#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_SHIFT 18 1312#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_SHIFT 18
1321#define TDIF_TASK_CONTEXT_ERRORINIOA_MASK 0x1 1313#define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK 0x1
1322#define TDIF_TASK_CONTEXT_ERRORINIOA_SHIFT 22 1314#define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_SHIFT 22
1323#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_MASK 0x1 1315#define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK 0x1
1324#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_SHIFT 23 1316#define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_SHIFT 23
1325#define TDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF 1317#define TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF
1326#define TDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 24 1318#define TDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 24
1327#define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1 1319#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1
1328#define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 28 1320#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 28
1329#define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1 1321#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1
1330#define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 29 1322#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 29
1331#define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1 1323#define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1
1332#define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 30 1324#define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 30
1333#define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1 1325#define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1
1334#define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31 1326#define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31
1335 __le32 offset_in_iob; 1327 __le32 offset_in_io_b;
1336 __le16 partial_crc_value_a; 1328 __le16 partial_crc_value_a;
1337 __le16 partial_checksum_valuea_; 1329 __le16 partial_checksum_value_a;
1338 __le32 offset_in_ioa; 1330 __le32 offset_in_io_a;
1339 u8 partial_dif_data_a[8]; 1331 u8 partial_dif_data_a[8];
1340 u8 partial_dif_data_b[8]; 1332 u8 partial_dif_data_b[8];
1341}; 1333};
1342 1334
1335/* Timers context */
1343struct timers_context { 1336struct timers_context {
1344 __le32 logical_client_0; 1337 __le32 logical_client_0;
1345#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF 1338#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF
@@ -1385,6 +1378,7 @@ struct timers_context {
1385#define TIMERS_CONTEXT_RESERVED7_SHIFT 29 1378#define TIMERS_CONTEXT_RESERVED7_SHIFT 29
1386}; 1379};
1387 1380
1381/* Enum for next_protocol field of tunnel_parsing_flags / tunnelTypeDesc */
1388enum tunnel_next_protocol { 1382enum tunnel_next_protocol {
1389 e_unknown = 0, 1383 e_unknown = 0,
1390 e_l2 = 1, 1384 e_l2 = 1,
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-27 10:13:56 -0400