2 files changed, 23 insertions, 1 deletions

diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index cbb872c1b607..8bdbb5f29494 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -61,6 +61,16 @@
 #define GICD_CTLR_ENABLE_G1A            (1U << 1)
 #define GICD_CTLR_ENABLE_G1             (1U << 0)
 
+#define GICD_IIDR_IMPLEMENTER_SHIFT     0
+#define GICD_IIDR_IMPLEMENTER_MASK      (0xfff << GICD_IIDR_IMPLEMENTER_SHIFT)
+#define GICD_IIDR_REVISION_SHIFT        12
+#define GICD_IIDR_REVISION_MASK         (0xf << GICD_IIDR_REVISION_SHIFT)
+#define GICD_IIDR_VARIANT_SHIFT         16
+#define GICD_IIDR_VARIANT_MASK          (0xf << GICD_IIDR_VARIANT_SHIFT)
+#define GICD_IIDR_PRODUCT_ID_SHIFT      24
+#define GICD_IIDR_PRODUCT_ID_MASK       (0xff << GICD_IIDR_PRODUCT_ID_SHIFT)
+
+
 /*
  * In systems with a single security state (what we emulate in KVM)
  * the meaning of the interrupt group enable bits is slightly different
@@ -73,6 +83,7 @@
 #define GICD_TYPER_MBIS                 (1U << 16)
 
 #define GICD_TYPER_ID_BITS(typer)       ((((typer) >> 19) & 0x1f) + 1)
+#define GICD_TYPER_NUM_LPIS(typer)      ((((typer) >> 11) & 0x1f) + 1)
 #define GICD_TYPER_IRQS(typer)          ((((typer) & 0x1f) + 1) * 32)
 
 #define GICD_IROUTER_SPI_MODE_ONE       (0U << 31)
@@ -576,8 +587,8 @@ struct rdists {
                 phys_addr_t     phys_base;
         } __percpu              *rdist;
         struct page             *prop_page;
-        int                     id_bits;
         u64                     flags;
+        u32                     gicd_typer;
         bool                    has_vlpis;
         bool                    has_direct_lpi;
 };
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 68d8b1f73682..6c4aaf04046c 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -71,6 +71,16 @@
                                         (GICD_INT_DEF_PRI << 8) |\
                                         GICD_INT_DEF_PRI)
 
+#define GICD_IIDR_IMPLEMENTER_SHIFT     0
+#define GICD_IIDR_IMPLEMENTER_MASK      (0xfff << GICD_IIDR_IMPLEMENTER_SHIFT)
+#define GICD_IIDR_REVISION_SHIFT        12
+#define GICD_IIDR_REVISION_MASK         (0xf << GICD_IIDR_REVISION_SHIFT)
+#define GICD_IIDR_VARIANT_SHIFT         16
+#define GICD_IIDR_VARIANT_MASK          (0xf << GICD_IIDR_VARIANT_SHIFT)
+#define GICD_IIDR_PRODUCT_ID_SHIFT      24
+#define GICD_IIDR_PRODUCT_ID_MASK       (0xff << GICD_IIDR_PRODUCT_ID_SHIFT)
+
+
 #define GICH_HCR                        0x0
 #define GICH_VTR                        0x4
 #define GICH_VMCR                       0x8
@@ -94,6 +104,7 @@
 #define GICH_LR_PENDING_BIT             (1 << 28)
 #define GICH_LR_ACTIVE_BIT              (1 << 29)
 #define GICH_LR_EOI                     (1 << 19)
+#define GICH_LR_GROUP1                  (1 << 30)
 #define GICH_LR_HW                      (1 << 31)
 
 #define GICH_VMCR_ENABLE_GRP0_SHIFT     0