1 files changed, 22 insertions, 1 deletions

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index f711be6e8c44..210a890008f9 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -399,6 +399,7 @@ struct clk_divider {
         spinlock_t      *lock;
 };
 
+#define clk_div_mask(width)     ((1 << (width)) - 1)
 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
 
 #define CLK_DIVIDER_ONE_BASED           BIT(0)
@@ -419,6 +420,10 @@ long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
                                unsigned long rate, unsigned long *prate,
                                const struct clk_div_table *table,
                                u8 width, unsigned long flags);
+long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
+                                  unsigned long rate, unsigned long *prate,
+                                  const struct clk_div_table *table, u8 width,
+                                  unsigned long flags, unsigned int val);
 int divider_get_val(unsigned long rate, unsigned long parent_rate,
                 const struct clk_div_table *table, u8 width,
                 unsigned long flags);
@@ -449,8 +454,9 @@ void clk_hw_unregister_divider(struct clk_hw *hw);
  *
  * @hw:         handle between common and hardware-specific interfaces
  * @reg:        register controlling multiplexer
+ * @table:      array of register values corresponding to the parent index
  * @shift:      shift to multiplexer bit field
- * @width:      width of mutliplexer bit field
+ * @mask:       mask of mutliplexer bit field
  * @flags:      hardware-specific flags
  * @lock:       register lock
  *
@@ -510,6 +516,10 @@ struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
                 void __iomem *reg, u8 shift, u32 mask,
                 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
 
+int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
+                         unsigned int val);
+unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
+
 void clk_unregister_mux(struct clk *clk);
 void clk_hw_unregister_mux(struct clk_hw *hw);
 
@@ -774,6 +784,17 @@ static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
                                          rate, prate, table, width, flags);
 }
 
+static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
+                                         unsigned long *prate,
+                                         const struct clk_div_table *table,
+                                         u8 width, unsigned long flags,
+                                         unsigned int val)
+{
+        return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
+                                            rate, prate, table, width, flags,
+                                            val);
+}
+
 /*
  * FIXME clock api without lock protection
  */