16 files changed, 550 insertions, 20 deletions

diff --git a/include/dt-bindings/clock/actions,s500-cmu.h b/include/dt-bindings/clock/actions,s500-cmu.h
new file mode 100644
index 000000000000..030981cd2d56
--- /dev/null
+++ b/include/dt-bindings/clock/actions,s500-cmu.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Device Tree binding constants for Actions Semi S500 Clock Management Unit
+ *
+ * Copyright (c) 2014 Actions Semi Inc.
+ * Copyright (c) 2018 LSI-TEC - Caninos Loucos
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_S500_CMU_H
+#define __DT_BINDINGS_CLOCK_S500_CMU_H
+
+#define CLK_NONE                0
+
+/* fixed rate clocks */
+#define CLK_LOSC                1
+#define CLK_HOSC                2
+
+/* pll clocks */
+#define CLK_CORE_PLL            3
+#define CLK_DEV_PLL             4
+#define CLK_DDR_PLL             5
+#define CLK_NAND_PLL            6
+#define CLK_DISPLAY_PLL         7
+#define CLK_ETHERNET_PLL        8
+#define CLK_AUDIO_PLL           9
+
+/* system clock */
+#define CLK_DEV                 10
+#define CLK_H                   11
+#define CLK_AHBPREDIV           12
+#define CLK_AHB                 13
+#define CLK_DE                  14
+#define CLK_BISP                15
+#define CLK_VCE                 16
+#define CLK_VDE                 17
+
+/* peripheral device clock */
+#define CLK_TIMER               18
+#define CLK_I2C0                19
+#define CLK_I2C1                20
+#define CLK_I2C2                21
+#define CLK_I2C3                22
+#define CLK_PWM0                23
+#define CLK_PWM1                24
+#define CLK_PWM2                25
+#define CLK_PWM3                26
+#define CLK_PWM4                27
+#define CLK_PWM5                28
+#define CLK_SD0                 29
+#define CLK_SD1                 30
+#define CLK_SD2                 31
+#define CLK_SENSOR0             32
+#define CLK_SENSOR1             33
+#define CLK_SPI0                34
+#define CLK_SPI1                35
+#define CLK_SPI2                36
+#define CLK_SPI3                37
+#define CLK_UART0               38
+#define CLK_UART1               39
+#define CLK_UART2               40
+#define CLK_UART3               41
+#define CLK_UART4               42
+#define CLK_UART5               43
+#define CLK_UART6               44
+#define CLK_DE1                 45
+#define CLK_DE2                 46
+#define CLK_I2SRX               47
+#define CLK_I2STX               48
+#define CLK_HDMI_AUDIO          49
+#define CLK_HDMI                50
+#define CLK_SPDIF               51
+#define CLK_NAND                52
+#define CLK_ECC                 53
+#define CLK_RMII_REF            54
+
+#define CLK_NR_CLKS            (CLK_RMII_REF + 1)
+
+#endif /* __DT_BINDINGS_CLOCK_S500_CMU_H */
diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h
index 61955016a55b..8ec4a269c7a6 100644
--- a/include/dt-bindings/clock/axg-aoclkc.h
+++ b/include/dt-bindings/clock/axg-aoclkc.h
@@ -21,6 +21,11 @@
 #define CLKID_AO_SAR_ADC_SEL    8
 #define CLKID_AO_SAR_ADC_DIV    9
 #define CLKID_AO_SAR_ADC_CLK    10
-#define CLKID_AO_ALT_XTAL       11
+#define CLKID_AO_CTS_OSCIN      11
+#define CLKID_AO_32K_PRE        12
+#define CLKID_AO_32K_DIV        13
+#define CLKID_AO_32K_SEL        14
+#define CLKID_AO_32K            15
+#define CLKID_AO_CTS_RTC_OSCIN  16
 
 #endif
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 98bd85ce1e45..25ffa53573a5 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -156,7 +156,7 @@
 #define CLK_ACLK_G2D_266                220
 #define CLK_ACLK_G2D_400                221
 #define CLK_ACLK_G3D_400                222
-#define CLK_ACLK_IMEM_SSX_266           223
+#define CLK_ACLK_IMEM_SSSX_266          223
 #define CLK_ACLK_BUS0_400               224
 #define CLK_ACLK_BUS1_400               225
 #define CLK_ACLK_IMEM_200               226
@@ -1406,4 +1406,10 @@
 
 #define CAM1_NR_CLK                                     113
 
+/* CMU_IMEM */
+#define CLK_ACLK_SLIMSSS                2
+#define CLK_PCLK_SLIMSSS                35
+
+#define IMEM_NR_CLK                     36
+
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
diff --git a/include/dt-bindings/clock/g12a-aoclkc.h b/include/dt-bindings/clock/g12a-aoclkc.h
new file mode 100644
index 000000000000..8db01ffbeb06
--- /dev/null
+++ b/include/dt-bindings/clock/g12a-aoclkc.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
+
+#define CLKID_AO_AHB            0
+#define CLKID_AO_IR_IN          1
+#define CLKID_AO_I2C_M0         2
+#define CLKID_AO_I2C_S0         3
+#define CLKID_AO_UART           4
+#define CLKID_AO_PROD_I2C       5
+#define CLKID_AO_UART2          6
+#define CLKID_AO_IR_OUT         7
+#define CLKID_AO_SAR_ADC        8
+#define CLKID_AO_MAILBOX        9
+#define CLKID_AO_M3             10
+#define CLKID_AO_AHB_SRAM       11
+#define CLKID_AO_RTI            12
+#define CLKID_AO_M4_FCLK        13
+#define CLKID_AO_M4_HCLK        14
+#define CLKID_AO_CLK81          15
+#define CLKID_AO_SAR_ADC_CLK    18
+#define CLKID_AO_32K            23
+#define CLKID_AO_CEC            27
+#define CLKID_AO_CTS_RTC_OSCIN  28
+
+#endif
diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h
new file mode 100644
index 000000000000..83b657038d1e
--- /dev/null
+++ b/include/dt-bindings/clock/g12a-clkc.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
+/*
+ * Meson-G12A clock tree IDs
+ *
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __G12A_CLKC_H
+#define __G12A_CLKC_H
+
+#define CLKID_SYS_PLL                           0
+#define CLKID_FIXED_PLL                         1
+#define CLKID_FCLK_DIV2                         2
+#define CLKID_FCLK_DIV3                         3
+#define CLKID_FCLK_DIV4                         4
+#define CLKID_FCLK_DIV5                         5
+#define CLKID_FCLK_DIV7                         6
+#define CLKID_GP0_PLL                           7
+#define CLKID_CLK81                             10
+#define CLKID_MPLL0                             11
+#define CLKID_MPLL1                             12
+#define CLKID_MPLL2                             13
+#define CLKID_MPLL3                             14
+#define CLKID_DDR                               15
+#define CLKID_DOS                               16
+#define CLKID_AUDIO_LOCKER                      17
+#define CLKID_MIPI_DSI_HOST                     18
+#define CLKID_ETH_PHY                           19
+#define CLKID_ISA                               20
+#define CLKID_PL301                             21
+#define CLKID_PERIPHS                           22
+#define CLKID_SPICC0                            23
+#define CLKID_I2C                               24
+#define CLKID_SANA                              25
+#define CLKID_SD                                26
+#define CLKID_RNG0                              27
+#define CLKID_UART0                             28
+#define CLKID_SPICC1                            29
+#define CLKID_HIU_IFACE                         30
+#define CLKID_MIPI_DSI_PHY                      31
+#define CLKID_ASSIST_MISC                       32
+#define CLKID_SD_EMMC_A                         33
+#define CLKID_SD_EMMC_B                         34
+#define CLKID_SD_EMMC_C                         35
+#define CLKID_AUDIO_CODEC                       36
+#define CLKID_AUDIO                             37
+#define CLKID_ETH                               38
+#define CLKID_DEMUX                             39
+#define CLKID_AUDIO_IFIFO                       40
+#define CLKID_ADC                               41
+#define CLKID_UART1                             42
+#define CLKID_G2D                               43
+#define CLKID_RESET                             44
+#define CLKID_PCIE_COMB                         45
+#define CLKID_PARSER                            46
+#define CLKID_USB                               47
+#define CLKID_PCIE_PHY                          48
+#define CLKID_AHB_ARB0                          49
+#define CLKID_AHB_DATA_BUS                      50
+#define CLKID_AHB_CTRL_BUS                      51
+#define CLKID_HTX_HDCP22                        52
+#define CLKID_HTX_PCLK                          53
+#define CLKID_BT656                             54
+#define CLKID_USB1_DDR_BRIDGE                   55
+#define CLKID_MMC_PCLK                          56
+#define CLKID_UART2                             57
+#define CLKID_VPU_INTR                          58
+#define CLKID_GIC                               59
+#define CLKID_SD_EMMC_A_CLK0                    60
+#define CLKID_SD_EMMC_B_CLK0                    61
+#define CLKID_SD_EMMC_C_CLK0                    62
+#define CLKID_HIFI_PLL                          74
+#define CLKID_VCLK2_VENCI0                      80
+#define CLKID_VCLK2_VENCI1                      81
+#define CLKID_VCLK2_VENCP0                      82
+#define CLKID_VCLK2_VENCP1                      83
+#define CLKID_VCLK2_VENCT0                      84
+#define CLKID_VCLK2_VENCT1                      85
+#define CLKID_VCLK2_OTHER                       86
+#define CLKID_VCLK2_ENCI                        87
+#define CLKID_VCLK2_ENCP                        88
+#define CLKID_DAC_CLK                           89
+#define CLKID_AOCLK                             90
+#define CLKID_IEC958                            91
+#define CLKID_ENC480P                           92
+#define CLKID_RNG1                              93
+#define CLKID_VCLK2_ENCT                        94
+#define CLKID_VCLK2_ENCL                        95
+#define CLKID_VCLK2_VENCLMMC                    96
+#define CLKID_VCLK2_VENCL                       97
+#define CLKID_VCLK2_OTHER1                      98
+#define CLKID_FCLK_DIV2P5                       99
+#define CLKID_DMA                               105
+#define CLKID_EFUSE                             106
+#define CLKID_ROM_BOOT                          107
+#define CLKID_RESET_SEC                         108
+#define CLKID_SEC_AHB_APB3                      109
+#define CLKID_VPU_0_SEL                         110
+#define CLKID_VPU_0                             112
+#define CLKID_VPU_1_SEL                         113
+#define CLKID_VPU_1                             115
+#define CLKID_VPU                               116
+#define CLKID_VAPB_0_SEL                        117
+#define CLKID_VAPB_0                            119
+#define CLKID_VAPB_1_SEL                        120
+#define CLKID_VAPB_1                            122
+#define CLKID_VAPB_SEL                          123
+#define CLKID_VAPB                              124
+#define CLKID_HDMI_PLL                          128
+#define CLKID_VID_PLL                           129
+#define CLKID_VCLK                              138
+#define CLKID_VCLK2                             139
+#define CLKID_VCLK_DIV1                         148
+#define CLKID_VCLK_DIV2                         149
+#define CLKID_VCLK_DIV4                         150
+#define CLKID_VCLK_DIV6                         151
+#define CLKID_VCLK_DIV12                        152
+#define CLKID_VCLK2_DIV1                        153
+#define CLKID_VCLK2_DIV2                        154
+#define CLKID_VCLK2_DIV4                        155
+#define CLKID_VCLK2_DIV6                        156
+#define CLKID_VCLK2_DIV12                       157
+#define CLKID_CTS_ENCI                          162
+#define CLKID_CTS_ENCP                          163
+#define CLKID_CTS_VDAC                          164
+#define CLKID_HDMI_TX                           165
+#define CLKID_HDMI                              168
+#define CLKID_MALI_0_SEL                        169
+#define CLKID_MALI_0                            171
+#define CLKID_MALI_1_SEL                        172
+#define CLKID_MALI_1                            174
+#define CLKID_MALI                              175
+#define CLKID_MPLL_5OM                          177
+
+#endif /* __G12A_CLKC_H */
diff --git a/include/dt-bindings/clock/gxbb-aoclkc.h b/include/dt-bindings/clock/gxbb-aoclkc.h
index 9d15e2221fdb..ec3b26319fc4 100644
--- a/include/dt-bindings/clock/gxbb-aoclkc.h
+++ b/include/dt-bindings/clock/gxbb-aoclkc.h
@@ -63,5 +63,12 @@
 #define CLKID_AO_UART2          4
 #define CLKID_AO_IR_BLASTER     5
 #define CLKID_AO_CEC_32K        6
+#define CLKID_AO_CTS_OSCIN      7
+#define CLKID_AO_32K_PRE        8
+#define CLKID_AO_32K_DIV        9
+#define CLKID_AO_32K_SEL        10
+#define CLKID_AO_32K            11
+#define CLKID_AO_CTS_RTC_OSCIN  12
+#define CLKID_AO_CLK81          13
 
 #endif
diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h
index d382fc71aa83..a81be5be6700 100644
--- a/include/dt-bindings/clock/imx5-clock.h
+++ b/include/dt-bindings/clock/imx5-clock.h
@@ -214,6 +214,7 @@
 #define IMX5_CLK_IEEE1588_SEL           202
 #define IMX5_CLK_IEEE1588_PODF          203
 #define IMX5_CLK_IEEE1588_GATE          204
-#define IMX5_CLK_END                    205
+#define IMX5_CLK_SCC2_IPG_GATE          205
+#define IMX5_CLK_END                    206
 
 #endif /* __DT_BINDINGS_CLOCK_IMX5_H */
diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
new file mode 100644
index 000000000000..1b4353e7b486
--- /dev/null
+++ b/include/dt-bindings/clock/imx8mm-clock.h
@@ -0,0 +1,244 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2017-2018 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H
+#define __DT_BINDINGS_CLOCK_IMX8MM_H
+
+#define IMX8MM_CLK_DUMMY                        0
+#define IMX8MM_CLK_32K                          1
+#define IMX8MM_CLK_24M                          2
+#define IMX8MM_OSC_HDMI_CLK                     3
+#define IMX8MM_CLK_EXT1                         4
+#define IMX8MM_CLK_EXT2                         5
+#define IMX8MM_CLK_EXT3                         6
+#define IMX8MM_CLK_EXT4                         7
+#define IMX8MM_AUDIO_PLL1_REF_SEL               8
+#define IMX8MM_AUDIO_PLL2_REF_SEL               9
+#define IMX8MM_VIDEO_PLL1_REF_SEL               10
+#define IMX8MM_DRAM_PLL_REF_SEL                 11
+#define IMX8MM_GPU_PLL_REF_SEL                  12
+#define IMX8MM_VPU_PLL_REF_SEL                  13
+#define IMX8MM_ARM_PLL_REF_SEL                  14
+#define IMX8MM_SYS_PLL1_REF_SEL                 15
+#define IMX8MM_SYS_PLL2_REF_SEL                 16
+#define IMX8MM_SYS_PLL3_REF_SEL                 17
+#define IMX8MM_AUDIO_PLL1                       18
+#define IMX8MM_AUDIO_PLL2                       19
+#define IMX8MM_VIDEO_PLL1                       20
+#define IMX8MM_DRAM_PLL                         21
+#define IMX8MM_GPU_PLL                          22
+#define IMX8MM_VPU_PLL                          23
+#define IMX8MM_ARM_PLL                          24
+#define IMX8MM_SYS_PLL1                         25
+#define IMX8MM_SYS_PLL2                         26
+#define IMX8MM_SYS_PLL3                         27
+#define IMX8MM_AUDIO_PLL1_BYPASS                28
+#define IMX8MM_AUDIO_PLL2_BYPASS                29
+#define IMX8MM_VIDEO_PLL1_BYPASS                30
+#define IMX8MM_DRAM_PLL_BYPASS                  31
+#define IMX8MM_GPU_PLL_BYPASS                   32
+#define IMX8MM_VPU_PLL_BYPASS                   33
+#define IMX8MM_ARM_PLL_BYPASS                   34
+#define IMX8MM_SYS_PLL1_BYPASS                  35
+#define IMX8MM_SYS_PLL2_BYPASS                  36
+#define IMX8MM_SYS_PLL3_BYPASS                  37
+#define IMX8MM_AUDIO_PLL1_OUT                   38
+#define IMX8MM_AUDIO_PLL2_OUT                   39
+#define IMX8MM_VIDEO_PLL1_OUT                   40
+#define IMX8MM_DRAM_PLL_OUT                     41
+#define IMX8MM_GPU_PLL_OUT                      42
+#define IMX8MM_VPU_PLL_OUT                      43
+#define IMX8MM_ARM_PLL_OUT                      44
+#define IMX8MM_SYS_PLL1_OUT                     45
+#define IMX8MM_SYS_PLL2_OUT                     46
+#define IMX8MM_SYS_PLL3_OUT                     47
+#define IMX8MM_SYS_PLL1_40M                     48
+#define IMX8MM_SYS_PLL1_80M                     49
+#define IMX8MM_SYS_PLL1_100M                    50
+#define IMX8MM_SYS_PLL1_133M                    51
+#define IMX8MM_SYS_PLL1_160M                    52
+#define IMX8MM_SYS_PLL1_200M                    53
+#define IMX8MM_SYS_PLL1_266M                    54
+#define IMX8MM_SYS_PLL1_400M                    55
+#define IMX8MM_SYS_PLL1_800M                    56
+#define IMX8MM_SYS_PLL2_50M                     57
+#define IMX8MM_SYS_PLL2_100M                    58
+#define IMX8MM_SYS_PLL2_125M                    59
+#define IMX8MM_SYS_PLL2_166M                    60
+#define IMX8MM_SYS_PLL2_200M                    61
+#define IMX8MM_SYS_PLL2_250M                    62
+#define IMX8MM_SYS_PLL2_333M                    63
+#define IMX8MM_SYS_PLL2_500M                    64
+#define IMX8MM_SYS_PLL2_1000M                   65
+
+/* core */
+#define IMX8MM_CLK_A53_SRC                      66
+#define IMX8MM_CLK_M4_SRC                       67
+#define IMX8MM_CLK_VPU_SRC                      68
+#define IMX8MM_CLK_GPU3D_SRC                    69
+#define IMX8MM_CLK_GPU2D_SRC                    70
+#define IMX8MM_CLK_A53_CG                       71
+#define IMX8MM_CLK_M4_CG                        72
+#define IMX8MM_CLK_VPU_CG                       73
+#define IMX8MM_CLK_GPU3D_CG                     74
+#define IMX8MM_CLK_GPU2D_CG                     75
+#define IMX8MM_CLK_A53_DIV                      76
+#define IMX8MM_CLK_M4_DIV                       77
+#define IMX8MM_CLK_VPU_DIV                      78
+#define IMX8MM_CLK_GPU3D_DIV                    79
+#define IMX8MM_CLK_GPU2D_DIV                    80
+
+/* bus */
+#define IMX8MM_CLK_MAIN_AXI                     81
+#define IMX8MM_CLK_ENET_AXI                     82
+#define IMX8MM_CLK_NAND_USDHC_BUS               83
+#define IMX8MM_CLK_VPU_BUS                      84
+#define IMX8MM_CLK_DISP_AXI                     85
+#define IMX8MM_CLK_DISP_APB                     86
+#define IMX8MM_CLK_DISP_RTRM                    87
+#define IMX8MM_CLK_USB_BUS                      88
+#define IMX8MM_CLK_GPU_AXI                      89
+#define IMX8MM_CLK_GPU_AHB                      90
+#define IMX8MM_CLK_NOC                          91
+#define IMX8MM_CLK_NOC_APB                      92
+
+#define IMX8MM_CLK_AHB                          93
+#define IMX8MM_CLK_AUDIO_AHB                    94
+#define IMX8MM_CLK_IPG_ROOT                     95
+#define IMX8MM_CLK_IPG_AUDIO_ROOT               96
+
+#define IMX8MM_CLK_DRAM_ALT                     97
+#define IMX8MM_CLK_DRAM_APB                     98
+#define IMX8MM_CLK_VPU_G1                       99
+#define IMX8MM_CLK_VPU_G2                       100
+#define IMX8MM_CLK_DISP_DTRC                    101
+#define IMX8MM_CLK_DISP_DC8000                  102
+#define IMX8MM_CLK_PCIE1_CTRL                   103
+#define IMX8MM_CLK_PCIE1_PHY                    104
+#define IMX8MM_CLK_PCIE1_AUX                    105
+#define IMX8MM_CLK_DC_PIXEL                     106
+#define IMX8MM_CLK_LCDIF_PIXEL                  107
+#define IMX8MM_CLK_SAI1                         108
+#define IMX8MM_CLK_SAI2                         109
+#define IMX8MM_CLK_SAI3                         110
+#define IMX8MM_CLK_SAI4                         111
+#define IMX8MM_CLK_SAI5                         112
+#define IMX8MM_CLK_SAI6                         113
+#define IMX8MM_CLK_SPDIF1                       114
+#define IMX8MM_CLK_SPDIF2                       115
+#define IMX8MM_CLK_ENET_REF                     116
+#define IMX8MM_CLK_ENET_TIMER                   117
+#define IMX8MM_CLK_ENET_PHY_REF                 118
+#define IMX8MM_CLK_NAND                         119
+#define IMX8MM_CLK_QSPI                         120
+#define IMX8MM_CLK_USDHC1                       121
+#define IMX8MM_CLK_USDHC2                       122
+#define IMX8MM_CLK_I2C1                         123
+#define IMX8MM_CLK_I2C2                         124
+#define IMX8MM_CLK_I2C3                         125
+#define IMX8MM_CLK_I2C4                         126
+#define IMX8MM_CLK_UART1                        127
+#define IMX8MM_CLK_UART2                        128
+#define IMX8MM_CLK_UART3                        129
+#define IMX8MM_CLK_UART4                        130
+#define IMX8MM_CLK_USB_CORE_REF                 131
+#define IMX8MM_CLK_USB_PHY_REF                  132
+#define IMX8MM_CLK_ECSPI1                       133
+#define IMX8MM_CLK_ECSPI2                       134
+#define IMX8MM_CLK_PWM1                         135
+#define IMX8MM_CLK_PWM2                         136
+#define IMX8MM_CLK_PWM3                         137
+#define IMX8MM_CLK_PWM4                         138
+#define IMX8MM_CLK_GPT1                         139
+#define IMX8MM_CLK_WDOG                         140
+#define IMX8MM_CLK_WRCLK                        141
+#define IMX8MM_CLK_DSI_CORE                     142
+#define IMX8MM_CLK_DSI_PHY_REF                  143
+#define IMX8MM_CLK_DSI_DBI                      144
+#define IMX8MM_CLK_USDHC3                       145
+#define IMX8MM_CLK_CSI1_CORE                    146
+#define IMX8MM_CLK_CSI1_PHY_REF                 147
+#define IMX8MM_CLK_CSI1_ESC                     148
+#define IMX8MM_CLK_CSI2_CORE                    149
+#define IMX8MM_CLK_CSI2_PHY_REF                 150
+#define IMX8MM_CLK_CSI2_ESC                     151
+#define IMX8MM_CLK_PCIE2_CTRL                   152
+#define IMX8MM_CLK_PCIE2_PHY                    153
+#define IMX8MM_CLK_PCIE2_AUX                    154
+#define IMX8MM_CLK_ECSPI3                       155
+#define IMX8MM_CLK_PDM                          156
+#define IMX8MM_CLK_VPU_H1                       157
+#define IMX8MM_CLK_CLKO1                        158
+
+#define IMX8MM_CLK_ECSPI1_ROOT                  159
+#define IMX8MM_CLK_ECSPI2_ROOT                  160
+#define IMX8MM_CLK_ECSPI3_ROOT                  161
+#define IMX8MM_CLK_ENET1_ROOT                   162
+#define IMX8MM_CLK_GPT1_ROOT                    163
+#define IMX8MM_CLK_I2C1_ROOT                    164
+#define IMX8MM_CLK_I2C2_ROOT                    165
+#define IMX8MM_CLK_I2C3_ROOT                    166
+#define IMX8MM_CLK_I2C4_ROOT                    167
+#define IMX8MM_CLK_OCOTP_ROOT                   168
+#define IMX8MM_CLK_PCIE1_ROOT                   169
+#define IMX8MM_CLK_PWM1_ROOT                    170
+#define IMX8MM_CLK_PWM2_ROOT                    171
+#define IMX8MM_CLK_PWM3_ROOT                    172
+#define IMX8MM_CLK_PWM4_ROOT                    173
+#define IMX8MM_CLK_QSPI_ROOT                    174
+#define IMX8MM_CLK_NAND_ROOT                    175
+#define IMX8MM_CLK_SAI1_ROOT                    176
+#define IMX8MM_CLK_SAI1_IPG                     177
+#define IMX8MM_CLK_SAI2_ROOT                    178
+#define IMX8MM_CLK_SAI2_IPG                     179
+#define IMX8MM_CLK_SAI3_ROOT                    180
+#define IMX8MM_CLK_SAI3_IPG                     181
+#define IMX8MM_CLK_SAI4_ROOT                    182
+#define IMX8MM_CLK_SAI4_IPG                     183
+#define IMX8MM_CLK_SAI5_ROOT                    184
+#define IMX8MM_CLK_SAI5_IPG                     185
+#define IMX8MM_CLK_SAI6_ROOT                    186
+#define IMX8MM_CLK_SAI6_IPG                     187
+#define IMX8MM_CLK_UART1_ROOT                   188
+#define IMX8MM_CLK_UART2_ROOT                   189
+#define IMX8MM_CLK_UART3_ROOT                   190
+#define IMX8MM_CLK_UART4_ROOT                   191
+#define IMX8MM_CLK_USB1_CTRL_ROOT               192
+#define IMX8MM_CLK_GPU3D_ROOT                   193
+#define IMX8MM_CLK_USDHC1_ROOT                  194
+#define IMX8MM_CLK_USDHC2_ROOT                  195
+#define IMX8MM_CLK_WDOG1_ROOT                   196
+#define IMX8MM_CLK_WDOG2_ROOT                   197
+#define IMX8MM_CLK_WDOG3_ROOT                   198
+#define IMX8MM_CLK_VPU_G1_ROOT                  199
+#define IMX8MM_CLK_GPU_BUS_ROOT                 200
+#define IMX8MM_CLK_VPU_H1_ROOT                  201
+#define IMX8MM_CLK_VPU_G2_ROOT                  202
+#define IMX8MM_CLK_PDM_ROOT                     203
+#define IMX8MM_CLK_DISP_ROOT                    204
+#define IMX8MM_CLK_DISP_AXI_ROOT                205
+#define IMX8MM_CLK_DISP_APB_ROOT                206
+#define IMX8MM_CLK_DISP_RTRM_ROOT               207
+#define IMX8MM_CLK_USDHC3_ROOT                  208
+#define IMX8MM_CLK_TMU_ROOT                     209
+#define IMX8MM_CLK_VPU_DEC_ROOT                 210
+#define IMX8MM_CLK_SDMA1_ROOT                   211
+#define IMX8MM_CLK_SDMA2_ROOT                   212
+#define IMX8MM_CLK_SDMA3_ROOT                   213
+#define IMX8MM_CLK_GPT_3M                       214
+#define IMX8MM_CLK_ARM                          215
+#define IMX8MM_CLK_PDM_IPG                      216
+#define IMX8MM_CLK_GPU2D_ROOT                   217
+#define IMX8MM_CLK_MU_ROOT                      218
+#define IMX8MM_CLK_CSI1_ROOT                    219
+
+#define IMX8MM_CLK_DRAM_CORE                    220
+#define IMX8MM_CLK_DRAM_ALT_ROOT                221
+
+#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK   222
+
+#define IMX8MM_CLK_END                          223
+
+#endif
diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
index b53be41929be..b58cc643c9c9 100644
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -350,7 +350,7 @@
 #define IMX8MQ_CLK_VPU_G2_ROOT                  241
 
 /* SCCG PLL GATE */
-#define IMX8MQ_SYS1_PLL_OUT                     232
+#define IMX8MQ_SYS1_PLL_OUT                     242
 #define IMX8MQ_SYS2_PLL_OUT                     243
 #define IMX8MQ_SYS3_PLL_OUT                     244
 #define IMX8MQ_DRAM_PLL_OUT                     245
@@ -372,24 +372,33 @@
 /* txesc clock */
 #define IMX8MQ_CLK_DSI_IPG_DIV                  256
 
-#define IMX8MQ_CLK_TMU_ROOT                     265
+#define IMX8MQ_CLK_TMU_ROOT                     257
 
 /* Display root clocks */
-#define IMX8MQ_CLK_DISP_AXI_ROOT                266
-#define IMX8MQ_CLK_DISP_APB_ROOT                267
-#define IMX8MQ_CLK_DISP_RTRM_ROOT               268
+#define IMX8MQ_CLK_DISP_AXI_ROOT                258
+#define IMX8MQ_CLK_DISP_APB_ROOT                259
+#define IMX8MQ_CLK_DISP_RTRM_ROOT               260
 
-#define IMX8MQ_CLK_OCOTP_ROOT                   269
+#define IMX8MQ_CLK_OCOTP_ROOT                   261
 
-#define IMX8MQ_CLK_DRAM_ALT_ROOT                270
-#define IMX8MQ_CLK_DRAM_CORE                    271
+#define IMX8MQ_CLK_DRAM_ALT_ROOT                262
+#define IMX8MQ_CLK_DRAM_CORE                    263
 
-#define IMX8MQ_CLK_MU_ROOT                      272
-#define IMX8MQ_VIDEO2_PLL_OUT                   273
+#define IMX8MQ_CLK_MU_ROOT                      264
+#define IMX8MQ_VIDEO2_PLL_OUT                   265
 
-#define IMX8MQ_CLK_CLKO2                        274
+#define IMX8MQ_CLK_CLKO2                        266
 
-#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK   275
+#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK   267
 
-#define IMX8MQ_CLK_END                          276
+#define IMX8MQ_CLK_CLKO1                        268
+#define IMX8MQ_CLK_ARM                          269
+
+#define IMX8MQ_CLK_GPIO1_ROOT                   270
+#define IMX8MQ_CLK_GPIO2_ROOT                   271
+#define IMX8MQ_CLK_GPIO3_ROOT                   272
+#define IMX8MQ_CLK_GPIO4_ROOT                   273
+#define IMX8MQ_CLK_GPIO5_ROOT                   274
+
+#define IMX8MQ_CLK_END                          275
 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
diff --git a/include/dt-bindings/clock/marvell,mmp2.h b/include/dt-bindings/clock/marvell,mmp2.h
index 7b24fc791146..e785c6eb3561 100644
--- a/include/dt-bindings/clock/marvell,mmp2.h
+++ b/include/dt-bindings/clock/marvell,mmp2.h
@@ -71,7 +71,7 @@
 #define MMP2_CLK_CCIC1_MIX              117
 #define MMP2_CLK_CCIC1_PHY              118
 #define MMP2_CLK_CCIC1_SPHY             119
-#define MMP2_CLK_SP                     120
+#define MMP2_CLK_DISP0_LCDC             120
 
 #define MMP2_NR_CLKS                    200
 #endif
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index 5fe2923382d0..8067077a62ca 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -104,6 +104,7 @@
 #define CLKID_MPLL2             95
 #define CLKID_NAND_CLK          112
 #define CLKID_ABP               124
+#define CLKID_APB               124
 #define CLKID_PERIPH            126
 #define CLKID_AXI               128
 #define CLKID_L2_DRAM           130
diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h
index 3658b0c14966..ede93a0ca156 100644
--- a/include/dt-bindings/clock/qcom,rpmcc.h
+++ b/include/dt-bindings/clock/qcom,rpmcc.h
@@ -127,5 +127,15 @@
 #define RPM_SMD_BIMC_GPU_A_CLK                  77
 #define RPM_SMD_QPIC_CLK                        78
 #define RPM_SMD_QPIC_CLK_A                      79
+#define RPM_SMD_LN_BB_CLK1                      80
+#define RPM_SMD_LN_BB_CLK1_A                    81
+#define RPM_SMD_LN_BB_CLK2                      82
+#define RPM_SMD_LN_BB_CLK2_A                    83
+#define RPM_SMD_LN_BB_CLK3_PIN                  84
+#define RPM_SMD_LN_BB_CLK3_A_PIN                85
+#define RPM_SMD_RF_CLK3                         86
+#define RPM_SMD_RF_CLK3_A                       87
+#define RPM_SMD_RF_CLK3_PIN                     88
+#define RPM_SMD_RF_CLK3_A_PIN                   89
 
 #endif
diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h
index f48fbd6f2095..edcab3f7b7d3 100644
--- a/include/dt-bindings/clock/qcom,rpmh.h
+++ b/include/dt-bindings/clock/qcom,rpmh.h
@@ -18,5 +18,6 @@
 #define RPMH_RF_CLK2_A                          9
 #define RPMH_RF_CLK3                            10
 #define RPMH_RF_CLK3_A                          11
+#define RPMH_IPA_CLK                            12
 
 #endif
diff --git a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
index 9bc5d45ff4b5..e355363f40c2 100644
--- a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h
@@ -54,5 +54,6 @@
 #define R8A774A1_CLK_CPEX               43
 #define R8A774A1_CLK_R                  44
 #define R8A774A1_CLK_OSC                45
+#define R8A774A1_CLK_CANFD              46
 
 #endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a774c0-cpg-mssr.h b/include/dt-bindings/clock/r8a774c0-cpg-mssr.h
index 8fe51b6aca28..8ad9cd6be8e9 100644
--- a/include/dt-bindings/clock/r8a774c0-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a774c0-cpg-mssr.h
@@ -56,5 +56,6 @@
 #define R8A774C0_CLK_CSI0               45
 #define R8A774C0_CLK_CP                 46
 #define R8A774C0_CLK_CPEX               47
+#define R8A774C0_CLK_CANFD              48
 
 #endif /* __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h
index 90ec780bfc68..4cdaf135829c 100644
--- a/include/dt-bindings/clock/stm32mp1-clks.h
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -248,7 +248,4 @@
 
 #define STM32MP1_LAST_CLK 232
 
-#define LTDC_K          LTDC_PX
-#define ETHMAC_K        ETHCK_K
-
 #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */