9 files changed, 352 insertions, 82 deletions

diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 514beb2d483a..bdb0d5548f39 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -68,7 +68,6 @@
 #include <drm/drm_agpsupport.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_fourcc.h>
-#include <drm/drm_global.h>
 #include <drm/drm_hashtab.h>
 #include <drm/drm_mm.h>
 #include <drm/drm_os_linux.h>
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 2f38d3598eb4..665b9cae7f43 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -508,6 +508,18 @@ struct drm_connector_state {
          * drm_writeback_signal_completion()
          */
         struct drm_writeback_job *writeback_job;
+
+        /**
+         * @max_requested_bpc: Connector property to limit the maximum bit
+         * depth of the pixels.
+         */
+        u8 max_requested_bpc;
+
+        /**
+         * @max_bpc: Connector max_bpc based on the requested max_bpc property
+         * and the connector bpc limitations obtained from edid.
+         */
+        u8 max_bpc;
 };
 
 /**
@@ -973,6 +985,12 @@ struct drm_connector {
          */
         struct drm_property_blob *path_blob_ptr;
 
+        /**
+         * @max_bpc_property: Default connector property for the max bpc to be
+         * driven out of the connector.
+         */
+        struct drm_property *max_bpc_property;
+
 #define DRM_CONNECTOR_POLL_HPD (1 << 0)
 #define DRM_CONNECTOR_POLL_CONNECT (1 << 1)
 #define DRM_CONNECTOR_POLL_DISCONNECT (1 << 2)
@@ -1245,6 +1263,8 @@ void drm_connector_set_link_status_property(struct drm_connector *connector,
                                             uint64_t link_status);
 int drm_connector_init_panel_orientation_property(
         struct drm_connector *connector, int width, int height);
+int drm_connector_attach_max_bpc_property(struct drm_connector *connector,
+                                          int min, int max);
 
 /**
  * struct drm_tile_group - Tile group metadata
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 9ad98e8d9ede..3314e91f6eb3 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -231,6 +231,8 @@
 #define DP_DSC_MAX_BITS_PER_PIXEL_LOW       0x067   /* eDP 1.4 */
 
 #define DP_DSC_MAX_BITS_PER_PIXEL_HI        0x068   /* eDP 1.4 */
+# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK  (0x3 << 0)
+# define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8
 
 #define DP_DSC_DEC_COLOR_FORMAT_CAP         0x069
 # define DP_DSC_RGB                         (1 << 0)
@@ -279,6 +281,8 @@
 # define DP_DSC_THROUGHPUT_MODE_1_1000      (14 << 4)
 
 #define DP_DSC_MAX_SLICE_WIDTH              0x06C
+#define DP_DSC_MIN_SLICE_WIDTH_VALUE        2560
+#define DP_DSC_SLICE_WIDTH_MULTIPLIER       320
 
 #define DP_DSC_SLICE_CAP_2                  0x06D
 # define DP_DSC_16_PER_DP_DSC_SINK          (1 << 0)
@@ -477,6 +481,7 @@
 # define DP_AUX_FRAME_SYNC_VALID            (1 << 0)
 
 #define DP_DSC_ENABLE                       0x160   /* DP 1.4 */
+# define DP_DECOMPRESSION_EN                (1 << 0)
 
 #define DP_PSR_EN_CFG                       0x170   /* XXX 1.2? */
 # define DP_PSR_ENABLE                      (1 << 0)
@@ -907,6 +912,57 @@
 #define DP_AUX_HDCP_KSV_FIFO            0x6802C
 #define DP_AUX_HDCP_AINFO               0x6803B
 
+/* DP HDCP2.2 parameter offsets in DPCD address space */
+#define DP_HDCP_2_2_REG_RTX_OFFSET              0x69000
+#define DP_HDCP_2_2_REG_TXCAPS_OFFSET           0x69008
+#define DP_HDCP_2_2_REG_CERT_RX_OFFSET          0x6900B
+#define DP_HDCP_2_2_REG_RRX_OFFSET              0x69215
+#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET          0x6921D
+#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET         0x69220
+#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET        0x692A0
+#define DP_HDCP_2_2_REG_M_OFFSET                0x692B0
+#define DP_HDCP_2_2_REG_HPRIME_OFFSET           0x692C0
+#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET        0x692E0
+#define DP_HDCP_2_2_REG_RN_OFFSET               0x692F0
+#define DP_HDCP_2_2_REG_LPRIME_OFFSET           0x692F8
+#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET         0x69318
+#define DP_HDCP_2_2_REG_RIV_OFFSET              0x69328
+#define DP_HDCP_2_2_REG_RXINFO_OFFSET           0x69330
+#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET        0x69332
+#define DP_HDCP_2_2_REG_VPRIME_OFFSET           0x69335
+#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET     0x69345
+#define DP_HDCP_2_2_REG_V_OFFSET                0x693E0
+#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET        0x693F0
+#define DP_HDCP_2_2_REG_K_OFFSET                0x693F3
+#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET   0x693F5
+#define DP_HDCP_2_2_REG_MPRIME_OFFSET           0x69473
+#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET         0x69493
+#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET      0x69494
+#define DP_HDCP_2_2_REG_DBG_OFFSET              0x69518
+
+/* DP HDCP message start offsets in DPCD address space */
+#define DP_HDCP_2_2_AKE_INIT_OFFSET             DP_HDCP_2_2_REG_RTX_OFFSET
+#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET        DP_HDCP_2_2_REG_CERT_RX_OFFSET
+#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET     DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
+#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET        DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET
+#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET      DP_HDCP_2_2_REG_HPRIME_OFFSET
+#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
+                                                DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
+#define DP_HDCP_2_2_LC_INIT_OFFSET              DP_HDCP_2_2_REG_RN_OFFSET
+#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET       DP_HDCP_2_2_REG_LPRIME_OFFSET
+#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET         DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
+#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET
+#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET         DP_HDCP_2_2_REG_V_OFFSET
+#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET    DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
+#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET     DP_HDCP_2_2_REG_MPRIME_OFFSET
+
+#define HDCP_2_2_DP_RXSTATUS_LEN                1
+#define HDCP_2_2_DP_RXSTATUS_READY(x)           ((x) & BIT(0))
+#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x)         ((x) & BIT(1))
+#define HDCP_2_2_DP_RXSTATUS_PAIRING(x)         ((x) & BIT(2))
+#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x)      ((x) & BIT(3))
+#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x)     ((x) & BIT(4))
+
 /* DP 1.2 Sideband message defines */
 /* peer device type - DP 1.2a Table 2-92 */
 #define DP_PEER_DEVICE_NONE             0x0
@@ -965,6 +1021,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
 
 #define DP_BRANCH_OUI_HEADER_SIZE       0xc
 #define DP_RECEIVER_CAP_SIZE            0xf
+#define DP_DSC_RECEIVER_CAP_SIZE        0xf
 #define EDP_PSR_RECEIVER_CAP_SIZE       2
 #define EDP_DISPLAY_CTL_CAP_SIZE        3
 
@@ -995,6 +1052,7 @@ struct dp_sdp_header {
 
 #define EDP_SDP_HEADER_REVISION_MASK            0x1F
 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES      0x1F
+#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
 
 struct edp_vsc_psr {
         struct dp_sdp_header sdp_header;
@@ -1061,6 +1119,43 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
         return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
 }
 
+/* DP/eDP DSC support */
+u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
+                                   bool is_edp);
+u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
+u8 drm_dp_dsc_sink_max_color_depth(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE]);
+
+static inline bool
+drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+        return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
+                DP_DSC_DECOMPRESSION_IS_SUPPORTED;
+}
+
+static inline u16
+drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+        return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
+                (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
+                 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK <<
+                 DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT);
+}
+
+static inline u32
+drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+        /* Max Slicewidth = Number of Pixels * 320 */
+        return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
+                DP_DSC_SLICE_WIDTH_MULTIPLIER;
+}
+
+/* Forward Error Correction Support on DP 1.4 */
+static inline bool
+drm_dp_sink_supports_fec(const u8 fec_capable)
+{
+        return fec_capable & DP_FEC_CAPABLE;
+}
+
 /*
  * DisplayPort AUX channel
  */
diff --git a/include/drm/drm_global.h b/include/drm/drm_global.h
deleted file mode 100644
index 3a830602a2e4..000000000000
--- a/include/drm/drm_global.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/**************************************************************************
- *
- * Copyright 2008-2009 VMware, Inc., Palo Alto, CA., USA
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
-/*
- * Authors: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
- */
-
-#ifndef _DRM_GLOBAL_H_
-#define _DRM_GLOBAL_H_
-enum drm_global_types {
-        DRM_GLOBAL_TTM_MEM = 0,
-        DRM_GLOBAL_TTM_BO,
-        DRM_GLOBAL_TTM_OBJECT,
-        DRM_GLOBAL_NUM
-};
-
-struct drm_global_reference {
-        enum drm_global_types global_type;
-        size_t size;
-        void *object;
-        int (*init) (struct drm_global_reference *);
-        void (*release) (struct drm_global_reference *);
-};
-
-void drm_global_init(void);
-void drm_global_release(void);
-int drm_global_item_ref(struct drm_global_reference *ref);
-void drm_global_item_unref(struct drm_global_reference *ref);
-
-#endif
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index 98e63d870139..a6de09c5e47f 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -38,4 +38,216 @@
 #define DRM_HDCP_DDC_BSTATUS                    0x41
 #define DRM_HDCP_DDC_KSV_FIFO                   0x43
 
+#define DRM_HDCP_1_4_SRM_ID                     0x8
+#define DRM_HDCP_1_4_VRL_LENGTH_SIZE            3
+#define DRM_HDCP_1_4_DCP_SIG_SIZE               40
+
+/* Protocol message definition for HDCP2.2 specification */
+/*
+ * Protected content streams are classified into 2 types:
+ * - Type0: Can be transmitted with HDCP 1.4+
+ * - Type1: Can be transmitted with HDCP 2.2+
+ */
+#define HDCP_STREAM_TYPE0                       0x00
+#define HDCP_STREAM_TYPE1                       0x01
+
+/* HDCP2.2 Msg IDs */
+#define HDCP_2_2_NULL_MSG                       1
+#define HDCP_2_2_AKE_INIT                       2
+#define HDCP_2_2_AKE_SEND_CERT                  3
+#define HDCP_2_2_AKE_NO_STORED_KM               4
+#define HDCP_2_2_AKE_STORED_KM                  5
+#define HDCP_2_2_AKE_SEND_HPRIME                7
+#define HDCP_2_2_AKE_SEND_PAIRING_INFO          8
+#define HDCP_2_2_LC_INIT                        9
+#define HDCP_2_2_LC_SEND_LPRIME                 10
+#define HDCP_2_2_SKE_SEND_EKS                   11
+#define HDCP_2_2_REP_SEND_RECVID_LIST           12
+#define HDCP_2_2_REP_SEND_ACK                   15
+#define HDCP_2_2_REP_STREAM_MANAGE              16
+#define HDCP_2_2_REP_STREAM_READY               17
+#define HDCP_2_2_ERRATA_DP_STREAM_TYPE          50
+
+#define HDCP_2_2_RTX_LEN                        8
+#define HDCP_2_2_RRX_LEN                        8
+
+#define HDCP_2_2_K_PUB_RX_MOD_N_LEN             128
+#define HDCP_2_2_K_PUB_RX_EXP_E_LEN             3
+#define HDCP_2_2_K_PUB_RX_LEN                   (HDCP_2_2_K_PUB_RX_MOD_N_LEN + \
+                                                 HDCP_2_2_K_PUB_RX_EXP_E_LEN)
+
+#define HDCP_2_2_DCP_LLC_SIG_LEN                384
+
+#define HDCP_2_2_E_KPUB_KM_LEN                  128
+#define HDCP_2_2_E_KH_KM_M_LEN                  (16 + 16)
+#define HDCP_2_2_H_PRIME_LEN                    32
+#define HDCP_2_2_E_KH_KM_LEN                    16
+#define HDCP_2_2_RN_LEN                         8
+#define HDCP_2_2_L_PRIME_LEN                    32
+#define HDCP_2_2_E_DKEY_KS_LEN                  16
+#define HDCP_2_2_RIV_LEN                        8
+#define HDCP_2_2_SEQ_NUM_LEN                    3
+#define HDCP_2_2_V_PRIME_HALF_LEN               (HDCP_2_2_L_PRIME_LEN / 2)
+#define HDCP_2_2_RECEIVER_ID_LEN                DRM_HDCP_KSV_LEN
+#define HDCP_2_2_MAX_DEVICE_COUNT               31
+#define HDCP_2_2_RECEIVER_IDS_MAX_LEN           (HDCP_2_2_RECEIVER_ID_LEN * \
+                                                 HDCP_2_2_MAX_DEVICE_COUNT)
+#define HDCP_2_2_MPRIME_LEN                     32
+
+/* Following Macros take a byte at a time for bit(s) masking */
+/*
+ * TODO: This has to be changed for DP MST, as multiple stream on
+ * same port is possible.
+ * For HDCP2.2 on HDMI and DP SST this value is always 1.
+ */
+#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT        1
+#define HDCP_2_2_TXCAP_MASK_LEN                 2
+#define HDCP_2_2_RXCAPS_LEN                     3
+#define HDCP_2_2_RX_REPEATER(x)                 ((x) & BIT(0))
+#define HDCP_2_2_DP_HDCP_CAPABLE(x)             ((x) & BIT(1))
+#define HDCP_2_2_RXINFO_LEN                     2
+
+/* HDCP1.x compliant device in downstream */
+#define HDCP_2_2_HDCP1_DEVICE_CONNECTED(x)      ((x) & BIT(0))
+
+/* HDCP2.0 Compliant repeater in downstream */
+#define HDCP_2_2_HDCP_2_0_REP_CONNECTED(x)      ((x) & BIT(1))
+#define HDCP_2_2_MAX_CASCADE_EXCEEDED(x)        ((x) & BIT(2))
+#define HDCP_2_2_MAX_DEVS_EXCEEDED(x)           ((x) & BIT(3))
+#define HDCP_2_2_DEV_COUNT_LO(x)                (((x) & (0xF << 4)) >> 4)
+#define HDCP_2_2_DEV_COUNT_HI(x)                ((x) & BIT(0))
+#define HDCP_2_2_DEPTH(x)                       (((x) & (0x7 << 1)) >> 1)
+
+struct hdcp2_cert_rx {
+        u8      receiver_id[HDCP_2_2_RECEIVER_ID_LEN];
+        u8      kpub_rx[HDCP_2_2_K_PUB_RX_LEN];
+        u8      reserved[2];
+        u8      dcp_signature[HDCP_2_2_DCP_LLC_SIG_LEN];
+} __packed;
+
+struct hdcp2_streamid_type {
+        u8      stream_id;
+        u8      stream_type;
+} __packed;
+
+/*
+ * The TxCaps field specified in the HDCP HDMI, DP specs
+ * This field is big endian as specified in the errata.
+ */
+struct hdcp2_tx_caps {
+        /* Transmitter must set this to 0x2 */
+        u8      version;
+
+        /* Reserved for HDCP and DP Spec. Read as Zero */
+        u8      tx_cap_mask[HDCP_2_2_TXCAP_MASK_LEN];
+} __packed;
+
+/* Main structures for HDCP2.2 protocol communication */
+struct hdcp2_ake_init {
+        u8                      msg_id;
+        u8                      r_tx[HDCP_2_2_RTX_LEN];
+        struct hdcp2_tx_caps    tx_caps;
+} __packed;
+
+struct hdcp2_ake_send_cert {
+        u8                      msg_id;
+        struct hdcp2_cert_rx    cert_rx;
+        u8                      r_rx[HDCP_2_2_RRX_LEN];
+        u8                      rx_caps[HDCP_2_2_RXCAPS_LEN];
+} __packed;
+
+struct hdcp2_ake_no_stored_km {
+        u8      msg_id;
+        u8      e_kpub_km[HDCP_2_2_E_KPUB_KM_LEN];
+} __packed;
+
+struct hdcp2_ake_stored_km {
+        u8      msg_id;
+        u8      e_kh_km_m[HDCP_2_2_E_KH_KM_M_LEN];
+} __packed;
+
+struct hdcp2_ake_send_hprime {
+        u8      msg_id;
+        u8      h_prime[HDCP_2_2_H_PRIME_LEN];
+} __packed;
+
+struct hdcp2_ake_send_pairing_info {
+        u8      msg_id;
+        u8      e_kh_km[HDCP_2_2_E_KH_KM_LEN];
+} __packed;
+
+struct hdcp2_lc_init {
+        u8      msg_id;
+        u8      r_n[HDCP_2_2_RN_LEN];
+} __packed;
+
+struct hdcp2_lc_send_lprime {
+        u8      msg_id;
+        u8      l_prime[HDCP_2_2_L_PRIME_LEN];
+} __packed;
+
+struct hdcp2_ske_send_eks {
+        u8      msg_id;
+        u8      e_dkey_ks[HDCP_2_2_E_DKEY_KS_LEN];
+        u8      riv[HDCP_2_2_RIV_LEN];
+} __packed;
+
+struct hdcp2_rep_send_receiverid_list {
+        u8      msg_id;
+        u8      rx_info[HDCP_2_2_RXINFO_LEN];
+        u8      seq_num_v[HDCP_2_2_SEQ_NUM_LEN];
+        u8      v_prime[HDCP_2_2_V_PRIME_HALF_LEN];
+        u8      receiver_ids[HDCP_2_2_RECEIVER_IDS_MAX_LEN];
+} __packed;
+
+struct hdcp2_rep_send_ack {
+        u8      msg_id;
+        u8      v[HDCP_2_2_V_PRIME_HALF_LEN];
+} __packed;
+
+struct hdcp2_rep_stream_manage {
+        u8                      msg_id;
+        u8                      seq_num_m[HDCP_2_2_SEQ_NUM_LEN];
+        __be16                  k;
+        struct hdcp2_streamid_type streams[HDCP_2_2_MAX_CONTENT_STREAMS_CNT];
+} __packed;
+
+struct hdcp2_rep_stream_ready {
+        u8      msg_id;
+        u8      m_prime[HDCP_2_2_MPRIME_LEN];
+} __packed;
+
+struct hdcp2_dp_errata_stream_type {
+        u8      msg_id;
+        u8      stream_type;
+} __packed;
+
+/* HDCP2.2 TIMEOUTs in mSec */
+#define HDCP_2_2_CERT_TIMEOUT_MS                100
+#define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS    1000
+#define HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS       200
+#define HDCP_2_2_PAIRING_TIMEOUT_MS             200
+#define HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS         20
+#define HDCP_2_2_DP_LPRIME_TIMEOUT_MS           7
+#define HDCP_2_2_RECVID_LIST_TIMEOUT_MS         3000
+#define HDCP_2_2_STREAM_READY_TIMEOUT_MS        100
+
+/* HDMI HDCP2.2 Register Offsets */
+#define HDCP_2_2_HDMI_REG_VER_OFFSET            0x50
+#define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET         0x60
+#define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET       0x70
+#define HDCP_2_2_HDMI_REG_RD_MSG_OFFSET         0x80
+#define HDCP_2_2_HDMI_REG_DBG_OFFSET            0xC0
+
+#define HDCP_2_2_HDMI_SUPPORT_MASK              BIT(2)
+#define HDCP_2_2_RX_CAPS_VERSION_VAL            0x02
+#define HDCP_2_2_SEQ_NUM_MAX                    0xFFFFFF
+#define HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN     200
+
+/* Below macros take a byte at a time and mask the bit(s) */
+#define HDCP_2_2_HDMI_RXSTATUS_LEN              2
+#define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x)     ((x) & 0x3)
+#define HDCP_2_2_HDMI_RXSTATUS_READY(x)         ((x) & BIT(2))
+#define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x)    ((x) & BIT(3))
+
 #endif
diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h
index d87b268f1781..926379d53484 100644
--- a/include/drm/gpu_scheduler.h
+++ b/include/drm/gpu_scheduler.h
@@ -264,6 +264,7 @@ struct drm_sched_backend_ops {
  * @hang_limit: once the hangs by a job crosses this limit then it is marked
  *              guilty and it will be considered for scheduling further.
  * @num_jobs: the number of jobs in queue in the scheduler
+ * @ready: marks if the underlying HW is ready to work
  *
  * One scheduler is implemented for each hardware ring.
  */
@@ -283,22 +284,26 @@ struct drm_gpu_scheduler {
         spinlock_t                      job_list_lock;
         int                             hang_limit;
         atomic_t                        num_jobs;
+        bool                    ready;
 };
 
 int drm_sched_init(struct drm_gpu_scheduler *sched,
                    const struct drm_sched_backend_ops *ops,
                    uint32_t hw_submission, unsigned hang_limit, long timeout,
                    const char *name);
+
 void drm_sched_fini(struct drm_gpu_scheduler *sched);
 int drm_sched_job_init(struct drm_sched_job *job,
                        struct drm_sched_entity *entity,
                        void *owner);
+void drm_sched_job_cleanup(struct drm_sched_job *job);
 void drm_sched_wakeup(struct drm_gpu_scheduler *sched);
 void drm_sched_hw_job_reset(struct drm_gpu_scheduler *sched,
                             struct drm_sched_job *job);
 void drm_sched_job_recovery(struct drm_gpu_scheduler *sched);
 bool drm_sched_dependency_optimized(struct dma_fence* fence,
                                     struct drm_sched_entity *entity);
+void drm_sched_fault(struct drm_gpu_scheduler *sched);
 void drm_sched_job_kickout(struct drm_sched_job *s_job);
 
 void drm_sched_rq_add_entity(struct drm_sched_rq *rq,
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index fd965ffbb92e..192667144693 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -365,16 +365,20 @@
         INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
 
 /* AML/KBL Y GT2 */
-#define INTEL_AML_GT2_IDS(info) \
+#define INTEL_AML_KBL_GT2_IDS(info) \
         INTEL_VGA_DEVICE(0x591C, info),  /* ULX GT2 */ \
         INTEL_VGA_DEVICE(0x87C0, info) /* ULX GT2 */
 
+/* AML/CFL Y GT2 */
+#define INTEL_AML_CFL_GT2_IDS(info) \
+        INTEL_VGA_DEVICE(0x87CA, info)
+
 #define INTEL_KBL_IDS(info) \
         INTEL_KBL_GT1_IDS(info), \
         INTEL_KBL_GT2_IDS(info), \
         INTEL_KBL_GT3_IDS(info), \
         INTEL_KBL_GT4_IDS(info), \
-        INTEL_AML_GT2_IDS(info)
+        INTEL_AML_KBL_GT2_IDS(info)
 
 /* CFL S */
 #define INTEL_CFL_S_GT1_IDS(info) \
@@ -407,17 +411,17 @@
 
 /* WHL/CFL U GT1 */
 #define INTEL_WHL_U_GT1_IDS(info) \
-        INTEL_VGA_DEVICE(0x3EA1, info)
+        INTEL_VGA_DEVICE(0x3EA1, info), \
+        INTEL_VGA_DEVICE(0x3EA4, info)
 
 /* WHL/CFL U GT2 */
 #define INTEL_WHL_U_GT2_IDS(info) \
-        INTEL_VGA_DEVICE(0x3EA0, info)
+        INTEL_VGA_DEVICE(0x3EA0, info), \
+        INTEL_VGA_DEVICE(0x3EA3, info)
 
 /* WHL/CFL U GT3 */
 #define INTEL_WHL_U_GT3_IDS(info) \
-        INTEL_VGA_DEVICE(0x3EA2, info), \
-        INTEL_VGA_DEVICE(0x3EA3, info), \
-        INTEL_VGA_DEVICE(0x3EA4, info)
+        INTEL_VGA_DEVICE(0x3EA2, info)
 
 #define INTEL_CFL_IDS(info)        \
         INTEL_CFL_S_GT1_IDS(info), \
@@ -427,7 +431,8 @@
         INTEL_CFL_U_GT3_IDS(info), \
         INTEL_WHL_U_GT1_IDS(info), \
         INTEL_WHL_U_GT2_IDS(info), \
-        INTEL_WHL_U_GT3_IDS(info)
+        INTEL_WHL_U_GT3_IDS(info), \
+        INTEL_AML_CFL_GT2_IDS(info)
 
 /* CNL */
 #define INTEL_CNL_IDS(info) \
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index e4fee8e02559..1021106438b2 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -31,7 +31,6 @@
 #define _TTM_BO_DRIVER_H_
 
 #include <drm/drm_mm.h>
-#include <drm/drm_global.h>
 #include <drm/drm_vma_manager.h>
 #include <linux/workqueue.h>
 #include <linux/fs.h>
@@ -385,15 +384,6 @@ struct ttm_bo_driver {
 };
 
 /**
- * struct ttm_bo_global_ref - Argument to initialize a struct ttm_bo_global.
- */
-
-struct ttm_bo_global_ref {
-        struct drm_global_reference ref;
-        struct ttm_mem_global *mem_glob;
-};
-
-/**
  * struct ttm_bo_global - Buffer object driver global data.
  *
  * @mem_glob: Pointer to a struct ttm_mem_global object for accounting.
@@ -407,7 +397,7 @@ struct ttm_bo_global_ref {
  * @swap_lru: Lru list of buffer objects used for swapping.
  */
 
-struct ttm_bo_global {
+extern struct ttm_bo_global {
 
         /**
          * Constant after init.
@@ -416,12 +406,12 @@ struct ttm_bo_global {
         struct kobject kobj;
         struct ttm_mem_global *mem_glob;
         struct page *dummy_read_page;
-        struct mutex device_list_mutex;
         spinlock_t lru_lock;
 
         /**
-         * Protected by device_list_mutex.
+         * Protected by ttm_global_mutex.
          */
+        unsigned int use_count;
         struct list_head device_list;
 
         /**
@@ -433,7 +423,7 @@ struct ttm_bo_global {
          * Internal protection.
          */
         atomic_t bo_count;
-};
+} ttm_bo_glob;
 
 
 #define TTM_NUM_MEM_TYPES 8
@@ -578,9 +568,6 @@ void ttm_bo_mem_put(struct ttm_buffer_object *bo, struct ttm_mem_reg *mem);
 void ttm_bo_mem_put_locked(struct ttm_buffer_object *bo,
                            struct ttm_mem_reg *mem);
 
-void ttm_bo_global_release(struct drm_global_reference *ref);
-int ttm_bo_global_init(struct drm_global_reference *ref);
-
 int ttm_bo_device_release(struct ttm_bo_device *bdev);
 
 /**
@@ -598,7 +585,7 @@ int ttm_bo_device_release(struct ttm_bo_device *bdev);
  * Returns:
  * !0: Failure.
  */
-int ttm_bo_device_init(struct ttm_bo_device *bdev, struct ttm_bo_global *glob,
+int ttm_bo_device_init(struct ttm_bo_device *bdev,
                        struct ttm_bo_driver *driver,
                        struct address_space *mapping,
                        uint64_t file_page_offset, bool need_dma32);
diff --git a/include/drm/ttm/ttm_memory.h b/include/drm/ttm/ttm_memory.h
index 737b5fed8003..3ff48a0a2d7b 100644
--- a/include/drm/ttm/ttm_memory.h
+++ b/include/drm/ttm/ttm_memory.h
@@ -63,7 +63,7 @@
 
 #define TTM_MEM_MAX_ZONES 2
 struct ttm_mem_zone;
-struct ttm_mem_global {
+extern struct ttm_mem_global {
         struct kobject kobj;
         struct ttm_bo_global *bo_glob;
         struct workqueue_struct *swap_queue;
@@ -78,7 +78,7 @@ struct ttm_mem_global {
 #else
         struct ttm_mem_zone *zone_dma32;
 #endif
-};
+} ttm_mem_glob;
 
 extern int ttm_mem_global_init(struct ttm_mem_global *glob);
 extern void ttm_mem_global_release(struct ttm_mem_global *glob);