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-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v2_0.c17
1 files changed, 9 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index 9ea99348e493..cb0b730ff77a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -167,8 +167,7 @@ static void vce_v2_0_init_cg(struct amdgpu_device *adev)
167 167
168static void vce_v2_0_mc_resume(struct amdgpu_device *adev) 168static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
169{ 169{
170 uint64_t addr = adev->vce.gpu_addr; 170 uint32_t size, offset;
171 uint32_t size;
172 171
173 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16)); 172 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
174 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); 173 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
@@ -181,19 +180,21 @@ static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
181 WREG32(mmVCE_LMI_SWAP_CNTL1, 0); 180 WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
182 WREG32(mmVCE_LMI_VM_CTRL, 0); 181 WREG32(mmVCE_LMI_VM_CTRL, 0);
183 182
184 addr += AMDGPU_VCE_FIRMWARE_OFFSET; 183 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
184
185 offset = AMDGPU_VCE_FIRMWARE_OFFSET;
185 size = VCE_V2_0_FW_SIZE; 186 size = VCE_V2_0_FW_SIZE;
186 WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff); 187 WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);
187 WREG32(mmVCE_VCPU_CACHE_SIZE0, size); 188 WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
188 189
189 addr += size; 190 offset += size;
190 size = VCE_V2_0_STACK_SIZE; 191 size = VCE_V2_0_STACK_SIZE;
191 WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff); 192 WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);
192 WREG32(mmVCE_VCPU_CACHE_SIZE1, size); 193 WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
193 194
194 addr += size; 195 offset += size;
195 size = VCE_V2_0_DATA_SIZE; 196 size = VCE_V2_0_DATA_SIZE;
196 WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff); 197 WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff);
197 WREG32(mmVCE_VCPU_CACHE_SIZE2, size); 198 WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
198 199
199 WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); 200 WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);