36 files changed, 1259 insertions, 72 deletions

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 6bdedd7cca2c..cf047c406d92 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -820,7 +820,7 @@ config PATA_PLATFORM
 
 config PATA_OF_PLATFORM
         tristate "OpenFirmware platform device PATA support"
-        depends on PATA_PLATFORM && OF
+        depends on PATA_PLATFORM && OF && OF_IRQ
         help
           This option enables support for generic directly connected ATA
           devices commonly found on embedded systems with OpenFirmware
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 8f0491037080..464fa2147dfb 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -65,4 +65,17 @@ config DEVFREQ_GOV_USERSPACE
 
 comment "DEVFREQ Drivers"
 
+config ARM_EXYNOS4_BUS_DEVFREQ
+        bool "ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver"
+        depends on CPU_EXYNOS4210 || CPU_EXYNOS4212 || CPU_EXYNOS4412
+        select ARCH_HAS_OPP
+        select DEVFREQ_GOV_SIMPLE_ONDEMAND
+        help
+          This adds the DEVFREQ driver for Exynos4210 memory bus (vdd_int)
+          and Exynos4212/4412 memory interface and bus (vdd_mif + vdd_int).
+          It reads PPMU counters of memory controllers and adjusts
+          the operating frequencies and voltages with OPP support.
+          To operate with optimal voltages, ASV support is required
+          (CONFIG_EXYNOS_ASV).
+
 endif # PM_DEVFREQ
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 4564a89e970a..8c464234f7e7 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -3,3 +3,6 @@ obj-$(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)	+= governor_simpleondemand.o
 obj-$(CONFIG_DEVFREQ_GOV_PERFORMANCE)   += governor_performance.o
 obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE)     += governor_powersave.o
 obj-$(CONFIG_DEVFREQ_GOV_USERSPACE)     += governor_userspace.o
+
+# DEVFREQ Drivers
+obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ)   += exynos4_bus.o
diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c
index 59d24e9cb8c5..c189b82f5ece 100644
--- a/drivers/devfreq/devfreq.c
+++ b/drivers/devfreq/devfreq.c
@@ -347,7 +347,7 @@ struct devfreq *devfreq_add_device(struct device *dev,
                 if (!IS_ERR(devfreq)) {
                         dev_err(dev, "%s: Unable to create devfreq for the device. It already has one.\n", __func__);
                         err = -EINVAL;
-                        goto out;
+                        goto err_out;
                 }
         }
 
@@ -356,7 +356,7 @@ struct devfreq *devfreq_add_device(struct device *dev,
                 dev_err(dev, "%s: Unable to create devfreq for the device\n",
                         __func__);
                 err = -ENOMEM;
-                goto out;
+                goto err_out;
         }
 
         mutex_init(&devfreq->lock);
@@ -399,17 +399,16 @@ struct devfreq *devfreq_add_device(struct device *dev,
                                    devfreq->next_polling);
         }
         mutex_unlock(&devfreq_list_lock);
-        goto out;
+out:
+        return devfreq;
+
 err_init:
         device_unregister(&devfreq->dev);
 err_dev:
         mutex_unlock(&devfreq->lock);
         kfree(devfreq);
-out:
-        if (err)
-                return ERR_PTR(err);
-        else
-                return devfreq;
+err_out:
+        return ERR_PTR(err);
 }
 
 /**
diff --git a/drivers/devfreq/exynos4_bus.c b/drivers/devfreq/exynos4_bus.c
new file mode 100644
index 000000000000..6460577d6701
--- /dev/null
+++ b/drivers/devfreq/exynos4_bus.c
@@ -0,0 +1,1135 @@
+/* drivers/devfreq/exynos4210_memorybus.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *      MyungJoo Ham <myungjoo.ham@samsung.com>
+ *
+ * EXYNOS4 - Memory/Bus clock frequency scaling support in DEVFREQ framework
+ *      This version supports EXYNOS4210 only. This changes bus frequencies
+ *      and vddint voltages. Exynos4412/4212 should be able to be supported
+ *      with minor modifications.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/mutex.h>
+#include <linux/suspend.h>
+#include <linux/opp.h>
+#include <linux/devfreq.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/module.h>
+
+/* Exynos4 ASV has been in the mailing list, but not upstreamed, yet. */
+#ifdef CONFIG_EXYNOS_ASV
+extern unsigned int exynos_result_of_asv;
+#endif
+
+#include <mach/regs-clock.h>
+
+#include <plat/map-s5p.h>
+
+#define MAX_SAFEVOLT    1200000 /* 1.2V */
+
+enum exynos4_busf_type {
+        TYPE_BUSF_EXYNOS4210,
+        TYPE_BUSF_EXYNOS4x12,
+};
+
+/* Assume that the bus is saturated if the utilization is 40% */
+#define BUS_SATURATION_RATIO    40
+
+enum ppmu_counter {
+        PPMU_PMNCNT0 = 0,
+        PPMU_PMCCNT1,
+        PPMU_PMNCNT2,
+        PPMU_PMNCNT3,
+        PPMU_PMNCNT_MAX,
+};
+struct exynos4_ppmu {
+        void __iomem *hw_base;
+        unsigned int ccnt;
+        unsigned int event;
+        unsigned int count[PPMU_PMNCNT_MAX];
+        bool ccnt_overflow;
+        bool count_overflow[PPMU_PMNCNT_MAX];
+};
+
+enum busclk_level_idx {
+        LV_0 = 0,
+        LV_1,
+        LV_2,
+        LV_3,
+        LV_4,
+        _LV_END
+};
+#define EX4210_LV_MAX   LV_2
+#define EX4x12_LV_MAX   LV_4
+#define EX4210_LV_NUM   (LV_2 + 1)
+#define EX4x12_LV_NUM   (LV_4 + 1)
+
+struct busfreq_data {
+        enum exynos4_busf_type type;
+        struct device *dev;
+        struct devfreq *devfreq;
+        bool disabled;
+        struct regulator *vdd_int;
+        struct regulator *vdd_mif; /* Exynos4412/4212 only */
+        struct opp *curr_opp;
+        struct exynos4_ppmu dmc[2];
+
+        struct notifier_block pm_notifier;
+        struct mutex lock;
+
+        /* Dividers calculated at boot/probe-time */
+        unsigned int dmc_divtable[_LV_END]; /* DMC0 */
+        unsigned int top_divtable[_LV_END];
+};
+
+struct bus_opp_table {
+        unsigned int idx;
+        unsigned long clk;
+        unsigned long volt;
+};
+
+/* 4210 controls clock of mif and voltage of int */
+static struct bus_opp_table exynos4210_busclk_table[] = {
+        {LV_0, 400000, 1150000},
+        {LV_1, 267000, 1050000},
+        {LV_2, 133000, 1025000},
+        {0, 0, 0},
+};
+
+/*
+ * MIF is the main control knob clock for exynox4x12 MIF/INT
+ * clock and voltage of both mif/int are controlled.
+ */
+static struct bus_opp_table exynos4x12_mifclk_table[] = {
+        {LV_0, 400000, 1100000},
+        {LV_1, 267000, 1000000},
+        {LV_2, 160000, 950000},
+        {LV_3, 133000, 950000},
+        {LV_4, 100000, 950000},
+        {0, 0, 0},
+};
+
+/*
+ * INT is not the control knob of 4x12. LV_x is not meant to represent
+ * the current performance. (MIF does)
+ */
+static struct bus_opp_table exynos4x12_intclk_table[] = {
+        {LV_0, 200000, 1000000},
+        {LV_1, 160000, 950000},
+        {LV_2, 133000, 925000},
+        {LV_3, 100000, 900000},
+        {0, 0, 0},
+};
+
+/* TODO: asv volt definitions are "__initdata"? */
+/* Some chips have different operating voltages */
+static unsigned int exynos4210_asv_volt[][EX4210_LV_NUM] = {
+        {1150000, 1050000, 1050000},
+        {1125000, 1025000, 1025000},
+        {1100000, 1000000, 1000000},
+        {1075000, 975000, 975000},
+        {1050000, 950000, 950000},
+};
+
+static unsigned int exynos4x12_mif_step_50[][EX4x12_LV_NUM] = {
+        /* 400      267     160     133     100 */
+        {1050000, 950000, 900000, 900000, 900000}, /* ASV0 */
+        {1050000, 950000, 900000, 900000, 900000}, /* ASV1 */
+        {1050000, 950000, 900000, 900000, 900000}, /* ASV2 */
+        {1050000, 900000, 900000, 900000, 900000}, /* ASV3 */
+        {1050000, 900000, 900000, 900000, 850000}, /* ASV4 */
+        {1050000, 900000, 900000, 850000, 850000}, /* ASV5 */
+        {1050000, 900000, 850000, 850000, 850000}, /* ASV6 */
+        {1050000, 900000, 850000, 850000, 850000}, /* ASV7 */
+        {1050000, 900000, 850000, 850000, 850000}, /* ASV8 */
+};
+
+static unsigned int exynos4x12_int_volt[][EX4x12_LV_NUM] = {
+        /* 200    160      133     100 */
+        {1000000, 950000, 925000, 900000}, /* ASV0 */
+        {975000,  925000, 925000, 900000}, /* ASV1 */
+        {950000,  925000, 900000, 875000}, /* ASV2 */
+        {950000,  900000, 900000, 875000}, /* ASV3 */
+        {925000,  875000, 875000, 875000}, /* ASV4 */
+        {900000,  850000, 850000, 850000}, /* ASV5 */
+        {900000,  850000, 850000, 850000}, /* ASV6 */
+        {900000,  850000, 850000, 850000}, /* ASV7 */
+        {900000,  850000, 850000, 850000}, /* ASV8 */
+};
+
+/*** Clock Divider Data for Exynos4210 ***/
+static unsigned int exynos4210_clkdiv_dmc0[][8] = {
+        /*
+         * Clock divider value for following
+         * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
+         *              DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
+         */
+
+        /* DMC L0: 400MHz */
+        { 3, 1, 1, 1, 1, 1, 3, 1 },
+        /* DMC L1: 266.7MHz */
+        { 4, 1, 1, 2, 1, 1, 3, 1 },
+        /* DMC L2: 133MHz */
+        { 5, 1, 1, 5, 1, 1, 3, 1 },
+};
+static unsigned int exynos4210_clkdiv_top[][5] = {
+        /*
+         * Clock divider value for following
+         * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
+         */
+        /* ACLK200 L0: 200MHz */
+        { 3, 7, 4, 5, 1 },
+        /* ACLK200 L1: 160MHz */
+        { 4, 7, 5, 6, 1 },
+        /* ACLK200 L2: 133MHz */
+        { 5, 7, 7, 7, 1 },
+};
+static unsigned int exynos4210_clkdiv_lr_bus[][2] = {
+        /*
+         * Clock divider value for following
+         * { DIVGDL/R, DIVGPL/R }
+         */
+        /* ACLK_GDL/R L1: 200MHz */
+        { 3, 1 },
+        /* ACLK_GDL/R L2: 160MHz */
+        { 4, 1 },
+        /* ACLK_GDL/R L3: 133MHz */
+        { 5, 1 },
+};
+
+/*** Clock Divider Data for Exynos4212/4412 ***/
+static unsigned int exynos4x12_clkdiv_dmc0[][6] = {
+        /*
+         * Clock divider value for following
+         * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
+         *              DIVDMCP}
+         */
+
+        /* DMC L0: 400MHz */
+        {3, 1, 1, 1, 1, 1},
+        /* DMC L1: 266.7MHz */
+        {4, 1, 1, 2, 1, 1},
+        /* DMC L2: 160MHz */
+        {5, 1, 1, 4, 1, 1},
+        /* DMC L3: 133MHz */
+        {5, 1, 1, 5, 1, 1},
+        /* DMC L4: 100MHz */
+        {7, 1, 1, 7, 1, 1},
+};
+static unsigned int exynos4x12_clkdiv_dmc1[][6] = {
+        /*
+         * Clock divider value for following
+         * { G2DACP, DIVC2C, DIVC2C_ACLK }
+         */
+
+        /* DMC L0: 400MHz */
+        {3, 1, 1},
+        /* DMC L1: 266.7MHz */
+        {4, 2, 1},
+        /* DMC L2: 160MHz */
+        {5, 4, 1},
+        /* DMC L3: 133MHz */
+        {5, 5, 1},
+        /* DMC L4: 100MHz */
+        {7, 7, 1},
+};
+static unsigned int exynos4x12_clkdiv_top[][5] = {
+        /*
+         * Clock divider value for following
+         * { DIVACLK266_GPS, DIVACLK100, DIVACLK160,
+                DIVACLK133, DIVONENAND }
+         */
+
+        /* ACLK_GDL/R L0: 200MHz */
+        {2, 7, 4, 5, 1},
+        /* ACLK_GDL/R L1: 200MHz */
+        {2, 7, 4, 5, 1},
+        /* ACLK_GDL/R L2: 160MHz */
+        {4, 7, 5, 7, 1},
+        /* ACLK_GDL/R L3: 133MHz */
+        {4, 7, 5, 7, 1},
+        /* ACLK_GDL/R L4: 100MHz */
+        {7, 7, 7, 7, 1},
+};
+static unsigned int exynos4x12_clkdiv_lr_bus[][2] = {
+        /*
+         * Clock divider value for following
+         * { DIVGDL/R, DIVGPL/R }
+         */
+
+        /* ACLK_GDL/R L0: 200MHz */
+        {3, 1},
+        /* ACLK_GDL/R L1: 200MHz */
+        {3, 1},
+        /* ACLK_GDL/R L2: 160MHz */
+        {4, 1},
+        /* ACLK_GDL/R L3: 133MHz */
+        {5, 1},
+        /* ACLK_GDL/R L4: 100MHz */
+        {7, 1},
+};
+static unsigned int exynos4x12_clkdiv_sclkip[][3] = {
+        /*
+         * Clock divider value for following
+         * { DIVMFC, DIVJPEG, DIVFIMC0~3}
+         */
+
+        /* SCLK_MFC: 200MHz */
+        {3, 3, 4},
+        /* SCLK_MFC: 200MHz */
+        {3, 3, 4},
+        /* SCLK_MFC: 160MHz */
+        {4, 4, 5},
+        /* SCLK_MFC: 133MHz */
+        {5, 5, 5},
+        /* SCLK_MFC: 100MHz */
+        {7, 7, 7},
+};
+
+
+static int exynos4210_set_busclk(struct busfreq_data *data, struct opp *opp)
+{
+        unsigned int index;
+        unsigned int tmp;
+
+        for (index = LV_0; index < EX4210_LV_NUM; index++)
+                if (opp_get_freq(opp) == exynos4210_busclk_table[index].clk)
+                        break;
+
+        if (index == EX4210_LV_NUM)
+                return -EINVAL;
+
+        /* Change Divider - DMC0 */
+        tmp = data->dmc_divtable[index];
+
+        __raw_writel(tmp, S5P_CLKDIV_DMC0);
+
+        do {
+                tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
+        } while (tmp & 0x11111111);
+
+        /* Change Divider - TOP */
+        tmp = data->top_divtable[index];
+
+        __raw_writel(tmp, S5P_CLKDIV_TOP);
+
+        do {
+                tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
+        } while (tmp & 0x11111);
+
+        /* Change Divider - LEFTBUS */
+        tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
+
+        tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
+
+        tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
+                                S5P_CLKDIV_BUS_GDLR_SHIFT) |
+                (exynos4210_clkdiv_lr_bus[index][1] <<
+                                S5P_CLKDIV_BUS_GPLR_SHIFT));
+
+        __raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
+
+        do {
+                tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
+        } while (tmp & 0x11);
+
+        /* Change Divider - RIGHTBUS */
+        tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
+
+        tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
+
+        tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
+                                S5P_CLKDIV_BUS_GDLR_SHIFT) |
+                (exynos4210_clkdiv_lr_bus[index][1] <<
+                                S5P_CLKDIV_BUS_GPLR_SHIFT));
+
+        __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
+
+        do {
+                tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
+        } while (tmp & 0x11);
+
+        return 0;
+}
+
+static int exynos4x12_set_busclk(struct busfreq_data *data, struct opp *opp)
+{
+        unsigned int index;
+        unsigned int tmp;
+
+        for (index = LV_0; index < EX4x12_LV_NUM; index++)
+                if (opp_get_freq(opp) == exynos4x12_mifclk_table[index].clk)
+                        break;
+
+        if (index == EX4x12_LV_NUM)
+                return -EINVAL;
+
+        /* Change Divider - DMC0 */
+        tmp = data->dmc_divtable[index];
+
+        __raw_writel(tmp, S5P_CLKDIV_DMC0);
+
+        do {
+                tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
+        } while (tmp & 0x11111111);
+
+        /* Change Divider - DMC1 */
+        tmp = __raw_readl(S5P_CLKDIV_DMC1);
+
+        tmp &= ~(S5P_CLKDIV_DMC1_G2D_ACP_MASK |
+                S5P_CLKDIV_DMC1_C2C_MASK |
+                S5P_CLKDIV_DMC1_C2CACLK_MASK);
+
+        tmp |= ((exynos4x12_clkdiv_dmc1[index][0] <<
+                                S5P_CLKDIV_DMC1_G2D_ACP_SHIFT) |
+                (exynos4x12_clkdiv_dmc1[index][1] <<
+                                S5P_CLKDIV_DMC1_C2C_SHIFT) |
+                (exynos4x12_clkdiv_dmc1[index][2] <<
+                                S5P_CLKDIV_DMC1_C2CACLK_SHIFT));
+
+        __raw_writel(tmp, S5P_CLKDIV_DMC1);
+
+        do {
+                tmp = __raw_readl(S5P_CLKDIV_STAT_DMC1);
+        } while (tmp & 0x111111);
+
+        /* Change Divider - TOP */
+        tmp = __raw_readl(S5P_CLKDIV_TOP);
+
+        tmp &= ~(S5P_CLKDIV_TOP_ACLK266_GPS_MASK |
+                S5P_CLKDIV_TOP_ACLK100_MASK |
+                S5P_CLKDIV_TOP_ACLK160_MASK |
+                S5P_CLKDIV_TOP_ACLK133_MASK |
+                S5P_CLKDIV_TOP_ONENAND_MASK);
+
+        tmp |= ((exynos4x12_clkdiv_top[index][0] <<
+                                S5P_CLKDIV_TOP_ACLK266_GPS_SHIFT) |
+                (exynos4x12_clkdiv_top[index][1] <<
+                                S5P_CLKDIV_TOP_ACLK100_SHIFT) |
+                (exynos4x12_clkdiv_top[index][2] <<
+                                S5P_CLKDIV_TOP_ACLK160_SHIFT) |
+                (exynos4x12_clkdiv_top[index][3] <<
+                                S5P_CLKDIV_TOP_ACLK133_SHIFT) |
+                (exynos4x12_clkdiv_top[index][4] <<
+                                S5P_CLKDIV_TOP_ONENAND_SHIFT));
+
+        __raw_writel(tmp, S5P_CLKDIV_TOP);
+
+        do {
+                tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
+        } while (tmp & 0x11111);
+
+        /* Change Divider - LEFTBUS */
+        tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
+
+        tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
+
+        tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
+                                S5P_CLKDIV_BUS_GDLR_SHIFT) |
+                (exynos4x12_clkdiv_lr_bus[index][1] <<
+                                S5P_CLKDIV_BUS_GPLR_SHIFT));
+
+        __raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
+
+        do {
+                tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
+        } while (tmp & 0x11);
+
+        /* Change Divider - RIGHTBUS */
+        tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
+
+        tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
+
+        tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
+                                S5P_CLKDIV_BUS_GDLR_SHIFT) |
+                (exynos4x12_clkdiv_lr_bus[index][1] <<
+                                S5P_CLKDIV_BUS_GPLR_SHIFT));
+
+        __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
+
+        do {
+                tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
+        } while (tmp & 0x11);
+
+        /* Change Divider - MFC */
+        tmp = __raw_readl(S5P_CLKDIV_MFC);
+
+        tmp &= ~(S5P_CLKDIV_MFC_MASK);
+
+        tmp |= ((exynos4x12_clkdiv_sclkip[index][0] <<
+                                S5P_CLKDIV_MFC_SHIFT));
+
+        __raw_writel(tmp, S5P_CLKDIV_MFC);
+
+        do {
+                tmp = __raw_readl(S5P_CLKDIV_STAT_MFC);
+        } while (tmp & 0x1);
+
+        /* Change Divider - JPEG */
+        tmp = __raw_readl(S5P_CLKDIV_CAM1);
+
+        tmp &= ~(S5P_CLKDIV_CAM1_JPEG_MASK);
+
+        tmp |= ((exynos4x12_clkdiv_sclkip[index][1] <<
+                                S5P_CLKDIV_CAM1_JPEG_SHIFT));
+
+        __raw_writel(tmp, S5P_CLKDIV_CAM1);
+
+        do {
+                tmp = __raw_readl(S5P_CLKDIV_STAT_CAM1);
+        } while (tmp & 0x1);
+
+        /* Change Divider - FIMC0~3 */
+        tmp = __raw_readl(S5P_CLKDIV_CAM);
+
+        tmp &= ~(S5P_CLKDIV_CAM_FIMC0_MASK | S5P_CLKDIV_CAM_FIMC1_MASK |
+                S5P_CLKDIV_CAM_FIMC2_MASK | S5P_CLKDIV_CAM_FIMC3_MASK);
+
+        tmp |= ((exynos4x12_clkdiv_sclkip[index][2] <<
+                                S5P_CLKDIV_CAM_FIMC0_SHIFT) |
+                (exynos4x12_clkdiv_sclkip[index][2] <<
+                                S5P_CLKDIV_CAM_FIMC1_SHIFT) |
+                (exynos4x12_clkdiv_sclkip[index][2] <<
+                                S5P_CLKDIV_CAM_FIMC2_SHIFT) |
+                (exynos4x12_clkdiv_sclkip[index][2] <<
+                                S5P_CLKDIV_CAM_FIMC3_SHIFT));
+
+        __raw_writel(tmp, S5P_CLKDIV_CAM);
+
+        do {
+                tmp = __raw_readl(S5P_CLKDIV_STAT_CAM1);
+        } while (tmp & 0x1111);
+
+        return 0;
+}
+
+
+static void busfreq_mon_reset(struct busfreq_data *data)
+{
+        unsigned int i;
+
+        for (i = 0; i < 2; i++) {
+                void __iomem *ppmu_base = data->dmc[i].hw_base;
+
+                /* Reset PPMU */
+                __raw_writel(0x8000000f, ppmu_base + 0xf010);
+                __raw_writel(0x8000000f, ppmu_base + 0xf050);
+                __raw_writel(0x6, ppmu_base + 0xf000);
+                __raw_writel(0x0, ppmu_base + 0xf100);
+
+                /* Set PPMU Event */
+                data->dmc[i].event = 0x6;
+                __raw_writel(((data->dmc[i].event << 12) | 0x1),
+                             ppmu_base + 0xfc);
+
+                /* Start PPMU */
+                __raw_writel(0x1, ppmu_base + 0xf000);
+        }
+}
+
+static void exynos4_read_ppmu(struct busfreq_data *data)
+{
+        int i, j;
+
+        for (i = 0; i < 2; i++) {
+                void __iomem *ppmu_base = data->dmc[i].hw_base;
+                u32 overflow;
+
+                /* Stop PPMU */
+                __raw_writel(0x0, ppmu_base + 0xf000);
+
+                /* Update local data from PPMU */
+                overflow = __raw_readl(ppmu_base + 0xf050);
+
+                data->dmc[i].ccnt = __raw_readl(ppmu_base + 0xf100);
+                data->dmc[i].ccnt_overflow = overflow & (1 << 31);
+
+                for (j = 0; j < PPMU_PMNCNT_MAX; j++) {
+                        data->dmc[i].count[j] = __raw_readl(
+                                        ppmu_base + (0xf110 + (0x10 * j)));
+                        data->dmc[i].count_overflow[j] = overflow & (1 << j);
+                }
+        }
+
+        busfreq_mon_reset(data);
+}
+
+static int exynos4x12_get_intspec(unsigned long mifclk)
+{
+        int i = 0;
+
+        while (exynos4x12_intclk_table[i].clk) {
+                if (exynos4x12_intclk_table[i].clk <= mifclk)
+                        return i;
+                i++;
+        }
+
+        return -EINVAL;
+}
+
+static int exynos4_bus_setvolt(struct busfreq_data *data, struct opp *opp,
+                               struct opp *oldopp)
+{
+        int err = 0, tmp;
+        unsigned long volt = opp_get_voltage(opp);
+
+        switch (data->type) {
+        case TYPE_BUSF_EXYNOS4210:
+                /* OPP represents DMC clock + INT voltage */
+                err = regulator_set_voltage(data->vdd_int, volt,
+                                            MAX_SAFEVOLT);
+                break;
+        case TYPE_BUSF_EXYNOS4x12:
+                /* OPP represents MIF clock + MIF voltage */
+                err = regulator_set_voltage(data->vdd_mif, volt,
+                                            MAX_SAFEVOLT);
+                if (err)
+                        break;
+
+                tmp = exynos4x12_get_intspec(opp_get_freq(opp));
+                if (tmp < 0) {
+                        err = tmp;
+                        regulator_set_voltage(data->vdd_mif,
+                                              opp_get_voltage(oldopp),
+                                              MAX_SAFEVOLT);
+                        break;
+                }
+                err = regulator_set_voltage(data->vdd_int,
+                                            exynos4x12_intclk_table[tmp].volt,
+                                            MAX_SAFEVOLT);
+                /*  Try to recover */
+                if (err)
+                        regulator_set_voltage(data->vdd_mif,
+                                              opp_get_voltage(oldopp),
+                                              MAX_SAFEVOLT);
+                break;
+        default:
+                err = -EINVAL;
+        }
+
+        return err;
+}
+
+static int exynos4_bus_target(struct device *dev, unsigned long *_freq)
+{
+        int err = 0;
+        struct platform_device *pdev = container_of(dev, struct platform_device,
+                                                    dev);
+        struct busfreq_data *data = platform_get_drvdata(pdev);
+        struct opp *opp = devfreq_recommended_opp(dev, _freq);
+        unsigned long old_freq = opp_get_freq(data->curr_opp);
+        unsigned long freq = opp_get_freq(opp);
+
+        if (old_freq == freq)
+                return 0;
+
+        dev_dbg(dev, "targetting %lukHz %luuV\n", freq, opp_get_voltage(opp));
+
+        mutex_lock(&data->lock);
+
+        if (data->disabled)
+                goto out;
+
+        if (old_freq < freq)
+                err = exynos4_bus_setvolt(data, opp, data->curr_opp);
+        if (err)
+                goto out;
+
+        if (old_freq != freq) {
+                switch (data->type) {
+                case TYPE_BUSF_EXYNOS4210:
+                        err = exynos4210_set_busclk(data, opp);
+                        break;
+                case TYPE_BUSF_EXYNOS4x12:
+                        err = exynos4x12_set_busclk(data, opp);
+                        break;
+                default:
+                        err = -EINVAL;
+                }
+        }
+        if (err)
+                goto out;
+
+        if (old_freq > freq)
+                err = exynos4_bus_setvolt(data, opp, data->curr_opp);
+        if (err)
+                goto out;
+
+        data->curr_opp = opp;
+out:
+        mutex_unlock(&data->lock);
+        return err;
+}
+
+static int exynos4_get_busier_dmc(struct busfreq_data *data)
+{
+        u64 p0 = data->dmc[0].count[0];
+        u64 p1 = data->dmc[1].count[0];
+
+        p0 *= data->dmc[1].ccnt;
+        p1 *= data->dmc[0].ccnt;
+
+        if (data->dmc[1].ccnt == 0)
+                return 0;
+
+        if (p0 > p1)
+                return 0;
+        return 1;
+}
+
+static int exynos4_bus_get_dev_status(struct device *dev,
+                                      struct devfreq_dev_status *stat)
+{
+        struct platform_device *pdev = container_of(dev, struct platform_device,
+                                                    dev);
+        struct busfreq_data *data = platform_get_drvdata(pdev);
+        int busier_dmc;
+        int cycles_x2 = 2; /* 2 x cycles */
+        void __iomem *addr;
+        u32 timing;
+        u32 memctrl;
+
+        exynos4_read_ppmu(data);
+        busier_dmc = exynos4_get_busier_dmc(data);
+        stat->current_frequency = opp_get_freq(data->curr_opp);
+
+        if (busier_dmc)
+                addr = S5P_VA_DMC1;
+        else
+                addr = S5P_VA_DMC0;
+
+        memctrl = __raw_readl(addr + 0x04); /* one of DDR2/3/LPDDR2 */
+        timing = __raw_readl(addr + 0x38); /* CL or WL/RL values */
+
+        switch ((memctrl >> 8) & 0xf) {
+        case 0x4: /* DDR2 */
+                cycles_x2 = ((timing >> 16) & 0xf) * 2;
+                break;
+        case 0x5: /* LPDDR2 */
+        case 0x6: /* DDR3 */
+                cycles_x2 = ((timing >> 8) & 0xf) + ((timing >> 0) & 0xf);
+                break;
+        default:
+                pr_err("%s: Unknown Memory Type(%d).\n", __func__,
+                       (memctrl >> 8) & 0xf);
+                return -EINVAL;
+        }
+
+        /* Number of cycles spent on memory access */
+        stat->busy_time = data->dmc[busier_dmc].count[0] / 2 * (cycles_x2 + 2);
+        stat->busy_time *= 100 / BUS_SATURATION_RATIO;
+        stat->total_time = data->dmc[busier_dmc].ccnt;
+
+        /* If the counters have overflown, retry */
+        if (data->dmc[busier_dmc].ccnt_overflow ||
+            data->dmc[busier_dmc].count_overflow[0])
+                return -EAGAIN;
+
+        return 0;
+}
+
+static void exynos4_bus_exit(struct device *dev)
+{
+        struct platform_device *pdev = container_of(dev, struct platform_device,
+                                                    dev);
+        struct busfreq_data *data = platform_get_drvdata(pdev);
+
+        devfreq_unregister_opp_notifier(dev, data->devfreq);
+}
+
+static struct devfreq_dev_profile exynos4_devfreq_profile = {
+        .initial_freq   = 400000,
+        .polling_ms     = 50,
+        .target         = exynos4_bus_target,
+        .get_dev_status = exynos4_bus_get_dev_status,
+        .exit           = exynos4_bus_exit,
+};
+
+static int exynos4210_init_tables(struct busfreq_data *data)
+{
+        u32 tmp;
+        int mgrp;
+        int i, err = 0;
+
+        tmp = __raw_readl(S5P_CLKDIV_DMC0);
+        for (i = LV_0; i < EX4210_LV_NUM; i++) {
+                tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK |
+                        S5P_CLKDIV_DMC0_ACPPCLK_MASK |
+                        S5P_CLKDIV_DMC0_DPHY_MASK |
+                        S5P_CLKDIV_DMC0_DMC_MASK |
+                        S5P_CLKDIV_DMC0_DMCD_MASK |
+                        S5P_CLKDIV_DMC0_DMCP_MASK |
+                        S5P_CLKDIV_DMC0_COPY2_MASK |
+                        S5P_CLKDIV_DMC0_CORETI_MASK);
+
+                tmp |= ((exynos4210_clkdiv_dmc0[i][0] <<
+                                        S5P_CLKDIV_DMC0_ACP_SHIFT) |
+                        (exynos4210_clkdiv_dmc0[i][1] <<
+                                        S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
+                        (exynos4210_clkdiv_dmc0[i][2] <<
+                                        S5P_CLKDIV_DMC0_DPHY_SHIFT) |
+                        (exynos4210_clkdiv_dmc0[i][3] <<
+                                        S5P_CLKDIV_DMC0_DMC_SHIFT) |
+                        (exynos4210_clkdiv_dmc0[i][4] <<
+                                        S5P_CLKDIV_DMC0_DMCD_SHIFT) |
+                        (exynos4210_clkdiv_dmc0[i][5] <<
+                                        S5P_CLKDIV_DMC0_DMCP_SHIFT) |
+                        (exynos4210_clkdiv_dmc0[i][6] <<
+                                        S5P_CLKDIV_DMC0_COPY2_SHIFT) |
+                        (exynos4210_clkdiv_dmc0[i][7] <<
+                                        S5P_CLKDIV_DMC0_CORETI_SHIFT));
+
+                data->dmc_divtable[i] = tmp;
+        }
+
+        tmp = __raw_readl(S5P_CLKDIV_TOP);
+        for (i = LV_0; i <  EX4210_LV_NUM; i++) {
+                tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK |
+                        S5P_CLKDIV_TOP_ACLK100_MASK |
+                        S5P_CLKDIV_TOP_ACLK160_MASK |
+                        S5P_CLKDIV_TOP_ACLK133_MASK |
+                        S5P_CLKDIV_TOP_ONENAND_MASK);
+
+                tmp |= ((exynos4210_clkdiv_top[i][0] <<
+                                        S5P_CLKDIV_TOP_ACLK200_SHIFT) |
+                        (exynos4210_clkdiv_top[i][1] <<
+                                        S5P_CLKDIV_TOP_ACLK100_SHIFT) |
+                        (exynos4210_clkdiv_top[i][2] <<
+                                        S5P_CLKDIV_TOP_ACLK160_SHIFT) |
+                        (exynos4210_clkdiv_top[i][3] <<
+                                        S5P_CLKDIV_TOP_ACLK133_SHIFT) |
+                        (exynos4210_clkdiv_top[i][4] <<
+                                        S5P_CLKDIV_TOP_ONENAND_SHIFT));
+
+                data->top_divtable[i] = tmp;
+        }
+
+#ifdef CONFIG_EXYNOS_ASV
+        tmp = exynos4_result_of_asv;
+#else
+        tmp = 0; /* Max voltages for the reliability of the unknown */
+#endif
+
+        pr_debug("ASV Group of Exynos4 is %d\n", tmp);
+        /* Use merged grouping for voltage */
+        switch (tmp) {
+        case 0:
+                mgrp = 0;
+                break;
+        case 1:
+        case 2:
+                mgrp = 1;
+                break;
+        case 3:
+        case 4:
+                mgrp = 2;
+                break;
+        case 5:
+        case 6:
+                mgrp = 3;
+                break;
+        case 7:
+                mgrp = 4;
+                break;
+        default:
+                pr_warn("Unknown ASV Group. Use max voltage.\n");
+                mgrp = 0;
+        }
+
+        for (i = LV_0; i < EX4210_LV_NUM; i++)
+                exynos4210_busclk_table[i].volt = exynos4210_asv_volt[mgrp][i];
+
+        for (i = LV_0; i < EX4210_LV_NUM; i++) {
+                err = opp_add(data->dev, exynos4210_busclk_table[i].clk,
+                              exynos4210_busclk_table[i].volt);
+                if (err) {
+                        dev_err(data->dev, "Cannot add opp entries.\n");
+                        return err;
+                }
+        }
+
+
+        return 0;
+}
+
+static int exynos4x12_init_tables(struct busfreq_data *data)
+{
+        unsigned int i;
+        unsigned int tmp;
+        int ret;
+
+        /* Enable pause function for DREX2 DVFS */
+        tmp = __raw_readl(S5P_DMC_PAUSE_CTRL);
+        tmp |= DMC_PAUSE_ENABLE;
+        __raw_writel(tmp, S5P_DMC_PAUSE_CTRL);
+
+        tmp = __raw_readl(S5P_CLKDIV_DMC0);
+
+        for (i = 0; i <  EX4x12_LV_NUM; i++) {
+                tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK |
+                        S5P_CLKDIV_DMC0_ACPPCLK_MASK |
+                        S5P_CLKDIV_DMC0_DPHY_MASK |
+                        S5P_CLKDIV_DMC0_DMC_MASK |
+                        S5P_CLKDIV_DMC0_DMCD_MASK |
+                        S5P_CLKDIV_DMC0_DMCP_MASK);
+
+                tmp |= ((exynos4x12_clkdiv_dmc0[i][0] <<
+                                        S5P_CLKDIV_DMC0_ACP_SHIFT) |
+                        (exynos4x12_clkdiv_dmc0[i][1] <<
+                                        S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
+                        (exynos4x12_clkdiv_dmc0[i][2] <<
+                                        S5P_CLKDIV_DMC0_DPHY_SHIFT) |
+                        (exynos4x12_clkdiv_dmc0[i][3] <<
+                                        S5P_CLKDIV_DMC0_DMC_SHIFT) |
+                        (exynos4x12_clkdiv_dmc0[i][4] <<
+                                        S5P_CLKDIV_DMC0_DMCD_SHIFT) |
+                        (exynos4x12_clkdiv_dmc0[i][5] <<
+                                        S5P_CLKDIV_DMC0_DMCP_SHIFT));
+
+                data->dmc_divtable[i] = tmp;
+        }
+
+#ifdef CONFIG_EXYNOS_ASV
+        tmp = exynos4_result_of_asv;
+#else
+        tmp = 0; /* Max voltages for the reliability of the unknown */
+#endif
+
+        if (tmp > 8)
+                tmp = 0;
+        pr_debug("ASV Group of Exynos4x12 is %d\n", tmp);
+
+        for (i = 0; i < EX4x12_LV_NUM; i++) {
+                exynos4x12_mifclk_table[i].volt =
+                        exynos4x12_mif_step_50[tmp][i];
+                exynos4x12_intclk_table[i].volt =
+                        exynos4x12_int_volt[tmp][i];
+        }
+
+        for (i = 0; i < EX4x12_LV_NUM; i++) {
+                ret = opp_add(data->dev, exynos4x12_mifclk_table[i].clk,
+                              exynos4x12_mifclk_table[i].volt);
+                if (ret) {
+                        dev_err(data->dev, "Fail to add opp entries.\n");
+                        return ret;
+                }
+        }
+
+        return 0;
+}
+
+static int exynos4_busfreq_pm_notifier_event(struct notifier_block *this,
+                unsigned long event, void *ptr)
+{
+        struct busfreq_data *data = container_of(this, struct busfreq_data,
+                                                 pm_notifier);
+        struct opp *opp;
+        unsigned long maxfreq = ULONG_MAX;
+        int err = 0;
+
+        switch (event) {
+        case PM_SUSPEND_PREPARE:
+                /* Set Fastest and Deactivate DVFS */
+                mutex_lock(&data->lock);
+
+                data->disabled = true;
+
+                opp = opp_find_freq_floor(data->dev, &maxfreq);
+
+                err = exynos4_bus_setvolt(data, opp, data->curr_opp);
+                if (err)
+                        goto unlock;
+
+                switch (data->type) {
+                case TYPE_BUSF_EXYNOS4210:
+                        err = exynos4210_set_busclk(data, opp);
+                        break;
+                case TYPE_BUSF_EXYNOS4x12:
+                        err = exynos4x12_set_busclk(data, opp);
+                        break;
+                default:
+                        err = -EINVAL;
+                }
+                if (err)
+                        goto unlock;
+
+                data->curr_opp = opp;
+unlock:
+                mutex_unlock(&data->lock);
+                if (err)
+                        return err;
+                return NOTIFY_OK;
+        case PM_POST_RESTORE:
+        case PM_POST_SUSPEND:
+                /* Reactivate */
+                mutex_lock(&data->lock);
+                data->disabled = false;
+                mutex_unlock(&data->lock);
+                return NOTIFY_OK;
+        }
+
+        return NOTIFY_DONE;
+}
+
+static __devinit int exynos4_busfreq_probe(struct platform_device *pdev)
+{
+        struct busfreq_data *data;
+        struct opp *opp;
+        struct device *dev = &pdev->dev;
+        int err = 0;
+
+        data = kzalloc(sizeof(struct busfreq_data), GFP_KERNEL);
+        if (data == NULL) {
+                dev_err(dev, "Cannot allocate memory.\n");
+                return -ENOMEM;
+        }
+
+        data->type = pdev->id_entry->driver_data;
+        data->dmc[0].hw_base = S5P_VA_DMC0;
+        data->dmc[1].hw_base = S5P_VA_DMC1;
+        data->pm_notifier.notifier_call = exynos4_busfreq_pm_notifier_event;
+        data->dev = dev;
+        mutex_init(&data->lock);
+
+        switch (data->type) {
+        case TYPE_BUSF_EXYNOS4210:
+                err = exynos4210_init_tables(data);
+                break;
+        case TYPE_BUSF_EXYNOS4x12:
+                err = exynos4x12_init_tables(data);
+                break;
+        default:
+                dev_err(dev, "Cannot determine the device id %d\n", data->type);
+                err = -EINVAL;
+        }
+        if (err)
+                goto err_regulator;
+
+        data->vdd_int = regulator_get(dev, "vdd_int");
+        if (IS_ERR(data->vdd_int)) {
+                dev_err(dev, "Cannot get the regulator \"vdd_int\"\n");
+                err = PTR_ERR(data->vdd_int);
+                goto err_regulator;
+        }
+        if (data->type == TYPE_BUSF_EXYNOS4x12) {
+                data->vdd_mif = regulator_get(dev, "vdd_mif");
+                if (IS_ERR(data->vdd_mif)) {
+                        dev_err(dev, "Cannot get the regulator \"vdd_mif\"\n");
+                        err = PTR_ERR(data->vdd_mif);
+                        regulator_put(data->vdd_int);
+                        goto err_regulator;
+
+                }
+        }
+
+        opp = opp_find_freq_floor(dev, &exynos4_devfreq_profile.initial_freq);
+        if (IS_ERR(opp)) {
+                dev_err(dev, "Invalid initial frequency %lu kHz.\n",
+                       exynos4_devfreq_profile.initial_freq);
+                err = PTR_ERR(opp);
+                goto err_opp_add;
+        }
+        data->curr_opp = opp;
+
+        platform_set_drvdata(pdev, data);
+
+        busfreq_mon_reset(data);
+
+        data->devfreq = devfreq_add_device(dev, &exynos4_devfreq_profile,
+                                           &devfreq_simple_ondemand, NULL);
+        if (IS_ERR(data->devfreq)) {
+                err = PTR_ERR(data->devfreq);
+                goto err_opp_add;
+        }
+
+        devfreq_register_opp_notifier(dev, data->devfreq);
+
+        err = register_pm_notifier(&data->pm_notifier);
+        if (err) {
+                dev_err(dev, "Failed to setup pm notifier\n");
+                goto err_devfreq_add;
+        }
+
+        return 0;
+err_devfreq_add:
+        devfreq_remove_device(data->devfreq);
+err_opp_add:
+        if (data->vdd_mif)
+                regulator_put(data->vdd_mif);
+        regulator_put(data->vdd_int);
+err_regulator:
+        kfree(data);
+        return err;
+}
+
+static __devexit int exynos4_busfreq_remove(struct platform_device *pdev)
+{
+        struct busfreq_data *data = platform_get_drvdata(pdev);
+
+        unregister_pm_notifier(&data->pm_notifier);
+        devfreq_remove_device(data->devfreq);
+        regulator_put(data->vdd_int);
+        if (data->vdd_mif)
+                regulator_put(data->vdd_mif);
+        kfree(data);
+
+        return 0;
+}
+
+static int exynos4_busfreq_resume(struct device *dev)
+{
+        struct platform_device *pdev = container_of(dev, struct platform_device,
+                                                    dev);
+        struct busfreq_data *data = platform_get_drvdata(pdev);
+
+        busfreq_mon_reset(data);
+        return 0;
+}
+
+static const struct dev_pm_ops exynos4_busfreq_pm = {
+        .resume = exynos4_busfreq_resume,
+};
+
+static const struct platform_device_id exynos4_busfreq_id[] = {
+        { "exynos4210-busfreq", TYPE_BUSF_EXYNOS4210 },
+        { "exynos4412-busfreq", TYPE_BUSF_EXYNOS4x12 },
+        { "exynos4212-busfreq", TYPE_BUSF_EXYNOS4x12 },
+        { },
+};
+
+static struct platform_driver exynos4_busfreq_driver = {
+        .probe  = exynos4_busfreq_probe,
+        .remove = __devexit_p(exynos4_busfreq_remove),
+        .id_table = exynos4_busfreq_id,
+        .driver = {
+                .name   = "exynos4-busfreq",
+                .owner  = THIS_MODULE,
+                .pm     = &exynos4_busfreq_pm,
+        },
+};
+
+static int __init exynos4_busfreq_init(void)
+{
+        return platform_driver_register(&exynos4_busfreq_driver);
+}
+late_initcall(exynos4_busfreq_init);
+
+static void __exit exynos4_busfreq_exit(void)
+{
+        platform_driver_unregister(&exynos4_busfreq_driver);
+}
+module_exit(exynos4_busfreq_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("EXYNOS4 busfreq driver with devfreq framework");
+MODULE_AUTHOR("MyungJoo Ham <myungjoo.ham@samsung.com>");
+MODULE_ALIAS("exynos4-busfreq");
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 5e00d1670aa9..92c9628c572d 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -3276,6 +3276,18 @@ int evergreen_init(struct radeon_device *rdev)
                         rdev->accel_working = false;
                 }
         }
+
+        /* Don't start up if the MC ucode is missing on BTC parts.
+         * The default clocks and voltages before the MC ucode
+         * is loaded are not suffient for advanced operations.
+         */
+        if (ASIC_IS_DCE5(rdev)) {
+                if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
+                        DRM_ERROR("radeon: MC ucode required for NI+.\n");
+                        return -EINVAL;
+                }
+        }
+
         return 0;
 }
 
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index 8aa1dbb45c67..f94b33ae2215 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -1093,7 +1093,6 @@ static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
         struct vmw_surface *surface = NULL;
         struct vmw_dma_buffer *bo = NULL;
         struct ttm_base_object *user_obj;
-        u64 required_size;
         int ret;
 
         /**
@@ -1102,8 +1101,9 @@ static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
          * requested framebuffer.
          */
 
-        required_size = mode_cmd->pitch * mode_cmd->height;
-        if (unlikely(required_size > (u64) dev_priv->vram_size)) {
+        if (!vmw_kms_validate_mode_vram(dev_priv,
+                                        mode_cmd->pitch,
+                                        mode_cmd->height)) {
                 DRM_ERROR("VRAM size is too small for requested mode.\n");
                 return ERR_PTR(-ENOMEM);
         }
diff --git a/drivers/md/bitmap.c b/drivers/md/bitmap.c
index b6907118283a..6d03774b176e 100644
--- a/drivers/md/bitmap.c
+++ b/drivers/md/bitmap.c
@@ -1393,9 +1393,6 @@ void bitmap_endwrite(struct bitmap *bitmap, sector_t offset, unsigned long secto
                          atomic_read(&bitmap->behind_writes),
                          bitmap->mddev->bitmap_info.max_write_behind);
         }
-        if (bitmap->mddev->degraded)
-                /* Never clear bits or update events_cleared when degraded */
-                success = 0;
 
         while (sectors) {
                 sector_t blocks;
@@ -1409,7 +1406,7 @@ void bitmap_endwrite(struct bitmap *bitmap, sector_t offset, unsigned long secto
                         return;
                 }
 
-                if (success &&
+                if (success && !bitmap->mddev->degraded &&
                     bitmap->events_cleared < bitmap->mddev->events) {
                         bitmap->events_cleared = bitmap->mddev->events;
                         bitmap->need_sync = 1;
diff --git a/drivers/md/linear.c b/drivers/md/linear.c
index c3273efd08cb..627456542fb3 100644
--- a/drivers/md/linear.c
+++ b/drivers/md/linear.c
@@ -230,6 +230,7 @@ static int linear_add(struct mddev *mddev, struct md_rdev *rdev)
                 return -EINVAL;
 
         rdev->raid_disk = rdev->saved_raid_disk;
+        rdev->saved_raid_disk = -1;
 
         newconf = linear_conf(mddev,mddev->raid_disks+1);
 
diff --git a/drivers/md/md.c b/drivers/md/md.c
index ee981737edfc..f47f1f8ac44b 100644
--- a/drivers/md/md.c
+++ b/drivers/md/md.c
@@ -7360,8 +7360,7 @@ static int remove_and_add_spares(struct mddev *mddev)
                                         spares++;
                                         md_new_event(mddev);
                                         set_bit(MD_CHANGE_DEVS, &mddev->flags);
-                                } else
-                                        break;
+                                }
                         }
                 }
         }
diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
index 31670f8d6b65..858fdbb7eb07 100644
--- a/drivers/md/raid5.c
+++ b/drivers/md/raid5.c
@@ -3065,11 +3065,17 @@ static void analyse_stripe(struct stripe_head *sh, struct stripe_head_state *s)
                         }
                 } else if (test_bit(In_sync, &rdev->flags))
                         set_bit(R5_Insync, &dev->flags);
-                else {
+                else if (sh->sector + STRIPE_SECTORS <= rdev->recovery_offset)
                         /* in sync if before recovery_offset */
-                        if (sh->sector + STRIPE_SECTORS <= rdev->recovery_offset)
-                                set_bit(R5_Insync, &dev->flags);
-                }
+                        set_bit(R5_Insync, &dev->flags);
+                else if (test_bit(R5_UPTODATE, &dev->flags) &&
+                         test_bit(R5_Expanded, &dev->flags))
+                        /* If we've reshaped into here, we assume it is Insync.
+                         * We will shortly update recovery_offset to make
+                         * it official.
+                         */
+                        set_bit(R5_Insync, &dev->flags);
+
                 if (rdev && test_bit(R5_WriteError, &dev->flags)) {
                         clear_bit(R5_Insync, &dev->flags);
                         if (!test_bit(Faulty, &rdev->flags)) {
diff --git a/drivers/media/video/omap3isp/ispccdc.c b/drivers/media/video/omap3isp/ispccdc.c
index b0b0fa5a3572..54a4a3f22e2e 100644
--- a/drivers/media/video/omap3isp/ispccdc.c
+++ b/drivers/media/video/omap3isp/ispccdc.c
@@ -1408,7 +1408,7 @@ static void ccdc_hs_vs_isr(struct isp_ccdc_device *ccdc)
 {
         struct isp_pipeline *pipe =
                 to_isp_pipeline(&ccdc->video_out.video.entity);
-        struct video_device *vdev = &ccdc->subdev.devnode;
+        struct video_device *vdev = ccdc->subdev.devnode;
         struct v4l2_event event;
 
         memset(&event, 0, sizeof(event));
diff --git a/drivers/media/video/omap3isp/ispstat.c b/drivers/media/video/omap3isp/ispstat.c
index 68d539456c55..bc0b2c7349b9 100644
--- a/drivers/media/video/omap3isp/ispstat.c
+++ b/drivers/media/video/omap3isp/ispstat.c
@@ -496,7 +496,7 @@ static int isp_stat_bufs_alloc(struct ispstat *stat, u32 size)
 
 static void isp_stat_queue_event(struct ispstat *stat, int err)
 {
-        struct video_device *vdev = &stat->subdev.devnode;
+        struct video_device *vdev = stat->subdev.devnode;
         struct v4l2_event event;
         struct omap3isp_stat_event_status *status = (void *)event.u.data;
 
diff --git a/drivers/mfd/ab5500-debugfs.c b/drivers/mfd/ab5500-debugfs.c
index 43c0ebb81956..b7b2d3483fd4 100644
--- a/drivers/mfd/ab5500-debugfs.c
+++ b/drivers/mfd/ab5500-debugfs.c
@@ -4,7 +4,7 @@
  * Debugfs support for the AB5500 MFD driver
  */
 
-#include <linux/export.h>
+#include <linux/module.h>
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
 #include <linux/mfd/ab5500/ab5500.h>
diff --git a/drivers/mfd/ab8500-core.c b/drivers/mfd/ab8500-core.c
index 1e9173804ede..d3d572b2317b 100644
--- a/drivers/mfd/ab8500-core.c
+++ b/drivers/mfd/ab8500-core.c
@@ -620,6 +620,7 @@ static struct resource __devinitdata ab8500_fg_resources[] = {
 
 static struct resource __devinitdata ab8500_chargalg_resources[] = {};
 
+#ifdef CONFIG_DEBUG_FS
 static struct resource __devinitdata ab8500_debug_resources[] = {
         {
                 .name   = "IRQ_FIRST",
@@ -634,6 +635,7 @@ static struct resource __devinitdata ab8500_debug_resources[] = {
                 .flags  = IORESOURCE_IRQ,
         },
 };
+#endif
 
 static struct resource __devinitdata ab8500_usb_resources[] = {
         {
diff --git a/drivers/mfd/adp5520.c b/drivers/mfd/adp5520.c
index f1d88483112c..8d816cce8322 100644
--- a/drivers/mfd/adp5520.c
+++ b/drivers/mfd/adp5520.c
@@ -109,7 +109,7 @@ int adp5520_set_bits(struct device *dev, int reg, uint8_t bit_mask)
 
         ret = __adp5520_read(chip->client, reg, &reg_val);
 
-        if (!ret && ((reg_val & bit_mask) == 0)) {
+        if (!ret && ((reg_val & bit_mask) != bit_mask)) {
                 reg_val |= bit_mask;
                 ret = __adp5520_write(chip->client, reg, reg_val);
         }
diff --git a/drivers/mfd/da903x.c b/drivers/mfd/da903x.c
index 1b79c37fd599..1924b857a0fb 100644
--- a/drivers/mfd/da903x.c
+++ b/drivers/mfd/da903x.c
@@ -182,7 +182,7 @@ int da903x_set_bits(struct device *dev, int reg, uint8_t bit_mask)
         if (ret)
                 goto out;
 
-        if ((reg_val & bit_mask) == 0) {
+        if ((reg_val & bit_mask) != bit_mask) {
                 reg_val |= bit_mask;
                 ret = __da903x_write(chip->client, reg, reg_val);
         }
@@ -549,6 +549,7 @@ static int __devexit da903x_remove(struct i2c_client *client)
         struct da903x_chip *chip = i2c_get_clientdata(client);
 
         da903x_remove_subdevs(chip);
+        free_irq(client->irq, chip);
         kfree(chip);
         return 0;
 }
diff --git a/drivers/mfd/jz4740-adc.c b/drivers/mfd/jz4740-adc.c
index 1e9ee533eacb..ef39528088f2 100644
--- a/drivers/mfd/jz4740-adc.c
+++ b/drivers/mfd/jz4740-adc.c
@@ -16,6 +16,7 @@
  */
 
 #include <linux/err.h>
+#include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
diff --git a/drivers/mfd/tps6586x.c b/drivers/mfd/tps6586x.c
index bba26d96c240..a5ddf31b60ca 100644
--- a/drivers/mfd/tps6586x.c
+++ b/drivers/mfd/tps6586x.c
@@ -197,7 +197,7 @@ int tps6586x_set_bits(struct device *dev, int reg, uint8_t bit_mask)
         if (ret)
                 goto out;
 
-        if ((reg_val & bit_mask) == 0) {
+        if ((reg_val & bit_mask) != bit_mask) {
                 reg_val |= bit_mask;
                 ret = __tps6586x_write(to_i2c_client(dev), reg, reg_val);
         }
diff --git a/drivers/mfd/tps65910.c b/drivers/mfd/tps65910.c
index 6f5b8cf2f652..c1da84bc1573 100644
--- a/drivers/mfd/tps65910.c
+++ b/drivers/mfd/tps65910.c
@@ -120,7 +120,7 @@ int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask)
                 goto out;
         }
 
-        data &= mask;
+        data &= ~mask;
         err = tps65910_i2c_write(tps65910, reg, 1, &data);
         if (err)
                 dev_err(tps65910->dev, "write to reg %x failed\n", reg);
diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index bfbd66021afd..61e70cfaa774 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -363,13 +363,13 @@ int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes)
                 pr_err("%s: invalid module number %d\n", DRIVER_NAME, mod_no);
                 return -EPERM;
         }
-        sid = twl_map[mod_no].sid;
-        twl = &twl_modules[sid];
-
         if (unlikely(!inuse)) {
-                pr_err("%s: client %d is not initialized\n", DRIVER_NAME, sid);
+                pr_err("%s: not initialized\n", DRIVER_NAME);
                 return -EPERM;
         }
+        sid = twl_map[mod_no].sid;
+        twl = &twl_modules[sid];
+
         mutex_lock(&twl->xfer_lock);
         /*
          * [MSG1]: fill the register address data
@@ -420,13 +420,13 @@ int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes)
                 pr_err("%s: invalid module number %d\n", DRIVER_NAME, mod_no);
                 return -EPERM;
         }
-        sid = twl_map[mod_no].sid;
-        twl = &twl_modules[sid];
-
         if (unlikely(!inuse)) {
-                pr_err("%s: client %d is not initialized\n", DRIVER_NAME, sid);
+                pr_err("%s: not initialized\n", DRIVER_NAME);
                 return -EPERM;
         }
+        sid = twl_map[mod_no].sid;
+        twl = &twl_modules[sid];
+
         mutex_lock(&twl->xfer_lock);
         /* [MSG1] fill the register address data */
         msg = &twl->xfer_msg[0];
diff --git a/drivers/mfd/twl4030-irq.c b/drivers/mfd/twl4030-irq.c
index f062c8cc6c38..29f11e0765fe 100644
--- a/drivers/mfd/twl4030-irq.c
+++ b/drivers/mfd/twl4030-irq.c
@@ -432,6 +432,7 @@ struct sih_agent {
         u32                     edge_change;
 
         struct mutex            irq_lock;
+        char                    *irq_name;
 };
 
 /*----------------------------------------------------------------------*/
@@ -589,7 +590,7 @@ static inline int sih_read_isr(const struct sih *sih)
  * Generic handler for SIH interrupts ... we "know" this is called
  * in task context, with IRQs enabled.
  */
-static void handle_twl4030_sih(unsigned irq, struct irq_desc *desc)
+static irqreturn_t handle_twl4030_sih(int irq, void *data)
 {
         struct sih_agent *agent = irq_get_handler_data(irq);
         const struct sih *sih = agent->sih;
@@ -602,7 +603,7 @@ static void handle_twl4030_sih(unsigned irq, struct irq_desc *desc)
                 pr_err("twl4030: %s SIH, read ISR error %d\n",
                         sih->name, isr);
                 /* REVISIT:  recover; eventually mask it all, etc */
-                return;
+                return IRQ_HANDLED;
         }
 
         while (isr) {
@@ -616,6 +617,7 @@ static void handle_twl4030_sih(unsigned irq, struct irq_desc *desc)
                         pr_err("twl4030: %s SIH, invalid ISR bit %d\n",
                                 sih->name, irq);
         }
+        return IRQ_HANDLED;
 }
 
 static unsigned twl4030_irq_next;
@@ -668,18 +670,19 @@ int twl4030_sih_setup(int module)
                 activate_irq(irq);
         }
 
-        status = irq_base;
         twl4030_irq_next += i;
 
         /* replace generic PIH handler (handle_simple_irq) */
         irq = sih_mod + twl4030_irq_base;
         irq_set_handler_data(irq, agent);
-        irq_set_chained_handler(irq, handle_twl4030_sih);
+        agent->irq_name = kasprintf(GFP_KERNEL, "twl4030_%s", sih->name);
+        status = request_threaded_irq(irq, NULL, handle_twl4030_sih, 0,
+                                      agent->irq_name ?: sih->name, NULL);
 
         pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name,
                         irq, irq_base, twl4030_irq_next - 1);
 
-        return status;
+        return status < 0 ? status : irq_base;
 }
 
 /* FIXME need a call to reverse twl4030_sih_setup() ... */
@@ -733,8 +736,9 @@ int twl4030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end)
         }
 
         /* install an irq handler to demultiplex the TWL4030 interrupt */
-        status = request_threaded_irq(irq_num, NULL, handle_twl4030_pih, 0,
-                                        "TWL4030-PIH", NULL);
+        status = request_threaded_irq(irq_num, NULL, handle_twl4030_pih,
+                                      IRQF_ONESHOT,
+                                      "TWL4030-PIH", NULL);
         if (status < 0) {
                 pr_err("twl4030: could not claim irq%d: %d\n", irq_num, status);
                 goto fail_rqirq;
diff --git a/drivers/mfd/wm8994-core.c b/drivers/mfd/wm8994-core.c
index 5d6ba132837e..61894fced8ea 100644
--- a/drivers/mfd/wm8994-core.c
+++ b/drivers/mfd/wm8994-core.c
@@ -239,6 +239,7 @@ static int wm8994_suspend(struct device *dev)
 
         switch (wm8994->type) {
         case WM8958:
+        case WM1811:
                 ret = wm8994_reg_read(wm8994, WM8958_MIC_DETECT_1);
                 if (ret < 0) {
                         dev_err(dev, "Failed to read power status: %d\n", ret);
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index 67bf07819992..c8f47f17186f 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -477,7 +477,6 @@ enum rtl_register_content {
         /* Config1 register p.24 */
         LEDS1           = (1 << 7),
         LEDS0           = (1 << 6),
-        MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
         Speed_down      = (1 << 4),
         MEMMAP          = (1 << 3),
         IOMAP           = (1 << 2),
@@ -485,6 +484,7 @@ enum rtl_register_content {
         PMEnable        = (1 << 0),     /* Power Management Enable */
 
         /* Config2 register p. 25 */
+        MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
         PCI_Clock_66MHz = 0x01,
         PCI_Clock_33MHz = 0x00,
 
@@ -3426,22 +3426,24 @@ static const struct rtl_cfg_info {
 };
 
 /* Cfg9346_Unlock assumed. */
-static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
+static unsigned rtl_try_msi(struct rtl8169_private *tp,
                             const struct rtl_cfg_info *cfg)
 {
+        void __iomem *ioaddr = tp->mmio_addr;
         unsigned msi = 0;
         u8 cfg2;
 
         cfg2 = RTL_R8(Config2) & ~MSIEnable;
         if (cfg->features & RTL_FEATURE_MSI) {
-                if (pci_enable_msi(pdev)) {
-                        dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
+                if (pci_enable_msi(tp->pci_dev)) {
+                        netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
                 } else {
                         cfg2 |= MSIEnable;
                         msi = RTL_FEATURE_MSI;
                 }
         }
-        RTL_W8(Config2, cfg2);
+        if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
+                RTL_W8(Config2, cfg2);
         return msi;
 }
 
@@ -4077,7 +4079,7 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
                 tp->features |= RTL_FEATURE_WOL;
         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
                 tp->features |= RTL_FEATURE_WOL;
-        tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
+        tp->features |= rtl_try_msi(tp, cfg);
         RTL_W8(Cfg9346, Cfg9346_Lock);
 
         if (rtl_tbi_enabled(tp)) {
diff --git a/drivers/net/ethernet/ti/davinci_cpdma.c b/drivers/net/ethernet/ti/davinci_cpdma.c
index dca9d3369cdd..c97d2f590855 100644
--- a/drivers/net/ethernet/ti/davinci_cpdma.c
+++ b/drivers/net/ethernet/ti/davinci_cpdma.c
@@ -836,11 +836,13 @@ int cpdma_chan_stop(struct cpdma_chan *chan)
         chan_write(chan, cp, CPDMA_TEARDOWN_VALUE);
 
         /* handle completed packets */
+        spin_unlock_irqrestore(&chan->lock, flags);
         do {
                 ret = __cpdma_chan_process(chan);
                 if (ret < 0)
                         break;
         } while ((ret & CPDMA_DESC_TD_COMPLETE) == 0);
+        spin_lock_irqsave(&chan->lock, flags);
 
         /* remaining packets haven't been tx/rx'ed, clean them up */
         while (chan->head) {
diff --git a/drivers/net/usb/asix.c b/drivers/net/usb/asix.c
index e6fed4d4cb77..e95f0e60a9bc 100644
--- a/drivers/net/usb/asix.c
+++ b/drivers/net/usb/asix.c
@@ -1655,6 +1655,10 @@ static const struct usb_device_id	products [] = {
         // ASIX 88772a
         USB_DEVICE(0x0db0, 0xa877),
         .driver_info = (unsigned long) &ax88772_info,
+}, {
+        // Asus USB Ethernet Adapter
+        USB_DEVICE (0x0b95, 0x7e2b),
+        .driver_info = (unsigned long) &ax88772_info,
 },
         { },            // END
 };
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c
index 888abc2be3a5..528d5f3e868c 100644
--- a/drivers/net/wireless/ath/ath9k/rc.c
+++ b/drivers/net/wireless/ath/ath9k/rc.c
@@ -1271,7 +1271,9 @@ static void ath_rc_init(struct ath_softc *sc,
 
         ath_rc_priv->max_valid_rate = k;
         ath_rc_sort_validrates(rate_table, ath_rc_priv);
-        ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4];
+        ath_rc_priv->rate_max_phy = (k > 4) ?
+                                        ath_rc_priv->valid_rate_index[k-4] :
+                                        ath_rc_priv->valid_rate_index[k-1];
         ath_rc_priv->rate_table = rate_table;
 
         ath_dbg(common, ATH_DBG_CONFIG,
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-rxon.c b/drivers/net/wireless/iwlwifi/iwl-agn-rxon.c
index a7a6def40d05..5c7c17c7166a 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-rxon.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-rxon.c
@@ -606,8 +606,8 @@ int iwlagn_mac_config(struct ieee80211_hw *hw, u32 changed)
                         if (ctx->ht.enabled) {
                                 /* if HT40 is used, it should not change
                                  * after associated except channel switch */
-                                if (iwl_is_associated_ctx(ctx) &&
-                                     !ctx->ht.is_40mhz)
+                                if (!ctx->ht.is_40mhz ||
+                                                !iwl_is_associated_ctx(ctx))
                                         iwlagn_config_ht40(conf, ctx);
                         } else
                                 ctx->ht.is_40mhz = false;
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-tx.c b/drivers/net/wireless/iwlwifi/iwl-agn-tx.c
index 35a6b71f358c..df1540ca6102 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-tx.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-tx.c
@@ -91,7 +91,10 @@ static void iwlagn_tx_cmd_build_basic(struct iwl_priv *priv,
                 tx_cmd->tid_tspec = qc[0] & 0xf;
                 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
         } else {
-                tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
+                if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
+                        tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
+                else
+                        tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
         }
 
         iwlagn_tx_cmd_protection(priv, info, fc, &tx_flags);
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c
index bacc06c95e7a..e0e9a3dfbc00 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn.c
@@ -2850,6 +2850,9 @@ static int iwlagn_mac_tx_sync(struct ieee80211_hw *hw,
         int ret;
         u8 sta_id;
 
+        if (ctx->ctxid != IWL_RXON_CTX_PAN)
+                return 0;
+
         IWL_DEBUG_MAC80211(priv, "enter\n");
         mutex_lock(&priv->shrd->mutex);
 
@@ -2898,6 +2901,9 @@ static void iwlagn_mac_finish_tx_sync(struct ieee80211_hw *hw,
         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
         struct iwl_rxon_context *ctx = vif_priv->ctx;
 
+        if (ctx->ctxid != IWL_RXON_CTX_PAN)
+                return;
+
         IWL_DEBUG_MAC80211(priv, "enter\n");
         mutex_lock(&priv->shrd->mutex);
 
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans-pcie.c b/drivers/net/wireless/iwlwifi/iwl-trans-pcie.c
index ce918980e977..5f17ab8e76ba 100644
--- a/drivers/net/wireless/iwlwifi/iwl-trans-pcie.c
+++ b/drivers/net/wireless/iwlwifi/iwl-trans-pcie.c
@@ -1197,9 +1197,7 @@ static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
 
         /* Set up entry for this TFD in Tx byte-count array */
-        if (is_agg)
-                iwl_trans_txq_update_byte_cnt_tbl(trans, txq,
-                                               le16_to_cpu(tx_cmd->len));
+        iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
 
         dma_sync_single_for_device(bus(trans)->dev, txcmd_phys, firstlen,
                         DMA_BIDIRECTIONAL);
diff --git a/drivers/net/wireless/mwifiex/cmdevt.c b/drivers/net/wireless/mwifiex/cmdevt.c
index ac278156d390..6e0a3eaecf70 100644
--- a/drivers/net/wireless/mwifiex/cmdevt.c
+++ b/drivers/net/wireless/mwifiex/cmdevt.c
@@ -939,7 +939,6 @@ mwifiex_cancel_pending_ioctl(struct mwifiex_adapter *adapter)
 {
         struct cmd_ctrl_node *cmd_node = NULL, *tmp_node = NULL;
         unsigned long cmd_flags;
-        unsigned long cmd_pending_q_flags;
         unsigned long scan_pending_q_flags;
         uint16_t cancel_scan_cmd = false;
 
@@ -949,12 +948,9 @@ mwifiex_cancel_pending_ioctl(struct mwifiex_adapter *adapter)
                 cmd_node = adapter->curr_cmd;
                 cmd_node->wait_q_enabled = false;
                 cmd_node->cmd_flag |= CMD_F_CANCELED;
-                spin_lock_irqsave(&adapter->cmd_pending_q_lock,
-                                  cmd_pending_q_flags);
-                list_del(&cmd_node->list);
-                spin_unlock_irqrestore(&adapter->cmd_pending_q_lock,
-                                       cmd_pending_q_flags);
                 mwifiex_insert_cmd_to_free_q(adapter, cmd_node);
+                mwifiex_complete_cmd(adapter, adapter->curr_cmd);
+                adapter->curr_cmd = NULL;
                 spin_unlock_irqrestore(&adapter->mwifiex_cmd_lock, cmd_flags);
         }
 
@@ -981,7 +977,6 @@ mwifiex_cancel_pending_ioctl(struct mwifiex_adapter *adapter)
                 spin_unlock_irqrestore(&adapter->mwifiex_cmd_lock, cmd_flags);
         }
         adapter->cmd_wait_q.status = -1;
-        mwifiex_complete_cmd(adapter, adapter->curr_cmd);
 }
 
 /*
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 717ebc9ff941..600d82348511 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -264,7 +264,7 @@ static int __devinit dwc3_core_init(struct dwc3 *dwc)
                 ret = -ENODEV;
                 goto err0;
         }
-        dwc->revision = reg & DWC3_GSNPSREV_MASK;
+        dwc->revision = reg;
 
         dwc3_core_soft_reset(dwc);
 
diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c
index 596a0b464e61..4dff83d2f265 100644
--- a/drivers/usb/gadget/epautoconf.c
+++ b/drivers/usb/gadget/epautoconf.c
@@ -130,9 +130,6 @@ ep_matches (
                         num_req_streams = ep_comp->bmAttributes & 0x1f;
                         if (num_req_streams > ep->max_streams)
                                 return 0;
-                        /* Update the ep_comp descriptor if needed */
-                        if (num_req_streams != ep->max_streams)
-                                ep_comp->bmAttributes = ep->max_streams;
                 }
 
         }
diff --git a/drivers/usb/host/isp1760-if.c b/drivers/usb/host/isp1760-if.c
index a7dc1e1d45f2..2ac4ac2e4ef9 100644
--- a/drivers/usb/host/isp1760-if.c
+++ b/drivers/usb/host/isp1760-if.c
@@ -18,7 +18,7 @@
 
 #include "isp1760-hcd.h"
 
-#ifdef CONFIG_OF
+#if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
 #include <linux/slab.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
@@ -31,7 +31,7 @@
 #include <linux/pci.h>
 #endif
 
-#ifdef CONFIG_OF
+#if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
 struct isp1760 {
         struct usb_hcd *hcd;
         int rst_gpio;
@@ -437,7 +437,7 @@ static int __init isp1760_init(void)
         ret = platform_driver_register(&isp1760_plat_driver);
         if (!ret)
                 any_ret = 0;
-#ifdef CONFIG_OF
+#if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
         ret = platform_driver_register(&isp1760_of_driver);
         if (!ret)
                 any_ret = 0;
@@ -457,7 +457,7 @@ module_init(isp1760_init);
 static void __exit isp1760_exit(void)
 {
         platform_driver_unregister(&isp1760_plat_driver);
-#ifdef CONFIG_OF
+#if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
         platform_driver_unregister(&isp1760_of_driver);
 #endif
 #ifdef CONFIG_PCI
diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
index 60ddba8066ea..79cb0af779fa 100644
--- a/drivers/usb/musb/musb_host.c
+++ b/drivers/usb/musb/musb_host.c
@@ -774,6 +774,10 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
                         if (musb->double_buffer_not_ok)
                                 musb_writew(epio, MUSB_TXMAXP,
                                                 hw_ep->max_packet_sz_tx);
+                        else if (can_bulk_split(musb, qh->type))
+                                musb_writew(epio, MUSB_TXMAXP, packet_sz
+                                        | ((hw_ep->max_packet_sz_tx /
+                                                packet_sz) - 1) << 11);
                         else
                                 musb_writew(epio, MUSB_TXMAXP,
                                                 qh->maxpacket |