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-rw-r--r--drivers/parisc/eisa.c104
1 files changed, 52 insertions, 52 deletions
diff --git a/drivers/parisc/eisa.c b/drivers/parisc/eisa.c
index 103095bbe8c0..59edee911f7d 100644
--- a/drivers/parisc/eisa.c
+++ b/drivers/parisc/eisa.c
@@ -14,16 +14,16 @@
14 * Wax ASIC also includes a PS/2 and RS-232 controller, but those are 14 * Wax ASIC also includes a PS/2 and RS-232 controller, but those are
15 * dealt with elsewhere; this file is concerned only with the EISA portions 15 * dealt with elsewhere; this file is concerned only with the EISA portions
16 * of Wax. 16 * of Wax.
17 * 17 *
18 * 18 *
19 * HINT: 19 * HINT:
20 * ----- 20 * -----
21 * To allow an ISA card to work properly in the EISA slot you need to 21 * To allow an ISA card to work properly in the EISA slot you need to
22 * set an edge trigger level. This may be done on the palo command line 22 * set an edge trigger level. This may be done on the palo command line
23 * by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with 23 * by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with
24 * n and n2 as the irq levels you want to use. 24 * n and n2 as the irq levels you want to use.
25 * 25 *
26 * Example: "eisa_irq_edge=10,11" allows ISA cards to operate at 26 * Example: "eisa_irq_edge=10,11" allows ISA cards to operate at
27 * irq levels 10 and 11. 27 * irq levels 10 and 11.
28 */ 28 */
29 29
@@ -46,9 +46,9 @@
46#include <asm/eisa_eeprom.h> 46#include <asm/eisa_eeprom.h>
47 47
48#if 0 48#if 0
49#define EISA_DBG(msg, arg... ) printk(KERN_DEBUG "eisa: " msg , ## arg ) 49#define EISA_DBG(msg, arg...) printk(KERN_DEBUG "eisa: " msg, ## arg)
50#else 50#else
51#define EISA_DBG(msg, arg... ) 51#define EISA_DBG(msg, arg...)
52#endif 52#endif
53 53
54#define SNAKES_EEPROM_BASE_ADDR 0xF0810400 54#define SNAKES_EEPROM_BASE_ADDR 0xF0810400
@@ -108,7 +108,7 @@ void eisa_out8(unsigned char data, unsigned short port)
108 108
109void eisa_out16(unsigned short data, unsigned short port) 109void eisa_out16(unsigned short data, unsigned short port)
110{ 110{
111 if (EISA_bus) 111 if (EISA_bus)
112 gsc_writew(cpu_to_le16(data), eisa_permute(port)); 112 gsc_writew(cpu_to_le16(data), eisa_permute(port));
113} 113}
114 114
@@ -135,9 +135,9 @@ static int master_mask;
135static int slave_mask; 135static int slave_mask;
136 136
137/* the trig level can be set with the 137/* the trig level can be set with the
138 * eisa_irq_edge=n,n,n commandline parameter 138 * eisa_irq_edge=n,n,n commandline parameter
139 * We should really read this from the EEPROM 139 * We should really read this from the EEPROM
140 * in the furure. 140 * in the furure.
141 */ 141 */
142/* irq 13,8,2,1,0 must be edge */ 142/* irq 13,8,2,1,0 must be edge */
143static unsigned int eisa_irq_level __read_mostly; /* default to edge triggered */ 143static unsigned int eisa_irq_level __read_mostly; /* default to edge triggered */
@@ -170,7 +170,7 @@ static void eisa_unmask_irq(struct irq_data *d)
170 unsigned int irq = d->irq; 170 unsigned int irq = d->irq;
171 unsigned long flags; 171 unsigned long flags;
172 EISA_DBG("enable irq %d\n", irq); 172 EISA_DBG("enable irq %d\n", irq);
173 173
174 spin_lock_irqsave(&eisa_irq_lock, flags); 174 spin_lock_irqsave(&eisa_irq_lock, flags);
175 if (irq & 8) { 175 if (irq & 8) {
176 slave_mask &= ~(1 << (irq&7)); 176 slave_mask &= ~(1 << (irq&7));
@@ -194,7 +194,7 @@ static irqreturn_t eisa_irq(int wax_irq, void *intr_dev)
194{ 194{
195 int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */ 195 int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */
196 unsigned long flags; 196 unsigned long flags;
197 197
198 spin_lock_irqsave(&eisa_irq_lock, flags); 198 spin_lock_irqsave(&eisa_irq_lock, flags);
199 /* read IRR command */ 199 /* read IRR command */
200 eisa_out8(0x0a, 0x20); 200 eisa_out8(0x0a, 0x20);
@@ -202,31 +202,31 @@ static irqreturn_t eisa_irq(int wax_irq, void *intr_dev)
202 202
203 EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n", 203 EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n",
204 irq, eisa_in8(0x20), eisa_in8(0xa0)); 204 irq, eisa_in8(0x20), eisa_in8(0xa0));
205 205
206 /* read ISR command */ 206 /* read ISR command */
207 eisa_out8(0x0a, 0x20); 207 eisa_out8(0x0a, 0x20);
208 eisa_out8(0x0a, 0xa0); 208 eisa_out8(0x0a, 0xa0);
209 EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n", 209 EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n",
210 eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1)); 210 eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1));
211 211
212 irq &= 0xf; 212 irq &= 0xf;
213 213
214 /* mask irq and write eoi */ 214 /* mask irq and write eoi */
215 if (irq & 8) { 215 if (irq & 8) {
216 slave_mask |= (1 << (irq&7)); 216 slave_mask |= (1 << (irq&7));
217 eisa_out8(slave_mask, 0xa1); 217 eisa_out8(slave_mask, 0xa1);
218 eisa_out8(0x60 | (irq&7),0xa0);/* 'Specific EOI' to slave */ 218 eisa_out8(0x60 | (irq&7),0xa0);/* 'Specific EOI' to slave */
219 eisa_out8(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */ 219 eisa_out8(0x62, 0x20); /* 'Specific EOI' to master-IRQ2 */
220 220
221 } else { 221 } else {
222 master_mask |= (1 << (irq&7)); 222 master_mask |= (1 << (irq&7));
223 eisa_out8(master_mask, 0x21); 223 eisa_out8(master_mask, 0x21);
224 eisa_out8(0x60|irq,0x20); /* 'Specific EOI' to master */ 224 eisa_out8(0x60|irq, 0x20); /* 'Specific EOI' to master */
225 } 225 }
226 spin_unlock_irqrestore(&eisa_irq_lock, flags); 226 spin_unlock_irqrestore(&eisa_irq_lock, flags);
227 227
228 generic_handle_irq(irq); 228 generic_handle_irq(irq);
229 229
230 spin_lock_irqsave(&eisa_irq_lock, flags); 230 spin_lock_irqsave(&eisa_irq_lock, flags);
231 /* unmask */ 231 /* unmask */
232 if (irq & 8) { 232 if (irq & 8) {
@@ -254,44 +254,44 @@ static struct irqaction irq2_action = {
254static void init_eisa_pic(void) 254static void init_eisa_pic(void)
255{ 255{
256 unsigned long flags; 256 unsigned long flags;
257 257
258 spin_lock_irqsave(&eisa_irq_lock, flags); 258 spin_lock_irqsave(&eisa_irq_lock, flags);
259 259
260 eisa_out8(0xff, 0x21); /* mask during init */ 260 eisa_out8(0xff, 0x21); /* mask during init */
261 eisa_out8(0xff, 0xa1); /* mask during init */ 261 eisa_out8(0xff, 0xa1); /* mask during init */
262 262
263 /* master pic */ 263 /* master pic */
264 eisa_out8(0x11,0x20); /* ICW1 */ 264 eisa_out8(0x11, 0x20); /* ICW1 */
265 eisa_out8(0x00,0x21); /* ICW2 */ 265 eisa_out8(0x00, 0x21); /* ICW2 */
266 eisa_out8(0x04,0x21); /* ICW3 */ 266 eisa_out8(0x04, 0x21); /* ICW3 */
267 eisa_out8(0x01,0x21); /* ICW4 */ 267 eisa_out8(0x01, 0x21); /* ICW4 */
268 eisa_out8(0x40,0x20); /* OCW2 */ 268 eisa_out8(0x40, 0x20); /* OCW2 */
269 269
270 /* slave pic */ 270 /* slave pic */
271 eisa_out8(0x11,0xa0); /* ICW1 */ 271 eisa_out8(0x11, 0xa0); /* ICW1 */
272 eisa_out8(0x08,0xa1); /* ICW2 */ 272 eisa_out8(0x08, 0xa1); /* ICW2 */
273 eisa_out8(0x02,0xa1); /* ICW3 */ 273 eisa_out8(0x02, 0xa1); /* ICW3 */
274 eisa_out8(0x01,0xa1); /* ICW4 */ 274 eisa_out8(0x01, 0xa1); /* ICW4 */
275 eisa_out8(0x40,0xa0); /* OCW2 */ 275 eisa_out8(0x40, 0xa0); /* OCW2 */
276 276
277 udelay(100); 277 udelay(100);
278 278
279 slave_mask = 0xff; 279 slave_mask = 0xff;
280 master_mask = 0xfb; 280 master_mask = 0xfb;
281 eisa_out8(slave_mask, 0xa1); /* OCW1 */ 281 eisa_out8(slave_mask, 0xa1); /* OCW1 */
282 eisa_out8(master_mask, 0x21); /* OCW1 */ 282 eisa_out8(master_mask, 0x21); /* OCW1 */
283 283
284 /* setup trig level */ 284 /* setup trig level */
285 EISA_DBG("EISA edge/level %04x\n", eisa_irq_level); 285 EISA_DBG("EISA edge/level %04x\n", eisa_irq_level);
286 286
287 eisa_out8(eisa_irq_level&0xff, 0x4d0); /* Set all irq's to edge */ 287 eisa_out8(eisa_irq_level&0xff, 0x4d0); /* Set all irq's to edge */
288 eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1); 288 eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1);
289 289
290 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21)); 290 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
291 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1)); 291 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
292 EISA_DBG("pic0 edge/level %02x\n", eisa_in8(0x4d0)); 292 EISA_DBG("pic0 edge/level %02x\n", eisa_in8(0x4d0));
293 EISA_DBG("pic1 edge/level %02x\n", eisa_in8(0x4d1)); 293 EISA_DBG("pic1 edge/level %02x\n", eisa_in8(0x4d1));
294 294
295 spin_unlock_irqrestore(&eisa_irq_lock, flags); 295 spin_unlock_irqrestore(&eisa_irq_lock, flags);
296} 296}
297 297
@@ -305,7 +305,7 @@ static int __init eisa_probe(struct parisc_device *dev)
305 305
306 char *name = is_mongoose(dev) ? "Mongoose" : "Wax"; 306 char *name = is_mongoose(dev) ? "Mongoose" : "Wax";
307 307
308 printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n", 308 printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n",
309 name, (unsigned long)dev->hpa.start); 309 name, (unsigned long)dev->hpa.start);
310 310
311 eisa_dev.hba.dev = dev; 311 eisa_dev.hba.dev = dev;
@@ -336,14 +336,14 @@ static int __init eisa_probe(struct parisc_device *dev)
336 printk(KERN_ERR "EISA: request_irq failed!\n"); 336 printk(KERN_ERR "EISA: request_irq failed!\n");
337 return result; 337 return result;
338 } 338 }
339 339
340 /* Reserve IRQ2 */ 340 /* Reserve IRQ2 */
341 setup_irq(2, &irq2_action); 341 setup_irq(2, &irq2_action);
342 for (i = 0; i < 16; i++) { 342 for (i = 0; i < 16; i++) {
343 irq_set_chip_and_handler(i, &eisa_interrupt_type, 343 irq_set_chip_and_handler(i, &eisa_interrupt_type,
344 handle_simple_irq); 344 handle_simple_irq);
345 } 345 }
346 346
347 EISA_bus = 1; 347 EISA_bus = 1;
348 348
349 if (dev->num_addrs) { 349 if (dev->num_addrs) {
@@ -375,7 +375,7 @@ static int __init eisa_probe(struct parisc_device *dev)
375 return -1; 375 return -1;
376 } 376 }
377 } 377 }
378 378
379 return 0; 379 return 0;
380} 380}
381 381
@@ -404,7 +404,7 @@ void eisa_make_irq_level(int num)
404{ 404{
405 if (eisa_irq_configured& (1<<num)) { 405 if (eisa_irq_configured& (1<<num)) {
406 printk(KERN_WARNING 406 printk(KERN_WARNING
407 "IRQ %d polarity configured twice (last to level)\n", 407 "IRQ %d polarity configured twice (last to level)\n",
408 num); 408 num);
409 } 409 }
410 eisa_irq_level |= (1<<num); /* set the corresponding bit */ 410 eisa_irq_level |= (1<<num); /* set the corresponding bit */
@@ -414,7 +414,7 @@ void eisa_make_irq_level(int num)
414void eisa_make_irq_edge(int num) 414void eisa_make_irq_edge(int num)
415{ 415{
416 if (eisa_irq_configured& (1<<num)) { 416 if (eisa_irq_configured& (1<<num)) {
417 printk(KERN_WARNING 417 printk(KERN_WARNING
418 "IRQ %d polarity configured twice (last to edge)\n", 418 "IRQ %d polarity configured twice (last to edge)\n",
419 num); 419 num);
420 } 420 }
@@ -430,18 +430,18 @@ static int __init eisa_irq_setup(char *str)
430 EISA_DBG("IRQ setup\n"); 430 EISA_DBG("IRQ setup\n");
431 while (cur != NULL) { 431 while (cur != NULL) {
432 char *pe; 432 char *pe;
433 433
434 val = (int) simple_strtoul(cur, &pe, 0); 434 val = (int) simple_strtoul(cur, &pe, 0);
435 if (val > 15 || val < 0) { 435 if (val > 15 || val < 0) {
436 printk(KERN_ERR "eisa: EISA irq value are 0-15\n"); 436 printk(KERN_ERR "eisa: EISA irq value are 0-15\n");
437 continue; 437 continue;
438 } 438 }
439 if (val == 2) { 439 if (val == 2) {
440 val = 9; 440 val = 9;
441 } 441 }
442 eisa_make_irq_edge(val); /* clear the corresponding bit */ 442 eisa_make_irq_edge(val); /* clear the corresponding bit */
443 EISA_DBG("setting IRQ %d to edge-triggered mode\n", val); 443 EISA_DBG("setting IRQ %d to edge-triggered mode\n", val);
444 444
445 if ((cur = strchr(cur, ','))) { 445 if ((cur = strchr(cur, ','))) {
446 cur++; 446 cur++;
447 } else { 447 } else {