diff options
Diffstat (limited to 'drivers/video/fbdev')
39 files changed, 1207 insertions, 954 deletions
diff --git a/drivers/video/fbdev/68328fb.c b/drivers/video/fbdev/68328fb.c index 552258c8f99d..17f21cedff9b 100644 --- a/drivers/video/fbdev/68328fb.c +++ b/drivers/video/fbdev/68328fb.c | |||
@@ -49,12 +49,6 @@ | |||
49 | #error wrong architecture for the MC68x328 frame buffer device | 49 | #error wrong architecture for the MC68x328 frame buffer device |
50 | #endif | 50 | #endif |
51 | 51 | ||
52 | #if defined(CONFIG_FB_68328_INVERT) | ||
53 | #define MC68X328FB_MONO_VISUAL FB_VISUAL_MONO01 | ||
54 | #else | ||
55 | #define MC68X328FB_MONO_VISUAL FB_VISUAL_MONO10 | ||
56 | #endif | ||
57 | |||
58 | static u_long videomemory; | 52 | static u_long videomemory; |
59 | static u_long videomemorysize; | 53 | static u_long videomemorysize; |
60 | 54 | ||
@@ -462,7 +456,7 @@ int __init mc68x328fb_init(void) | |||
462 | fb_info.fix.line_length = | 456 | fb_info.fix.line_length = |
463 | get_line_length(mc68x328fb_default.xres_virtual, mc68x328fb_default.bits_per_pixel); | 457 | get_line_length(mc68x328fb_default.xres_virtual, mc68x328fb_default.bits_per_pixel); |
464 | fb_info.fix.visual = (mc68x328fb_default.bits_per_pixel) == 1 ? | 458 | fb_info.fix.visual = (mc68x328fb_default.bits_per_pixel) == 1 ? |
465 | MC68X328FB_MONO_VISUAL : FB_VISUAL_PSEUDOCOLOR; | 459 | FB_VISUAL_MONO10 : FB_VISUAL_PSEUDOCOLOR; |
466 | if (fb_info.var.bits_per_pixel == 1) { | 460 | if (fb_info.var.bits_per_pixel == 1) { |
467 | fb_info.var.red.length = fb_info.var.green.length = fb_info.var.blue.length = 1; | 461 | fb_info.var.red.length = fb_info.var.green.length = fb_info.var.blue.length = 1; |
468 | fb_info.var.red.offset = fb_info.var.green.offset = fb_info.var.blue.offset = 0; | 462 | fb_info.var.red.offset = fb_info.var.green.offset = fb_info.var.blue.offset = 0; |
diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig index f1458c95a688..ccbe2ae22ac5 100644 --- a/drivers/video/fbdev/Kconfig +++ b/drivers/video/fbdev/Kconfig | |||
@@ -284,6 +284,8 @@ config FB_ARMCLCD | |||
284 | select FB_CFB_FILLRECT | 284 | select FB_CFB_FILLRECT |
285 | select FB_CFB_COPYAREA | 285 | select FB_CFB_COPYAREA |
286 | select FB_CFB_IMAGEBLIT | 286 | select FB_CFB_IMAGEBLIT |
287 | select FB_MODE_HELPERS if OF | ||
288 | select VIDEOMODE_HELPERS if OF | ||
287 | help | 289 | help |
288 | This framebuffer device driver is for the ARM PrimeCell PL110 | 290 | This framebuffer device driver is for the ARM PrimeCell PL110 |
289 | Colour LCD controller. ARM PrimeCells provide the building | 291 | Colour LCD controller. ARM PrimeCells provide the building |
@@ -294,6 +296,12 @@ config FB_ARMCLCD | |||
294 | here and read <file:Documentation/kbuild/modules.txt>. The module | 296 | here and read <file:Documentation/kbuild/modules.txt>. The module |
295 | will be called amba-clcd. | 297 | will be called amba-clcd. |
296 | 298 | ||
299 | # Helper logic selected only by the ARM Versatile platform family. | ||
300 | config PLAT_VERSATILE_CLCD | ||
301 | def_bool ARCH_VERSATILE || ARCH_REALVIEW || ARCH_VEXPRESS | ||
302 | depends on ARM | ||
303 | depends on FB_ARMCLCD && FB=y | ||
304 | |||
297 | config FB_ACORN | 305 | config FB_ACORN |
298 | bool "Acorn VIDC support" | 306 | bool "Acorn VIDC support" |
299 | depends on (FB = y) && ARM && ARCH_ACORN | 307 | depends on (FB = y) && ARM && ARCH_ACORN |
@@ -305,15 +313,26 @@ config FB_ACORN | |||
305 | hardware found in Acorn RISC PCs and other ARM-based machines. If | 313 | hardware found in Acorn RISC PCs and other ARM-based machines. If |
306 | unsure, say N. | 314 | unsure, say N. |
307 | 315 | ||
308 | config FB_CLPS711X | 316 | config FB_CLPS711X_OLD |
309 | bool "CLPS711X LCD support" | 317 | tristate |
310 | depends on (FB = y) && ARM && ARCH_CLPS711X | ||
311 | select FB_CFB_FILLRECT | 318 | select FB_CFB_FILLRECT |
312 | select FB_CFB_COPYAREA | 319 | select FB_CFB_COPYAREA |
313 | select FB_CFB_IMAGEBLIT | 320 | select FB_CFB_IMAGEBLIT |
321 | |||
322 | config FB_CLPS711X | ||
323 | tristate "CLPS711X LCD support" | ||
324 | depends on FB && (ARCH_CLPS711X || COMPILE_TEST) | ||
325 | select FB_CLPS711X_OLD if ARCH_CLPS711X && !ARCH_MULTIPLATFORM | ||
326 | select BACKLIGHT_LCD_SUPPORT | ||
327 | select FB_MODE_HELPERS | ||
328 | select FB_SYS_FILLRECT | ||
329 | select FB_SYS_COPYAREA | ||
330 | select FB_SYS_IMAGEBLIT | ||
331 | select LCD_CLASS_DEVICE | ||
332 | select VIDEOMODE_HELPERS | ||
314 | help | 333 | help |
315 | Say Y to enable the Framebuffer driver for the CLPS7111 and | 334 | Say Y to enable the Framebuffer driver for the Cirrus Logic |
316 | EP7212 processors. | 335 | CLPS711X CPUs. |
317 | 336 | ||
318 | config FB_SA1100 | 337 | config FB_SA1100 |
319 | bool "SA-1100 LCD support" | 338 | bool "SA-1100 LCD support" |
@@ -2022,8 +2041,8 @@ config FB_TMIO_ACCELL | |||
2022 | 2041 | ||
2023 | config FB_S3C | 2042 | config FB_S3C |
2024 | tristate "Samsung S3C framebuffer support" | 2043 | tristate "Samsung S3C framebuffer support" |
2025 | depends on FB && (CPU_S3C2416 || ARCH_S3C64XX || ARCH_S5P64X0 || \ | 2044 | depends on FB && (CPU_S3C2416 || ARCH_S3C64XX || \ |
2026 | ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS) | 2045 | ARCH_S5PV210 || ARCH_EXYNOS) |
2027 | select FB_CFB_FILLRECT | 2046 | select FB_CFB_FILLRECT |
2028 | select FB_CFB_COPYAREA | 2047 | select FB_CFB_COPYAREA |
2029 | select FB_CFB_IMAGEBLIT | 2048 | select FB_CFB_IMAGEBLIT |
diff --git a/drivers/video/fbdev/Makefile b/drivers/video/fbdev/Makefile index 0284f2a12538..1979afffccfe 100644 --- a/drivers/video/fbdev/Makefile +++ b/drivers/video/fbdev/Makefile | |||
@@ -14,7 +14,8 @@ obj-$(CONFIG_FB_WMT_GE_ROPS) += wmt_ge_rops.o | |||
14 | # Hardware specific drivers go first | 14 | # Hardware specific drivers go first |
15 | obj-$(CONFIG_FB_AMIGA) += amifb.o c2p_planar.o | 15 | obj-$(CONFIG_FB_AMIGA) += amifb.o c2p_planar.o |
16 | obj-$(CONFIG_FB_ARC) += arcfb.o | 16 | obj-$(CONFIG_FB_ARC) += arcfb.o |
17 | obj-$(CONFIG_FB_CLPS711X) += clps711xfb.o | 17 | obj-$(CONFIG_FB_CLPS711X) += clps711x-fb.o |
18 | obj-$(CONFIG_FB_CLPS711X_OLD) += clps711xfb.o | ||
18 | obj-$(CONFIG_FB_CYBER2000) += cyber2000fb.o | 19 | obj-$(CONFIG_FB_CYBER2000) += cyber2000fb.o |
19 | obj-$(CONFIG_FB_GRVGA) += grvga.o | 20 | obj-$(CONFIG_FB_GRVGA) += grvga.o |
20 | obj-$(CONFIG_FB_PM2) += pm2fb.o | 21 | obj-$(CONFIG_FB_PM2) += pm2fb.o |
@@ -78,6 +79,7 @@ obj-$(CONFIG_FB_ATMEL) += atmel_lcdfb.o | |||
78 | obj-$(CONFIG_FB_PVR2) += pvr2fb.o | 79 | obj-$(CONFIG_FB_PVR2) += pvr2fb.o |
79 | obj-$(CONFIG_FB_VOODOO1) += sstfb.o | 80 | obj-$(CONFIG_FB_VOODOO1) += sstfb.o |
80 | obj-$(CONFIG_FB_ARMCLCD) += amba-clcd.o | 81 | obj-$(CONFIG_FB_ARMCLCD) += amba-clcd.o |
82 | obj-$(CONFIG_PLAT_VERSATILE_CLCD) += amba-clcd-versatile.o | ||
81 | obj-$(CONFIG_FB_GOLDFISH) += goldfishfb.o | 83 | obj-$(CONFIG_FB_GOLDFISH) += goldfishfb.o |
82 | obj-$(CONFIG_FB_68328) += 68328fb.o | 84 | obj-$(CONFIG_FB_68328) += 68328fb.o |
83 | obj-$(CONFIG_FB_GBE) += gbefb.o | 85 | obj-$(CONFIG_FB_GBE) += gbefb.o |
diff --git a/drivers/video/fbdev/amba-clcd-versatile.c b/drivers/video/fbdev/amba-clcd-versatile.c new file mode 100644 index 000000000000..7a8afcd4573e --- /dev/null +++ b/drivers/video/fbdev/amba-clcd-versatile.c | |||
@@ -0,0 +1,182 @@ | |||
1 | #include <linux/device.h> | ||
2 | #include <linux/dma-mapping.h> | ||
3 | #include <linux/amba/bus.h> | ||
4 | #include <linux/amba/clcd.h> | ||
5 | #include <linux/platform_data/video-clcd-versatile.h> | ||
6 | |||
7 | static struct clcd_panel vga = { | ||
8 | .mode = { | ||
9 | .name = "VGA", | ||
10 | .refresh = 60, | ||
11 | .xres = 640, | ||
12 | .yres = 480, | ||
13 | .pixclock = 39721, | ||
14 | .left_margin = 40, | ||
15 | .right_margin = 24, | ||
16 | .upper_margin = 32, | ||
17 | .lower_margin = 11, | ||
18 | .hsync_len = 96, | ||
19 | .vsync_len = 2, | ||
20 | .sync = 0, | ||
21 | .vmode = FB_VMODE_NONINTERLACED, | ||
22 | }, | ||
23 | .width = -1, | ||
24 | .height = -1, | ||
25 | .tim2 = TIM2_BCD | TIM2_IPC, | ||
26 | .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), | ||
27 | .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888, | ||
28 | .bpp = 16, | ||
29 | }; | ||
30 | |||
31 | static struct clcd_panel xvga = { | ||
32 | .mode = { | ||
33 | .name = "XVGA", | ||
34 | .refresh = 60, | ||
35 | .xres = 1024, | ||
36 | .yres = 768, | ||
37 | .pixclock = 15748, | ||
38 | .left_margin = 152, | ||
39 | .right_margin = 48, | ||
40 | .upper_margin = 23, | ||
41 | .lower_margin = 3, | ||
42 | .hsync_len = 104, | ||
43 | .vsync_len = 4, | ||
44 | .sync = 0, | ||
45 | .vmode = FB_VMODE_NONINTERLACED, | ||
46 | }, | ||
47 | .width = -1, | ||
48 | .height = -1, | ||
49 | .tim2 = TIM2_BCD | TIM2_IPC, | ||
50 | .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), | ||
51 | .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888, | ||
52 | .bpp = 16, | ||
53 | }; | ||
54 | |||
55 | /* Sanyo TM38QV67A02A - 3.8 inch QVGA (320x240) Color TFT */ | ||
56 | static struct clcd_panel sanyo_tm38qv67a02a = { | ||
57 | .mode = { | ||
58 | .name = "Sanyo TM38QV67A02A", | ||
59 | .refresh = 116, | ||
60 | .xres = 320, | ||
61 | .yres = 240, | ||
62 | .pixclock = 100000, | ||
63 | .left_margin = 6, | ||
64 | .right_margin = 6, | ||
65 | .upper_margin = 5, | ||
66 | .lower_margin = 5, | ||
67 | .hsync_len = 6, | ||
68 | .vsync_len = 6, | ||
69 | .sync = 0, | ||
70 | .vmode = FB_VMODE_NONINTERLACED, | ||
71 | }, | ||
72 | .width = -1, | ||
73 | .height = -1, | ||
74 | .tim2 = TIM2_BCD, | ||
75 | .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), | ||
76 | .caps = CLCD_CAP_5551, | ||
77 | .bpp = 16, | ||
78 | }; | ||
79 | |||
80 | static struct clcd_panel sanyo_2_5_in = { | ||
81 | .mode = { | ||
82 | .name = "Sanyo QVGA Portrait", | ||
83 | .refresh = 116, | ||
84 | .xres = 240, | ||
85 | .yres = 320, | ||
86 | .pixclock = 100000, | ||
87 | .left_margin = 20, | ||
88 | .right_margin = 10, | ||
89 | .upper_margin = 2, | ||
90 | .lower_margin = 2, | ||
91 | .hsync_len = 10, | ||
92 | .vsync_len = 2, | ||
93 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | ||
94 | .vmode = FB_VMODE_NONINTERLACED, | ||
95 | }, | ||
96 | .width = -1, | ||
97 | .height = -1, | ||
98 | .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC, | ||
99 | .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), | ||
100 | .caps = CLCD_CAP_5551, | ||
101 | .bpp = 16, | ||
102 | }; | ||
103 | |||
104 | /* Epson L2F50113T00 - 2.2 inch 176x220 Color TFT */ | ||
105 | static struct clcd_panel epson_l2f50113t00 = { | ||
106 | .mode = { | ||
107 | .name = "Epson L2F50113T00", | ||
108 | .refresh = 390, | ||
109 | .xres = 176, | ||
110 | .yres = 220, | ||
111 | .pixclock = 62500, | ||
112 | .left_margin = 3, | ||
113 | .right_margin = 2, | ||
114 | .upper_margin = 1, | ||
115 | .lower_margin = 0, | ||
116 | .hsync_len = 3, | ||
117 | .vsync_len = 2, | ||
118 | .sync = 0, | ||
119 | .vmode = FB_VMODE_NONINTERLACED, | ||
120 | }, | ||
121 | .width = -1, | ||
122 | .height = -1, | ||
123 | .tim2 = TIM2_BCD | TIM2_IPC, | ||
124 | .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), | ||
125 | .caps = CLCD_CAP_5551, | ||
126 | .bpp = 16, | ||
127 | }; | ||
128 | |||
129 | static struct clcd_panel *panels[] = { | ||
130 | &vga, | ||
131 | &xvga, | ||
132 | &sanyo_tm38qv67a02a, | ||
133 | &sanyo_2_5_in, | ||
134 | &epson_l2f50113t00, | ||
135 | }; | ||
136 | |||
137 | struct clcd_panel *versatile_clcd_get_panel(const char *name) | ||
138 | { | ||
139 | int i; | ||
140 | |||
141 | for (i = 0; i < ARRAY_SIZE(panels); i++) | ||
142 | if (strcmp(panels[i]->mode.name, name) == 0) | ||
143 | break; | ||
144 | |||
145 | if (i < ARRAY_SIZE(panels)) | ||
146 | return panels[i]; | ||
147 | |||
148 | pr_err("CLCD: couldn't get parameters for panel %s\n", name); | ||
149 | |||
150 | return NULL; | ||
151 | } | ||
152 | |||
153 | int versatile_clcd_setup_dma(struct clcd_fb *fb, unsigned long framesize) | ||
154 | { | ||
155 | dma_addr_t dma; | ||
156 | |||
157 | fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize, | ||
158 | &dma, GFP_KERNEL); | ||
159 | if (!fb->fb.screen_base) { | ||
160 | pr_err("CLCD: unable to map framebuffer\n"); | ||
161 | return -ENOMEM; | ||
162 | } | ||
163 | |||
164 | fb->fb.fix.smem_start = dma; | ||
165 | fb->fb.fix.smem_len = framesize; | ||
166 | |||
167 | return 0; | ||
168 | } | ||
169 | |||
170 | int versatile_clcd_mmap_dma(struct clcd_fb *fb, struct vm_area_struct *vma) | ||
171 | { | ||
172 | return dma_mmap_writecombine(&fb->dev->dev, vma, | ||
173 | fb->fb.screen_base, | ||
174 | fb->fb.fix.smem_start, | ||
175 | fb->fb.fix.smem_len); | ||
176 | } | ||
177 | |||
178 | void versatile_clcd_remove_dma(struct clcd_fb *fb) | ||
179 | { | ||
180 | dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len, | ||
181 | fb->fb.screen_base, fb->fb.fix.smem_start); | ||
182 | } | ||
diff --git a/drivers/video/fbdev/amba-clcd.c b/drivers/video/fbdev/amba-clcd.c index 14d6b3793e0a..beadd3edaa17 100644 --- a/drivers/video/fbdev/amba-clcd.c +++ b/drivers/video/fbdev/amba-clcd.c | |||
@@ -26,6 +26,13 @@ | |||
26 | #include <linux/amba/clcd.h> | 26 | #include <linux/amba/clcd.h> |
27 | #include <linux/clk.h> | 27 | #include <linux/clk.h> |
28 | #include <linux/hardirq.h> | 28 | #include <linux/hardirq.h> |
29 | #include <linux/dma-mapping.h> | ||
30 | #include <linux/of.h> | ||
31 | #include <linux/of_address.h> | ||
32 | #include <linux/of_graph.h> | ||
33 | #include <video/display_timing.h> | ||
34 | #include <video/of_display_timing.h> | ||
35 | #include <video/videomode.h> | ||
29 | 36 | ||
30 | #include <asm/sizes.h> | 37 | #include <asm/sizes.h> |
31 | 38 | ||
@@ -543,6 +550,259 @@ static int clcdfb_register(struct clcd_fb *fb) | |||
543 | return ret; | 550 | return ret; |
544 | } | 551 | } |
545 | 552 | ||
553 | #ifdef CONFIG_OF | ||
554 | static int clcdfb_of_get_dpi_panel_mode(struct device_node *node, | ||
555 | struct fb_videomode *mode) | ||
556 | { | ||
557 | int err; | ||
558 | struct display_timing timing; | ||
559 | struct videomode video; | ||
560 | |||
561 | err = of_get_display_timing(node, "panel-timing", &timing); | ||
562 | if (err) | ||
563 | return err; | ||
564 | |||
565 | videomode_from_timing(&timing, &video); | ||
566 | |||
567 | err = fb_videomode_from_videomode(&video, mode); | ||
568 | if (err) | ||
569 | return err; | ||
570 | |||
571 | return 0; | ||
572 | } | ||
573 | |||
574 | static int clcdfb_snprintf_mode(char *buf, int size, struct fb_videomode *mode) | ||
575 | { | ||
576 | return snprintf(buf, size, "%ux%u@%u", mode->xres, mode->yres, | ||
577 | mode->refresh); | ||
578 | } | ||
579 | |||
580 | static int clcdfb_of_get_mode(struct device *dev, struct device_node *endpoint, | ||
581 | struct fb_videomode *mode) | ||
582 | { | ||
583 | int err; | ||
584 | struct device_node *panel; | ||
585 | char *name; | ||
586 | int len; | ||
587 | |||
588 | panel = of_graph_get_remote_port_parent(endpoint); | ||
589 | if (!panel) | ||
590 | return -ENODEV; | ||
591 | |||
592 | /* Only directly connected DPI panels supported for now */ | ||
593 | if (of_device_is_compatible(panel, "panel-dpi")) | ||
594 | err = clcdfb_of_get_dpi_panel_mode(panel, mode); | ||
595 | else | ||
596 | err = -ENOENT; | ||
597 | if (err) | ||
598 | return err; | ||
599 | |||
600 | len = clcdfb_snprintf_mode(NULL, 0, mode); | ||
601 | name = devm_kzalloc(dev, len + 1, GFP_KERNEL); | ||
602 | clcdfb_snprintf_mode(name, len + 1, mode); | ||
603 | mode->name = name; | ||
604 | |||
605 | return 0; | ||
606 | } | ||
607 | |||
608 | static int clcdfb_of_init_tft_panel(struct clcd_fb *fb, u32 r0, u32 g0, u32 b0) | ||
609 | { | ||
610 | static struct { | ||
611 | unsigned int part; | ||
612 | u32 r0, g0, b0; | ||
613 | u32 caps; | ||
614 | } panels[] = { | ||
615 | { 0x110, 1, 7, 13, CLCD_CAP_5551 }, | ||
616 | { 0x110, 0, 8, 16, CLCD_CAP_888 }, | ||
617 | { 0x111, 4, 14, 20, CLCD_CAP_444 }, | ||
618 | { 0x111, 3, 11, 19, CLCD_CAP_444 | CLCD_CAP_5551 }, | ||
619 | { 0x111, 3, 10, 19, CLCD_CAP_444 | CLCD_CAP_5551 | | ||
620 | CLCD_CAP_565 }, | ||
621 | { 0x111, 0, 8, 16, CLCD_CAP_444 | CLCD_CAP_5551 | | ||
622 | CLCD_CAP_565 | CLCD_CAP_888 }, | ||
623 | }; | ||
624 | int i; | ||
625 | |||
626 | /* Bypass pixel clock divider, data output on the falling edge */ | ||
627 | fb->panel->tim2 = TIM2_BCD | TIM2_IPC; | ||
628 | |||
629 | /* TFT display, vert. comp. interrupt at the start of the back porch */ | ||
630 | fb->panel->cntl |= CNTL_LCDTFT | CNTL_LCDVCOMP(1); | ||
631 | |||
632 | fb->panel->caps = 0; | ||
633 | |||
634 | /* Match the setup with known variants */ | ||
635 | for (i = 0; i < ARRAY_SIZE(panels) && !fb->panel->caps; i++) { | ||
636 | if (amba_part(fb->dev) != panels[i].part) | ||
637 | continue; | ||
638 | if (g0 != panels[i].g0) | ||
639 | continue; | ||
640 | if (r0 == panels[i].r0 && b0 == panels[i].b0) | ||
641 | fb->panel->caps = panels[i].caps & CLCD_CAP_RGB; | ||
642 | if (r0 == panels[i].b0 && b0 == panels[i].r0) | ||
643 | fb->panel->caps = panels[i].caps & CLCD_CAP_BGR; | ||
644 | } | ||
645 | |||
646 | return fb->panel->caps ? 0 : -EINVAL; | ||
647 | } | ||
648 | |||
649 | static int clcdfb_of_init_display(struct clcd_fb *fb) | ||
650 | { | ||
651 | struct device_node *endpoint; | ||
652 | int err; | ||
653 | u32 max_bandwidth; | ||
654 | u32 tft_r0b0g0[3]; | ||
655 | |||
656 | fb->panel = devm_kzalloc(&fb->dev->dev, sizeof(*fb->panel), GFP_KERNEL); | ||
657 | if (!fb->panel) | ||
658 | return -ENOMEM; | ||
659 | |||
660 | endpoint = of_graph_get_next_endpoint(fb->dev->dev.of_node, NULL); | ||
661 | if (!endpoint) | ||
662 | return -ENODEV; | ||
663 | |||
664 | err = clcdfb_of_get_mode(&fb->dev->dev, endpoint, &fb->panel->mode); | ||
665 | if (err) | ||
666 | return err; | ||
667 | |||
668 | err = of_property_read_u32(fb->dev->dev.of_node, "max-memory-bandwidth", | ||
669 | &max_bandwidth); | ||
670 | if (!err) | ||
671 | fb->panel->bpp = 8 * max_bandwidth / (fb->panel->mode.xres * | ||
672 | fb->panel->mode.yres * fb->panel->mode.refresh); | ||
673 | else | ||
674 | fb->panel->bpp = 32; | ||
675 | |||
676 | #ifdef CONFIG_CPU_BIG_ENDIAN | ||
677 | fb->panel->cntl |= CNTL_BEBO; | ||
678 | #endif | ||
679 | fb->panel->width = -1; | ||
680 | fb->panel->height = -1; | ||
681 | |||
682 | if (of_property_read_u32_array(endpoint, | ||
683 | "arm,pl11x,tft-r0g0b0-pads", | ||
684 | tft_r0b0g0, ARRAY_SIZE(tft_r0b0g0)) == 0) | ||
685 | return clcdfb_of_init_tft_panel(fb, tft_r0b0g0[0], | ||
686 | tft_r0b0g0[1], tft_r0b0g0[2]); | ||
687 | |||
688 | return -ENOENT; | ||
689 | } | ||
690 | |||
691 | static int clcdfb_of_vram_setup(struct clcd_fb *fb) | ||
692 | { | ||
693 | int err; | ||
694 | struct device_node *memory; | ||
695 | u64 size; | ||
696 | |||
697 | err = clcdfb_of_init_display(fb); | ||
698 | if (err) | ||
699 | return err; | ||
700 | |||
701 | memory = of_parse_phandle(fb->dev->dev.of_node, "memory-region", 0); | ||
702 | if (!memory) | ||
703 | return -ENODEV; | ||
704 | |||
705 | fb->fb.screen_base = of_iomap(memory, 0); | ||
706 | if (!fb->fb.screen_base) | ||
707 | return -ENOMEM; | ||
708 | |||
709 | fb->fb.fix.smem_start = of_translate_address(memory, | ||
710 | of_get_address(memory, 0, &size, NULL)); | ||
711 | fb->fb.fix.smem_len = size; | ||
712 | |||
713 | return 0; | ||
714 | } | ||
715 | |||
716 | static int clcdfb_of_vram_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) | ||
717 | { | ||
718 | unsigned long off, user_size, kernel_size; | ||
719 | |||
720 | |||
721 | off = vma->vm_pgoff << PAGE_SHIFT; | ||
722 | user_size = vma->vm_end - vma->vm_start; | ||
723 | kernel_size = fb->fb.fix.smem_len; | ||
724 | |||
725 | if (off >= kernel_size || user_size > (kernel_size - off)) | ||
726 | return -ENXIO; | ||
727 | |||
728 | return remap_pfn_range(vma, vma->vm_start, | ||
729 | __phys_to_pfn(fb->fb.fix.smem_start) + vma->vm_pgoff, | ||
730 | user_size, | ||
731 | pgprot_writecombine(vma->vm_page_prot)); | ||
732 | } | ||
733 | |||
734 | static void clcdfb_of_vram_remove(struct clcd_fb *fb) | ||
735 | { | ||
736 | iounmap(fb->fb.screen_base); | ||
737 | } | ||
738 | |||
739 | static int clcdfb_of_dma_setup(struct clcd_fb *fb) | ||
740 | { | ||
741 | unsigned long framesize; | ||
742 | dma_addr_t dma; | ||
743 | int err; | ||
744 | |||
745 | err = clcdfb_of_init_display(fb); | ||
746 | if (err) | ||
747 | return err; | ||
748 | |||
749 | framesize = fb->panel->mode.xres * fb->panel->mode.yres * | ||
750 | fb->panel->bpp / 8; | ||
751 | fb->fb.screen_base = dma_alloc_coherent(&fb->dev->dev, framesize, | ||
752 | &dma, GFP_KERNEL); | ||
753 | if (!fb->fb.screen_base) | ||
754 | return -ENOMEM; | ||
755 | |||
756 | fb->fb.fix.smem_start = dma; | ||
757 | fb->fb.fix.smem_len = framesize; | ||
758 | |||
759 | return 0; | ||
760 | } | ||
761 | |||
762 | static int clcdfb_of_dma_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) | ||
763 | { | ||
764 | return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base, | ||
765 | fb->fb.fix.smem_start, fb->fb.fix.smem_len); | ||
766 | } | ||
767 | |||
768 | static void clcdfb_of_dma_remove(struct clcd_fb *fb) | ||
769 | { | ||
770 | dma_free_coherent(&fb->dev->dev, fb->fb.fix.smem_len, | ||
771 | fb->fb.screen_base, fb->fb.fix.smem_start); | ||
772 | } | ||
773 | |||
774 | static struct clcd_board *clcdfb_of_get_board(struct amba_device *dev) | ||
775 | { | ||
776 | struct clcd_board *board = devm_kzalloc(&dev->dev, sizeof(*board), | ||
777 | GFP_KERNEL); | ||
778 | struct device_node *node = dev->dev.of_node; | ||
779 | |||
780 | if (!board) | ||
781 | return NULL; | ||
782 | |||
783 | board->name = of_node_full_name(node); | ||
784 | board->caps = CLCD_CAP_ALL; | ||
785 | board->check = clcdfb_check; | ||
786 | board->decode = clcdfb_decode; | ||
787 | if (of_find_property(node, "memory-region", NULL)) { | ||
788 | board->setup = clcdfb_of_vram_setup; | ||
789 | board->mmap = clcdfb_of_vram_mmap; | ||
790 | board->remove = clcdfb_of_vram_remove; | ||
791 | } else { | ||
792 | board->setup = clcdfb_of_dma_setup; | ||
793 | board->mmap = clcdfb_of_dma_mmap; | ||
794 | board->remove = clcdfb_of_dma_remove; | ||
795 | } | ||
796 | |||
797 | return board; | ||
798 | } | ||
799 | #else | ||
800 | static struct clcd_board *clcdfb_of_get_board(struct amba_device *dev) | ||
801 | { | ||
802 | return NULL; | ||
803 | } | ||
804 | #endif | ||
805 | |||
546 | static int clcdfb_probe(struct amba_device *dev, const struct amba_id *id) | 806 | static int clcdfb_probe(struct amba_device *dev, const struct amba_id *id) |
547 | { | 807 | { |
548 | struct clcd_board *board = dev_get_platdata(&dev->dev); | 808 | struct clcd_board *board = dev_get_platdata(&dev->dev); |
@@ -550,6 +810,9 @@ static int clcdfb_probe(struct amba_device *dev, const struct amba_id *id) | |||
550 | int ret; | 810 | int ret; |
551 | 811 | ||
552 | if (!board) | 812 | if (!board) |
813 | board = clcdfb_of_get_board(dev); | ||
814 | |||
815 | if (!board) | ||
553 | return -EINVAL; | 816 | return -EINVAL; |
554 | 817 | ||
555 | ret = dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32)); | 818 | ret = dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32)); |
diff --git a/drivers/video/fbdev/atmel_lcdfb.c b/drivers/video/fbdev/atmel_lcdfb.c index d36e830d6fc6..92640d46770a 100644 --- a/drivers/video/fbdev/atmel_lcdfb.c +++ b/drivers/video/fbdev/atmel_lcdfb.c | |||
@@ -290,7 +290,7 @@ static void init_contrast(struct atmel_lcdfb_info *sinfo) | |||
290 | 290 | ||
291 | /* contrast pwm can be 'inverted' */ | 291 | /* contrast pwm can be 'inverted' */ |
292 | if (pdata->lcdcon_pol_negative) | 292 | if (pdata->lcdcon_pol_negative) |
293 | contrast_ctr &= ~(ATMEL_LCDC_POL_POSITIVE); | 293 | contrast_ctr &= ~(ATMEL_LCDC_POL_POSITIVE); |
294 | 294 | ||
295 | /* have some default contrast/backlight settings */ | 295 | /* have some default contrast/backlight settings */ |
296 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr); | 296 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr); |
@@ -1097,6 +1097,7 @@ static int atmel_lcdfb_of_init(struct atmel_lcdfb_info *sinfo) | |||
1097 | pdata->lcd_wiring_mode = ret; | 1097 | pdata->lcd_wiring_mode = ret; |
1098 | 1098 | ||
1099 | pdata->lcdcon_is_backlight = of_property_read_bool(display_np, "atmel,lcdcon-backlight"); | 1099 | pdata->lcdcon_is_backlight = of_property_read_bool(display_np, "atmel,lcdcon-backlight"); |
1100 | pdata->lcdcon_pol_negative = of_property_read_bool(display_np, "atmel,lcdcon-backlight-inverted"); | ||
1100 | 1101 | ||
1101 | timings = of_get_display_timings(display_np); | 1102 | timings = of_get_display_timings(display_np); |
1102 | if (!timings) { | 1103 | if (!timings) { |
diff --git a/drivers/video/fbdev/aty/aty128fb.c b/drivers/video/fbdev/aty/aty128fb.c index 52108be69e77..ff6070170d01 100644 --- a/drivers/video/fbdev/aty/aty128fb.c +++ b/drivers/video/fbdev/aty/aty128fb.c | |||
@@ -1802,13 +1802,7 @@ static int aty128_bl_update_status(struct backlight_device *bd) | |||
1802 | return 0; | 1802 | return 0; |
1803 | } | 1803 | } |
1804 | 1804 | ||
1805 | static int aty128_bl_get_brightness(struct backlight_device *bd) | ||
1806 | { | ||
1807 | return bd->props.brightness; | ||
1808 | } | ||
1809 | |||
1810 | static const struct backlight_ops aty128_bl_data = { | 1805 | static const struct backlight_ops aty128_bl_data = { |
1811 | .get_brightness = aty128_bl_get_brightness, | ||
1812 | .update_status = aty128_bl_update_status, | 1806 | .update_status = aty128_bl_update_status, |
1813 | }; | 1807 | }; |
1814 | 1808 | ||
diff --git a/drivers/video/fbdev/aty/atyfb_base.c b/drivers/video/fbdev/aty/atyfb_base.c index c3d0074a32db..37ec09b3fffd 100644 --- a/drivers/video/fbdev/aty/atyfb_base.c +++ b/drivers/video/fbdev/aty/atyfb_base.c | |||
@@ -2211,13 +2211,7 @@ static int aty_bl_update_status(struct backlight_device *bd) | |||
2211 | return 0; | 2211 | return 0; |
2212 | } | 2212 | } |
2213 | 2213 | ||
2214 | static int aty_bl_get_brightness(struct backlight_device *bd) | ||
2215 | { | ||
2216 | return bd->props.brightness; | ||
2217 | } | ||
2218 | |||
2219 | static const struct backlight_ops aty_bl_data = { | 2214 | static const struct backlight_ops aty_bl_data = { |
2220 | .get_brightness = aty_bl_get_brightness, | ||
2221 | .update_status = aty_bl_update_status, | 2215 | .update_status = aty_bl_update_status, |
2222 | }; | 2216 | }; |
2223 | 2217 | ||
diff --git a/drivers/video/fbdev/aty/radeon_backlight.c b/drivers/video/fbdev/aty/radeon_backlight.c index db572df7e1ef..301d6d6aeead 100644 --- a/drivers/video/fbdev/aty/radeon_backlight.c +++ b/drivers/video/fbdev/aty/radeon_backlight.c | |||
@@ -123,13 +123,7 @@ static int radeon_bl_update_status(struct backlight_device *bd) | |||
123 | return 0; | 123 | return 0; |
124 | } | 124 | } |
125 | 125 | ||
126 | static int radeon_bl_get_brightness(struct backlight_device *bd) | ||
127 | { | ||
128 | return bd->props.brightness; | ||
129 | } | ||
130 | |||
131 | static const struct backlight_ops radeon_bl_data = { | 126 | static const struct backlight_ops radeon_bl_data = { |
132 | .get_brightness = radeon_bl_get_brightness, | ||
133 | .update_status = radeon_bl_update_status, | 127 | .update_status = radeon_bl_update_status, |
134 | }; | 128 | }; |
135 | 129 | ||
diff --git a/drivers/video/fbdev/au1100fb.c b/drivers/video/fbdev/au1100fb.c index 372d4aea9d1c..0676746ec68c 100644 --- a/drivers/video/fbdev/au1100fb.c +++ b/drivers/video/fbdev/au1100fb.c | |||
@@ -41,6 +41,7 @@ | |||
41 | * with this program; if not, write to the Free Software Foundation, Inc., | 41 | * with this program; if not, write to the Free Software Foundation, Inc., |
42 | * 675 Mass Ave, Cambridge, MA 02139, USA. | 42 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
43 | */ | 43 | */ |
44 | #include <linux/clk.h> | ||
44 | #include <linux/module.h> | 45 | #include <linux/module.h> |
45 | #include <linux/kernel.h> | 46 | #include <linux/kernel.h> |
46 | #include <linux/errno.h> | 47 | #include <linux/errno.h> |
@@ -113,7 +114,7 @@ static int au1100fb_fb_blank(int blank_mode, struct fb_info *fbi) | |||
113 | case VESA_NO_BLANKING: | 114 | case VESA_NO_BLANKING: |
114 | /* Turn on panel */ | 115 | /* Turn on panel */ |
115 | fbdev->regs->lcd_control |= LCD_CONTROL_GO; | 116 | fbdev->regs->lcd_control |= LCD_CONTROL_GO; |
116 | au_sync(); | 117 | wmb(); /* drain writebuffer */ |
117 | break; | 118 | break; |
118 | 119 | ||
119 | case VESA_VSYNC_SUSPEND: | 120 | case VESA_VSYNC_SUSPEND: |
@@ -121,7 +122,7 @@ static int au1100fb_fb_blank(int blank_mode, struct fb_info *fbi) | |||
121 | case VESA_POWERDOWN: | 122 | case VESA_POWERDOWN: |
122 | /* Turn off panel */ | 123 | /* Turn off panel */ |
123 | fbdev->regs->lcd_control &= ~LCD_CONTROL_GO; | 124 | fbdev->regs->lcd_control &= ~LCD_CONTROL_GO; |
124 | au_sync(); | 125 | wmb(); /* drain writebuffer */ |
125 | break; | 126 | break; |
126 | default: | 127 | default: |
127 | break; | 128 | break; |
@@ -434,7 +435,7 @@ static int au1100fb_drv_probe(struct platform_device *dev) | |||
434 | struct au1100fb_device *fbdev = NULL; | 435 | struct au1100fb_device *fbdev = NULL; |
435 | struct resource *regs_res; | 436 | struct resource *regs_res; |
436 | unsigned long page; | 437 | unsigned long page; |
437 | u32 sys_clksrc; | 438 | struct clk *c; |
438 | 439 | ||
439 | /* Allocate new device private */ | 440 | /* Allocate new device private */ |
440 | fbdev = devm_kzalloc(&dev->dev, sizeof(struct au1100fb_device), | 441 | fbdev = devm_kzalloc(&dev->dev, sizeof(struct au1100fb_device), |
@@ -473,6 +474,13 @@ static int au1100fb_drv_probe(struct platform_device *dev) | |||
473 | print_dbg("Register memory map at %p", fbdev->regs); | 474 | print_dbg("Register memory map at %p", fbdev->regs); |
474 | print_dbg("phys=0x%08x, size=%d", fbdev->regs_phys, fbdev->regs_len); | 475 | print_dbg("phys=0x%08x, size=%d", fbdev->regs_phys, fbdev->regs_len); |
475 | 476 | ||
477 | c = clk_get(NULL, "lcd_intclk"); | ||
478 | if (!IS_ERR(c)) { | ||
479 | fbdev->lcdclk = c; | ||
480 | clk_set_rate(c, 48000000); | ||
481 | clk_prepare_enable(c); | ||
482 | } | ||
483 | |||
476 | /* Allocate the framebuffer to the maximum screen size * nbr of video buffers */ | 484 | /* Allocate the framebuffer to the maximum screen size * nbr of video buffers */ |
477 | fbdev->fb_len = fbdev->panel->xres * fbdev->panel->yres * | 485 | fbdev->fb_len = fbdev->panel->xres * fbdev->panel->yres * |
478 | (fbdev->panel->bpp >> 3) * AU1100FB_NBR_VIDEO_BUFFERS; | 486 | (fbdev->panel->bpp >> 3) * AU1100FB_NBR_VIDEO_BUFFERS; |
@@ -506,10 +514,6 @@ static int au1100fb_drv_probe(struct platform_device *dev) | |||
506 | print_dbg("Framebuffer memory map at %p", fbdev->fb_mem); | 514 | print_dbg("Framebuffer memory map at %p", fbdev->fb_mem); |
507 | print_dbg("phys=0x%08x, size=%dK", fbdev->fb_phys, fbdev->fb_len / 1024); | 515 | print_dbg("phys=0x%08x, size=%dK", fbdev->fb_phys, fbdev->fb_len / 1024); |
508 | 516 | ||
509 | /* Setup LCD clock to AUX (48 MHz) */ | ||
510 | sys_clksrc = au_readl(SYS_CLKSRC) & ~(SYS_CS_ML_MASK | SYS_CS_DL | SYS_CS_CL); | ||
511 | au_writel((sys_clksrc | (1 << SYS_CS_ML_BIT)), SYS_CLKSRC); | ||
512 | |||
513 | /* load the panel info into the var struct */ | 517 | /* load the panel info into the var struct */ |
514 | au1100fb_var.bits_per_pixel = fbdev->panel->bpp; | 518 | au1100fb_var.bits_per_pixel = fbdev->panel->bpp; |
515 | au1100fb_var.xres = fbdev->panel->xres; | 519 | au1100fb_var.xres = fbdev->panel->xres; |
@@ -546,6 +550,10 @@ static int au1100fb_drv_probe(struct platform_device *dev) | |||
546 | return 0; | 550 | return 0; |
547 | 551 | ||
548 | failed: | 552 | failed: |
553 | if (fbdev->lcdclk) { | ||
554 | clk_disable_unprepare(fbdev->lcdclk); | ||
555 | clk_put(fbdev->lcdclk); | ||
556 | } | ||
549 | if (fbdev->fb_mem) { | 557 | if (fbdev->fb_mem) { |
550 | dma_free_noncoherent(&dev->dev, fbdev->fb_len, fbdev->fb_mem, | 558 | dma_free_noncoherent(&dev->dev, fbdev->fb_len, fbdev->fb_mem, |
551 | fbdev->fb_phys); | 559 | fbdev->fb_phys); |
@@ -576,11 +584,15 @@ int au1100fb_drv_remove(struct platform_device *dev) | |||
576 | 584 | ||
577 | fb_dealloc_cmap(&fbdev->info.cmap); | 585 | fb_dealloc_cmap(&fbdev->info.cmap); |
578 | 586 | ||
587 | if (fbdev->lcdclk) { | ||
588 | clk_disable_unprepare(fbdev->lcdclk); | ||
589 | clk_put(fbdev->lcdclk); | ||
590 | } | ||
591 | |||
579 | return 0; | 592 | return 0; |
580 | } | 593 | } |
581 | 594 | ||
582 | #ifdef CONFIG_PM | 595 | #ifdef CONFIG_PM |
583 | static u32 sys_clksrc; | ||
584 | static struct au1100fb_regs fbregs; | 596 | static struct au1100fb_regs fbregs; |
585 | 597 | ||
586 | int au1100fb_drv_suspend(struct platform_device *dev, pm_message_t state) | 598 | int au1100fb_drv_suspend(struct platform_device *dev, pm_message_t state) |
@@ -590,14 +602,11 @@ int au1100fb_drv_suspend(struct platform_device *dev, pm_message_t state) | |||
590 | if (!fbdev) | 602 | if (!fbdev) |
591 | return 0; | 603 | return 0; |
592 | 604 | ||
593 | /* Save the clock source state */ | ||
594 | sys_clksrc = au_readl(SYS_CLKSRC); | ||
595 | |||
596 | /* Blank the LCD */ | 605 | /* Blank the LCD */ |
597 | au1100fb_fb_blank(VESA_POWERDOWN, &fbdev->info); | 606 | au1100fb_fb_blank(VESA_POWERDOWN, &fbdev->info); |
598 | 607 | ||
599 | /* Stop LCD clocking */ | 608 | if (fbdev->lcdclk) |
600 | au_writel(sys_clksrc & ~SYS_CS_ML_MASK, SYS_CLKSRC); | 609 | clk_disable(fbdev->lcdclk); |
601 | 610 | ||
602 | memcpy(&fbregs, fbdev->regs, sizeof(struct au1100fb_regs)); | 611 | memcpy(&fbregs, fbdev->regs, sizeof(struct au1100fb_regs)); |
603 | 612 | ||
@@ -613,8 +622,8 @@ int au1100fb_drv_resume(struct platform_device *dev) | |||
613 | 622 | ||
614 | memcpy(fbdev->regs, &fbregs, sizeof(struct au1100fb_regs)); | 623 | memcpy(fbdev->regs, &fbregs, sizeof(struct au1100fb_regs)); |
615 | 624 | ||
616 | /* Restart LCD clocking */ | 625 | if (fbdev->lcdclk) |
617 | au_writel(sys_clksrc, SYS_CLKSRC); | 626 | clk_enable(fbdev->lcdclk); |
618 | 627 | ||
619 | /* Unblank the LCD */ | 628 | /* Unblank the LCD */ |
620 | au1100fb_fb_blank(VESA_NO_BLANKING, &fbdev->info); | 629 | au1100fb_fb_blank(VESA_NO_BLANKING, &fbdev->info); |
diff --git a/drivers/video/fbdev/au1100fb.h b/drivers/video/fbdev/au1100fb.h index 12d9642d5465..9af19939a9c6 100644 --- a/drivers/video/fbdev/au1100fb.h +++ b/drivers/video/fbdev/au1100fb.h | |||
@@ -109,6 +109,7 @@ struct au1100fb_device { | |||
109 | size_t fb_len; | 109 | size_t fb_len; |
110 | dma_addr_t fb_phys; | 110 | dma_addr_t fb_phys; |
111 | int panel_idx; | 111 | int panel_idx; |
112 | struct clk *lcdclk; | ||
112 | }; | 113 | }; |
113 | 114 | ||
114 | /********************************************************************/ | 115 | /********************************************************************/ |
diff --git a/drivers/video/fbdev/au1200fb.c b/drivers/video/fbdev/au1200fb.c index 4cfba78a1458..40494dbdf519 100644 --- a/drivers/video/fbdev/au1200fb.c +++ b/drivers/video/fbdev/au1200fb.c | |||
@@ -30,6 +30,7 @@ | |||
30 | * 675 Mass Ave, Cambridge, MA 02139, USA. | 30 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
31 | */ | 31 | */ |
32 | 32 | ||
33 | #include <linux/clk.h> | ||
33 | #include <linux/module.h> | 34 | #include <linux/module.h> |
34 | #include <linux/platform_device.h> | 35 | #include <linux/platform_device.h> |
35 | #include <linux/kernel.h> | 36 | #include <linux/kernel.h> |
@@ -330,9 +331,8 @@ struct panel_settings | |||
330 | uint32 mode_pwmhi; | 331 | uint32 mode_pwmhi; |
331 | uint32 mode_outmask; | 332 | uint32 mode_outmask; |
332 | uint32 mode_fifoctrl; | 333 | uint32 mode_fifoctrl; |
333 | uint32 mode_toyclksrc; | ||
334 | uint32 mode_backlight; | 334 | uint32 mode_backlight; |
335 | uint32 mode_auxpll; | 335 | uint32 lcdclk; |
336 | #define Xres min_xres | 336 | #define Xres min_xres |
337 | #define Yres min_yres | 337 | #define Yres min_yres |
338 | u32 min_xres; /* Minimum horizontal resolution */ | 338 | u32 min_xres; /* Minimum horizontal resolution */ |
@@ -379,9 +379,8 @@ static struct panel_settings known_lcd_panels[] = | |||
379 | .mode_pwmhi = 0x00000000, | 379 | .mode_pwmhi = 0x00000000, |
380 | .mode_outmask = 0x00FFFFFF, | 380 | .mode_outmask = 0x00FFFFFF, |
381 | .mode_fifoctrl = 0x2f2f2f2f, | 381 | .mode_fifoctrl = 0x2f2f2f2f, |
382 | .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ | ||
383 | .mode_backlight = 0x00000000, | 382 | .mode_backlight = 0x00000000, |
384 | .mode_auxpll = 8, /* 96MHz AUXPLL */ | 383 | .lcdclk = 96, |
385 | 320, 320, | 384 | 320, 320, |
386 | 240, 240, | 385 | 240, 240, |
387 | }, | 386 | }, |
@@ -407,9 +406,8 @@ static struct panel_settings known_lcd_panels[] = | |||
407 | .mode_pwmhi = 0x00000000, | 406 | .mode_pwmhi = 0x00000000, |
408 | .mode_outmask = 0x00FFFFFF, | 407 | .mode_outmask = 0x00FFFFFF, |
409 | .mode_fifoctrl = 0x2f2f2f2f, | 408 | .mode_fifoctrl = 0x2f2f2f2f, |
410 | .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ | ||
411 | .mode_backlight = 0x00000000, | 409 | .mode_backlight = 0x00000000, |
412 | .mode_auxpll = 8, /* 96MHz AUXPLL */ | 410 | .lcdclk = 96, |
413 | 640, 480, | 411 | 640, 480, |
414 | 640, 480, | 412 | 640, 480, |
415 | }, | 413 | }, |
@@ -435,9 +433,8 @@ static struct panel_settings known_lcd_panels[] = | |||
435 | .mode_pwmhi = 0x00000000, | 433 | .mode_pwmhi = 0x00000000, |
436 | .mode_outmask = 0x00FFFFFF, | 434 | .mode_outmask = 0x00FFFFFF, |
437 | .mode_fifoctrl = 0x2f2f2f2f, | 435 | .mode_fifoctrl = 0x2f2f2f2f, |
438 | .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ | ||
439 | .mode_backlight = 0x00000000, | 436 | .mode_backlight = 0x00000000, |
440 | .mode_auxpll = 8, /* 96MHz AUXPLL */ | 437 | .lcdclk = 96, |
441 | 800, 800, | 438 | 800, 800, |
442 | 600, 600, | 439 | 600, 600, |
443 | }, | 440 | }, |
@@ -463,9 +460,8 @@ static struct panel_settings known_lcd_panels[] = | |||
463 | .mode_pwmhi = 0x00000000, | 460 | .mode_pwmhi = 0x00000000, |
464 | .mode_outmask = 0x00FFFFFF, | 461 | .mode_outmask = 0x00FFFFFF, |
465 | .mode_fifoctrl = 0x2f2f2f2f, | 462 | .mode_fifoctrl = 0x2f2f2f2f, |
466 | .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ | ||
467 | .mode_backlight = 0x00000000, | 463 | .mode_backlight = 0x00000000, |
468 | .mode_auxpll = 6, /* 72MHz AUXPLL */ | 464 | .lcdclk = 72, |
469 | 1024, 1024, | 465 | 1024, 1024, |
470 | 768, 768, | 466 | 768, 768, |
471 | }, | 467 | }, |
@@ -491,9 +487,8 @@ static struct panel_settings known_lcd_panels[] = | |||
491 | .mode_pwmhi = 0x00000000, | 487 | .mode_pwmhi = 0x00000000, |
492 | .mode_outmask = 0x00FFFFFF, | 488 | .mode_outmask = 0x00FFFFFF, |
493 | .mode_fifoctrl = 0x2f2f2f2f, | 489 | .mode_fifoctrl = 0x2f2f2f2f, |
494 | .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ | ||
495 | .mode_backlight = 0x00000000, | 490 | .mode_backlight = 0x00000000, |
496 | .mode_auxpll = 10, /* 120MHz AUXPLL */ | 491 | .lcdclk = 120, |
497 | 1280, 1280, | 492 | 1280, 1280, |
498 | 1024, 1024, | 493 | 1024, 1024, |
499 | }, | 494 | }, |
@@ -519,9 +514,8 @@ static struct panel_settings known_lcd_panels[] = | |||
519 | .mode_pwmhi = 0x03400000, /* SCB 0x0 */ | 514 | .mode_pwmhi = 0x03400000, /* SCB 0x0 */ |
520 | .mode_outmask = 0x00FFFFFF, | 515 | .mode_outmask = 0x00FFFFFF, |
521 | .mode_fifoctrl = 0x2f2f2f2f, | 516 | .mode_fifoctrl = 0x2f2f2f2f, |
522 | .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ | ||
523 | .mode_backlight = 0x00000000, | 517 | .mode_backlight = 0x00000000, |
524 | .mode_auxpll = 8, /* 96MHz AUXPLL */ | 518 | .lcdclk = 96, |
525 | 1024, 1024, | 519 | 1024, 1024, |
526 | 768, 768, | 520 | 768, 768, |
527 | }, | 521 | }, |
@@ -550,9 +544,8 @@ static struct panel_settings known_lcd_panels[] = | |||
550 | .mode_pwmhi = 0x03400000, | 544 | .mode_pwmhi = 0x03400000, |
551 | .mode_outmask = 0x00fcfcfc, | 545 | .mode_outmask = 0x00fcfcfc, |
552 | .mode_fifoctrl = 0x2f2f2f2f, | 546 | .mode_fifoctrl = 0x2f2f2f2f, |
553 | .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ | ||
554 | .mode_backlight = 0x00000000, | 547 | .mode_backlight = 0x00000000, |
555 | .mode_auxpll = 8, /* 96MHz AUXPLL */ | 548 | .lcdclk = 96, |
556 | 640, 480, | 549 | 640, 480, |
557 | 640, 480, | 550 | 640, 480, |
558 | }, | 551 | }, |
@@ -581,9 +574,8 @@ static struct panel_settings known_lcd_panels[] = | |||
581 | .mode_pwmhi = 0x03400000, | 574 | .mode_pwmhi = 0x03400000, |
582 | .mode_outmask = 0x00fcfcfc, | 575 | .mode_outmask = 0x00fcfcfc, |
583 | .mode_fifoctrl = 0x2f2f2f2f, | 576 | .mode_fifoctrl = 0x2f2f2f2f, |
584 | .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ | ||
585 | .mode_backlight = 0x00000000, | 577 | .mode_backlight = 0x00000000, |
586 | .mode_auxpll = 8, /* 96MHz AUXPLL */ | 578 | .lcdclk = 96, /* 96MHz AUXPLL */ |
587 | 320, 320, | 579 | 320, 320, |
588 | 240, 240, | 580 | 240, 240, |
589 | }, | 581 | }, |
@@ -612,9 +604,8 @@ static struct panel_settings known_lcd_panels[] = | |||
612 | .mode_pwmhi = 0x03400000, | 604 | .mode_pwmhi = 0x03400000, |
613 | .mode_outmask = 0x00fcfcfc, | 605 | .mode_outmask = 0x00fcfcfc, |
614 | .mode_fifoctrl = 0x2f2f2f2f, | 606 | .mode_fifoctrl = 0x2f2f2f2f, |
615 | .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ | ||
616 | .mode_backlight = 0x00000000, | 607 | .mode_backlight = 0x00000000, |
617 | .mode_auxpll = 8, /* 96MHz AUXPLL */ | 608 | .lcdclk = 96, |
618 | 856, 856, | 609 | 856, 856, |
619 | 480, 480, | 610 | 480, 480, |
620 | }, | 611 | }, |
@@ -646,9 +637,8 @@ static struct panel_settings known_lcd_panels[] = | |||
646 | .mode_pwmhi = 0x00000000, | 637 | .mode_pwmhi = 0x00000000, |
647 | .mode_outmask = 0x00FFFFFF, | 638 | .mode_outmask = 0x00FFFFFF, |
648 | .mode_fifoctrl = 0x2f2f2f2f, | 639 | .mode_fifoctrl = 0x2f2f2f2f, |
649 | .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ | ||
650 | .mode_backlight = 0x00000000, | 640 | .mode_backlight = 0x00000000, |
651 | .mode_auxpll = (48/12) * 2, | 641 | .lcdclk = 96, |
652 | 800, 800, | 642 | 800, 800, |
653 | 480, 480, | 643 | 480, 480, |
654 | }, | 644 | }, |
@@ -764,7 +754,7 @@ static int au1200_setlocation (struct au1200fb_device *fbdev, int plane, | |||
764 | 754 | ||
765 | /* Disable the window while making changes, then restore WINEN */ | 755 | /* Disable the window while making changes, then restore WINEN */ |
766 | winenable = lcd->winenable & (1 << plane); | 756 | winenable = lcd->winenable & (1 << plane); |
767 | au_sync(); | 757 | wmb(); /* drain writebuffer */ |
768 | lcd->winenable &= ~(1 << plane); | 758 | lcd->winenable &= ~(1 << plane); |
769 | lcd->window[plane].winctrl0 = winctrl0; | 759 | lcd->window[plane].winctrl0 = winctrl0; |
770 | lcd->window[plane].winctrl1 = winctrl1; | 760 | lcd->window[plane].winctrl1 = winctrl1; |
@@ -772,7 +762,7 @@ static int au1200_setlocation (struct au1200fb_device *fbdev, int plane, | |||
772 | lcd->window[plane].winbuf1 = fbdev->fb_phys; | 762 | lcd->window[plane].winbuf1 = fbdev->fb_phys; |
773 | lcd->window[plane].winbufctrl = 0; /* select winbuf0 */ | 763 | lcd->window[plane].winbufctrl = 0; /* select winbuf0 */ |
774 | lcd->winenable |= winenable; | 764 | lcd->winenable |= winenable; |
775 | au_sync(); | 765 | wmb(); /* drain writebuffer */ |
776 | 766 | ||
777 | return 0; | 767 | return 0; |
778 | } | 768 | } |
@@ -788,22 +778,21 @@ static void au1200_setpanel(struct panel_settings *newpanel, | |||
788 | /* Make sure all windows disabled */ | 778 | /* Make sure all windows disabled */ |
789 | winenable = lcd->winenable; | 779 | winenable = lcd->winenable; |
790 | lcd->winenable = 0; | 780 | lcd->winenable = 0; |
791 | au_sync(); | 781 | wmb(); /* drain writebuffer */ |
792 | /* | 782 | /* |
793 | * Ensure everything is disabled before reconfiguring | 783 | * Ensure everything is disabled before reconfiguring |
794 | */ | 784 | */ |
795 | if (lcd->screen & LCD_SCREEN_SEN) { | 785 | if (lcd->screen & LCD_SCREEN_SEN) { |
796 | /* Wait for vertical sync period */ | 786 | /* Wait for vertical sync period */ |
797 | lcd->intstatus = LCD_INT_SS; | 787 | lcd->intstatus = LCD_INT_SS; |
798 | while ((lcd->intstatus & LCD_INT_SS) == 0) { | 788 | while ((lcd->intstatus & LCD_INT_SS) == 0) |
799 | au_sync(); | 789 | ; |
800 | } | ||
801 | 790 | ||
802 | lcd->screen &= ~LCD_SCREEN_SEN; /*disable the controller*/ | 791 | lcd->screen &= ~LCD_SCREEN_SEN; /*disable the controller*/ |
803 | 792 | ||
804 | do { | 793 | do { |
805 | lcd->intstatus = lcd->intstatus; /*clear interrupts*/ | 794 | lcd->intstatus = lcd->intstatus; /*clear interrupts*/ |
806 | au_sync(); | 795 | wmb(); /* drain writebuffer */ |
807 | /*wait for controller to shut down*/ | 796 | /*wait for controller to shut down*/ |
808 | } while ((lcd->intstatus & LCD_INT_SD) == 0); | 797 | } while ((lcd->intstatus & LCD_INT_SD) == 0); |
809 | 798 | ||
@@ -829,11 +818,17 @@ static void au1200_setpanel(struct panel_settings *newpanel, | |||
829 | */ | 818 | */ |
830 | if (!(panel->mode_clkcontrol & LCD_CLKCONTROL_EXT)) | 819 | if (!(panel->mode_clkcontrol & LCD_CLKCONTROL_EXT)) |
831 | { | 820 | { |
832 | uint32 sys_clksrc; | 821 | struct clk *c = clk_get(NULL, "lcd_intclk"); |
833 | au_writel(panel->mode_auxpll, SYS_AUXPLL); | 822 | long r, pc = panel->lcdclk * 1000000; |
834 | sys_clksrc = au_readl(SYS_CLKSRC) & ~0x0000001f; | 823 | |
835 | sys_clksrc |= panel->mode_toyclksrc; | 824 | if (!IS_ERR(c)) { |
836 | au_writel(sys_clksrc, SYS_CLKSRC); | 825 | r = clk_round_rate(c, pc); |
826 | if ((pc - r) < (pc / 10)) { /* 10% slack */ | ||
827 | clk_set_rate(c, r); | ||
828 | clk_prepare_enable(c); | ||
829 | } | ||
830 | clk_put(c); | ||
831 | } | ||
837 | } | 832 | } |
838 | 833 | ||
839 | /* | 834 | /* |
@@ -847,7 +842,7 @@ static void au1200_setpanel(struct panel_settings *newpanel, | |||
847 | lcd->pwmhi = panel->mode_pwmhi; | 842 | lcd->pwmhi = panel->mode_pwmhi; |
848 | lcd->outmask = panel->mode_outmask; | 843 | lcd->outmask = panel->mode_outmask; |
849 | lcd->fifoctrl = panel->mode_fifoctrl; | 844 | lcd->fifoctrl = panel->mode_fifoctrl; |
850 | au_sync(); | 845 | wmb(); /* drain writebuffer */ |
851 | 846 | ||
852 | /* fixme: Check window settings to make sure still valid | 847 | /* fixme: Check window settings to make sure still valid |
853 | * for new geometry */ | 848 | * for new geometry */ |
@@ -863,7 +858,7 @@ static void au1200_setpanel(struct panel_settings *newpanel, | |||
863 | * Re-enable screen now that it is configured | 858 | * Re-enable screen now that it is configured |
864 | */ | 859 | */ |
865 | lcd->screen |= LCD_SCREEN_SEN; | 860 | lcd->screen |= LCD_SCREEN_SEN; |
866 | au_sync(); | 861 | wmb(); /* drain writebuffer */ |
867 | 862 | ||
868 | /* Call init of panel */ | 863 | /* Call init of panel */ |
869 | if (pd->panel_init) | 864 | if (pd->panel_init) |
@@ -956,7 +951,7 @@ static void au1200_setmode(struct au1200fb_device *fbdev) | |||
956 | | LCD_WINCTRL2_SCY_1 | 951 | | LCD_WINCTRL2_SCY_1 |
957 | ) ; | 952 | ) ; |
958 | lcd->winenable |= win->w[plane].mode_winenable; | 953 | lcd->winenable |= win->w[plane].mode_winenable; |
959 | au_sync(); | 954 | wmb(); /* drain writebuffer */ |
960 | } | 955 | } |
961 | 956 | ||
962 | 957 | ||
@@ -1270,7 +1265,7 @@ static void set_global(u_int cmd, struct au1200_lcd_global_regs_t *pdata) | |||
1270 | 1265 | ||
1271 | if (pdata->flags & SCREEN_MASK) | 1266 | if (pdata->flags & SCREEN_MASK) |
1272 | lcd->colorkeymsk = pdata->mask; | 1267 | lcd->colorkeymsk = pdata->mask; |
1273 | au_sync(); | 1268 | wmb(); /* drain writebuffer */ |
1274 | } | 1269 | } |
1275 | 1270 | ||
1276 | static void get_global(u_int cmd, struct au1200_lcd_global_regs_t *pdata) | 1271 | static void get_global(u_int cmd, struct au1200_lcd_global_regs_t *pdata) |
@@ -1288,7 +1283,7 @@ static void get_global(u_int cmd, struct au1200_lcd_global_regs_t *pdata) | |||
1288 | hi1 = (lcd->pwmhi >> 16) + 1; | 1283 | hi1 = (lcd->pwmhi >> 16) + 1; |
1289 | divider = (lcd->pwmdiv & 0x3FFFF) + 1; | 1284 | divider = (lcd->pwmdiv & 0x3FFFF) + 1; |
1290 | pdata->brightness = ((hi1 << 8) / divider) - 1; | 1285 | pdata->brightness = ((hi1 << 8) / divider) - 1; |
1291 | au_sync(); | 1286 | wmb(); /* drain writebuffer */ |
1292 | } | 1287 | } |
1293 | 1288 | ||
1294 | static void set_window(unsigned int plane, | 1289 | static void set_window(unsigned int plane, |
@@ -1387,7 +1382,7 @@ static void set_window(unsigned int plane, | |||
1387 | val |= (pdata->enable & 1) << plane; | 1382 | val |= (pdata->enable & 1) << plane; |
1388 | lcd->winenable = val; | 1383 | lcd->winenable = val; |
1389 | } | 1384 | } |
1390 | au_sync(); | 1385 | wmb(); /* drain writebuffer */ |
1391 | } | 1386 | } |
1392 | 1387 | ||
1393 | static void get_window(unsigned int plane, | 1388 | static void get_window(unsigned int plane, |
@@ -1414,7 +1409,7 @@ static void get_window(unsigned int plane, | |||
1414 | pdata->ram_array_mode = (lcd->window[plane].winctrl2 & LCD_WINCTRL2_RAM) >> 21; | 1409 | pdata->ram_array_mode = (lcd->window[plane].winctrl2 & LCD_WINCTRL2_RAM) >> 21; |
1415 | 1410 | ||
1416 | pdata->enable = (lcd->winenable >> plane) & 1; | 1411 | pdata->enable = (lcd->winenable >> plane) & 1; |
1417 | au_sync(); | 1412 | wmb(); /* drain writebuffer */ |
1418 | } | 1413 | } |
1419 | 1414 | ||
1420 | static int au1200fb_ioctl(struct fb_info *info, unsigned int cmd, | 1415 | static int au1200fb_ioctl(struct fb_info *info, unsigned int cmd, |
@@ -1511,7 +1506,7 @@ static irqreturn_t au1200fb_handle_irq(int irq, void* dev_id) | |||
1511 | { | 1506 | { |
1512 | /* Nothing to do for now, just clear any pending interrupt */ | 1507 | /* Nothing to do for now, just clear any pending interrupt */ |
1513 | lcd->intstatus = lcd->intstatus; | 1508 | lcd->intstatus = lcd->intstatus; |
1514 | au_sync(); | 1509 | wmb(); /* drain writebuffer */ |
1515 | 1510 | ||
1516 | return IRQ_HANDLED; | 1511 | return IRQ_HANDLED; |
1517 | } | 1512 | } |
@@ -1809,7 +1804,7 @@ static int au1200fb_drv_suspend(struct device *dev) | |||
1809 | au1200_setpanel(NULL, pd); | 1804 | au1200_setpanel(NULL, pd); |
1810 | 1805 | ||
1811 | lcd->outmask = 0; | 1806 | lcd->outmask = 0; |
1812 | au_sync(); | 1807 | wmb(); /* drain writebuffer */ |
1813 | 1808 | ||
1814 | return 0; | 1809 | return 0; |
1815 | } | 1810 | } |
diff --git a/drivers/video/fbdev/clps711x-fb.c b/drivers/video/fbdev/clps711x-fb.c new file mode 100644 index 000000000000..49a7bb4ef02f --- /dev/null +++ b/drivers/video/fbdev/clps711x-fb.c | |||
@@ -0,0 +1,397 @@ | |||
1 | /* | ||
2 | * Cirrus Logic CLPS711X FB driver | ||
3 | * | ||
4 | * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> | ||
5 | * Based on driver by Russell King <rmk@arm.linux.org.uk> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | */ | ||
12 | |||
13 | #include <linux/clk.h> | ||
14 | #include <linux/fb.h> | ||
15 | #include <linux/io.h> | ||
16 | #include <linux/lcd.h> | ||
17 | #include <linux/module.h> | ||
18 | #include <linux/of.h> | ||
19 | #include <linux/platform_device.h> | ||
20 | #include <linux/regmap.h> | ||
21 | #include <linux/mfd/syscon.h> | ||
22 | #include <linux/mfd/syscon/clps711x.h> | ||
23 | #include <linux/regulator/consumer.h> | ||
24 | #include <video/of_display_timing.h> | ||
25 | |||
26 | #define CLPS711X_FB_NAME "clps711x-fb" | ||
27 | #define CLPS711X_FB_BPP_MAX (4) | ||
28 | |||
29 | /* Registers relative to LCDCON */ | ||
30 | #define CLPS711X_LCDCON (0x0000) | ||
31 | # define LCDCON_GSEN BIT(30) | ||
32 | # define LCDCON_GSMD BIT(31) | ||
33 | #define CLPS711X_PALLSW (0x0280) | ||
34 | #define CLPS711X_PALMSW (0x02c0) | ||
35 | #define CLPS711X_FBADDR (0x0d40) | ||
36 | |||
37 | struct clps711x_fb_info { | ||
38 | struct clk *clk; | ||
39 | void __iomem *base; | ||
40 | struct regmap *syscon; | ||
41 | resource_size_t buffsize; | ||
42 | struct fb_videomode mode; | ||
43 | struct regulator *lcd_pwr; | ||
44 | u32 ac_prescale; | ||
45 | bool cmap_invert; | ||
46 | }; | ||
47 | |||
48 | static int clps711x_fb_setcolreg(u_int regno, u_int red, u_int green, | ||
49 | u_int blue, u_int transp, struct fb_info *info) | ||
50 | { | ||
51 | struct clps711x_fb_info *cfb = info->par; | ||
52 | u32 level, mask, shift; | ||
53 | |||
54 | if (regno >= BIT(info->var.bits_per_pixel)) | ||
55 | return -EINVAL; | ||
56 | |||
57 | shift = 4 * (regno & 7); | ||
58 | mask = 0xf << shift; | ||
59 | /* gray = 0.30*R + 0.58*G + 0.11*B */ | ||
60 | level = (((red * 77 + green * 151 + blue * 28) >> 20) << shift) & mask; | ||
61 | if (cfb->cmap_invert) | ||
62 | level = 0xf - level; | ||
63 | |||
64 | regno = (regno < 8) ? CLPS711X_PALLSW : CLPS711X_PALMSW; | ||
65 | |||
66 | writel((readl(cfb->base + regno) & ~mask) | level, cfb->base + regno); | ||
67 | |||
68 | return 0; | ||
69 | } | ||
70 | |||
71 | static int clps711x_fb_check_var(struct fb_var_screeninfo *var, | ||
72 | struct fb_info *info) | ||
73 | { | ||
74 | u32 val; | ||
75 | |||
76 | if (var->bits_per_pixel < 1 || | ||
77 | var->bits_per_pixel > CLPS711X_FB_BPP_MAX) | ||
78 | return -EINVAL; | ||
79 | |||
80 | if (!var->pixclock) | ||
81 | return -EINVAL; | ||
82 | |||
83 | val = DIV_ROUND_UP(var->xres, 16) - 1; | ||
84 | if (val < 0x01 || val > 0x3f) | ||
85 | return -EINVAL; | ||
86 | |||
87 | val = DIV_ROUND_UP(var->yres * var->xres * var->bits_per_pixel, 128); | ||
88 | val--; | ||
89 | if (val < 0x001 || val > 0x1fff) | ||
90 | return -EINVAL; | ||
91 | |||
92 | var->transp.msb_right = 0; | ||
93 | var->transp.offset = 0; | ||
94 | var->transp.length = 0; | ||
95 | var->red.msb_right = 0; | ||
96 | var->red.offset = 0; | ||
97 | var->red.length = var->bits_per_pixel; | ||
98 | var->green = var->red; | ||
99 | var->blue = var->red; | ||
100 | var->grayscale = var->bits_per_pixel > 1; | ||
101 | |||
102 | return 0; | ||
103 | } | ||
104 | |||
105 | static int clps711x_fb_set_par(struct fb_info *info) | ||
106 | { | ||
107 | struct clps711x_fb_info *cfb = info->par; | ||
108 | resource_size_t size; | ||
109 | u32 lcdcon, pps; | ||
110 | |||
111 | size = (info->var.xres * info->var.yres * info->var.bits_per_pixel) / 8; | ||
112 | if (size > cfb->buffsize) | ||
113 | return -EINVAL; | ||
114 | |||
115 | switch (info->var.bits_per_pixel) { | ||
116 | case 1: | ||
117 | info->fix.visual = FB_VISUAL_MONO01; | ||
118 | break; | ||
119 | case 2: | ||
120 | case 4: | ||
121 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; | ||
122 | break; | ||
123 | default: | ||
124 | return -EINVAL; | ||
125 | } | ||
126 | |||
127 | info->fix.line_length = info->var.xres * info->var.bits_per_pixel / 8; | ||
128 | info->fix.smem_len = size; | ||
129 | |||
130 | lcdcon = (info->var.xres * info->var.yres * | ||
131 | info->var.bits_per_pixel) / 128 - 1; | ||
132 | lcdcon |= ((info->var.xres / 16) - 1) << 13; | ||
133 | lcdcon |= (cfb->ac_prescale & 0x1f) << 25; | ||
134 | |||
135 | pps = clk_get_rate(cfb->clk) / (PICOS2KHZ(info->var.pixclock) * 1000); | ||
136 | if (pps) | ||
137 | pps--; | ||
138 | lcdcon |= (pps & 0x3f) << 19; | ||
139 | |||
140 | if (info->var.bits_per_pixel == 4) | ||
141 | lcdcon |= LCDCON_GSMD; | ||
142 | if (info->var.bits_per_pixel >= 2) | ||
143 | lcdcon |= LCDCON_GSEN; | ||
144 | |||
145 | /* LCDCON must only be changed while the LCD is disabled */ | ||
146 | regmap_update_bits(cfb->syscon, SYSCON_OFFSET, SYSCON1_LCDEN, 0); | ||
147 | writel(lcdcon, cfb->base + CLPS711X_LCDCON); | ||
148 | regmap_update_bits(cfb->syscon, SYSCON_OFFSET, | ||
149 | SYSCON1_LCDEN, SYSCON1_LCDEN); | ||
150 | |||
151 | return 0; | ||
152 | } | ||
153 | |||
154 | static int clps711x_fb_blank(int blank, struct fb_info *info) | ||
155 | { | ||
156 | /* Return happy */ | ||
157 | return 0; | ||
158 | } | ||
159 | |||
160 | static struct fb_ops clps711x_fb_ops = { | ||
161 | .owner = THIS_MODULE, | ||
162 | .fb_setcolreg = clps711x_fb_setcolreg, | ||
163 | .fb_check_var = clps711x_fb_check_var, | ||
164 | .fb_set_par = clps711x_fb_set_par, | ||
165 | .fb_blank = clps711x_fb_blank, | ||
166 | .fb_fillrect = sys_fillrect, | ||
167 | .fb_copyarea = sys_copyarea, | ||
168 | .fb_imageblit = sys_imageblit, | ||
169 | }; | ||
170 | |||
171 | static int clps711x_lcd_check_fb(struct lcd_device *lcddev, struct fb_info *fi) | ||
172 | { | ||
173 | struct clps711x_fb_info *cfb = dev_get_drvdata(&lcddev->dev); | ||
174 | |||
175 | return (!fi || fi->par == cfb) ? 1 : 0; | ||
176 | } | ||
177 | |||
178 | static int clps711x_lcd_get_power(struct lcd_device *lcddev) | ||
179 | { | ||
180 | struct clps711x_fb_info *cfb = dev_get_drvdata(&lcddev->dev); | ||
181 | |||
182 | if (!IS_ERR_OR_NULL(cfb->lcd_pwr)) | ||
183 | if (!regulator_is_enabled(cfb->lcd_pwr)) | ||
184 | return FB_BLANK_NORMAL; | ||
185 | |||
186 | return FB_BLANK_UNBLANK; | ||
187 | } | ||
188 | |||
189 | static int clps711x_lcd_set_power(struct lcd_device *lcddev, int blank) | ||
190 | { | ||
191 | struct clps711x_fb_info *cfb = dev_get_drvdata(&lcddev->dev); | ||
192 | |||
193 | if (!IS_ERR_OR_NULL(cfb->lcd_pwr)) { | ||
194 | if (blank == FB_BLANK_UNBLANK) { | ||
195 | if (!regulator_is_enabled(cfb->lcd_pwr)) | ||
196 | return regulator_enable(cfb->lcd_pwr); | ||
197 | } else { | ||
198 | if (regulator_is_enabled(cfb->lcd_pwr)) | ||
199 | return regulator_disable(cfb->lcd_pwr); | ||
200 | } | ||
201 | } | ||
202 | |||
203 | return 0; | ||
204 | } | ||
205 | |||
206 | static struct lcd_ops clps711x_lcd_ops = { | ||
207 | .check_fb = clps711x_lcd_check_fb, | ||
208 | .get_power = clps711x_lcd_get_power, | ||
209 | .set_power = clps711x_lcd_set_power, | ||
210 | }; | ||
211 | |||
212 | static int clps711x_fb_probe(struct platform_device *pdev) | ||
213 | { | ||
214 | struct device *dev = &pdev->dev; | ||
215 | struct device_node *disp, *np = dev->of_node; | ||
216 | struct clps711x_fb_info *cfb; | ||
217 | struct lcd_device *lcd; | ||
218 | struct fb_info *info; | ||
219 | struct resource *res; | ||
220 | int ret = -ENOENT; | ||
221 | u32 val; | ||
222 | |||
223 | if (fb_get_options(CLPS711X_FB_NAME, NULL)) | ||
224 | return -ENODEV; | ||
225 | |||
226 | info = framebuffer_alloc(sizeof(*cfb), dev); | ||
227 | if (!info) | ||
228 | return -ENOMEM; | ||
229 | |||
230 | cfb = info->par; | ||
231 | platform_set_drvdata(pdev, info); | ||
232 | |||
233 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
234 | if (!res) | ||
235 | goto out_fb_release; | ||
236 | cfb->base = devm_ioremap(dev, res->start, resource_size(res)); | ||
237 | if (!cfb->base) { | ||
238 | ret = -ENOMEM; | ||
239 | goto out_fb_release; | ||
240 | } | ||
241 | |||
242 | info->fix.mmio_start = res->start; | ||
243 | info->fix.mmio_len = resource_size(res); | ||
244 | |||
245 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | ||
246 | info->screen_base = devm_ioremap_resource(dev, res); | ||
247 | if (IS_ERR(info->screen_base)) { | ||
248 | ret = PTR_ERR(info->screen_base); | ||
249 | goto out_fb_release; | ||
250 | } | ||
251 | |||
252 | /* Physical address should be aligned to 256 MiB */ | ||
253 | if (res->start & 0x0fffffff) { | ||
254 | ret = -EINVAL; | ||
255 | goto out_fb_release; | ||
256 | } | ||
257 | |||
258 | info->apertures = alloc_apertures(1); | ||
259 | if (!info->apertures) { | ||
260 | ret = -ENOMEM; | ||
261 | goto out_fb_release; | ||
262 | } | ||
263 | |||
264 | cfb->buffsize = resource_size(res); | ||
265 | info->fix.smem_start = res->start; | ||
266 | info->apertures->ranges[0].base = info->fix.smem_start; | ||
267 | info->apertures->ranges[0].size = cfb->buffsize; | ||
268 | |||
269 | cfb->clk = devm_clk_get(dev, NULL); | ||
270 | if (IS_ERR(cfb->clk)) { | ||
271 | ret = PTR_ERR(cfb->clk); | ||
272 | goto out_fb_release; | ||
273 | } | ||
274 | |||
275 | cfb->syscon = | ||
276 | syscon_regmap_lookup_by_compatible("cirrus,clps711x-syscon1"); | ||
277 | if (IS_ERR(cfb->syscon)) { | ||
278 | ret = PTR_ERR(cfb->syscon); | ||
279 | goto out_fb_release; | ||
280 | } | ||
281 | |||
282 | disp = of_parse_phandle(np, "display", 0); | ||
283 | if (!disp) { | ||
284 | dev_err(&pdev->dev, "No display defined\n"); | ||
285 | ret = -ENODATA; | ||
286 | goto out_fb_release; | ||
287 | } | ||
288 | |||
289 | ret = of_get_fb_videomode(disp, &cfb->mode, OF_USE_NATIVE_MODE); | ||
290 | if (ret) | ||
291 | goto out_fb_release; | ||
292 | |||
293 | of_property_read_u32(disp, "ac-prescale", &cfb->ac_prescale); | ||
294 | cfb->cmap_invert = of_property_read_bool(disp, "cmap-invert"); | ||
295 | |||
296 | ret = of_property_read_u32(disp, "bits-per-pixel", | ||
297 | &info->var.bits_per_pixel); | ||
298 | if (ret) | ||
299 | goto out_fb_release; | ||
300 | |||
301 | /* Force disable LCD on any mismatch */ | ||
302 | if (info->fix.smem_start != (readb(cfb->base + CLPS711X_FBADDR) << 28)) | ||
303 | regmap_update_bits(cfb->syscon, SYSCON_OFFSET, | ||
304 | SYSCON1_LCDEN, 0); | ||
305 | |||
306 | ret = regmap_read(cfb->syscon, SYSCON_OFFSET, &val); | ||
307 | if (ret) | ||
308 | goto out_fb_release; | ||
309 | |||
310 | if (!(val & SYSCON1_LCDEN)) { | ||
311 | /* Setup start FB address */ | ||
312 | writeb(info->fix.smem_start >> 28, cfb->base + CLPS711X_FBADDR); | ||
313 | /* Clean FB memory */ | ||
314 | memset_io(info->screen_base, 0, cfb->buffsize); | ||
315 | } | ||
316 | |||
317 | cfb->lcd_pwr = devm_regulator_get(dev, "lcd"); | ||
318 | if (PTR_ERR(cfb->lcd_pwr) == -EPROBE_DEFER) { | ||
319 | ret = -EPROBE_DEFER; | ||
320 | goto out_fb_release; | ||
321 | } | ||
322 | |||
323 | info->fbops = &clps711x_fb_ops; | ||
324 | info->flags = FBINFO_DEFAULT; | ||
325 | info->var.activate = FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW; | ||
326 | info->var.height = -1; | ||
327 | info->var.width = -1; | ||
328 | info->var.vmode = FB_VMODE_NONINTERLACED; | ||
329 | info->fix.type = FB_TYPE_PACKED_PIXELS; | ||
330 | info->fix.accel = FB_ACCEL_NONE; | ||
331 | strlcpy(info->fix.id, CLPS711X_FB_NAME, sizeof(info->fix.id)); | ||
332 | fb_videomode_to_var(&info->var, &cfb->mode); | ||
333 | |||
334 | ret = fb_alloc_cmap(&info->cmap, BIT(CLPS711X_FB_BPP_MAX), 0); | ||
335 | if (ret) | ||
336 | goto out_fb_release; | ||
337 | |||
338 | ret = fb_set_var(info, &info->var); | ||
339 | if (ret) | ||
340 | goto out_fb_dealloc_cmap; | ||
341 | |||
342 | ret = register_framebuffer(info); | ||
343 | if (ret) | ||
344 | goto out_fb_dealloc_cmap; | ||
345 | |||
346 | lcd = devm_lcd_device_register(dev, "clps711x-lcd", dev, cfb, | ||
347 | &clps711x_lcd_ops); | ||
348 | if (!IS_ERR(lcd)) | ||
349 | return 0; | ||
350 | |||
351 | ret = PTR_ERR(lcd); | ||
352 | unregister_framebuffer(info); | ||
353 | |||
354 | out_fb_dealloc_cmap: | ||
355 | regmap_update_bits(cfb->syscon, SYSCON_OFFSET, SYSCON1_LCDEN, 0); | ||
356 | fb_dealloc_cmap(&info->cmap); | ||
357 | |||
358 | out_fb_release: | ||
359 | framebuffer_release(info); | ||
360 | |||
361 | return ret; | ||
362 | } | ||
363 | |||
364 | static int clps711x_fb_remove(struct platform_device *pdev) | ||
365 | { | ||
366 | struct fb_info *info = platform_get_drvdata(pdev); | ||
367 | struct clps711x_fb_info *cfb = info->par; | ||
368 | |||
369 | regmap_update_bits(cfb->syscon, SYSCON_OFFSET, SYSCON1_LCDEN, 0); | ||
370 | |||
371 | unregister_framebuffer(info); | ||
372 | fb_dealloc_cmap(&info->cmap); | ||
373 | framebuffer_release(info); | ||
374 | |||
375 | return 0; | ||
376 | } | ||
377 | |||
378 | static const struct of_device_id clps711x_fb_dt_ids[] = { | ||
379 | { .compatible = "cirrus,clps711x-fb", }, | ||
380 | { } | ||
381 | }; | ||
382 | MODULE_DEVICE_TABLE(of, clps711x_fb_dt_ids); | ||
383 | |||
384 | static struct platform_driver clps711x_fb_driver = { | ||
385 | .driver = { | ||
386 | .name = CLPS711X_FB_NAME, | ||
387 | .owner = THIS_MODULE, | ||
388 | .of_match_table = clps711x_fb_dt_ids, | ||
389 | }, | ||
390 | .probe = clps711x_fb_probe, | ||
391 | .remove = clps711x_fb_remove, | ||
392 | }; | ||
393 | module_platform_driver(clps711x_fb_driver); | ||
394 | |||
395 | MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); | ||
396 | MODULE_DESCRIPTION("Cirrus Logic CLPS711X FB driver"); | ||
397 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/video/fbdev/da8xx-fb.c b/drivers/video/fbdev/da8xx-fb.c index a8484f768d04..788f6b37fce7 100644 --- a/drivers/video/fbdev/da8xx-fb.c +++ b/drivers/video/fbdev/da8xx-fb.c | |||
@@ -1447,18 +1447,15 @@ static int fb_probe(struct platform_device *device) | |||
1447 | da8xx_fb_fix.line_length - 1; | 1447 | da8xx_fb_fix.line_length - 1; |
1448 | 1448 | ||
1449 | /* allocate palette buffer */ | 1449 | /* allocate palette buffer */ |
1450 | par->v_palette_base = dma_alloc_coherent(NULL, | 1450 | par->v_palette_base = dma_zalloc_coherent(NULL, PALETTE_SIZE, |
1451 | PALETTE_SIZE, | 1451 | (resource_size_t *)&par->p_palette_base, |
1452 | (resource_size_t *) | 1452 | GFP_KERNEL | GFP_DMA); |
1453 | &par->p_palette_base, | ||
1454 | GFP_KERNEL | GFP_DMA); | ||
1455 | if (!par->v_palette_base) { | 1453 | if (!par->v_palette_base) { |
1456 | dev_err(&device->dev, | 1454 | dev_err(&device->dev, |
1457 | "GLCD: kmalloc for palette buffer failed\n"); | 1455 | "GLCD: kmalloc for palette buffer failed\n"); |
1458 | ret = -EINVAL; | 1456 | ret = -EINVAL; |
1459 | goto err_release_fb_mem; | 1457 | goto err_release_fb_mem; |
1460 | } | 1458 | } |
1461 | memset(par->v_palette_base, 0, PALETTE_SIZE); | ||
1462 | 1459 | ||
1463 | par->irq = platform_get_irq(device, 0); | 1460 | par->irq = platform_get_irq(device, 0); |
1464 | if (par->irq < 0) { | 1461 | if (par->irq < 0) { |
diff --git a/drivers/video/fbdev/efifb.c b/drivers/video/fbdev/efifb.c index ae9618ff6735..982f6abe6faf 100644 --- a/drivers/video/fbdev/efifb.c +++ b/drivers/video/fbdev/efifb.c | |||
@@ -19,8 +19,6 @@ | |||
19 | 19 | ||
20 | static bool request_mem_succeeded = false; | 20 | static bool request_mem_succeeded = false; |
21 | 21 | ||
22 | static struct pci_dev *default_vga; | ||
23 | |||
24 | static struct fb_var_screeninfo efifb_defined = { | 22 | static struct fb_var_screeninfo efifb_defined = { |
25 | .activate = FB_ACTIVATE_NOW, | 23 | .activate = FB_ACTIVATE_NOW, |
26 | .height = -1, | 24 | .height = -1, |
@@ -84,23 +82,10 @@ static struct fb_ops efifb_ops = { | |||
84 | .fb_imageblit = cfb_imageblit, | 82 | .fb_imageblit = cfb_imageblit, |
85 | }; | 83 | }; |
86 | 84 | ||
87 | struct pci_dev *vga_default_device(void) | ||
88 | { | ||
89 | return default_vga; | ||
90 | } | ||
91 | |||
92 | EXPORT_SYMBOL_GPL(vga_default_device); | ||
93 | |||
94 | void vga_set_default_device(struct pci_dev *pdev) | ||
95 | { | ||
96 | default_vga = pdev; | ||
97 | } | ||
98 | |||
99 | static int efifb_setup(char *options) | 85 | static int efifb_setup(char *options) |
100 | { | 86 | { |
101 | char *this_opt; | 87 | char *this_opt; |
102 | int i; | 88 | int i; |
103 | struct pci_dev *dev = NULL; | ||
104 | 89 | ||
105 | if (options && *options) { | 90 | if (options && *options) { |
106 | while ((this_opt = strsep(&options, ",")) != NULL) { | 91 | while ((this_opt = strsep(&options, ",")) != NULL) { |
@@ -126,30 +111,6 @@ static int efifb_setup(char *options) | |||
126 | } | 111 | } |
127 | } | 112 | } |
128 | 113 | ||
129 | for_each_pci_dev(dev) { | ||
130 | int i; | ||
131 | |||
132 | if ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) | ||
133 | continue; | ||
134 | |||
135 | for (i=0; i < DEVICE_COUNT_RESOURCE; i++) { | ||
136 | resource_size_t start, end; | ||
137 | |||
138 | if (!(pci_resource_flags(dev, i) & IORESOURCE_MEM)) | ||
139 | continue; | ||
140 | |||
141 | start = pci_resource_start(dev, i); | ||
142 | end = pci_resource_end(dev, i); | ||
143 | |||
144 | if (!start || !end) | ||
145 | continue; | ||
146 | |||
147 | if (screen_info.lfb_base >= start && | ||
148 | (screen_info.lfb_base + screen_info.lfb_size) < end) | ||
149 | default_vga = dev; | ||
150 | } | ||
151 | } | ||
152 | |||
153 | return 0; | 114 | return 0; |
154 | } | 115 | } |
155 | 116 | ||
diff --git a/drivers/video/fbdev/exynos/s6e8ax0.c b/drivers/video/fbdev/exynos/s6e8ax0.c index 29e70ed3f154..95873f26e39c 100644 --- a/drivers/video/fbdev/exynos/s6e8ax0.c +++ b/drivers/video/fbdev/exynos/s6e8ax0.c | |||
@@ -704,11 +704,6 @@ static int s6e8ax0_get_power(struct lcd_device *ld) | |||
704 | return lcd->power; | 704 | return lcd->power; |
705 | } | 705 | } |
706 | 706 | ||
707 | static int s6e8ax0_get_brightness(struct backlight_device *bd) | ||
708 | { | ||
709 | return bd->props.brightness; | ||
710 | } | ||
711 | |||
712 | static int s6e8ax0_set_brightness(struct backlight_device *bd) | 707 | static int s6e8ax0_set_brightness(struct backlight_device *bd) |
713 | { | 708 | { |
714 | int ret = 0, brightness = bd->props.brightness; | 709 | int ret = 0, brightness = bd->props.brightness; |
@@ -736,7 +731,6 @@ static struct lcd_ops s6e8ax0_lcd_ops = { | |||
736 | }; | 731 | }; |
737 | 732 | ||
738 | static const struct backlight_ops s6e8ax0_backlight_ops = { | 733 | static const struct backlight_ops s6e8ax0_backlight_ops = { |
739 | .get_brightness = s6e8ax0_get_brightness, | ||
740 | .update_status = s6e8ax0_set_brightness, | 734 | .update_status = s6e8ax0_set_brightness, |
741 | }; | 735 | }; |
742 | 736 | ||
diff --git a/drivers/video/fbdev/hyperv_fb.c b/drivers/video/fbdev/hyperv_fb.c index e23392ec5af3..42543362f163 100644 --- a/drivers/video/fbdev/hyperv_fb.c +++ b/drivers/video/fbdev/hyperv_fb.c | |||
@@ -224,6 +224,11 @@ struct hvfb_par { | |||
224 | u32 pseudo_palette[16]; | 224 | u32 pseudo_palette[16]; |
225 | u8 init_buf[MAX_VMBUS_PKT_SIZE]; | 225 | u8 init_buf[MAX_VMBUS_PKT_SIZE]; |
226 | u8 recv_buf[MAX_VMBUS_PKT_SIZE]; | 226 | u8 recv_buf[MAX_VMBUS_PKT_SIZE]; |
227 | |||
228 | /* If true, the VSC notifies the VSP on every framebuffer change */ | ||
229 | bool synchronous_fb; | ||
230 | |||
231 | struct notifier_block hvfb_panic_nb; | ||
227 | }; | 232 | }; |
228 | 233 | ||
229 | static uint screen_width = HVFB_WIDTH; | 234 | static uint screen_width = HVFB_WIDTH; |
@@ -532,6 +537,19 @@ static void hvfb_update_work(struct work_struct *w) | |||
532 | schedule_delayed_work(&par->dwork, HVFB_UPDATE_DELAY); | 537 | schedule_delayed_work(&par->dwork, HVFB_UPDATE_DELAY); |
533 | } | 538 | } |
534 | 539 | ||
540 | static int hvfb_on_panic(struct notifier_block *nb, | ||
541 | unsigned long e, void *p) | ||
542 | { | ||
543 | struct hvfb_par *par; | ||
544 | struct fb_info *info; | ||
545 | |||
546 | par = container_of(nb, struct hvfb_par, hvfb_panic_nb); | ||
547 | par->synchronous_fb = true; | ||
548 | info = par->info; | ||
549 | synthvid_update(info); | ||
550 | |||
551 | return NOTIFY_DONE; | ||
552 | } | ||
535 | 553 | ||
536 | /* Framebuffer operation handlers */ | 554 | /* Framebuffer operation handlers */ |
537 | 555 | ||
@@ -582,14 +600,44 @@ static int hvfb_blank(int blank, struct fb_info *info) | |||
582 | return 1; /* get fb_blank to set the colormap to all black */ | 600 | return 1; /* get fb_blank to set the colormap to all black */ |
583 | } | 601 | } |
584 | 602 | ||
603 | static void hvfb_cfb_fillrect(struct fb_info *p, | ||
604 | const struct fb_fillrect *rect) | ||
605 | { | ||
606 | struct hvfb_par *par = p->par; | ||
607 | |||
608 | cfb_fillrect(p, rect); | ||
609 | if (par->synchronous_fb) | ||
610 | synthvid_update(p); | ||
611 | } | ||
612 | |||
613 | static void hvfb_cfb_copyarea(struct fb_info *p, | ||
614 | const struct fb_copyarea *area) | ||
615 | { | ||
616 | struct hvfb_par *par = p->par; | ||
617 | |||
618 | cfb_copyarea(p, area); | ||
619 | if (par->synchronous_fb) | ||
620 | synthvid_update(p); | ||
621 | } | ||
622 | |||
623 | static void hvfb_cfb_imageblit(struct fb_info *p, | ||
624 | const struct fb_image *image) | ||
625 | { | ||
626 | struct hvfb_par *par = p->par; | ||
627 | |||
628 | cfb_imageblit(p, image); | ||
629 | if (par->synchronous_fb) | ||
630 | synthvid_update(p); | ||
631 | } | ||
632 | |||
585 | static struct fb_ops hvfb_ops = { | 633 | static struct fb_ops hvfb_ops = { |
586 | .owner = THIS_MODULE, | 634 | .owner = THIS_MODULE, |
587 | .fb_check_var = hvfb_check_var, | 635 | .fb_check_var = hvfb_check_var, |
588 | .fb_set_par = hvfb_set_par, | 636 | .fb_set_par = hvfb_set_par, |
589 | .fb_setcolreg = hvfb_setcolreg, | 637 | .fb_setcolreg = hvfb_setcolreg, |
590 | .fb_fillrect = cfb_fillrect, | 638 | .fb_fillrect = hvfb_cfb_fillrect, |
591 | .fb_copyarea = cfb_copyarea, | 639 | .fb_copyarea = hvfb_cfb_copyarea, |
592 | .fb_imageblit = cfb_imageblit, | 640 | .fb_imageblit = hvfb_cfb_imageblit, |
593 | .fb_blank = hvfb_blank, | 641 | .fb_blank = hvfb_blank, |
594 | }; | 642 | }; |
595 | 643 | ||
@@ -801,6 +849,11 @@ static int hvfb_probe(struct hv_device *hdev, | |||
801 | 849 | ||
802 | par->fb_ready = true; | 850 | par->fb_ready = true; |
803 | 851 | ||
852 | par->synchronous_fb = false; | ||
853 | par->hvfb_panic_nb.notifier_call = hvfb_on_panic; | ||
854 | atomic_notifier_chain_register(&panic_notifier_list, | ||
855 | &par->hvfb_panic_nb); | ||
856 | |||
804 | return 0; | 857 | return 0; |
805 | 858 | ||
806 | error: | 859 | error: |
@@ -820,6 +873,9 @@ static int hvfb_remove(struct hv_device *hdev) | |||
820 | struct fb_info *info = hv_get_drvdata(hdev); | 873 | struct fb_info *info = hv_get_drvdata(hdev); |
821 | struct hvfb_par *par = info->par; | 874 | struct hvfb_par *par = info->par; |
822 | 875 | ||
876 | atomic_notifier_chain_unregister(&panic_notifier_list, | ||
877 | &par->hvfb_panic_nb); | ||
878 | |||
823 | par->update = false; | 879 | par->update = false; |
824 | par->fb_ready = false; | 880 | par->fb_ready = false; |
825 | 881 | ||
@@ -836,7 +892,7 @@ static int hvfb_remove(struct hv_device *hdev) | |||
836 | } | 892 | } |
837 | 893 | ||
838 | 894 | ||
839 | static DEFINE_PCI_DEVICE_TABLE(pci_stub_id_table) = { | 895 | static const struct pci_device_id pci_stub_id_table[] = { |
840 | { | 896 | { |
841 | .vendor = PCI_VENDOR_ID_MICROSOFT, | 897 | .vendor = PCI_VENDOR_ID_MICROSOFT, |
842 | .device = PCI_DEVICE_ID_HYPERV_VIDEO, | 898 | .device = PCI_DEVICE_ID_HYPERV_VIDEO, |
diff --git a/drivers/video/fbdev/i740fb.c b/drivers/video/fbdev/i740fb.c index ca7c9df193b0..a2b4204b42bb 100644 --- a/drivers/video/fbdev/i740fb.c +++ b/drivers/video/fbdev/i740fb.c | |||
@@ -1260,7 +1260,7 @@ fail: | |||
1260 | #define I740_ID_PCI 0x00d1 | 1260 | #define I740_ID_PCI 0x00d1 |
1261 | #define I740_ID_AGP 0x7800 | 1261 | #define I740_ID_AGP 0x7800 |
1262 | 1262 | ||
1263 | static DEFINE_PCI_DEVICE_TABLE(i740fb_id_table) = { | 1263 | static const struct pci_device_id i740fb_id_table[] = { |
1264 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, I740_ID_PCI) }, | 1264 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, I740_ID_PCI) }, |
1265 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, I740_ID_AGP) }, | 1265 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, I740_ID_AGP) }, |
1266 | { 0 } | 1266 | { 0 } |
diff --git a/drivers/video/fbdev/mbx/mbxfb.c b/drivers/video/fbdev/mbx/mbxfb.c index 2bd52ed8832c..698df9543e30 100644 --- a/drivers/video/fbdev/mbx/mbxfb.c +++ b/drivers/video/fbdev/mbx/mbxfb.c | |||
@@ -628,14 +628,14 @@ static int mbxfb_ioctl(struct fb_info *info, unsigned int cmd, | |||
628 | case MBXFB_IOCS_PLANEORDER: | 628 | case MBXFB_IOCS_PLANEORDER: |
629 | if (copy_from_user(&porder, (void __user*)arg, | 629 | if (copy_from_user(&porder, (void __user*)arg, |
630 | sizeof(struct mbxfb_planeorder))) | 630 | sizeof(struct mbxfb_planeorder))) |
631 | return -EFAULT; | 631 | return -EFAULT; |
632 | 632 | ||
633 | return mbxfb_ioctl_planeorder(&porder); | 633 | return mbxfb_ioctl_planeorder(&porder); |
634 | 634 | ||
635 | case MBXFB_IOCS_ALPHA: | 635 | case MBXFB_IOCS_ALPHA: |
636 | if (copy_from_user(&alpha, (void __user*)arg, | 636 | if (copy_from_user(&alpha, (void __user*)arg, |
637 | sizeof(struct mbxfb_alphaCtl))) | 637 | sizeof(struct mbxfb_alphaCtl))) |
638 | return -EFAULT; | 638 | return -EFAULT; |
639 | 639 | ||
640 | return mbxfb_ioctl_alphactl(&alpha); | 640 | return mbxfb_ioctl_alphactl(&alpha); |
641 | 641 | ||
diff --git a/drivers/video/fbdev/msm/mddi_client_dummy.c b/drivers/video/fbdev/msm/mddi_client_dummy.c index f1b0dfcc9717..cdb8f69a5d88 100644 --- a/drivers/video/fbdev/msm/mddi_client_dummy.c +++ b/drivers/video/fbdev/msm/mddi_client_dummy.c | |||
@@ -15,6 +15,7 @@ | |||
15 | * GNU General Public License for more details. | 15 | * GNU General Public License for more details. |
16 | */ | 16 | */ |
17 | 17 | ||
18 | #include <linux/device.h> | ||
18 | #include <linux/slab.h> | 19 | #include <linux/slab.h> |
19 | #include <linux/module.h> | 20 | #include <linux/module.h> |
20 | #include <linux/kernel.h> | 21 | #include <linux/kernel.h> |
@@ -51,8 +52,7 @@ static int mddi_dummy_probe(struct platform_device *pdev) | |||
51 | { | 52 | { |
52 | struct msm_mddi_client_data *client_data = pdev->dev.platform_data; | 53 | struct msm_mddi_client_data *client_data = pdev->dev.platform_data; |
53 | struct panel_info *panel = | 54 | struct panel_info *panel = |
54 | kzalloc(sizeof(struct panel_info), GFP_KERNEL); | 55 | devm_kzalloc(&pdev->dev, sizeof(struct panel_info), GFP_KERNEL); |
55 | int ret; | ||
56 | if (!panel) | 56 | if (!panel) |
57 | return -ENOMEM; | 57 | return -ENOMEM; |
58 | platform_set_drvdata(pdev, panel); | 58 | platform_set_drvdata(pdev, panel); |
@@ -67,24 +67,11 @@ static int mddi_dummy_probe(struct platform_device *pdev) | |||
67 | client_data->fb_resource, 1); | 67 | client_data->fb_resource, 1); |
68 | panel->panel_data.fb_data = client_data->private_client_data; | 68 | panel->panel_data.fb_data = client_data->private_client_data; |
69 | panel->pdev.dev.platform_data = &panel->panel_data; | 69 | panel->pdev.dev.platform_data = &panel->panel_data; |
70 | ret = platform_device_register(&panel->pdev); | 70 | return platform_device_register(&panel->pdev); |
71 | if (ret) { | ||
72 | kfree(panel); | ||
73 | return ret; | ||
74 | } | ||
75 | return 0; | ||
76 | } | ||
77 | |||
78 | static int mddi_dummy_remove(struct platform_device *pdev) | ||
79 | { | ||
80 | struct panel_info *panel = platform_get_drvdata(pdev); | ||
81 | kfree(panel); | ||
82 | return 0; | ||
83 | } | 71 | } |
84 | 72 | ||
85 | static struct platform_driver mddi_client_dummy = { | 73 | static struct platform_driver mddi_client_dummy = { |
86 | .probe = mddi_dummy_probe, | 74 | .probe = mddi_dummy_probe, |
87 | .remove = mddi_dummy_remove, | ||
88 | .driver = { .name = "mddi_c_dummy" }, | 75 | .driver = { .name = "mddi_c_dummy" }, |
89 | }; | 76 | }; |
90 | 77 | ||
diff --git a/drivers/video/fbdev/nvidia/nv_backlight.c b/drivers/video/fbdev/nvidia/nv_backlight.c index 8471008aa6ff..5c151b2ea683 100644 --- a/drivers/video/fbdev/nvidia/nv_backlight.c +++ b/drivers/video/fbdev/nvidia/nv_backlight.c | |||
@@ -82,13 +82,7 @@ static int nvidia_bl_update_status(struct backlight_device *bd) | |||
82 | return 0; | 82 | return 0; |
83 | } | 83 | } |
84 | 84 | ||
85 | static int nvidia_bl_get_brightness(struct backlight_device *bd) | ||
86 | { | ||
87 | return bd->props.brightness; | ||
88 | } | ||
89 | |||
90 | static const struct backlight_ops nvidia_bl_ops = { | 85 | static const struct backlight_ops nvidia_bl_ops = { |
91 | .get_brightness = nvidia_bl_get_brightness, | ||
92 | .update_status = nvidia_bl_update_status, | 86 | .update_status = nvidia_bl_update_status, |
93 | }; | 87 | }; |
94 | 88 | ||
diff --git a/drivers/video/fbdev/omap2/displays-new/connector-hdmi.c b/drivers/video/fbdev/omap2/displays-new/connector-hdmi.c index 4420ccb69aa9..131c6e260898 100644 --- a/drivers/video/fbdev/omap2/displays-new/connector-hdmi.c +++ b/drivers/video/fbdev/omap2/displays-new/connector-hdmi.c | |||
@@ -262,6 +262,23 @@ static int hdmic_audio_config(struct omap_dss_device *dssdev, | |||
262 | return 0; | 262 | return 0; |
263 | } | 263 | } |
264 | 264 | ||
265 | static int hdmic_set_hdmi_mode(struct omap_dss_device *dssdev, bool hdmi_mode) | ||
266 | { | ||
267 | struct panel_drv_data *ddata = to_panel_data(dssdev); | ||
268 | struct omap_dss_device *in = ddata->in; | ||
269 | |||
270 | return in->ops.hdmi->set_hdmi_mode(in, hdmi_mode); | ||
271 | } | ||
272 | |||
273 | static int hdmic_set_infoframe(struct omap_dss_device *dssdev, | ||
274 | const struct hdmi_avi_infoframe *avi) | ||
275 | { | ||
276 | struct panel_drv_data *ddata = to_panel_data(dssdev); | ||
277 | struct omap_dss_device *in = ddata->in; | ||
278 | |||
279 | return in->ops.hdmi->set_infoframe(in, avi); | ||
280 | } | ||
281 | |||
265 | static struct omap_dss_driver hdmic_driver = { | 282 | static struct omap_dss_driver hdmic_driver = { |
266 | .connect = hdmic_connect, | 283 | .connect = hdmic_connect, |
267 | .disconnect = hdmic_disconnect, | 284 | .disconnect = hdmic_disconnect, |
@@ -277,6 +294,8 @@ static struct omap_dss_driver hdmic_driver = { | |||
277 | 294 | ||
278 | .read_edid = hdmic_read_edid, | 295 | .read_edid = hdmic_read_edid, |
279 | .detect = hdmic_detect, | 296 | .detect = hdmic_detect, |
297 | .set_hdmi_mode = hdmic_set_hdmi_mode, | ||
298 | .set_hdmi_infoframe = hdmic_set_infoframe, | ||
280 | 299 | ||
281 | .audio_enable = hdmic_audio_enable, | 300 | .audio_enable = hdmic_audio_enable, |
282 | .audio_disable = hdmic_audio_disable, | 301 | .audio_disable = hdmic_audio_disable, |
diff --git a/drivers/video/fbdev/omap2/displays-new/encoder-tpd12s015.c b/drivers/video/fbdev/omap2/displays-new/encoder-tpd12s015.c index 7e33686171e3..c891d8f84cb2 100644 --- a/drivers/video/fbdev/omap2/displays-new/encoder-tpd12s015.c +++ b/drivers/video/fbdev/omap2/displays-new/encoder-tpd12s015.c | |||
@@ -242,6 +242,24 @@ static int tpd_audio_config(struct omap_dss_device *dssdev, | |||
242 | return in->ops.hdmi->audio_config(in, audio); | 242 | return in->ops.hdmi->audio_config(in, audio); |
243 | } | 243 | } |
244 | 244 | ||
245 | static int tpd_set_infoframe(struct omap_dss_device *dssdev, | ||
246 | const struct hdmi_avi_infoframe *avi) | ||
247 | { | ||
248 | struct panel_drv_data *ddata = to_panel_data(dssdev); | ||
249 | struct omap_dss_device *in = ddata->in; | ||
250 | |||
251 | return in->ops.hdmi->set_infoframe(in, avi); | ||
252 | } | ||
253 | |||
254 | static int tpd_set_hdmi_mode(struct omap_dss_device *dssdev, | ||
255 | bool hdmi_mode) | ||
256 | { | ||
257 | struct panel_drv_data *ddata = to_panel_data(dssdev); | ||
258 | struct omap_dss_device *in = ddata->in; | ||
259 | |||
260 | return in->ops.hdmi->set_hdmi_mode(in, hdmi_mode); | ||
261 | } | ||
262 | |||
245 | static const struct omapdss_hdmi_ops tpd_hdmi_ops = { | 263 | static const struct omapdss_hdmi_ops tpd_hdmi_ops = { |
246 | .connect = tpd_connect, | 264 | .connect = tpd_connect, |
247 | .disconnect = tpd_disconnect, | 265 | .disconnect = tpd_disconnect, |
@@ -255,6 +273,8 @@ static const struct omapdss_hdmi_ops tpd_hdmi_ops = { | |||
255 | 273 | ||
256 | .read_edid = tpd_read_edid, | 274 | .read_edid = tpd_read_edid, |
257 | .detect = tpd_detect, | 275 | .detect = tpd_detect, |
276 | .set_infoframe = tpd_set_infoframe, | ||
277 | .set_hdmi_mode = tpd_set_hdmi_mode, | ||
258 | 278 | ||
259 | .audio_enable = tpd_audio_enable, | 279 | .audio_enable = tpd_audio_enable, |
260 | .audio_disable = tpd_audio_disable, | 280 | .audio_disable = tpd_audio_disable, |
diff --git a/drivers/video/fbdev/omap2/displays-new/panel-sony-acx565akm.c b/drivers/video/fbdev/omap2/displays-new/panel-sony-acx565akm.c index c7ba4d8b928a..617f8d2f5127 100644 --- a/drivers/video/fbdev/omap2/displays-new/panel-sony-acx565akm.c +++ b/drivers/video/fbdev/omap2/displays-new/panel-sony-acx565akm.c | |||
@@ -817,6 +817,10 @@ static int acx565akm_probe(struct spi_device *spi) | |||
817 | 817 | ||
818 | bldev = backlight_device_register("acx565akm", &ddata->spi->dev, | 818 | bldev = backlight_device_register("acx565akm", &ddata->spi->dev, |
819 | ddata, &acx565akm_bl_ops, &props); | 819 | ddata, &acx565akm_bl_ops, &props); |
820 | if (IS_ERR(bldev)) { | ||
821 | r = PTR_ERR(bldev); | ||
822 | goto err_reg_bl; | ||
823 | } | ||
820 | ddata->bl_dev = bldev; | 824 | ddata->bl_dev = bldev; |
821 | if (ddata->has_cabc) { | 825 | if (ddata->has_cabc) { |
822 | r = sysfs_create_group(&bldev->dev.kobj, &bldev_attr_group); | 826 | r = sysfs_create_group(&bldev->dev.kobj, &bldev_attr_group); |
@@ -862,6 +866,7 @@ err_reg: | |||
862 | sysfs_remove_group(&bldev->dev.kobj, &bldev_attr_group); | 866 | sysfs_remove_group(&bldev->dev.kobj, &bldev_attr_group); |
863 | err_sysfs: | 867 | err_sysfs: |
864 | backlight_device_unregister(bldev); | 868 | backlight_device_unregister(bldev); |
869 | err_reg_bl: | ||
865 | err_detect: | 870 | err_detect: |
866 | err_gpio: | 871 | err_gpio: |
867 | omap_dss_put_device(ddata->in); | 872 | omap_dss_put_device(ddata->in); |
diff --git a/drivers/video/fbdev/omap2/dss/Kconfig b/drivers/video/fbdev/omap2/dss/Kconfig index 285bcd103dce..3d5eb6c36c22 100644 --- a/drivers/video/fbdev/omap2/dss/Kconfig +++ b/drivers/video/fbdev/omap2/dss/Kconfig | |||
@@ -5,6 +5,7 @@ menuconfig OMAP2_DSS | |||
5 | tristate "OMAP2+ Display Subsystem support" | 5 | tristate "OMAP2+ Display Subsystem support" |
6 | select VIDEOMODE_HELPERS | 6 | select VIDEOMODE_HELPERS |
7 | select OMAP2_DSS_INIT | 7 | select OMAP2_DSS_INIT |
8 | select HDMI | ||
8 | help | 9 | help |
9 | OMAP2+ Display Subsystem support. | 10 | OMAP2+ Display Subsystem support. |
10 | 11 | ||
diff --git a/drivers/video/fbdev/omap2/dss/dispc.c b/drivers/video/fbdev/omap2/dss/dispc.c index 7aa33b0f4a1f..be053aa80880 100644 --- a/drivers/video/fbdev/omap2/dss/dispc.c +++ b/drivers/video/fbdev/omap2/dss/dispc.c | |||
@@ -2879,19 +2879,24 @@ static bool _dispc_mgr_pclk_ok(enum omap_channel channel, | |||
2879 | bool dispc_mgr_timings_ok(enum omap_channel channel, | 2879 | bool dispc_mgr_timings_ok(enum omap_channel channel, |
2880 | const struct omap_video_timings *timings) | 2880 | const struct omap_video_timings *timings) |
2881 | { | 2881 | { |
2882 | bool timings_ok; | 2882 | if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res)) |
2883 | 2883 | return false; | |
2884 | timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res); | ||
2885 | 2884 | ||
2886 | timings_ok &= _dispc_mgr_pclk_ok(channel, timings->pixelclock); | 2885 | if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock)) |
2886 | return false; | ||
2887 | 2887 | ||
2888 | if (dss_mgr_is_lcd(channel)) { | 2888 | if (dss_mgr_is_lcd(channel)) { |
2889 | timings_ok &= _dispc_lcd_timings_ok(timings->hsw, timings->hfp, | 2889 | /* TODO: OMAP4+ supports interlace for LCD outputs */ |
2890 | if (timings->interlace) | ||
2891 | return false; | ||
2892 | |||
2893 | if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp, | ||
2890 | timings->hbp, timings->vsw, timings->vfp, | 2894 | timings->hbp, timings->vsw, timings->vfp, |
2891 | timings->vbp); | 2895 | timings->vbp)) |
2896 | return false; | ||
2892 | } | 2897 | } |
2893 | 2898 | ||
2894 | return timings_ok; | 2899 | return true; |
2895 | } | 2900 | } |
2896 | 2901 | ||
2897 | static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw, | 2902 | static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw, |
@@ -3257,13 +3262,10 @@ static void dispc_dump_regs(struct seq_file *s) | |||
3257 | if (i == OMAP_DSS_CHANNEL_DIGIT) | 3262 | if (i == OMAP_DSS_CHANNEL_DIGIT) |
3258 | continue; | 3263 | continue; |
3259 | 3264 | ||
3260 | DUMPREG(i, DISPC_DEFAULT_COLOR); | ||
3261 | DUMPREG(i, DISPC_TRANS_COLOR); | ||
3262 | DUMPREG(i, DISPC_TIMING_H); | 3265 | DUMPREG(i, DISPC_TIMING_H); |
3263 | DUMPREG(i, DISPC_TIMING_V); | 3266 | DUMPREG(i, DISPC_TIMING_V); |
3264 | DUMPREG(i, DISPC_POL_FREQ); | 3267 | DUMPREG(i, DISPC_POL_FREQ); |
3265 | DUMPREG(i, DISPC_DIVISORo); | 3268 | DUMPREG(i, DISPC_DIVISORo); |
3266 | DUMPREG(i, DISPC_SIZE_MGR); | ||
3267 | 3269 | ||
3268 | DUMPREG(i, DISPC_DATA_CYCLE1); | 3270 | DUMPREG(i, DISPC_DATA_CYCLE1); |
3269 | DUMPREG(i, DISPC_DATA_CYCLE2); | 3271 | DUMPREG(i, DISPC_DATA_CYCLE2); |
diff --git a/drivers/video/fbdev/omap2/dss/dsi.c b/drivers/video/fbdev/omap2/dss/dsi.c index 4755a34a5422..56b92444c54f 100644 --- a/drivers/video/fbdev/omap2/dss/dsi.c +++ b/drivers/video/fbdev/omap2/dss/dsi.c | |||
@@ -5658,18 +5658,11 @@ err_runtime_get: | |||
5658 | return r; | 5658 | return r; |
5659 | } | 5659 | } |
5660 | 5660 | ||
5661 | static int dsi_unregister_child(struct device *dev, void *data) | ||
5662 | { | ||
5663 | struct platform_device *pdev = to_platform_device(dev); | ||
5664 | platform_device_unregister(pdev); | ||
5665 | return 0; | ||
5666 | } | ||
5667 | |||
5668 | static int __exit omap_dsihw_remove(struct platform_device *dsidev) | 5661 | static int __exit omap_dsihw_remove(struct platform_device *dsidev) |
5669 | { | 5662 | { |
5670 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | 5663 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
5671 | 5664 | ||
5672 | device_for_each_child(&dsidev->dev, NULL, dsi_unregister_child); | 5665 | of_platform_depopulate(&dsidev->dev); |
5673 | 5666 | ||
5674 | WARN_ON(dsi->scp_clk_refcount > 0); | 5667 | WARN_ON(dsi->scp_clk_refcount > 0); |
5675 | 5668 | ||
diff --git a/drivers/video/fbdev/omap2/dss/hdmi.h b/drivers/video/fbdev/omap2/dss/hdmi.h index fbee07816337..262771b9b76b 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi.h +++ b/drivers/video/fbdev/omap2/dss/hdmi.h | |||
@@ -22,6 +22,7 @@ | |||
22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
24 | #include <linux/platform_device.h> | 24 | #include <linux/platform_device.h> |
25 | #include <linux/hdmi.h> | ||
25 | #include <video/omapdss.h> | 26 | #include <video/omapdss.h> |
26 | 27 | ||
27 | #include "dss.h" | 28 | #include "dss.h" |
@@ -142,7 +143,7 @@ enum hdmi_audio_samples_perword { | |||
142 | HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1 | 143 | HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1 |
143 | }; | 144 | }; |
144 | 145 | ||
145 | enum hdmi_audio_sample_size { | 146 | enum hdmi_audio_sample_size_omap { |
146 | HDMI_AUDIO_SAMPLE_16BITS = 0, | 147 | HDMI_AUDIO_SAMPLE_16BITS = 0, |
147 | HDMI_AUDIO_SAMPLE_24BITS = 1 | 148 | HDMI_AUDIO_SAMPLE_24BITS = 1 |
148 | }; | 149 | }; |
@@ -178,59 +179,6 @@ enum hdmi_audio_mclk_mode { | |||
178 | HDMI_AUDIO_MCLK_192FS = 7 | 179 | HDMI_AUDIO_MCLK_192FS = 7 |
179 | }; | 180 | }; |
180 | 181 | ||
181 | /* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */ | ||
182 | enum hdmi_core_infoframe { | ||
183 | HDMI_INFOFRAME_AVI_DB1Y_RGB = 0, | ||
184 | HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1, | ||
185 | HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2, | ||
186 | HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0, | ||
187 | HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON = 1, | ||
188 | HDMI_INFOFRAME_AVI_DB1B_NO = 0, | ||
189 | HDMI_INFOFRAME_AVI_DB1B_VERT = 1, | ||
190 | HDMI_INFOFRAME_AVI_DB1B_HORI = 2, | ||
191 | HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3, | ||
192 | HDMI_INFOFRAME_AVI_DB1S_0 = 0, | ||
193 | HDMI_INFOFRAME_AVI_DB1S_1 = 1, | ||
194 | HDMI_INFOFRAME_AVI_DB1S_2 = 2, | ||
195 | HDMI_INFOFRAME_AVI_DB2C_NO = 0, | ||
196 | HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1, | ||
197 | HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2, | ||
198 | HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3, | ||
199 | HDMI_INFOFRAME_AVI_DB2M_NO = 0, | ||
200 | HDMI_INFOFRAME_AVI_DB2M_43 = 1, | ||
201 | HDMI_INFOFRAME_AVI_DB2M_169 = 2, | ||
202 | HDMI_INFOFRAME_AVI_DB2R_SAME = 8, | ||
203 | HDMI_INFOFRAME_AVI_DB2R_43 = 9, | ||
204 | HDMI_INFOFRAME_AVI_DB2R_169 = 10, | ||
205 | HDMI_INFOFRAME_AVI_DB2R_149 = 11, | ||
206 | HDMI_INFOFRAME_AVI_DB3ITC_NO = 0, | ||
207 | HDMI_INFOFRAME_AVI_DB3ITC_YES = 1, | ||
208 | HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0, | ||
209 | HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1, | ||
210 | HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0, | ||
211 | HDMI_INFOFRAME_AVI_DB3Q_LR = 1, | ||
212 | HDMI_INFOFRAME_AVI_DB3Q_FR = 2, | ||
213 | HDMI_INFOFRAME_AVI_DB3SC_NO = 0, | ||
214 | HDMI_INFOFRAME_AVI_DB3SC_HORI = 1, | ||
215 | HDMI_INFOFRAME_AVI_DB3SC_VERT = 2, | ||
216 | HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3, | ||
217 | HDMI_INFOFRAME_AVI_DB5PR_NO = 0, | ||
218 | HDMI_INFOFRAME_AVI_DB5PR_2 = 1, | ||
219 | HDMI_INFOFRAME_AVI_DB5PR_3 = 2, | ||
220 | HDMI_INFOFRAME_AVI_DB5PR_4 = 3, | ||
221 | HDMI_INFOFRAME_AVI_DB5PR_5 = 4, | ||
222 | HDMI_INFOFRAME_AVI_DB5PR_6 = 5, | ||
223 | HDMI_INFOFRAME_AVI_DB5PR_7 = 6, | ||
224 | HDMI_INFOFRAME_AVI_DB5PR_8 = 7, | ||
225 | HDMI_INFOFRAME_AVI_DB5PR_9 = 8, | ||
226 | HDMI_INFOFRAME_AVI_DB5PR_10 = 9, | ||
227 | }; | ||
228 | |||
229 | struct hdmi_cm { | ||
230 | int code; | ||
231 | int mode; | ||
232 | }; | ||
233 | |||
234 | struct hdmi_video_format { | 182 | struct hdmi_video_format { |
235 | enum hdmi_packing_mode packing_mode; | 183 | enum hdmi_packing_mode packing_mode; |
236 | u32 y_res; /* Line per panel */ | 184 | u32 y_res; /* Line per panel */ |
@@ -239,7 +187,8 @@ struct hdmi_video_format { | |||
239 | 187 | ||
240 | struct hdmi_config { | 188 | struct hdmi_config { |
241 | struct omap_video_timings timings; | 189 | struct omap_video_timings timings; |
242 | struct hdmi_cm cm; | 190 | struct hdmi_avi_infoframe infoframe; |
191 | enum hdmi_core_hdmi_dvi hdmi_dvi_mode; | ||
243 | }; | 192 | }; |
244 | 193 | ||
245 | /* HDMI PLL structure */ | 194 | /* HDMI PLL structure */ |
@@ -260,7 +209,7 @@ struct hdmi_audio_format { | |||
260 | enum hdmi_audio_justify justification; | 209 | enum hdmi_audio_justify justification; |
261 | enum hdmi_audio_sample_order sample_order; | 210 | enum hdmi_audio_sample_order sample_order; |
262 | enum hdmi_audio_samples_perword samples_per_word; | 211 | enum hdmi_audio_samples_perword samples_per_word; |
263 | enum hdmi_audio_sample_size sample_size; | 212 | enum hdmi_audio_sample_size_omap sample_size; |
264 | enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end; | 213 | enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end; |
265 | }; | 214 | }; |
266 | 215 | ||
@@ -298,47 +247,6 @@ struct hdmi_core_audio_config { | |||
298 | bool en_spdif; | 247 | bool en_spdif; |
299 | }; | 248 | }; |
300 | 249 | ||
301 | /* | ||
302 | * Refer to section 8.2 in HDMI 1.3 specification for | ||
303 | * details about infoframe databytes | ||
304 | */ | ||
305 | struct hdmi_core_infoframe_avi { | ||
306 | /* Y0, Y1 rgb,yCbCr */ | ||
307 | u8 db1_format; | ||
308 | /* A0 Active information Present */ | ||
309 | u8 db1_active_info; | ||
310 | /* B0, B1 Bar info data valid */ | ||
311 | u8 db1_bar_info_dv; | ||
312 | /* S0, S1 scan information */ | ||
313 | u8 db1_scan_info; | ||
314 | /* C0, C1 colorimetry */ | ||
315 | u8 db2_colorimetry; | ||
316 | /* M0, M1 Aspect ratio (4:3, 16:9) */ | ||
317 | u8 db2_aspect_ratio; | ||
318 | /* R0...R3 Active format aspect ratio */ | ||
319 | u8 db2_active_fmt_ar; | ||
320 | /* ITC IT content. */ | ||
321 | u8 db3_itc; | ||
322 | /* EC0, EC1, EC2 Extended colorimetry */ | ||
323 | u8 db3_ec; | ||
324 | /* Q1, Q0 Quantization range */ | ||
325 | u8 db3_q_range; | ||
326 | /* SC1, SC0 Non-uniform picture scaling */ | ||
327 | u8 db3_nup_scaling; | ||
328 | /* VIC0..6 Video format identification */ | ||
329 | u8 db4_videocode; | ||
330 | /* PR0..PR3 Pixel repetition factor */ | ||
331 | u8 db5_pixel_repeat; | ||
332 | /* Line number end of top bar */ | ||
333 | u16 db6_7_line_eoftop; | ||
334 | /* Line number start of bottom bar */ | ||
335 | u16 db8_9_line_sofbottom; | ||
336 | /* Pixel number end of left bar */ | ||
337 | u16 db10_11_pixel_eofleft; | ||
338 | /* Pixel number start of right bar */ | ||
339 | u16 db12_13_pixel_sofright; | ||
340 | }; | ||
341 | |||
342 | struct hdmi_wp_data { | 250 | struct hdmi_wp_data { |
343 | void __iomem *base; | 251 | void __iomem *base; |
344 | }; | 252 | }; |
@@ -358,8 +266,6 @@ struct hdmi_phy_data { | |||
358 | 266 | ||
359 | struct hdmi_core_data { | 267 | struct hdmi_core_data { |
360 | void __iomem *base; | 268 | void __iomem *base; |
361 | |||
362 | struct hdmi_core_infoframe_avi avi_cfg; | ||
363 | }; | 269 | }; |
364 | 270 | ||
365 | static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx, | 271 | static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx, |
@@ -425,9 +331,6 @@ int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy); | |||
425 | int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes); | 331 | int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes); |
426 | 332 | ||
427 | /* HDMI common funcs */ | 333 | /* HDMI common funcs */ |
428 | const struct hdmi_config *hdmi_default_timing(void); | ||
429 | const struct hdmi_config *hdmi_get_timings(int mode, int code); | ||
430 | struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing); | ||
431 | int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep, | 334 | int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep, |
432 | struct hdmi_phy_data *phy); | 335 | struct hdmi_phy_data *phy); |
433 | 336 | ||
diff --git a/drivers/video/fbdev/omap2/dss/hdmi4.c b/drivers/video/fbdev/omap2/dss/hdmi4.c index 626aad2bef46..6a8550cf43e5 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi4.c +++ b/drivers/video/fbdev/omap2/dss/hdmi4.c | |||
@@ -281,29 +281,11 @@ static int hdmi_display_check_timing(struct omap_dss_device *dssdev, | |||
281 | static void hdmi_display_set_timing(struct omap_dss_device *dssdev, | 281 | static void hdmi_display_set_timing(struct omap_dss_device *dssdev, |
282 | struct omap_video_timings *timings) | 282 | struct omap_video_timings *timings) |
283 | { | 283 | { |
284 | struct hdmi_cm cm; | ||
285 | const struct hdmi_config *t; | ||
286 | |||
287 | mutex_lock(&hdmi.lock); | 284 | mutex_lock(&hdmi.lock); |
288 | 285 | ||
289 | cm = hdmi_get_code(timings); | 286 | hdmi.cfg.timings = *timings; |
290 | hdmi.cfg.cm = cm; | ||
291 | |||
292 | t = hdmi_get_timings(cm.mode, cm.code); | ||
293 | if (t != NULL) { | ||
294 | hdmi.cfg = *t; | ||
295 | |||
296 | dispc_set_tv_pclk(t->timings.pixelclock); | ||
297 | } else { | ||
298 | hdmi.cfg.timings = *timings; | ||
299 | hdmi.cfg.cm.code = 0; | ||
300 | hdmi.cfg.cm.mode = HDMI_DVI; | ||
301 | |||
302 | dispc_set_tv_pclk(timings->pixelclock); | ||
303 | } | ||
304 | 287 | ||
305 | DSSDBG("using mode: %s, code %d\n", hdmi.cfg.cm.mode == HDMI_DVI ? | 288 | dispc_set_tv_pclk(timings->pixelclock); |
306 | "DVI" : "HDMI", hdmi.cfg.cm.code); | ||
307 | 289 | ||
308 | mutex_unlock(&hdmi.lock); | 290 | mutex_unlock(&hdmi.lock); |
309 | } | 291 | } |
@@ -311,14 +293,7 @@ static void hdmi_display_set_timing(struct omap_dss_device *dssdev, | |||
311 | static void hdmi_display_get_timings(struct omap_dss_device *dssdev, | 293 | static void hdmi_display_get_timings(struct omap_dss_device *dssdev, |
312 | struct omap_video_timings *timings) | 294 | struct omap_video_timings *timings) |
313 | { | 295 | { |
314 | const struct hdmi_config *cfg; | 296 | *timings = hdmi.cfg.timings; |
315 | struct hdmi_cm cm = hdmi.cfg.cm; | ||
316 | |||
317 | cfg = hdmi_get_timings(cm.mode, cm.code); | ||
318 | if (cfg == NULL) | ||
319 | cfg = hdmi_default_timing(); | ||
320 | |||
321 | memcpy(timings, &cfg->timings, sizeof(cfg->timings)); | ||
322 | } | 297 | } |
323 | 298 | ||
324 | static void hdmi_dump_regs(struct seq_file *s) | 299 | static void hdmi_dump_regs(struct seq_file *s) |
@@ -516,7 +491,7 @@ static int hdmi_audio_enable(struct omap_dss_device *dssdev) | |||
516 | 491 | ||
517 | mutex_lock(&hdmi.lock); | 492 | mutex_lock(&hdmi.lock); |
518 | 493 | ||
519 | if (!hdmi_mode_has_audio(hdmi.cfg.cm.mode)) { | 494 | if (!hdmi_mode_has_audio(hdmi.cfg.hdmi_dvi_mode)) { |
520 | r = -EPERM; | 495 | r = -EPERM; |
521 | goto err; | 496 | goto err; |
522 | } | 497 | } |
@@ -554,7 +529,7 @@ static bool hdmi_audio_supported(struct omap_dss_device *dssdev) | |||
554 | 529 | ||
555 | mutex_lock(&hdmi.lock); | 530 | mutex_lock(&hdmi.lock); |
556 | 531 | ||
557 | r = hdmi_mode_has_audio(hdmi.cfg.cm.mode); | 532 | r = hdmi_mode_has_audio(hdmi.cfg.hdmi_dvi_mode); |
558 | 533 | ||
559 | mutex_unlock(&hdmi.lock); | 534 | mutex_unlock(&hdmi.lock); |
560 | return r; | 535 | return r; |
@@ -568,7 +543,7 @@ static int hdmi_audio_config(struct omap_dss_device *dssdev, | |||
568 | 543 | ||
569 | mutex_lock(&hdmi.lock); | 544 | mutex_lock(&hdmi.lock); |
570 | 545 | ||
571 | if (!hdmi_mode_has_audio(hdmi.cfg.cm.mode)) { | 546 | if (!hdmi_mode_has_audio(hdmi.cfg.hdmi_dvi_mode)) { |
572 | r = -EPERM; | 547 | r = -EPERM; |
573 | goto err; | 548 | goto err; |
574 | } | 549 | } |
@@ -615,6 +590,20 @@ static int hdmi_audio_config(struct omap_dss_device *dssdev, | |||
615 | } | 590 | } |
616 | #endif | 591 | #endif |
617 | 592 | ||
593 | static int hdmi_set_infoframe(struct omap_dss_device *dssdev, | ||
594 | const struct hdmi_avi_infoframe *avi) | ||
595 | { | ||
596 | hdmi.cfg.infoframe = *avi; | ||
597 | return 0; | ||
598 | } | ||
599 | |||
600 | static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev, | ||
601 | bool hdmi_mode) | ||
602 | { | ||
603 | hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI; | ||
604 | return 0; | ||
605 | } | ||
606 | |||
618 | static const struct omapdss_hdmi_ops hdmi_ops = { | 607 | static const struct omapdss_hdmi_ops hdmi_ops = { |
619 | .connect = hdmi_connect, | 608 | .connect = hdmi_connect, |
620 | .disconnect = hdmi_disconnect, | 609 | .disconnect = hdmi_disconnect, |
@@ -627,6 +616,8 @@ static const struct omapdss_hdmi_ops hdmi_ops = { | |||
627 | .get_timings = hdmi_display_get_timings, | 616 | .get_timings = hdmi_display_get_timings, |
628 | 617 | ||
629 | .read_edid = hdmi_read_edid, | 618 | .read_edid = hdmi_read_edid, |
619 | .set_infoframe = hdmi_set_infoframe, | ||
620 | .set_hdmi_mode = hdmi_set_hdmi_mode, | ||
630 | 621 | ||
631 | .audio_enable = hdmi_audio_enable, | 622 | .audio_enable = hdmi_audio_enable, |
632 | .audio_disable = hdmi_audio_disable, | 623 | .audio_disable = hdmi_audio_disable, |
diff --git a/drivers/video/fbdev/omap2/dss/hdmi4_core.c b/drivers/video/fbdev/omap2/dss/hdmi4_core.c index 8bde7b7e95ff..4ad39cfce254 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi4_core.c +++ b/drivers/video/fbdev/omap2/dss/hdmi4_core.c | |||
@@ -197,9 +197,7 @@ int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len) | |||
197 | return l; | 197 | return l; |
198 | } | 198 | } |
199 | 199 | ||
200 | static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, | 200 | static void hdmi_core_init(struct hdmi_core_video_config *video_cfg) |
201 | struct hdmi_core_infoframe_avi *avi_cfg, | ||
202 | struct hdmi_core_packet_enable_repeat *repeat_cfg) | ||
203 | { | 201 | { |
204 | DSSDBG("Enter hdmi_core_init\n"); | 202 | DSSDBG("Enter hdmi_core_init\n"); |
205 | 203 | ||
@@ -210,35 +208,6 @@ static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, | |||
210 | video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE; | 208 | video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE; |
211 | video_cfg->hdmi_dvi = HDMI_DVI; | 209 | video_cfg->hdmi_dvi = HDMI_DVI; |
212 | video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK; | 210 | video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK; |
213 | |||
214 | /* info frame */ | ||
215 | avi_cfg->db1_format = 0; | ||
216 | avi_cfg->db1_active_info = 0; | ||
217 | avi_cfg->db1_bar_info_dv = 0; | ||
218 | avi_cfg->db1_scan_info = 0; | ||
219 | avi_cfg->db2_colorimetry = 0; | ||
220 | avi_cfg->db2_aspect_ratio = 0; | ||
221 | avi_cfg->db2_active_fmt_ar = 0; | ||
222 | avi_cfg->db3_itc = 0; | ||
223 | avi_cfg->db3_ec = 0; | ||
224 | avi_cfg->db3_q_range = 0; | ||
225 | avi_cfg->db3_nup_scaling = 0; | ||
226 | avi_cfg->db4_videocode = 0; | ||
227 | avi_cfg->db5_pixel_repeat = 0; | ||
228 | avi_cfg->db6_7_line_eoftop = 0; | ||
229 | avi_cfg->db8_9_line_sofbottom = 0; | ||
230 | avi_cfg->db10_11_pixel_eofleft = 0; | ||
231 | avi_cfg->db12_13_pixel_sofright = 0; | ||
232 | |||
233 | /* packet enable and repeat */ | ||
234 | repeat_cfg->audio_pkt = 0; | ||
235 | repeat_cfg->audio_pkt_repeat = 0; | ||
236 | repeat_cfg->avi_infoframe = 0; | ||
237 | repeat_cfg->avi_infoframe_repeat = 0; | ||
238 | repeat_cfg->gen_cntrl_pkt = 0; | ||
239 | repeat_cfg->gen_cntrl_pkt_repeat = 0; | ||
240 | repeat_cfg->generic_pkt = 0; | ||
241 | repeat_cfg->generic_pkt_repeat = 0; | ||
242 | } | 211 | } |
243 | 212 | ||
244 | static void hdmi_core_powerdown_disable(struct hdmi_core_data *core) | 213 | static void hdmi_core_powerdown_disable(struct hdmi_core_data *core) |
@@ -303,80 +272,22 @@ static void hdmi_core_video_config(struct hdmi_core_data *core, | |||
303 | HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5); | 272 | HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5); |
304 | } | 273 | } |
305 | 274 | ||
306 | static void hdmi_core_aux_infoframe_avi_config(struct hdmi_core_data *core) | 275 | static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core, |
276 | struct hdmi_avi_infoframe *frame) | ||
307 | { | 277 | { |
308 | u32 val; | ||
309 | char sum = 0, checksum = 0; | ||
310 | void __iomem *av_base = hdmi_av_base(core); | 278 | void __iomem *av_base = hdmi_av_base(core); |
311 | struct hdmi_core_infoframe_avi info_avi = core->avi_cfg; | 279 | u8 data[HDMI_INFOFRAME_SIZE(AVI)]; |
312 | 280 | int i; | |
313 | sum += 0x82 + 0x002 + 0x00D; | ||
314 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082); | ||
315 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002); | ||
316 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D); | ||
317 | |||
318 | val = (info_avi.db1_format << 5) | | ||
319 | (info_avi.db1_active_info << 4) | | ||
320 | (info_avi.db1_bar_info_dv << 2) | | ||
321 | (info_avi.db1_scan_info); | ||
322 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val); | ||
323 | sum += val; | ||
324 | |||
325 | val = (info_avi.db2_colorimetry << 6) | | ||
326 | (info_avi.db2_aspect_ratio << 4) | | ||
327 | (info_avi.db2_active_fmt_ar); | ||
328 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val); | ||
329 | sum += val; | ||
330 | |||
331 | val = (info_avi.db3_itc << 7) | | ||
332 | (info_avi.db3_ec << 4) | | ||
333 | (info_avi.db3_q_range << 2) | | ||
334 | (info_avi.db3_nup_scaling); | ||
335 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val); | ||
336 | sum += val; | ||
337 | |||
338 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3), | ||
339 | info_avi.db4_videocode); | ||
340 | sum += info_avi.db4_videocode; | ||
341 | |||
342 | val = info_avi.db5_pixel_repeat; | ||
343 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val); | ||
344 | sum += val; | ||
345 | |||
346 | val = info_avi.db6_7_line_eoftop & 0x00FF; | ||
347 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val); | ||
348 | sum += val; | ||
349 | |||
350 | val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF); | ||
351 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val); | ||
352 | sum += val; | ||
353 | |||
354 | val = info_avi.db8_9_line_sofbottom & 0x00FF; | ||
355 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val); | ||
356 | sum += val; | ||
357 | |||
358 | val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF); | ||
359 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val); | ||
360 | sum += val; | ||
361 | |||
362 | val = info_avi.db10_11_pixel_eofleft & 0x00FF; | ||
363 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val); | ||
364 | sum += val; | ||
365 | |||
366 | val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF); | ||
367 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val); | ||
368 | sum += val; | ||
369 | |||
370 | val = info_avi.db12_13_pixel_sofright & 0x00FF; | ||
371 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val); | ||
372 | sum += val; | ||
373 | |||
374 | val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF); | ||
375 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val); | ||
376 | sum += val; | ||
377 | 281 | ||
378 | checksum = 0x100 - sum; | 282 | hdmi_avi_infoframe_pack(frame, data, sizeof(data)); |
379 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum); | 283 | |
284 | print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data, | ||
285 | HDMI_INFOFRAME_SIZE(AVI), false); | ||
286 | |||
287 | for (i = 0; i < sizeof(data); ++i) { | ||
288 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_BASE + i * 4, | ||
289 | data[i]); | ||
290 | } | ||
380 | } | 291 | } |
381 | 292 | ||
382 | static void hdmi_core_av_packet_config(struct hdmi_core_data *core, | 293 | static void hdmi_core_av_packet_config(struct hdmi_core_data *core, |
@@ -404,11 +315,10 @@ void hdmi4_configure(struct hdmi_core_data *core, | |||
404 | struct omap_video_timings video_timing; | 315 | struct omap_video_timings video_timing; |
405 | struct hdmi_video_format video_format; | 316 | struct hdmi_video_format video_format; |
406 | /* HDMI core */ | 317 | /* HDMI core */ |
407 | struct hdmi_core_infoframe_avi *avi_cfg = &core->avi_cfg; | ||
408 | struct hdmi_core_video_config v_core_cfg; | 318 | struct hdmi_core_video_config v_core_cfg; |
409 | struct hdmi_core_packet_enable_repeat repeat_cfg; | 319 | struct hdmi_core_packet_enable_repeat repeat_cfg = { 0 }; |
410 | 320 | ||
411 | hdmi_core_init(&v_core_cfg, avi_cfg, &repeat_cfg); | 321 | hdmi_core_init(&v_core_cfg); |
412 | 322 | ||
413 | hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg); | 323 | hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg); |
414 | 324 | ||
@@ -431,44 +341,24 @@ void hdmi4_configure(struct hdmi_core_data *core, | |||
431 | hdmi_core_powerdown_disable(core); | 341 | hdmi_core_powerdown_disable(core); |
432 | 342 | ||
433 | v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL; | 343 | v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL; |
434 | v_core_cfg.hdmi_dvi = cfg->cm.mode; | 344 | v_core_cfg.hdmi_dvi = cfg->hdmi_dvi_mode; |
435 | 345 | ||
436 | hdmi_core_video_config(core, &v_core_cfg); | 346 | hdmi_core_video_config(core, &v_core_cfg); |
437 | 347 | ||
438 | /* release software reset in the core */ | 348 | /* release software reset in the core */ |
439 | hdmi_core_swreset_release(core); | 349 | hdmi_core_swreset_release(core); |
440 | 350 | ||
441 | /* | 351 | if (cfg->hdmi_dvi_mode == HDMI_HDMI) { |
442 | * configure packet | 352 | hdmi_core_write_avi_infoframe(core, &cfg->infoframe); |
443 | * info frame video see doc CEA861-D page 65 | 353 | |
444 | */ | 354 | /* enable/repeat the infoframe */ |
445 | avi_cfg->db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB; | 355 | repeat_cfg.avi_infoframe = HDMI_PACKETENABLE; |
446 | avi_cfg->db1_active_info = | 356 | repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON; |
447 | HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF; | 357 | /* wakeup */ |
448 | avi_cfg->db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO; | 358 | repeat_cfg.audio_pkt = HDMI_PACKETENABLE; |
449 | avi_cfg->db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0; | 359 | repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON; |
450 | avi_cfg->db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO; | 360 | } |
451 | avi_cfg->db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO; | ||
452 | avi_cfg->db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME; | ||
453 | avi_cfg->db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO; | ||
454 | avi_cfg->db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601; | ||
455 | avi_cfg->db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT; | ||
456 | avi_cfg->db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO; | ||
457 | avi_cfg->db4_videocode = cfg->cm.code; | ||
458 | avi_cfg->db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO; | ||
459 | avi_cfg->db6_7_line_eoftop = 0; | ||
460 | avi_cfg->db8_9_line_sofbottom = 0; | ||
461 | avi_cfg->db10_11_pixel_eofleft = 0; | ||
462 | avi_cfg->db12_13_pixel_sofright = 0; | ||
463 | |||
464 | hdmi_core_aux_infoframe_avi_config(core); | ||
465 | 361 | ||
466 | /* enable/repeat the infoframe */ | ||
467 | repeat_cfg.avi_infoframe = HDMI_PACKETENABLE; | ||
468 | repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON; | ||
469 | /* wakeup */ | ||
470 | repeat_cfg.audio_pkt = HDMI_PACKETENABLE; | ||
471 | repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON; | ||
472 | hdmi_core_av_packet_config(core, repeat_cfg); | 362 | hdmi_core_av_packet_config(core, repeat_cfg); |
473 | } | 363 | } |
474 | 364 | ||
diff --git a/drivers/video/fbdev/omap2/dss/hdmi4_core.h b/drivers/video/fbdev/omap2/dss/hdmi4_core.h index bb646896fa82..827909eb6c50 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi4_core.h +++ b/drivers/video/fbdev/omap2/dss/hdmi4_core.h | |||
@@ -145,6 +145,7 @@ | |||
145 | #define HDMI_CORE_AV_DPD 0xF4 | 145 | #define HDMI_CORE_AV_DPD 0xF4 |
146 | #define HDMI_CORE_AV_PB_CTRL1 0xF8 | 146 | #define HDMI_CORE_AV_PB_CTRL1 0xF8 |
147 | #define HDMI_CORE_AV_PB_CTRL2 0xFC | 147 | #define HDMI_CORE_AV_PB_CTRL2 0xFC |
148 | #define HDMI_CORE_AV_AVI_BASE 0x100 | ||
148 | #define HDMI_CORE_AV_AVI_TYPE 0x100 | 149 | #define HDMI_CORE_AV_AVI_TYPE 0x100 |
149 | #define HDMI_CORE_AV_AVI_VERS 0x104 | 150 | #define HDMI_CORE_AV_AVI_VERS 0x104 |
150 | #define HDMI_CORE_AV_AVI_LEN 0x108 | 151 | #define HDMI_CORE_AV_AVI_LEN 0x108 |
diff --git a/drivers/video/fbdev/omap2/dss/hdmi5.c b/drivers/video/fbdev/omap2/dss/hdmi5.c index c468b9e1f295..32d02ec34d23 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi5.c +++ b/drivers/video/fbdev/omap2/dss/hdmi5.c | |||
@@ -299,29 +299,11 @@ static int hdmi_display_check_timing(struct omap_dss_device *dssdev, | |||
299 | static void hdmi_display_set_timing(struct omap_dss_device *dssdev, | 299 | static void hdmi_display_set_timing(struct omap_dss_device *dssdev, |
300 | struct omap_video_timings *timings) | 300 | struct omap_video_timings *timings) |
301 | { | 301 | { |
302 | struct hdmi_cm cm; | ||
303 | const struct hdmi_config *t; | ||
304 | |||
305 | mutex_lock(&hdmi.lock); | 302 | mutex_lock(&hdmi.lock); |
306 | 303 | ||
307 | cm = hdmi_get_code(timings); | 304 | hdmi.cfg.timings = *timings; |
308 | hdmi.cfg.cm = cm; | ||
309 | |||
310 | t = hdmi_get_timings(cm.mode, cm.code); | ||
311 | if (t != NULL) { | ||
312 | hdmi.cfg = *t; | ||
313 | |||
314 | dispc_set_tv_pclk(t->timings.pixelclock); | ||
315 | } else { | ||
316 | hdmi.cfg.timings = *timings; | ||
317 | hdmi.cfg.cm.code = 0; | ||
318 | hdmi.cfg.cm.mode = HDMI_DVI; | ||
319 | |||
320 | dispc_set_tv_pclk(timings->pixelclock); | ||
321 | } | ||
322 | 305 | ||
323 | DSSDBG("using mode: %s, code %d\n", hdmi.cfg.cm.mode == HDMI_DVI ? | 306 | dispc_set_tv_pclk(timings->pixelclock); |
324 | "DVI" : "HDMI", hdmi.cfg.cm.code); | ||
325 | 307 | ||
326 | mutex_unlock(&hdmi.lock); | 308 | mutex_unlock(&hdmi.lock); |
327 | } | 309 | } |
@@ -329,14 +311,7 @@ static void hdmi_display_set_timing(struct omap_dss_device *dssdev, | |||
329 | static void hdmi_display_get_timings(struct omap_dss_device *dssdev, | 311 | static void hdmi_display_get_timings(struct omap_dss_device *dssdev, |
330 | struct omap_video_timings *timings) | 312 | struct omap_video_timings *timings) |
331 | { | 313 | { |
332 | const struct hdmi_config *cfg; | 314 | *timings = hdmi.cfg.timings; |
333 | struct hdmi_cm cm = hdmi.cfg.cm; | ||
334 | |||
335 | cfg = hdmi_get_timings(cm.mode, cm.code); | ||
336 | if (cfg == NULL) | ||
337 | cfg = hdmi_default_timing(); | ||
338 | |||
339 | memcpy(timings, &cfg->timings, sizeof(cfg->timings)); | ||
340 | } | 315 | } |
341 | 316 | ||
342 | static void hdmi_dump_regs(struct seq_file *s) | 317 | static void hdmi_dump_regs(struct seq_file *s) |
@@ -541,7 +516,7 @@ static int hdmi_audio_enable(struct omap_dss_device *dssdev) | |||
541 | 516 | ||
542 | mutex_lock(&hdmi.lock); | 517 | mutex_lock(&hdmi.lock); |
543 | 518 | ||
544 | if (!hdmi_mode_has_audio(hdmi.cfg.cm.mode)) { | 519 | if (!hdmi_mode_has_audio(hdmi.cfg.hdmi_dvi_mode)) { |
545 | r = -EPERM; | 520 | r = -EPERM; |
546 | goto err; | 521 | goto err; |
547 | } | 522 | } |
@@ -579,7 +554,7 @@ static bool hdmi_audio_supported(struct omap_dss_device *dssdev) | |||
579 | 554 | ||
580 | mutex_lock(&hdmi.lock); | 555 | mutex_lock(&hdmi.lock); |
581 | 556 | ||
582 | r = hdmi_mode_has_audio(hdmi.cfg.cm.mode); | 557 | r = hdmi_mode_has_audio(hdmi.cfg.hdmi_dvi_mode); |
583 | 558 | ||
584 | mutex_unlock(&hdmi.lock); | 559 | mutex_unlock(&hdmi.lock); |
585 | return r; | 560 | return r; |
@@ -593,7 +568,7 @@ static int hdmi_audio_config(struct omap_dss_device *dssdev, | |||
593 | 568 | ||
594 | mutex_lock(&hdmi.lock); | 569 | mutex_lock(&hdmi.lock); |
595 | 570 | ||
596 | if (!hdmi_mode_has_audio(hdmi.cfg.cm.mode)) { | 571 | if (!hdmi_mode_has_audio(hdmi.cfg.hdmi_dvi_mode)) { |
597 | r = -EPERM; | 572 | r = -EPERM; |
598 | goto err; | 573 | goto err; |
599 | } | 574 | } |
@@ -640,6 +615,20 @@ static int hdmi_audio_config(struct omap_dss_device *dssdev, | |||
640 | } | 615 | } |
641 | #endif | 616 | #endif |
642 | 617 | ||
618 | static int hdmi_set_infoframe(struct omap_dss_device *dssdev, | ||
619 | const struct hdmi_avi_infoframe *avi) | ||
620 | { | ||
621 | hdmi.cfg.infoframe = *avi; | ||
622 | return 0; | ||
623 | } | ||
624 | |||
625 | static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev, | ||
626 | bool hdmi_mode) | ||
627 | { | ||
628 | hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI; | ||
629 | return 0; | ||
630 | } | ||
631 | |||
643 | static const struct omapdss_hdmi_ops hdmi_ops = { | 632 | static const struct omapdss_hdmi_ops hdmi_ops = { |
644 | .connect = hdmi_connect, | 633 | .connect = hdmi_connect, |
645 | .disconnect = hdmi_disconnect, | 634 | .disconnect = hdmi_disconnect, |
@@ -652,6 +641,8 @@ static const struct omapdss_hdmi_ops hdmi_ops = { | |||
652 | .get_timings = hdmi_display_get_timings, | 641 | .get_timings = hdmi_display_get_timings, |
653 | 642 | ||
654 | .read_edid = hdmi_read_edid, | 643 | .read_edid = hdmi_read_edid, |
644 | .set_infoframe = hdmi_set_infoframe, | ||
645 | .set_hdmi_mode = hdmi_set_hdmi_mode, | ||
655 | 646 | ||
656 | .audio_enable = hdmi_audio_enable, | 647 | .audio_enable = hdmi_audio_enable, |
657 | .audio_disable = hdmi_audio_disable, | 648 | .audio_disable = hdmi_audio_disable, |
diff --git a/drivers/video/fbdev/omap2/dss/hdmi5_core.c b/drivers/video/fbdev/omap2/dss/hdmi5_core.c index 7528c7a42aa5..83acbf7a8c89 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi5_core.c +++ b/drivers/video/fbdev/omap2/dss/hdmi5_core.c | |||
@@ -290,7 +290,6 @@ void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s) | |||
290 | } | 290 | } |
291 | 291 | ||
292 | static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg, | 292 | static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg, |
293 | struct hdmi_core_infoframe_avi *avi_cfg, | ||
294 | struct hdmi_config *cfg) | 293 | struct hdmi_config *cfg) |
295 | { | 294 | { |
296 | DSSDBG("hdmi_core_init\n"); | 295 | DSSDBG("hdmi_core_init\n"); |
@@ -312,27 +311,8 @@ static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg, | |||
312 | video_cfg->vblank_osc = 0; /* Always 0 - need to confirm */ | 311 | video_cfg->vblank_osc = 0; /* Always 0 - need to confirm */ |
313 | video_cfg->vblank = cfg->timings.vsw + | 312 | video_cfg->vblank = cfg->timings.vsw + |
314 | cfg->timings.vfp + cfg->timings.vbp; | 313 | cfg->timings.vfp + cfg->timings.vbp; |
315 | video_cfg->v_fc_config.cm.mode = cfg->cm.mode; | 314 | video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode; |
316 | video_cfg->v_fc_config.timings.interlace = cfg->timings.interlace; | 315 | video_cfg->v_fc_config.timings.interlace = cfg->timings.interlace; |
317 | |||
318 | /* info frame */ | ||
319 | avi_cfg->db1_format = 0; | ||
320 | avi_cfg->db1_active_info = 0; | ||
321 | avi_cfg->db1_bar_info_dv = 0; | ||
322 | avi_cfg->db1_scan_info = 0; | ||
323 | avi_cfg->db2_colorimetry = 0; | ||
324 | avi_cfg->db2_aspect_ratio = 0; | ||
325 | avi_cfg->db2_active_fmt_ar = 0; | ||
326 | avi_cfg->db3_itc = 0; | ||
327 | avi_cfg->db3_ec = 0; | ||
328 | avi_cfg->db3_q_range = 0; | ||
329 | avi_cfg->db3_nup_scaling = 0; | ||
330 | avi_cfg->db4_videocode = 0; | ||
331 | avi_cfg->db5_pixel_repeat = 0; | ||
332 | avi_cfg->db6_7_line_eoftop = 0; | ||
333 | avi_cfg->db8_9_line_sofbottom = 0; | ||
334 | avi_cfg->db10_11_pixel_eofleft = 0; | ||
335 | avi_cfg->db12_13_pixel_sofright = 0; | ||
336 | } | 316 | } |
337 | 317 | ||
338 | /* DSS_HDMI_CORE_VIDEO_CONFIG */ | 318 | /* DSS_HDMI_CORE_VIDEO_CONFIG */ |
@@ -398,7 +378,7 @@ static void hdmi_core_video_config(struct hdmi_core_data *core, | |||
398 | 378 | ||
399 | /* select DVI mode */ | 379 | /* select DVI mode */ |
400 | REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF, | 380 | REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF, |
401 | cfg->v_fc_config.cm.mode, 3, 3); | 381 | cfg->v_fc_config.hdmi_dvi_mode, 3, 3); |
402 | } | 382 | } |
403 | 383 | ||
404 | static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core) | 384 | static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core) |
@@ -438,24 +418,60 @@ static void hdmi_core_config_video_sampler(struct hdmi_core_data *core) | |||
438 | REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0); | 418 | REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0); |
439 | } | 419 | } |
440 | 420 | ||
441 | static void hdmi_core_aux_infoframe_avi_config(struct hdmi_core_data *core) | 421 | static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core, |
422 | struct hdmi_avi_infoframe *frame) | ||
442 | { | 423 | { |
443 | void __iomem *base = core->base; | 424 | void __iomem *base = core->base; |
444 | struct hdmi_core_infoframe_avi avi = core->avi_cfg; | 425 | u8 data[HDMI_INFOFRAME_SIZE(AVI)]; |
445 | 426 | u8 *ptr; | |
446 | REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF0, avi.db1_format, 1, 0); | 427 | unsigned y, a, b, s; |
447 | REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF0, avi.db1_active_info, 6, 6); | 428 | unsigned c, m, r; |
448 | REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF0, avi.db1_bar_info_dv, 3, 2); | 429 | unsigned itc, ec, q, sc; |
449 | REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF0, avi.db1_scan_info, 5, 4); | 430 | unsigned vic; |
450 | REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF1, avi.db2_colorimetry, 7, 6); | 431 | unsigned yq, cn, pr; |
451 | REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF1, avi.db2_aspect_ratio, 5, 4); | 432 | |
452 | REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF1, avi.db2_active_fmt_ar, 3, 0); | 433 | hdmi_avi_infoframe_pack(frame, data, sizeof(data)); |
453 | REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF2, avi.db3_itc, 7, 7); | 434 | |
454 | REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF2, avi.db3_ec, 6, 4); | 435 | print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data, |
455 | REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF2, avi.db3_q_range, 3, 2); | 436 | HDMI_INFOFRAME_SIZE(AVI), false); |
456 | REG_FLD_MOD(base, HDMI_CORE_FC_AVICONF2, avi.db3_nup_scaling, 1, 0); | 437 | |
457 | REG_FLD_MOD(base, HDMI_CORE_FC_AVIVID, avi.db4_videocode, 6, 0); | 438 | ptr = data + HDMI_INFOFRAME_HEADER_SIZE; |
458 | REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, avi.db5_pixel_repeat, 3, 0); | 439 | |
440 | y = (ptr[0] >> 5) & 0x3; | ||
441 | a = (ptr[0] >> 4) & 0x1; | ||
442 | b = (ptr[0] >> 2) & 0x3; | ||
443 | s = (ptr[0] >> 0) & 0x3; | ||
444 | |||
445 | c = (ptr[1] >> 6) & 0x3; | ||
446 | m = (ptr[1] >> 4) & 0x3; | ||
447 | r = (ptr[1] >> 0) & 0x3; | ||
448 | |||
449 | itc = (ptr[2] >> 7) & 0x1; | ||
450 | ec = (ptr[2] >> 4) & 0x7; | ||
451 | q = (ptr[2] >> 2) & 0x3; | ||
452 | sc = (ptr[2] >> 0) & 0x3; | ||
453 | |||
454 | vic = ptr[3]; | ||
455 | |||
456 | yq = (ptr[4] >> 6) & 0x3; | ||
457 | cn = (ptr[4] >> 4) & 0x3; | ||
458 | pr = (ptr[4] >> 0) & 0xf; | ||
459 | |||
460 | hdmi_write_reg(base, HDMI_CORE_FC_AVICONF0, | ||
461 | (a << 6) | (s << 4) | (b << 2) | (y << 0)); | ||
462 | |||
463 | hdmi_write_reg(base, HDMI_CORE_FC_AVICONF1, | ||
464 | (c << 6) | (m << 4) | (r << 0)); | ||
465 | |||
466 | hdmi_write_reg(base, HDMI_CORE_FC_AVICONF2, | ||
467 | (itc << 7) | (ec << 4) | (q << 2) | (sc << 0)); | ||
468 | |||
469 | hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic); | ||
470 | |||
471 | hdmi_write_reg(base, HDMI_CORE_FC_AVICONF3, | ||
472 | (yq << 2) | (cn << 0)); | ||
473 | |||
474 | REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0); | ||
459 | } | 475 | } |
460 | 476 | ||
461 | static void hdmi_core_csc_config(struct hdmi_core_data *core, | 477 | static void hdmi_core_csc_config(struct hdmi_core_data *core, |
@@ -497,10 +513,8 @@ static void hdmi_core_configure_range(struct hdmi_core_data *core) | |||
497 | 513 | ||
498 | /* support limited range with 24 bit color depth for now */ | 514 | /* support limited range with 24 bit color depth for now */ |
499 | csc_coeff = csc_table_deepcolor[0]; | 515 | csc_coeff = csc_table_deepcolor[0]; |
500 | core->avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_LR; | ||
501 | 516 | ||
502 | hdmi_core_csc_config(core, csc_coeff); | 517 | hdmi_core_csc_config(core, csc_coeff); |
503 | hdmi_core_aux_infoframe_avi_config(core); | ||
504 | } | 518 | } |
505 | 519 | ||
506 | static void hdmi_core_enable_video_path(struct hdmi_core_data *core) | 520 | static void hdmi_core_enable_video_path(struct hdmi_core_data *core) |
@@ -591,11 +605,10 @@ void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, | |||
591 | struct omap_video_timings video_timing; | 605 | struct omap_video_timings video_timing; |
592 | struct hdmi_video_format video_format; | 606 | struct hdmi_video_format video_format; |
593 | struct hdmi_core_vid_config v_core_cfg; | 607 | struct hdmi_core_vid_config v_core_cfg; |
594 | struct hdmi_core_infoframe_avi *avi_cfg = &core->avi_cfg; | ||
595 | 608 | ||
596 | hdmi_core_mask_interrupts(core); | 609 | hdmi_core_mask_interrupts(core); |
597 | 610 | ||
598 | hdmi_core_init(&v_core_cfg, avi_cfg, cfg); | 611 | hdmi_core_init(&v_core_cfg, cfg); |
599 | 612 | ||
600 | hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg); | 613 | hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg); |
601 | 614 | ||
@@ -608,7 +621,9 @@ void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, | |||
608 | 621 | ||
609 | hdmi_wp_video_config_interface(wp, &video_timing); | 622 | hdmi_wp_video_config_interface(wp, &video_timing); |
610 | 623 | ||
624 | /* support limited range with 24 bit color depth for now */ | ||
611 | hdmi_core_configure_range(core); | 625 | hdmi_core_configure_range(core); |
626 | cfg->infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_LIMITED; | ||
612 | 627 | ||
613 | /* | 628 | /* |
614 | * configure core video part, set software reset in the core | 629 | * configure core video part, set software reset in the core |
@@ -621,29 +636,8 @@ void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, | |||
621 | hdmi_core_config_csc(core); | 636 | hdmi_core_config_csc(core); |
622 | hdmi_core_config_video_sampler(core); | 637 | hdmi_core_config_video_sampler(core); |
623 | 638 | ||
624 | /* | 639 | if (cfg->hdmi_dvi_mode == HDMI_HDMI) |
625 | * configure packet info frame video see doc CEA861-D page 65 | 640 | hdmi_core_write_avi_infoframe(core, &cfg->infoframe); |
626 | */ | ||
627 | avi_cfg->db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB; | ||
628 | avi_cfg->db1_active_info = | ||
629 | HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF; | ||
630 | avi_cfg->db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO; | ||
631 | avi_cfg->db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0; | ||
632 | avi_cfg->db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO; | ||
633 | avi_cfg->db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO; | ||
634 | avi_cfg->db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME; | ||
635 | avi_cfg->db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO; | ||
636 | avi_cfg->db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601; | ||
637 | avi_cfg->db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT; | ||
638 | avi_cfg->db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO; | ||
639 | avi_cfg->db4_videocode = cfg->cm.code; | ||
640 | avi_cfg->db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO; | ||
641 | avi_cfg->db6_7_line_eoftop = 0; | ||
642 | avi_cfg->db8_9_line_sofbottom = 0; | ||
643 | avi_cfg->db10_11_pixel_eofleft = 0; | ||
644 | avi_cfg->db12_13_pixel_sofright = 0; | ||
645 | |||
646 | hdmi_core_aux_infoframe_avi_config(core); | ||
647 | 641 | ||
648 | hdmi_core_enable_video_path(core); | 642 | hdmi_core_enable_video_path(core); |
649 | 643 | ||
diff --git a/drivers/video/fbdev/omap2/dss/hdmi_common.c b/drivers/video/fbdev/omap2/dss/hdmi_common.c index 9a2c39cf297f..7d5f1039de9f 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi_common.c +++ b/drivers/video/fbdev/omap2/dss/hdmi_common.c | |||
@@ -1,18 +1,4 @@ | |||
1 | 1 | ||
2 | /* | ||
3 | * Logic for the below structure : | ||
4 | * user enters the CEA or VESA timings by specifying the HDMI/DVI code. | ||
5 | * There is a correspondence between CEA/VESA timing and code, please | ||
6 | * refer to section 6.3 in HDMI 1.3 specification for timing code. | ||
7 | * | ||
8 | * In the below structure, cea_vesa_timings corresponds to all OMAP4 | ||
9 | * supported CEA and VESA timing values.code_cea corresponds to the CEA | ||
10 | * code, It is used to get the timing from cea_vesa_timing array.Similarly | ||
11 | * with code_vesa. Code_index is used for back mapping, that is once EDID | ||
12 | * is read from the TV, EDID is parsed to find the timing values and then | ||
13 | * map it to corresponding CEA or VESA index. | ||
14 | */ | ||
15 | |||
16 | #define DSS_SUBSYS_NAME "HDMI" | 2 | #define DSS_SUBSYS_NAME "HDMI" |
17 | 3 | ||
18 | #include <linux/kernel.h> | 4 | #include <linux/kernel.h> |
@@ -22,308 +8,6 @@ | |||
22 | 8 | ||
23 | #include "hdmi.h" | 9 | #include "hdmi.h" |
24 | 10 | ||
25 | static const struct hdmi_config cea_timings[] = { | ||
26 | { | ||
27 | { 640, 480, 25200000, 96, 16, 48, 2, 10, 33, | ||
28 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
29 | false, }, | ||
30 | { 1, HDMI_HDMI }, | ||
31 | }, | ||
32 | { | ||
33 | { 720, 480, 27027000, 62, 16, 60, 6, 9, 30, | ||
34 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
35 | false, }, | ||
36 | { 2, HDMI_HDMI }, | ||
37 | }, | ||
38 | { | ||
39 | { 1280, 720, 74250000, 40, 110, 220, 5, 5, 20, | ||
40 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
41 | false, }, | ||
42 | { 4, HDMI_HDMI }, | ||
43 | }, | ||
44 | { | ||
45 | { 1920, 540, 74250000, 44, 88, 148, 5, 2, 15, | ||
46 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
47 | true, }, | ||
48 | { 5, HDMI_HDMI }, | ||
49 | }, | ||
50 | { | ||
51 | { 1440, 240, 27027000, 124, 38, 114, 3, 4, 15, | ||
52 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
53 | true, }, | ||
54 | { 6, HDMI_HDMI }, | ||
55 | }, | ||
56 | { | ||
57 | { 1920, 1080, 148500000, 44, 88, 148, 5, 4, 36, | ||
58 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
59 | false, }, | ||
60 | { 16, HDMI_HDMI }, | ||
61 | }, | ||
62 | { | ||
63 | { 720, 576, 27000000, 64, 12, 68, 5, 5, 39, | ||
64 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
65 | false, }, | ||
66 | { 17, HDMI_HDMI }, | ||
67 | }, | ||
68 | { | ||
69 | { 1280, 720, 74250000, 40, 440, 220, 5, 5, 20, | ||
70 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
71 | false, }, | ||
72 | { 19, HDMI_HDMI }, | ||
73 | }, | ||
74 | { | ||
75 | { 1920, 540, 74250000, 44, 528, 148, 5, 2, 15, | ||
76 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
77 | true, }, | ||
78 | { 20, HDMI_HDMI }, | ||
79 | }, | ||
80 | { | ||
81 | { 1440, 288, 27000000, 126, 24, 138, 3, 2, 19, | ||
82 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
83 | true, }, | ||
84 | { 21, HDMI_HDMI }, | ||
85 | }, | ||
86 | { | ||
87 | { 1440, 576, 54000000, 128, 24, 136, 5, 5, 39, | ||
88 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
89 | false, }, | ||
90 | { 29, HDMI_HDMI }, | ||
91 | }, | ||
92 | { | ||
93 | { 1920, 1080, 148500000, 44, 528, 148, 5, 4, 36, | ||
94 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
95 | false, }, | ||
96 | { 31, HDMI_HDMI }, | ||
97 | }, | ||
98 | { | ||
99 | { 1920, 1080, 74250000, 44, 638, 148, 5, 4, 36, | ||
100 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
101 | false, }, | ||
102 | { 32, HDMI_HDMI }, | ||
103 | }, | ||
104 | { | ||
105 | { 2880, 480, 108108000, 248, 64, 240, 6, 9, 30, | ||
106 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
107 | false, }, | ||
108 | { 35, HDMI_HDMI }, | ||
109 | }, | ||
110 | { | ||
111 | { 2880, 576, 108000000, 256, 48, 272, 5, 5, 39, | ||
112 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
113 | false, }, | ||
114 | { 37, HDMI_HDMI }, | ||
115 | }, | ||
116 | }; | ||
117 | |||
118 | static const struct hdmi_config vesa_timings[] = { | ||
119 | /* VESA From Here */ | ||
120 | { | ||
121 | { 640, 480, 25175000, 96, 16, 48, 2, 11, 31, | ||
122 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
123 | false, }, | ||
124 | { 4, HDMI_DVI }, | ||
125 | }, | ||
126 | { | ||
127 | { 800, 600, 40000000, 128, 40, 88, 4, 1, 23, | ||
128 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
129 | false, }, | ||
130 | { 9, HDMI_DVI }, | ||
131 | }, | ||
132 | { | ||
133 | { 848, 480, 33750000, 112, 16, 112, 8, 6, 23, | ||
134 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
135 | false, }, | ||
136 | { 0xE, HDMI_DVI }, | ||
137 | }, | ||
138 | { | ||
139 | { 1280, 768, 79500000, 128, 64, 192, 7, 3, 20, | ||
140 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | ||
141 | false, }, | ||
142 | { 0x17, HDMI_DVI }, | ||
143 | }, | ||
144 | { | ||
145 | { 1280, 800, 83500000, 128, 72, 200, 6, 3, 22, | ||
146 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | ||
147 | false, }, | ||
148 | { 0x1C, HDMI_DVI }, | ||
149 | }, | ||
150 | { | ||
151 | { 1360, 768, 85500000, 112, 64, 256, 6, 3, 18, | ||
152 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
153 | false, }, | ||
154 | { 0x27, HDMI_DVI }, | ||
155 | }, | ||
156 | { | ||
157 | { 1280, 960, 108000000, 112, 96, 312, 3, 1, 36, | ||
158 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
159 | false, }, | ||
160 | { 0x20, HDMI_DVI }, | ||
161 | }, | ||
162 | { | ||
163 | { 1280, 1024, 108000000, 112, 48, 248, 3, 1, 38, | ||
164 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
165 | false, }, | ||
166 | { 0x23, HDMI_DVI }, | ||
167 | }, | ||
168 | { | ||
169 | { 1024, 768, 65000000, 136, 24, 160, 6, 3, 29, | ||
170 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | ||
171 | false, }, | ||
172 | { 0x10, HDMI_DVI }, | ||
173 | }, | ||
174 | { | ||
175 | { 1400, 1050, 121750000, 144, 88, 232, 4, 3, 32, | ||
176 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | ||
177 | false, }, | ||
178 | { 0x2A, HDMI_DVI }, | ||
179 | }, | ||
180 | { | ||
181 | { 1440, 900, 106500000, 152, 80, 232, 6, 3, 25, | ||
182 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | ||
183 | false, }, | ||
184 | { 0x2F, HDMI_DVI }, | ||
185 | }, | ||
186 | { | ||
187 | { 1680, 1050, 146250000, 176 , 104, 280, 6, 3, 30, | ||
188 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | ||
189 | false, }, | ||
190 | { 0x3A, HDMI_DVI }, | ||
191 | }, | ||
192 | { | ||
193 | { 1366, 768, 85500000, 143, 70, 213, 3, 3, 24, | ||
194 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
195 | false, }, | ||
196 | { 0x51, HDMI_DVI }, | ||
197 | }, | ||
198 | { | ||
199 | { 1920, 1080, 148500000, 44, 148, 80, 5, 4, 36, | ||
200 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
201 | false, }, | ||
202 | { 0x52, HDMI_DVI }, | ||
203 | }, | ||
204 | { | ||
205 | { 1280, 768, 68250000, 32, 48, 80, 7, 3, 12, | ||
206 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | ||
207 | false, }, | ||
208 | { 0x16, HDMI_DVI }, | ||
209 | }, | ||
210 | { | ||
211 | { 1400, 1050, 101000000, 32, 48, 80, 4, 3, 23, | ||
212 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | ||
213 | false, }, | ||
214 | { 0x29, HDMI_DVI }, | ||
215 | }, | ||
216 | { | ||
217 | { 1680, 1050, 119000000, 32, 48, 80, 6, 3, 21, | ||
218 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | ||
219 | false, }, | ||
220 | { 0x39, HDMI_DVI }, | ||
221 | }, | ||
222 | { | ||
223 | { 1280, 800, 79500000, 32, 48, 80, 6, 3, 14, | ||
224 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | ||
225 | false, }, | ||
226 | { 0x1B, HDMI_DVI }, | ||
227 | }, | ||
228 | { | ||
229 | { 1280, 720, 74250000, 40, 110, 220, 5, 5, 20, | ||
230 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | ||
231 | false, }, | ||
232 | { 0x55, HDMI_DVI }, | ||
233 | }, | ||
234 | { | ||
235 | { 1920, 1200, 154000000, 32, 48, 80, 6, 3, 26, | ||
236 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | ||
237 | false, }, | ||
238 | { 0x44, HDMI_DVI }, | ||
239 | }, | ||
240 | }; | ||
241 | |||
242 | const struct hdmi_config *hdmi_default_timing(void) | ||
243 | { | ||
244 | return &vesa_timings[0]; | ||
245 | } | ||
246 | |||
247 | static const struct hdmi_config *hdmi_find_timing(int code, | ||
248 | const struct hdmi_config *timings_arr, int len) | ||
249 | { | ||
250 | int i; | ||
251 | |||
252 | for (i = 0; i < len; i++) { | ||
253 | if (timings_arr[i].cm.code == code) | ||
254 | return &timings_arr[i]; | ||
255 | } | ||
256 | |||
257 | return NULL; | ||
258 | } | ||
259 | |||
260 | const struct hdmi_config *hdmi_get_timings(int mode, int code) | ||
261 | { | ||
262 | const struct hdmi_config *arr; | ||
263 | int len; | ||
264 | |||
265 | if (mode == HDMI_DVI) { | ||
266 | arr = vesa_timings; | ||
267 | len = ARRAY_SIZE(vesa_timings); | ||
268 | } else { | ||
269 | arr = cea_timings; | ||
270 | len = ARRAY_SIZE(cea_timings); | ||
271 | } | ||
272 | |||
273 | return hdmi_find_timing(code, arr, len); | ||
274 | } | ||
275 | |||
276 | static bool hdmi_timings_compare(struct omap_video_timings *timing1, | ||
277 | const struct omap_video_timings *timing2) | ||
278 | { | ||
279 | int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync; | ||
280 | |||
281 | if ((DIV_ROUND_CLOSEST(timing2->pixelclock, 1000000) == | ||
282 | DIV_ROUND_CLOSEST(timing1->pixelclock, 1000000)) && | ||
283 | (timing2->x_res == timing1->x_res) && | ||
284 | (timing2->y_res == timing1->y_res)) { | ||
285 | |||
286 | timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp; | ||
287 | timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp; | ||
288 | timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp; | ||
289 | timing1_vsync = timing1->vfp + timing1->vsw + timing1->vbp; | ||
290 | |||
291 | DSSDBG("timing1_hsync = %d timing1_vsync = %d"\ | ||
292 | "timing2_hsync = %d timing2_vsync = %d\n", | ||
293 | timing1_hsync, timing1_vsync, | ||
294 | timing2_hsync, timing2_vsync); | ||
295 | |||
296 | if ((timing1_hsync == timing2_hsync) && | ||
297 | (timing1_vsync == timing2_vsync)) { | ||
298 | return true; | ||
299 | } | ||
300 | } | ||
301 | return false; | ||
302 | } | ||
303 | |||
304 | struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing) | ||
305 | { | ||
306 | int i; | ||
307 | struct hdmi_cm cm = {-1}; | ||
308 | DSSDBG("hdmi_get_code\n"); | ||
309 | |||
310 | for (i = 0; i < ARRAY_SIZE(cea_timings); i++) { | ||
311 | if (hdmi_timings_compare(timing, &cea_timings[i].timings)) { | ||
312 | cm = cea_timings[i].cm; | ||
313 | goto end; | ||
314 | } | ||
315 | } | ||
316 | for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) { | ||
317 | if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) { | ||
318 | cm = vesa_timings[i].cm; | ||
319 | goto end; | ||
320 | } | ||
321 | } | ||
322 | |||
323 | end: | ||
324 | return cm; | ||
325 | } | ||
326 | |||
327 | int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep, | 11 | int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep, |
328 | struct hdmi_phy_data *phy) | 12 | struct hdmi_phy_data *phy) |
329 | { | 13 | { |
diff --git a/drivers/video/fbdev/riva/fbdev.c b/drivers/video/fbdev/riva/fbdev.c index 8a8d7f060784..be73727c7227 100644 --- a/drivers/video/fbdev/riva/fbdev.c +++ b/drivers/video/fbdev/riva/fbdev.c | |||
@@ -326,13 +326,7 @@ static int riva_bl_update_status(struct backlight_device *bd) | |||
326 | return 0; | 326 | return 0; |
327 | } | 327 | } |
328 | 328 | ||
329 | static int riva_bl_get_brightness(struct backlight_device *bd) | ||
330 | { | ||
331 | return bd->props.brightness; | ||
332 | } | ||
333 | |||
334 | static const struct backlight_ops riva_bl_ops = { | 329 | static const struct backlight_ops riva_bl_ops = { |
335 | .get_brightness = riva_bl_get_brightness, | ||
336 | .update_status = riva_bl_update_status, | 330 | .update_status = riva_bl_update_status, |
337 | }; | 331 | }; |
338 | 332 | ||
diff --git a/drivers/video/fbdev/s3c-fb.c b/drivers/video/fbdev/s3c-fb.c index 62acae2694a9..b33abb0a433d 100644 --- a/drivers/video/fbdev/s3c-fb.c +++ b/drivers/video/fbdev/s3c-fb.c | |||
@@ -1805,38 +1805,6 @@ static struct s3c_fb_driverdata s3c_fb_data_64xx = { | |||
1805 | .win[4] = &s3c_fb_data_64xx_wins[4], | 1805 | .win[4] = &s3c_fb_data_64xx_wins[4], |
1806 | }; | 1806 | }; |
1807 | 1807 | ||
1808 | static struct s3c_fb_driverdata s3c_fb_data_s5pc100 = { | ||
1809 | .variant = { | ||
1810 | .nr_windows = 5, | ||
1811 | .vidtcon = VIDTCON0, | ||
1812 | .wincon = WINCON(0), | ||
1813 | .winmap = WINxMAP(0), | ||
1814 | .keycon = WKEYCON, | ||
1815 | .osd = VIDOSD_BASE, | ||
1816 | .osd_stride = 16, | ||
1817 | .buf_start = VIDW_BUF_START(0), | ||
1818 | .buf_size = VIDW_BUF_SIZE(0), | ||
1819 | .buf_end = VIDW_BUF_END(0), | ||
1820 | |||
1821 | .palette = { | ||
1822 | [0] = 0x2400, | ||
1823 | [1] = 0x2800, | ||
1824 | [2] = 0x2c00, | ||
1825 | [3] = 0x3000, | ||
1826 | [4] = 0x3400, | ||
1827 | }, | ||
1828 | |||
1829 | .has_prtcon = 1, | ||
1830 | .has_blendcon = 1, | ||
1831 | .has_clksel = 1, | ||
1832 | }, | ||
1833 | .win[0] = &s3c_fb_data_s5p_wins[0], | ||
1834 | .win[1] = &s3c_fb_data_s5p_wins[1], | ||
1835 | .win[2] = &s3c_fb_data_s5p_wins[2], | ||
1836 | .win[3] = &s3c_fb_data_s5p_wins[3], | ||
1837 | .win[4] = &s3c_fb_data_s5p_wins[4], | ||
1838 | }; | ||
1839 | |||
1840 | static struct s3c_fb_driverdata s3c_fb_data_s5pv210 = { | 1808 | static struct s3c_fb_driverdata s3c_fb_data_s5pv210 = { |
1841 | .variant = { | 1809 | .variant = { |
1842 | .nr_windows = 5, | 1810 | .nr_windows = 5, |
@@ -1970,41 +1938,11 @@ static struct s3c_fb_driverdata s3c_fb_data_s3c2443 = { | |||
1970 | }, | 1938 | }, |
1971 | }; | 1939 | }; |
1972 | 1940 | ||
1973 | static struct s3c_fb_driverdata s3c_fb_data_s5p64x0 = { | ||
1974 | .variant = { | ||
1975 | .nr_windows = 3, | ||
1976 | .vidtcon = VIDTCON0, | ||
1977 | .wincon = WINCON(0), | ||
1978 | .winmap = WINxMAP(0), | ||
1979 | .keycon = WKEYCON, | ||
1980 | .osd = VIDOSD_BASE, | ||
1981 | .osd_stride = 16, | ||
1982 | .buf_start = VIDW_BUF_START(0), | ||
1983 | .buf_size = VIDW_BUF_SIZE(0), | ||
1984 | .buf_end = VIDW_BUF_END(0), | ||
1985 | |||
1986 | .palette = { | ||
1987 | [0] = 0x2400, | ||
1988 | [1] = 0x2800, | ||
1989 | [2] = 0x2c00, | ||
1990 | }, | ||
1991 | |||
1992 | .has_blendcon = 1, | ||
1993 | .has_fixvclk = 1, | ||
1994 | }, | ||
1995 | .win[0] = &s3c_fb_data_s5p_wins[0], | ||
1996 | .win[1] = &s3c_fb_data_s5p_wins[1], | ||
1997 | .win[2] = &s3c_fb_data_s5p_wins[2], | ||
1998 | }; | ||
1999 | |||
2000 | static struct platform_device_id s3c_fb_driver_ids[] = { | 1941 | static struct platform_device_id s3c_fb_driver_ids[] = { |
2001 | { | 1942 | { |
2002 | .name = "s3c-fb", | 1943 | .name = "s3c-fb", |
2003 | .driver_data = (unsigned long)&s3c_fb_data_64xx, | 1944 | .driver_data = (unsigned long)&s3c_fb_data_64xx, |
2004 | }, { | 1945 | }, { |
2005 | .name = "s5pc100-fb", | ||
2006 | .driver_data = (unsigned long)&s3c_fb_data_s5pc100, | ||
2007 | }, { | ||
2008 | .name = "s5pv210-fb", | 1946 | .name = "s5pv210-fb", |
2009 | .driver_data = (unsigned long)&s3c_fb_data_s5pv210, | 1947 | .driver_data = (unsigned long)&s3c_fb_data_s5pv210, |
2010 | }, { | 1948 | }, { |
@@ -2016,9 +1954,6 @@ static struct platform_device_id s3c_fb_driver_ids[] = { | |||
2016 | }, { | 1954 | }, { |
2017 | .name = "s3c2443-fb", | 1955 | .name = "s3c2443-fb", |
2018 | .driver_data = (unsigned long)&s3c_fb_data_s3c2443, | 1956 | .driver_data = (unsigned long)&s3c_fb_data_s3c2443, |
2019 | }, { | ||
2020 | .name = "s5p64x0-fb", | ||
2021 | .driver_data = (unsigned long)&s3c_fb_data_s5p64x0, | ||
2022 | }, | 1957 | }, |
2023 | {}, | 1958 | {}, |
2024 | }; | 1959 | }; |
diff --git a/drivers/video/fbdev/s3c2410fb.c b/drivers/video/fbdev/s3c2410fb.c index 81af5a63e9e1..43c63a4f3178 100644 --- a/drivers/video/fbdev/s3c2410fb.c +++ b/drivers/video/fbdev/s3c2410fb.c | |||
@@ -616,7 +616,7 @@ static int s3c2410fb_debug_store(struct device *dev, | |||
616 | return len; | 616 | return len; |
617 | } | 617 | } |
618 | 618 | ||
619 | static DEVICE_ATTR(debug, 0666, s3c2410fb_debug_show, s3c2410fb_debug_store); | 619 | static DEVICE_ATTR(debug, 0664, s3c2410fb_debug_show, s3c2410fb_debug_store); |
620 | 620 | ||
621 | static struct fb_ops s3c2410fb_ops = { | 621 | static struct fb_ops s3c2410fb_ops = { |
622 | .owner = THIS_MODULE, | 622 | .owner = THIS_MODULE, |
@@ -932,7 +932,7 @@ static int s3c24xxfb_probe(struct platform_device *pdev, | |||
932 | goto release_irq; | 932 | goto release_irq; |
933 | } | 933 | } |
934 | 934 | ||
935 | clk_enable(info->clk); | 935 | clk_prepare_enable(info->clk); |
936 | dprintk("got and enabled clock\n"); | 936 | dprintk("got and enabled clock\n"); |
937 | 937 | ||
938 | usleep_range(1000, 1100); | 938 | usleep_range(1000, 1100); |
@@ -996,7 +996,7 @@ static int s3c24xxfb_probe(struct platform_device *pdev, | |||
996 | free_video_memory: | 996 | free_video_memory: |
997 | s3c2410fb_unmap_video_memory(fbinfo); | 997 | s3c2410fb_unmap_video_memory(fbinfo); |
998 | release_clock: | 998 | release_clock: |
999 | clk_disable(info->clk); | 999 | clk_disable_unprepare(info->clk); |
1000 | clk_put(info->clk); | 1000 | clk_put(info->clk); |
1001 | release_irq: | 1001 | release_irq: |
1002 | free_irq(irq, info); | 1002 | free_irq(irq, info); |
@@ -1038,7 +1038,7 @@ static int s3c2410fb_remove(struct platform_device *pdev) | |||
1038 | s3c2410fb_unmap_video_memory(fbinfo); | 1038 | s3c2410fb_unmap_video_memory(fbinfo); |
1039 | 1039 | ||
1040 | if (info->clk) { | 1040 | if (info->clk) { |
1041 | clk_disable(info->clk); | 1041 | clk_disable_unprepare(info->clk); |
1042 | clk_put(info->clk); | 1042 | clk_put(info->clk); |
1043 | info->clk = NULL; | 1043 | info->clk = NULL; |
1044 | } | 1044 | } |
@@ -1070,7 +1070,7 @@ static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state) | |||
1070 | * before the clock goes off again (bjd) */ | 1070 | * before the clock goes off again (bjd) */ |
1071 | 1071 | ||
1072 | usleep_range(1000, 1100); | 1072 | usleep_range(1000, 1100); |
1073 | clk_disable(info->clk); | 1073 | clk_disable_unprepare(info->clk); |
1074 | 1074 | ||
1075 | return 0; | 1075 | return 0; |
1076 | } | 1076 | } |
@@ -1080,7 +1080,7 @@ static int s3c2410fb_resume(struct platform_device *dev) | |||
1080 | struct fb_info *fbinfo = platform_get_drvdata(dev); | 1080 | struct fb_info *fbinfo = platform_get_drvdata(dev); |
1081 | struct s3c2410fb_info *info = fbinfo->par; | 1081 | struct s3c2410fb_info *info = fbinfo->par; |
1082 | 1082 | ||
1083 | clk_enable(info->clk); | 1083 | clk_prepare_enable(info->clk); |
1084 | usleep_range(1000, 1100); | 1084 | usleep_range(1000, 1100); |
1085 | 1085 | ||
1086 | s3c2410fb_init_registers(fbinfo); | 1086 | s3c2410fb_init_registers(fbinfo); |
diff --git a/drivers/video/fbdev/sis/init.c b/drivers/video/fbdev/sis/init.c index bd40f5ecd901..dfe3eb769638 100644 --- a/drivers/video/fbdev/sis/init.c +++ b/drivers/video/fbdev/sis/init.c | |||
@@ -1511,7 +1511,7 @@ SiS_Get310DRAMType(struct SiS_Private *SiS_Pr) | |||
1511 | } else if(SiS_Pr->ChipType >= SIS_340) { | 1511 | } else if(SiS_Pr->ChipType >= SIS_340) { |
1512 | /* TODO */ | 1512 | /* TODO */ |
1513 | data = 0; | 1513 | data = 0; |
1514 | } if(SiS_Pr->ChipType >= SIS_661) { | 1514 | } else if(SiS_Pr->ChipType >= SIS_661) { |
1515 | if(SiS_Pr->SiS_ROMNew) { | 1515 | if(SiS_Pr->SiS_ROMNew) { |
1516 | data = ((SiS_GetReg(SiS_Pr->SiS_P3d4,0x78) & 0xc0) >> 6); | 1516 | data = ((SiS_GetReg(SiS_Pr->SiS_P3d4,0x78) & 0xc0) >> 6); |
1517 | } else { | 1517 | } else { |
diff --git a/drivers/video/fbdev/sis/sis_main.c b/drivers/video/fbdev/sis/sis_main.c index 22ad028bf123..3f12a2dd959a 100644 --- a/drivers/video/fbdev/sis/sis_main.c +++ b/drivers/video/fbdev/sis/sis_main.c | |||
@@ -1572,10 +1572,6 @@ sisfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |||
1572 | /* Adapt RGB settings */ | 1572 | /* Adapt RGB settings */ |
1573 | sisfb_bpp_to_var(ivideo, var); | 1573 | sisfb_bpp_to_var(ivideo, var); |
1574 | 1574 | ||
1575 | /* Sanity check for offsets */ | ||
1576 | if(var->xoffset < 0) var->xoffset = 0; | ||
1577 | if(var->yoffset < 0) var->yoffset = 0; | ||
1578 | |||
1579 | if(var->xres > var->xres_virtual) | 1575 | if(var->xres > var->xres_virtual) |
1580 | var->xres_virtual = var->xres; | 1576 | var->xres_virtual = var->xres; |
1581 | 1577 | ||