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-rw-r--r--drivers/tty/serial/mvebu-uart.c495
1 files changed, 389 insertions, 106 deletions
diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c
index 45b57c294d13..a100e98259d7 100644
--- a/drivers/tty/serial/mvebu-uart.c
+++ b/drivers/tty/serial/mvebu-uart.c
@@ -1,21 +1,10 @@
1// SPDX-License-Identifier: GPL-2.0+
1/* 2/*
2* *************************************************************************** 3* ***************************************************************************
3* Marvell Armada-3700 Serial Driver 4* Marvell Armada-3700 Serial Driver
4* Author: Wilson Ding <dingwei@marvell.com> 5* Author: Wilson Ding <dingwei@marvell.com>
5* Copyright (C) 2015 Marvell International Ltd. 6* Copyright (C) 2015 Marvell International Ltd.
6* *************************************************************************** 7* ***************************************************************************
7* This program is free software: you can redistribute it and/or modify it
8* under the terms of the GNU General Public License as published by the Free
9* Software Foundation, either version 2 of the License, or any later version.
10*
11* This program is distributed in the hope that it will be useful,
12* but WITHOUT ANY WARRANTY; without even the implied warranty of
13* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14* GNU General Public License for more details.
15*
16* You should have received a copy of the GNU General Public License
17* along with this program. If not, see <http://www.gnu.org/licenses/>.
18* ***************************************************************************
19*/ 8*/
20 9
21#include <linux/clk.h> 10#include <linux/clk.h>
@@ -38,46 +27,40 @@
38#include <linux/tty_flip.h> 27#include <linux/tty_flip.h>
39 28
40/* Register Map */ 29/* Register Map */
41#define UART_RBR 0x00 30#define UART_STD_RBR 0x00
42#define RBR_BRK_DET BIT(15) 31#define UART_EXT_RBR 0x18
43#define RBR_FRM_ERR_DET BIT(14)
44#define RBR_PAR_ERR_DET BIT(13)
45#define RBR_OVR_ERR_DET BIT(12)
46 32
47#define UART_TSH 0x04 33#define UART_STD_TSH 0x04
34#define UART_EXT_TSH 0x1C
48 35
49#define UART_CTRL 0x08 36#define UART_STD_CTRL1 0x08
37#define UART_EXT_CTRL1 0x04
50#define CTRL_SOFT_RST BIT(31) 38#define CTRL_SOFT_RST BIT(31)
51#define CTRL_TXFIFO_RST BIT(15) 39#define CTRL_TXFIFO_RST BIT(15)
52#define CTRL_RXFIFO_RST BIT(14) 40#define CTRL_RXFIFO_RST BIT(14)
53#define CTRL_ST_MIRR_EN BIT(13)
54#define CTRL_LPBK_EN BIT(12)
55#define CTRL_SND_BRK_SEQ BIT(11) 41#define CTRL_SND_BRK_SEQ BIT(11)
56#define CTRL_PAR_EN BIT(10)
57#define CTRL_TWO_STOP BIT(9)
58#define CTRL_TX_HFL_INT BIT(8)
59#define CTRL_RX_HFL_INT BIT(7)
60#define CTRL_TX_EMP_INT BIT(6)
61#define CTRL_TX_RDY_INT BIT(5)
62#define CTRL_RX_RDY_INT BIT(4)
63#define CTRL_BRK_DET_INT BIT(3) 42#define CTRL_BRK_DET_INT BIT(3)
64#define CTRL_FRM_ERR_INT BIT(2) 43#define CTRL_FRM_ERR_INT BIT(2)
65#define CTRL_PAR_ERR_INT BIT(1) 44#define CTRL_PAR_ERR_INT BIT(1)
66#define CTRL_OVR_ERR_INT BIT(0) 45#define CTRL_OVR_ERR_INT BIT(0)
67#define CTRL_RX_INT (CTRL_RX_RDY_INT | CTRL_BRK_DET_INT |\ 46#define CTRL_BRK_INT (CTRL_BRK_DET_INT | CTRL_FRM_ERR_INT | \
68 CTRL_FRM_ERR_INT | CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT) 47 CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT)
48
49#define UART_STD_CTRL2 UART_STD_CTRL1
50#define UART_EXT_CTRL2 0x20
51#define CTRL_STD_TX_RDY_INT BIT(5)
52#define CTRL_EXT_TX_RDY_INT BIT(6)
53#define CTRL_STD_RX_RDY_INT BIT(4)
54#define CTRL_EXT_RX_RDY_INT BIT(5)
69 55
70#define UART_STAT 0x0c 56#define UART_STAT 0x0C
71#define STAT_TX_FIFO_EMP BIT(13) 57#define STAT_TX_FIFO_EMP BIT(13)
72#define STAT_RX_FIFO_EMP BIT(12)
73#define STAT_TX_FIFO_FUL BIT(11) 58#define STAT_TX_FIFO_FUL BIT(11)
74#define STAT_TX_FIFO_HFL BIT(10)
75#define STAT_RX_TOGL BIT(9)
76#define STAT_RX_FIFO_FUL BIT(8)
77#define STAT_RX_FIFO_HFL BIT(7)
78#define STAT_TX_EMP BIT(6) 59#define STAT_TX_EMP BIT(6)
79#define STAT_TX_RDY BIT(5) 60#define STAT_STD_TX_RDY BIT(5)
80#define STAT_RX_RDY BIT(4) 61#define STAT_EXT_TX_RDY BIT(15)
62#define STAT_STD_RX_RDY BIT(4)
63#define STAT_EXT_RX_RDY BIT(14)
81#define STAT_BRK_DET BIT(3) 64#define STAT_BRK_DET BIT(3)
82#define STAT_FRM_ERR BIT(2) 65#define STAT_FRM_ERR BIT(2)
83#define STAT_PAR_ERR BIT(1) 66#define STAT_PAR_ERR BIT(1)
@@ -86,18 +69,73 @@
86 | STAT_PAR_ERR | STAT_OVR_ERR) 69 | STAT_PAR_ERR | STAT_OVR_ERR)
87 70
88#define UART_BRDV 0x10 71#define UART_BRDV 0x10
72#define BRDV_BAUD_MASK 0x3FF
89 73
90#define MVEBU_NR_UARTS 1 74#define MVEBU_NR_UARTS 2
91 75
92#define MVEBU_UART_TYPE "mvebu-uart" 76#define MVEBU_UART_TYPE "mvebu-uart"
77#define DRIVER_NAME "mvebu_serial"
78
79enum {
80 /* Either there is only one summed IRQ... */
81 UART_IRQ_SUM = 0,
82 /* ...or there are two separate IRQ for RX and TX */
83 UART_RX_IRQ = 0,
84 UART_TX_IRQ,
85 UART_IRQ_COUNT
86};
93 87
94static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS]; 88/* Diverging register offsets */
89struct uart_regs_layout {
90 unsigned int rbr;
91 unsigned int tsh;
92 unsigned int ctrl;
93 unsigned int intr;
94};
95
96/* Diverging flags */
97struct uart_flags {
98 unsigned int ctrl_tx_rdy_int;
99 unsigned int ctrl_rx_rdy_int;
100 unsigned int stat_tx_rdy;
101 unsigned int stat_rx_rdy;
102};
103
104/* Driver data, a structure for each UART port */
105struct mvebu_uart_driver_data {
106 bool is_ext;
107 struct uart_regs_layout regs;
108 struct uart_flags flags;
109};
95 110
96struct mvebu_uart_data { 111/* MVEBU UART driver structure */
112struct mvebu_uart {
97 struct uart_port *port; 113 struct uart_port *port;
98 struct clk *clk; 114 struct clk *clk;
115 int irq[UART_IRQ_COUNT];
116 unsigned char __iomem *nb;
117 struct mvebu_uart_driver_data *data;
99}; 118};
100 119
120static struct mvebu_uart *to_mvuart(struct uart_port *port)
121{
122 return (struct mvebu_uart *)port->private_data;
123}
124
125#define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext)
126
127#define UART_RBR(port) (to_mvuart(port)->data->regs.rbr)
128#define UART_TSH(port) (to_mvuart(port)->data->regs.tsh)
129#define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl)
130#define UART_INTR(port) (to_mvuart(port)->data->regs.intr)
131
132#define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int)
133#define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int)
134#define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy)
135#define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy)
136
137static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS];
138
101/* Core UART Driver Operations */ 139/* Core UART Driver Operations */
102static unsigned int mvebu_uart_tx_empty(struct uart_port *port) 140static unsigned int mvebu_uart_tx_empty(struct uart_port *port)
103{ 141{
@@ -127,26 +165,39 @@ static void mvebu_uart_set_mctrl(struct uart_port *port,
127 165
128static void mvebu_uart_stop_tx(struct uart_port *port) 166static void mvebu_uart_stop_tx(struct uart_port *port)
129{ 167{
130 unsigned int ctl = readl(port->membase + UART_CTRL); 168 unsigned int ctl = readl(port->membase + UART_INTR(port));
131 169
132 ctl &= ~CTRL_TX_RDY_INT; 170 ctl &= ~CTRL_TX_RDY_INT(port);
133 writel(ctl, port->membase + UART_CTRL); 171 writel(ctl, port->membase + UART_INTR(port));
134} 172}
135 173
136static void mvebu_uart_start_tx(struct uart_port *port) 174static void mvebu_uart_start_tx(struct uart_port *port)
137{ 175{
138 unsigned int ctl = readl(port->membase + UART_CTRL); 176 unsigned int ctl;
177 struct circ_buf *xmit = &port->state->xmit;
178
179 if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) {
180 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
181 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
182 port->icount.tx++;
183 }
139 184
140 ctl |= CTRL_TX_RDY_INT; 185 ctl = readl(port->membase + UART_INTR(port));
141 writel(ctl, port->membase + UART_CTRL); 186 ctl |= CTRL_TX_RDY_INT(port);
187 writel(ctl, port->membase + UART_INTR(port));
142} 188}
143 189
144static void mvebu_uart_stop_rx(struct uart_port *port) 190static void mvebu_uart_stop_rx(struct uart_port *port)
145{ 191{
146 unsigned int ctl = readl(port->membase + UART_CTRL); 192 unsigned int ctl;
193
194 ctl = readl(port->membase + UART_CTRL(port));
195 ctl &= ~CTRL_BRK_INT;
196 writel(ctl, port->membase + UART_CTRL(port));
147 197
148 ctl &= ~CTRL_RX_INT; 198 ctl = readl(port->membase + UART_INTR(port));
149 writel(ctl, port->membase + UART_CTRL); 199 ctl &= ~CTRL_RX_RDY_INT(port);
200 writel(ctl, port->membase + UART_INTR(port));
150} 201}
151 202
152static void mvebu_uart_break_ctl(struct uart_port *port, int brk) 203static void mvebu_uart_break_ctl(struct uart_port *port, int brk)
@@ -155,12 +206,12 @@ static void mvebu_uart_break_ctl(struct uart_port *port, int brk)
155 unsigned long flags; 206 unsigned long flags;
156 207
157 spin_lock_irqsave(&port->lock, flags); 208 spin_lock_irqsave(&port->lock, flags);
158 ctl = readl(port->membase + UART_CTRL); 209 ctl = readl(port->membase + UART_CTRL(port));
159 if (brk == -1) 210 if (brk == -1)
160 ctl |= CTRL_SND_BRK_SEQ; 211 ctl |= CTRL_SND_BRK_SEQ;
161 else 212 else
162 ctl &= ~CTRL_SND_BRK_SEQ; 213 ctl &= ~CTRL_SND_BRK_SEQ;
163 writel(ctl, port->membase + UART_CTRL); 214 writel(ctl, port->membase + UART_CTRL(port));
164 spin_unlock_irqrestore(&port->lock, flags); 215 spin_unlock_irqrestore(&port->lock, flags);
165} 216}
166 217
@@ -171,8 +222,8 @@ static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
171 char flag = 0; 222 char flag = 0;
172 223
173 do { 224 do {
174 if (status & STAT_RX_RDY) { 225 if (status & STAT_RX_RDY(port)) {
175 ch = readl(port->membase + UART_RBR); 226 ch = readl(port->membase + UART_RBR(port));
176 ch &= 0xff; 227 ch &= 0xff;
177 flag = TTY_NORMAL; 228 flag = TTY_NORMAL;
178 port->icount.rx++; 229 port->icount.rx++;
@@ -198,7 +249,7 @@ static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
198 goto ignore_char; 249 goto ignore_char;
199 250
200 if (status & port->ignore_status_mask & STAT_PAR_ERR) 251 if (status & port->ignore_status_mask & STAT_PAR_ERR)
201 status &= ~STAT_RX_RDY; 252 status &= ~STAT_RX_RDY(port);
202 253
203 status &= port->read_status_mask; 254 status &= port->read_status_mask;
204 255
@@ -207,7 +258,7 @@ static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
207 258
208 status &= ~port->ignore_status_mask; 259 status &= ~port->ignore_status_mask;
209 260
210 if (status & STAT_RX_RDY) 261 if (status & STAT_RX_RDY(port))
211 tty_insert_flip_char(tport, ch, flag); 262 tty_insert_flip_char(tport, ch, flag);
212 263
213 if (status & STAT_BRK_DET) 264 if (status & STAT_BRK_DET)
@@ -221,7 +272,7 @@ static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
221 272
222ignore_char: 273ignore_char:
223 status = readl(port->membase + UART_STAT); 274 status = readl(port->membase + UART_STAT);
224 } while (status & (STAT_RX_RDY | STAT_BRK_DET)); 275 } while (status & (STAT_RX_RDY(port) | STAT_BRK_DET));
225 276
226 tty_flip_buffer_push(tport); 277 tty_flip_buffer_push(tport);
227} 278}
@@ -233,7 +284,7 @@ static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status)
233 unsigned int st; 284 unsigned int st;
234 285
235 if (port->x_char) { 286 if (port->x_char) {
236 writel(port->x_char, port->membase + UART_TSH); 287 writel(port->x_char, port->membase + UART_TSH(port));
237 port->icount.tx++; 288 port->icount.tx++;
238 port->x_char = 0; 289 port->x_char = 0;
239 return; 290 return;
@@ -245,7 +296,7 @@ static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status)
245 } 296 }
246 297
247 for (count = 0; count < port->fifosize; count++) { 298 for (count = 0; count < port->fifosize; count++) {
248 writel(xmit->buf[xmit->tail], port->membase + UART_TSH); 299 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
249 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 300 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
250 port->icount.tx++; 301 port->icount.tx++;
251 302
@@ -269,10 +320,34 @@ static irqreturn_t mvebu_uart_isr(int irq, void *dev_id)
269 struct uart_port *port = (struct uart_port *)dev_id; 320 struct uart_port *port = (struct uart_port *)dev_id;
270 unsigned int st = readl(port->membase + UART_STAT); 321 unsigned int st = readl(port->membase + UART_STAT);
271 322
272 if (st & (STAT_RX_RDY | STAT_OVR_ERR | STAT_FRM_ERR | STAT_BRK_DET)) 323 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
324 STAT_BRK_DET))
273 mvebu_uart_rx_chars(port, st); 325 mvebu_uart_rx_chars(port, st);
274 326
275 if (st & STAT_TX_RDY) 327 if (st & STAT_TX_RDY(port))
328 mvebu_uart_tx_chars(port, st);
329
330 return IRQ_HANDLED;
331}
332
333static irqreturn_t mvebu_uart_rx_isr(int irq, void *dev_id)
334{
335 struct uart_port *port = (struct uart_port *)dev_id;
336 unsigned int st = readl(port->membase + UART_STAT);
337
338 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
339 STAT_BRK_DET))
340 mvebu_uart_rx_chars(port, st);
341
342 return IRQ_HANDLED;
343}
344
345static irqreturn_t mvebu_uart_tx_isr(int irq, void *dev_id)
346{
347 struct uart_port *port = (struct uart_port *)dev_id;
348 unsigned int st = readl(port->membase + UART_STAT);
349
350 if (st & STAT_TX_RDY(port))
276 mvebu_uart_tx_chars(port, st); 351 mvebu_uart_tx_chars(port, st);
277 352
278 return IRQ_HANDLED; 353 return IRQ_HANDLED;
@@ -280,18 +355,57 @@ static irqreturn_t mvebu_uart_isr(int irq, void *dev_id)
280 355
281static int mvebu_uart_startup(struct uart_port *port) 356static int mvebu_uart_startup(struct uart_port *port)
282{ 357{
358 struct mvebu_uart *mvuart = to_mvuart(port);
359 unsigned int ctl;
283 int ret; 360 int ret;
284 361
285 writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST, 362 writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST,
286 port->membase + UART_CTRL); 363 port->membase + UART_CTRL(port));
287 udelay(1); 364 udelay(1);
288 writel(CTRL_RX_INT, port->membase + UART_CTRL);
289 365
290 ret = request_irq(port->irq, mvebu_uart_isr, port->irqflags, "serial", 366 /* Clear the error bits of state register before IRQ request */
291 port); 367 ret = readl(port->membase + UART_STAT);
292 if (ret) { 368 ret |= STAT_BRK_ERR;
293 dev_err(port->dev, "failed to request irq\n"); 369 writel(ret, port->membase + UART_STAT);
294 return ret; 370
371 writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));
372
373 ctl = readl(port->membase + UART_INTR(port));
374 ctl |= CTRL_RX_RDY_INT(port);
375 writel(ctl, port->membase + UART_INTR(port));
376
377 if (!mvuart->irq[UART_TX_IRQ]) {
378 /* Old bindings with just one interrupt (UART0 only) */
379 ret = devm_request_irq(port->dev, mvuart->irq[UART_IRQ_SUM],
380 mvebu_uart_isr, port->irqflags,
381 dev_name(port->dev), port);
382 if (ret) {
383 dev_err(port->dev, "unable to request IRQ %d\n",
384 mvuart->irq[UART_IRQ_SUM]);
385 return ret;
386 }
387 } else {
388 /* New bindings with an IRQ for RX and TX (both UART) */
389 ret = devm_request_irq(port->dev, mvuart->irq[UART_RX_IRQ],
390 mvebu_uart_rx_isr, port->irqflags,
391 dev_name(port->dev), port);
392 if (ret) {
393 dev_err(port->dev, "unable to request IRQ %d\n",
394 mvuart->irq[UART_RX_IRQ]);
395 return ret;
396 }
397
398 ret = devm_request_irq(port->dev, mvuart->irq[UART_TX_IRQ],
399 mvebu_uart_tx_isr, port->irqflags,
400 dev_name(port->dev),
401 port);
402 if (ret) {
403 dev_err(port->dev, "unable to request IRQ %d\n",
404 mvuart->irq[UART_TX_IRQ]);
405 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ],
406 port);
407 return ret;
408 }
295 } 409 }
296 410
297 return 0; 411 return 0;
@@ -299,9 +413,41 @@ static int mvebu_uart_startup(struct uart_port *port)
299 413
300static void mvebu_uart_shutdown(struct uart_port *port) 414static void mvebu_uart_shutdown(struct uart_port *port)
301{ 415{
302 writel(0, port->membase + UART_CTRL); 416 struct mvebu_uart *mvuart = to_mvuart(port);
417
418 writel(0, port->membase + UART_INTR(port));
419
420 if (!mvuart->irq[UART_TX_IRQ]) {
421 devm_free_irq(port->dev, mvuart->irq[UART_IRQ_SUM], port);
422 } else {
423 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], port);
424 devm_free_irq(port->dev, mvuart->irq[UART_TX_IRQ], port);
425 }
426}
427
428static int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud)
429{
430 struct mvebu_uart *mvuart = to_mvuart(port);
431 unsigned int baud_rate_div;
432 u32 brdv;
433
434 if (IS_ERR(mvuart->clk))
435 return -PTR_ERR(mvuart->clk);
436
437 /*
438 * The UART clock is divided by the value of the divisor to generate
439 * UCLK_OUT clock, which is 16 times faster than the baudrate.
440 * This prescaler can achieve all standard baudrates until 230400.
441 * Higher baudrates could be achieved for the extended UART by using the
442 * programmable oversampling stack (also called fractional divisor).
443 */
444 baud_rate_div = DIV_ROUND_UP(port->uartclk, baud * 16);
445 brdv = readl(port->membase + UART_BRDV);
446 brdv &= ~BRDV_BAUD_MASK;
447 brdv |= baud_rate_div;
448 writel(brdv, port->membase + UART_BRDV);
303 449
304 free_irq(port->irq, port); 450 return 0;
305} 451}
306 452
307static void mvebu_uart_set_termios(struct uart_port *port, 453static void mvebu_uart_set_termios(struct uart_port *port,
@@ -313,8 +459,8 @@ static void mvebu_uart_set_termios(struct uart_port *port,
313 459
314 spin_lock_irqsave(&port->lock, flags); 460 spin_lock_irqsave(&port->lock, flags);
315 461
316 port->read_status_mask = STAT_RX_RDY | STAT_OVR_ERR | 462 port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR |
317 STAT_TX_RDY | STAT_TX_FIFO_FUL; 463 STAT_TX_RDY(port) | STAT_TX_FIFO_FUL;
318 464
319 if (termios->c_iflag & INPCK) 465 if (termios->c_iflag & INPCK)
320 port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR; 466 port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR;
@@ -325,13 +471,32 @@ static void mvebu_uart_set_termios(struct uart_port *port,
325 STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR; 471 STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR;
326 472
327 if ((termios->c_cflag & CREAD) == 0) 473 if ((termios->c_cflag & CREAD) == 0)
328 port->ignore_status_mask |= STAT_RX_RDY | STAT_BRK_ERR; 474 port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR;
329 475
330 if (old) 476 /*
331 tty_termios_copy_hw(termios, old); 477 * Maximum achievable frequency with simple baudrate divisor is 230400.
478 * Since the error per bit frame would be of more than 15%, achieving
479 * higher frequencies would require to implement the fractional divisor
480 * feature.
481 */
482 baud = uart_get_baud_rate(port, termios, old, 0, 230400);
483 if (mvebu_uart_baud_rate_set(port, baud)) {
484 /* No clock available, baudrate cannot be changed */
485 if (old)
486 baud = uart_get_baud_rate(port, old, NULL, 0, 230400);
487 } else {
488 tty_termios_encode_baud_rate(termios, baud, baud);
489 uart_update_timeout(port, termios->c_cflag, baud);
490 }
332 491
333 baud = uart_get_baud_rate(port, termios, old, 0, 460800); 492 /* Only the following flag changes are supported */
334 uart_update_timeout(port, termios->c_cflag, baud); 493 if (old) {
494 termios->c_iflag &= INPCK | IGNPAR;
495 termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR);
496 termios->c_cflag &= CREAD | CBAUD;
497 termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD);
498 termios->c_lflag = old->c_lflag;
499 }
335 500
336 spin_unlock_irqrestore(&port->lock, flags); 501 spin_unlock_irqrestore(&port->lock, flags);
337} 502}
@@ -356,10 +521,10 @@ static int mvebu_uart_get_poll_char(struct uart_port *port)
356{ 521{
357 unsigned int st = readl(port->membase + UART_STAT); 522 unsigned int st = readl(port->membase + UART_STAT);
358 523
359 if (!(st & STAT_RX_RDY)) 524 if (!(st & STAT_RX_RDY(port)))
360 return NO_POLL_CHAR; 525 return NO_POLL_CHAR;
361 526
362 return readl(port->membase + UART_RBR); 527 return readl(port->membase + UART_RBR(port));
363} 528}
364 529
365static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c) 530static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c)
@@ -375,7 +540,7 @@ static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c)
375 udelay(1); 540 udelay(1);
376 } 541 }
377 542
378 writel(c, port->membase + UART_TSH); 543 writel(c, port->membase + UART_TSH(port));
379} 544}
380#endif 545#endif
381 546
@@ -413,7 +578,8 @@ static void mvebu_uart_putc(struct uart_port *port, int c)
413 break; 578 break;
414 } 579 }
415 580
416 writel(c, port->membase + UART_TSH); 581 /* At early stage, DT is not parsed yet, only use UART0 */
582 writel(c, port->membase + UART_STD_TSH);
417 583
418 for (;;) { 584 for (;;) {
419 st = readl(port->membase + UART_STAT); 585 st = readl(port->membase + UART_STAT);
@@ -458,7 +624,7 @@ static void wait_for_xmitr(struct uart_port *port)
458static void mvebu_uart_console_putchar(struct uart_port *port, int ch) 624static void mvebu_uart_console_putchar(struct uart_port *port, int ch)
459{ 625{
460 wait_for_xmitr(port); 626 wait_for_xmitr(port);
461 writel(ch, port->membase + UART_TSH); 627 writel(ch, port->membase + UART_TSH(port));
462} 628}
463 629
464static void mvebu_uart_console_write(struct console *co, const char *s, 630static void mvebu_uart_console_write(struct console *co, const char *s,
@@ -466,7 +632,7 @@ static void mvebu_uart_console_write(struct console *co, const char *s,
466{ 632{
467 struct uart_port *port = &mvebu_uart_ports[co->index]; 633 struct uart_port *port = &mvebu_uart_ports[co->index];
468 unsigned long flags; 634 unsigned long flags;
469 unsigned int ier; 635 unsigned int ier, intr, ctl;
470 int locked = 1; 636 int locked = 1;
471 637
472 if (oops_in_progress) 638 if (oops_in_progress)
@@ -474,16 +640,23 @@ static void mvebu_uart_console_write(struct console *co, const char *s,
474 else 640 else
475 spin_lock_irqsave(&port->lock, flags); 641 spin_lock_irqsave(&port->lock, flags);
476 642
477 ier = readl(port->membase + UART_CTRL) & 643 ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT;
478 (CTRL_RX_INT | CTRL_TX_RDY_INT); 644 intr = readl(port->membase + UART_INTR(port)) &
479 writel(0, port->membase + UART_CTRL); 645 (CTRL_RX_RDY_INT(port) | CTRL_TX_RDY_INT(port));
646 writel(0, port->membase + UART_CTRL(port));
647 writel(0, port->membase + UART_INTR(port));
480 648
481 uart_console_write(port, s, count, mvebu_uart_console_putchar); 649 uart_console_write(port, s, count, mvebu_uart_console_putchar);
482 650
483 wait_for_xmitr(port); 651 wait_for_xmitr(port);
484 652
485 if (ier) 653 if (ier)
486 writel(ier, port->membase + UART_CTRL); 654 writel(ier, port->membase + UART_CTRL(port));
655
656 if (intr) {
657 ctl = intr | readl(port->membase + UART_INTR(port));
658 writel(ctl, port->membase + UART_INTR(port));
659 }
487 660
488 if (locked) 661 if (locked)
489 spin_unlock_irqrestore(&port->lock, flags); 662 spin_unlock_irqrestore(&port->lock, flags);
@@ -538,7 +711,7 @@ console_initcall(mvebu_uart_console_init);
538 711
539static struct uart_driver mvebu_uart_driver = { 712static struct uart_driver mvebu_uart_driver = {
540 .owner = THIS_MODULE, 713 .owner = THIS_MODULE,
541 .driver_name = "mvebu_serial", 714 .driver_name = DRIVER_NAME,
542 .dev_name = "ttyMV", 715 .dev_name = "ttyMV",
543 .nr = MVEBU_NR_UARTS, 716 .nr = MVEBU_NR_UARTS,
544#ifdef CONFIG_SERIAL_MVEBU_CONSOLE 717#ifdef CONFIG_SERIAL_MVEBU_CONSOLE
@@ -546,20 +719,39 @@ static struct uart_driver mvebu_uart_driver = {
546#endif 719#endif
547}; 720};
548 721
722static const struct of_device_id mvebu_uart_of_match[];
723
724/* Counter to keep track of each UART port id when not using CONFIG_OF */
725static int uart_num_counter;
726
549static int mvebu_uart_probe(struct platform_device *pdev) 727static int mvebu_uart_probe(struct platform_device *pdev)
550{ 728{
551 struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0); 729 struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
552 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 730 const struct of_device_id *match = of_match_device(mvebu_uart_of_match,
731 &pdev->dev);
553 struct uart_port *port; 732 struct uart_port *port;
554 struct mvebu_uart_data *data; 733 struct mvebu_uart *mvuart;
555 int ret; 734 int ret, id, irq;
735
736 if (!reg) {
737 dev_err(&pdev->dev, "no registers defined\n");
738 return -EINVAL;
739 }
740
741 /* Assume that all UART ports have a DT alias or none has */
742 id = of_alias_get_id(pdev->dev.of_node, "serial");
743 if (!pdev->dev.of_node || id < 0)
744 pdev->id = uart_num_counter++;
745 else
746 pdev->id = id;
556 747
557 if (!reg || !irq) { 748 if (pdev->id >= MVEBU_NR_UARTS) {
558 dev_err(&pdev->dev, "no registers/irq defined\n"); 749 dev_err(&pdev->dev, "cannot have more than %d UART ports\n",
750 MVEBU_NR_UARTS);
559 return -EINVAL; 751 return -EINVAL;
560 } 752 }
561 753
562 port = &mvebu_uart_ports[0]; 754 port = &mvebu_uart_ports[pdev->id];
563 755
564 spin_lock_init(&port->lock); 756 spin_lock_init(&port->lock);
565 757
@@ -571,9 +763,14 @@ static int mvebu_uart_probe(struct platform_device *pdev)
571 port->fifosize = 32; 763 port->fifosize = 32;
572 port->iotype = UPIO_MEM32; 764 port->iotype = UPIO_MEM32;
573 port->flags = UPF_FIXED_PORT; 765 port->flags = UPF_FIXED_PORT;
574 port->line = 0; /* single port: force line number to 0 */ 766 port->line = pdev->id;
575 767
576 port->irq = irq->start; 768 /*
769 * IRQ number is not stored in this structure because we may have two of
770 * them per port (RX and TX). Instead, use the driver UART structure
771 * array so called ->irq[].
772 */
773 port->irq = 0;
577 port->irqflags = 0; 774 port->irqflags = 0;
578 port->mapbase = reg->start; 775 port->mapbase = reg->start;
579 776
@@ -581,15 +778,70 @@ static int mvebu_uart_probe(struct platform_device *pdev)
581 if (IS_ERR(port->membase)) 778 if (IS_ERR(port->membase))
582 return -PTR_ERR(port->membase); 779 return -PTR_ERR(port->membase);
583 780
584 data = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart_data), 781 mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart),
585 GFP_KERNEL); 782 GFP_KERNEL);
586 if (!data) 783 if (!mvuart)
587 return -ENOMEM; 784 return -ENOMEM;
588 785
589 data->port = port; 786 /* Get controller data depending on the compatible string */
787 mvuart->data = (struct mvebu_uart_driver_data *)match->data;
788 mvuart->port = port;
789
790 port->private_data = mvuart;
791 platform_set_drvdata(pdev, mvuart);
792
793 /* Get fixed clock frequency */
794 mvuart->clk = devm_clk_get(&pdev->dev, NULL);
795 if (IS_ERR(mvuart->clk)) {
796 if (PTR_ERR(mvuart->clk) == -EPROBE_DEFER)
797 return PTR_ERR(mvuart->clk);
798
799 if (IS_EXTENDED(port)) {
800 dev_err(&pdev->dev, "unable to get UART clock\n");
801 return PTR_ERR(mvuart->clk);
802 }
803 } else {
804 if (!clk_prepare_enable(mvuart->clk))
805 port->uartclk = clk_get_rate(mvuart->clk);
806 }
807
808 /* Manage interrupts */
809 if (platform_irq_count(pdev) == 1) {
810 /* Old bindings: no name on the single unamed UART0 IRQ */
811 irq = platform_get_irq(pdev, 0);
812 if (irq < 0) {
813 dev_err(&pdev->dev, "unable to get UART IRQ\n");
814 return irq;
815 }
816
817 mvuart->irq[UART_IRQ_SUM] = irq;
818 } else {
819 /*
820 * New bindings: named interrupts (RX, TX) for both UARTS,
821 * only make use of uart-rx and uart-tx interrupts, do not use
822 * uart-sum of UART0 port.
823 */
824 irq = platform_get_irq_byname(pdev, "uart-rx");
825 if (irq < 0) {
826 dev_err(&pdev->dev, "unable to get 'uart-rx' IRQ\n");
827 return irq;
828 }
829
830 mvuart->irq[UART_RX_IRQ] = irq;
590 831
591 port->private_data = data; 832 irq = platform_get_irq_byname(pdev, "uart-tx");
592 platform_set_drvdata(pdev, data); 833 if (irq < 0) {
834 dev_err(&pdev->dev, "unable to get 'uart-tx' IRQ\n");
835 return irq;
836 }
837
838 mvuart->irq[UART_TX_IRQ] = irq;
839 }
840
841 /* UART Soft Reset*/
842 writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));
843 udelay(1);
844 writel(0, port->membase + UART_CTRL(port));
593 845
594 ret = uart_add_one_port(&mvebu_uart_driver, port); 846 ret = uart_add_one_port(&mvebu_uart_driver, port);
595 if (ret) 847 if (ret)
@@ -597,9 +849,40 @@ static int mvebu_uart_probe(struct platform_device *pdev)
597 return 0; 849 return 0;
598} 850}
599 851
852static struct mvebu_uart_driver_data uart_std_driver_data = {
853 .is_ext = false,
854 .regs.rbr = UART_STD_RBR,
855 .regs.tsh = UART_STD_TSH,
856 .regs.ctrl = UART_STD_CTRL1,
857 .regs.intr = UART_STD_CTRL2,
858 .flags.ctrl_tx_rdy_int = CTRL_STD_TX_RDY_INT,
859 .flags.ctrl_rx_rdy_int = CTRL_STD_RX_RDY_INT,
860 .flags.stat_tx_rdy = STAT_STD_TX_RDY,
861 .flags.stat_rx_rdy = STAT_STD_RX_RDY,
862};
863
864static struct mvebu_uart_driver_data uart_ext_driver_data = {
865 .is_ext = true,
866 .regs.rbr = UART_EXT_RBR,
867 .regs.tsh = UART_EXT_TSH,
868 .regs.ctrl = UART_EXT_CTRL1,
869 .regs.intr = UART_EXT_CTRL2,
870 .flags.ctrl_tx_rdy_int = CTRL_EXT_TX_RDY_INT,
871 .flags.ctrl_rx_rdy_int = CTRL_EXT_RX_RDY_INT,
872 .flags.stat_tx_rdy = STAT_EXT_TX_RDY,
873 .flags.stat_rx_rdy = STAT_EXT_RX_RDY,
874};
875
600/* Match table for of_platform binding */ 876/* Match table for of_platform binding */
601static const struct of_device_id mvebu_uart_of_match[] = { 877static const struct of_device_id mvebu_uart_of_match[] = {
602 { .compatible = "marvell,armada-3700-uart", }, 878 {
879 .compatible = "marvell,armada-3700-uart",
880 .data = (void *)&uart_std_driver_data,
881 },
882 {
883 .compatible = "marvell,armada-3700-uart-ext",
884 .data = (void *)&uart_ext_driver_data,
885 },
603 {} 886 {}
604}; 887};
605 888
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 13:16:21 -0400