diff options
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-atmel.c | 12 | ||||
| -rw-r--r-- | drivers/spi/spi-dw-mid.c | 6 | ||||
| -rw-r--r-- | drivers/spi/spi-dw-pci.c | 4 | ||||
| -rw-r--r-- | drivers/spi/spi-dw.c | 4 | ||||
| -rw-r--r-- | drivers/spi/spi-img-spfi.c | 7 | ||||
| -rw-r--r-- | drivers/spi/spi-pl022.c | 2 | ||||
| -rw-r--r-- | drivers/spi/spi-ti-qspi.c | 22 |
7 files changed, 46 insertions, 11 deletions
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c index 9af7841f2e8c..06de34001c66 100644 --- a/drivers/spi/spi-atmel.c +++ b/drivers/spi/spi-atmel.c | |||
| @@ -764,17 +764,17 @@ static void atmel_spi_pdc_next_xfer(struct spi_master *master, | |||
| 764 | (unsigned long long)xfer->rx_dma); | 764 | (unsigned long long)xfer->rx_dma); |
| 765 | } | 765 | } |
| 766 | 766 | ||
| 767 | /* REVISIT: We're waiting for ENDRX before we start the next | 767 | /* REVISIT: We're waiting for RXBUFF before we start the next |
| 768 | * transfer because we need to handle some difficult timing | 768 | * transfer because we need to handle some difficult timing |
| 769 | * issues otherwise. If we wait for ENDTX in one transfer and | 769 | * issues otherwise. If we wait for TXBUFE in one transfer and |
| 770 | * then starts waiting for ENDRX in the next, it's difficult | 770 | * then starts waiting for RXBUFF in the next, it's difficult |
| 771 | * to tell the difference between the ENDRX interrupt we're | 771 | * to tell the difference between the RXBUFF interrupt we're |
| 772 | * actually waiting for and the ENDRX interrupt of the | 772 | * actually waiting for and the RXBUFF interrupt of the |
| 773 | * previous transfer. | 773 | * previous transfer. |
| 774 | * | 774 | * |
| 775 | * It should be doable, though. Just not now... | 775 | * It should be doable, though. Just not now... |
| 776 | */ | 776 | */ |
| 777 | spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES)); | 777 | spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES)); |
| 778 | spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN)); | 778 | spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN)); |
| 779 | } | 779 | } |
| 780 | 780 | ||
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c index a0197fd4e95c..3ce39d10fafb 100644 --- a/drivers/spi/spi-dw-mid.c +++ b/drivers/spi/spi-dw-mid.c | |||
| @@ -139,6 +139,9 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws) | |||
| 139 | 1, | 139 | 1, |
| 140 | DMA_MEM_TO_DEV, | 140 | DMA_MEM_TO_DEV, |
| 141 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | 141 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 142 | if (!txdesc) | ||
| 143 | return NULL; | ||
| 144 | |||
| 142 | txdesc->callback = dw_spi_dma_tx_done; | 145 | txdesc->callback = dw_spi_dma_tx_done; |
| 143 | txdesc->callback_param = dws; | 146 | txdesc->callback_param = dws; |
| 144 | 147 | ||
| @@ -184,6 +187,9 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws) | |||
| 184 | 1, | 187 | 1, |
| 185 | DMA_DEV_TO_MEM, | 188 | DMA_DEV_TO_MEM, |
| 186 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | 189 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 190 | if (!rxdesc) | ||
| 191 | return NULL; | ||
| 192 | |||
| 187 | rxdesc->callback = dw_spi_dma_rx_done; | 193 | rxdesc->callback = dw_spi_dma_rx_done; |
| 188 | rxdesc->callback_param = dws; | 194 | rxdesc->callback_param = dws; |
| 189 | 195 | ||
diff --git a/drivers/spi/spi-dw-pci.c b/drivers/spi/spi-dw-pci.c index 5ba331047cbe..6d331e0db331 100644 --- a/drivers/spi/spi-dw-pci.c +++ b/drivers/spi/spi-dw-pci.c | |||
| @@ -36,13 +36,13 @@ struct spi_pci_desc { | |||
| 36 | 36 | ||
| 37 | static struct spi_pci_desc spi_pci_mid_desc_1 = { | 37 | static struct spi_pci_desc spi_pci_mid_desc_1 = { |
| 38 | .setup = dw_spi_mid_init, | 38 | .setup = dw_spi_mid_init, |
| 39 | .num_cs = 32, | 39 | .num_cs = 5, |
| 40 | .bus_num = 0, | 40 | .bus_num = 0, |
| 41 | }; | 41 | }; |
| 42 | 42 | ||
| 43 | static struct spi_pci_desc spi_pci_mid_desc_2 = { | 43 | static struct spi_pci_desc spi_pci_mid_desc_2 = { |
| 44 | .setup = dw_spi_mid_init, | 44 | .setup = dw_spi_mid_init, |
| 45 | .num_cs = 4, | 45 | .num_cs = 2, |
| 46 | .bus_num = 1, | 46 | .bus_num = 1, |
| 47 | }; | 47 | }; |
| 48 | 48 | ||
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index 5a97a62b298a..4847afba89f4 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c | |||
| @@ -621,14 +621,14 @@ static void spi_hw_init(struct device *dev, struct dw_spi *dws) | |||
| 621 | if (!dws->fifo_len) { | 621 | if (!dws->fifo_len) { |
| 622 | u32 fifo; | 622 | u32 fifo; |
| 623 | 623 | ||
| 624 | for (fifo = 2; fifo <= 256; fifo++) { | 624 | for (fifo = 1; fifo < 256; fifo++) { |
| 625 | dw_writew(dws, DW_SPI_TXFLTR, fifo); | 625 | dw_writew(dws, DW_SPI_TXFLTR, fifo); |
| 626 | if (fifo != dw_readw(dws, DW_SPI_TXFLTR)) | 626 | if (fifo != dw_readw(dws, DW_SPI_TXFLTR)) |
| 627 | break; | 627 | break; |
| 628 | } | 628 | } |
| 629 | dw_writew(dws, DW_SPI_TXFLTR, 0); | 629 | dw_writew(dws, DW_SPI_TXFLTR, 0); |
| 630 | 630 | ||
| 631 | dws->fifo_len = (fifo == 2) ? 0 : fifo - 1; | 631 | dws->fifo_len = (fifo == 1) ? 0 : fifo; |
| 632 | dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len); | 632 | dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len); |
| 633 | } | 633 | } |
| 634 | } | 634 | } |
diff --git a/drivers/spi/spi-img-spfi.c b/drivers/spi/spi-img-spfi.c index c01567d53581..e649bc7d4c08 100644 --- a/drivers/spi/spi-img-spfi.c +++ b/drivers/spi/spi-img-spfi.c | |||
| @@ -459,6 +459,13 @@ static int img_spfi_transfer_one(struct spi_master *master, | |||
| 459 | unsigned long flags; | 459 | unsigned long flags; |
| 460 | int ret; | 460 | int ret; |
| 461 | 461 | ||
| 462 | if (xfer->len > SPFI_TRANSACTION_TSIZE_MASK) { | ||
| 463 | dev_err(spfi->dev, | ||
| 464 | "Transfer length (%d) is greater than the max supported (%d)", | ||
| 465 | xfer->len, SPFI_TRANSACTION_TSIZE_MASK); | ||
| 466 | return -EINVAL; | ||
| 467 | } | ||
| 468 | |||
| 462 | /* | 469 | /* |
| 463 | * Stop all DMA and reset the controller if the previous transaction | 470 | * Stop all DMA and reset the controller if the previous transaction |
| 464 | * timed-out and never completed it's DMA. | 471 | * timed-out and never completed it's DMA. |
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c index 89ca162801da..ee513a85296b 100644 --- a/drivers/spi/spi-pl022.c +++ b/drivers/spi/spi-pl022.c | |||
| @@ -534,12 +534,12 @@ static void giveback(struct pl022 *pl022) | |||
| 534 | pl022->cur_msg = NULL; | 534 | pl022->cur_msg = NULL; |
| 535 | pl022->cur_transfer = NULL; | 535 | pl022->cur_transfer = NULL; |
| 536 | pl022->cur_chip = NULL; | 536 | pl022->cur_chip = NULL; |
| 537 | spi_finalize_current_message(pl022->master); | ||
| 538 | 537 | ||
| 539 | /* disable the SPI/SSP operation */ | 538 | /* disable the SPI/SSP operation */ |
| 540 | writew((readw(SSP_CR1(pl022->virtbase)) & | 539 | writew((readw(SSP_CR1(pl022->virtbase)) & |
| 541 | (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); | 540 | (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); |
| 542 | 541 | ||
| 542 | spi_finalize_current_message(pl022->master); | ||
| 543 | } | 543 | } |
| 544 | 544 | ||
| 545 | /** | 545 | /** |
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c index 884a716e50cb..5c0616870358 100644 --- a/drivers/spi/spi-ti-qspi.c +++ b/drivers/spi/spi-ti-qspi.c | |||
| @@ -101,6 +101,7 @@ struct ti_qspi { | |||
| 101 | #define QSPI_FLEN(n) ((n - 1) << 0) | 101 | #define QSPI_FLEN(n) ((n - 1) << 0) |
| 102 | 102 | ||
| 103 | /* STATUS REGISTER */ | 103 | /* STATUS REGISTER */ |
| 104 | #define BUSY 0x01 | ||
| 104 | #define WC 0x02 | 105 | #define WC 0x02 |
| 105 | 106 | ||
| 106 | /* INTERRUPT REGISTER */ | 107 | /* INTERRUPT REGISTER */ |
| @@ -199,6 +200,21 @@ static void ti_qspi_restore_ctx(struct ti_qspi *qspi) | |||
| 199 | ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG); | 200 | ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG); |
| 200 | } | 201 | } |
| 201 | 202 | ||
| 203 | static inline u32 qspi_is_busy(struct ti_qspi *qspi) | ||
| 204 | { | ||
| 205 | u32 stat; | ||
| 206 | unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT; | ||
| 207 | |||
| 208 | stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); | ||
| 209 | while ((stat & BUSY) && time_after(timeout, jiffies)) { | ||
| 210 | cpu_relax(); | ||
| 211 | stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); | ||
| 212 | } | ||
| 213 | |||
| 214 | WARN(stat & BUSY, "qspi busy\n"); | ||
| 215 | return stat & BUSY; | ||
| 216 | } | ||
| 217 | |||
| 202 | static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t) | 218 | static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t) |
| 203 | { | 219 | { |
| 204 | int wlen, count; | 220 | int wlen, count; |
| @@ -211,6 +227,9 @@ static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t) | |||
| 211 | wlen = t->bits_per_word >> 3; /* in bytes */ | 227 | wlen = t->bits_per_word >> 3; /* in bytes */ |
| 212 | 228 | ||
| 213 | while (count) { | 229 | while (count) { |
| 230 | if (qspi_is_busy(qspi)) | ||
| 231 | return -EBUSY; | ||
| 232 | |||
| 214 | switch (wlen) { | 233 | switch (wlen) { |
| 215 | case 1: | 234 | case 1: |
| 216 | dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n", | 235 | dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n", |
| @@ -266,6 +285,9 @@ static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t) | |||
| 266 | 285 | ||
| 267 | while (count) { | 286 | while (count) { |
| 268 | dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc); | 287 | dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc); |
| 288 | if (qspi_is_busy(qspi)) | ||
| 289 | return -EBUSY; | ||
| 290 | |||
| 269 | ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); | 291 | ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); |
| 270 | if (!wait_for_completion_timeout(&qspi->transfer_complete, | 292 | if (!wait_for_completion_timeout(&qspi->transfer_complete, |
| 271 | QSPI_COMPLETION_TIMEOUT)) { | 293 | QSPI_COMPLETION_TIMEOUT)) { |
