diff options
Diffstat (limited to 'drivers/spi/spi-imx.c')
| -rw-r--r-- | drivers/spi/spi-imx.c | 218 |
1 files changed, 196 insertions, 22 deletions
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index f9698b7aeb3b..babb15f07995 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c | |||
| @@ -56,6 +56,7 @@ | |||
| 56 | 56 | ||
| 57 | /* The maximum bytes that a sdma BD can transfer.*/ | 57 | /* The maximum bytes that a sdma BD can transfer.*/ |
| 58 | #define MAX_SDMA_BD_BYTES (1 << 15) | 58 | #define MAX_SDMA_BD_BYTES (1 << 15) |
| 59 | #define MX51_ECSPI_CTRL_MAX_BURST 512 | ||
| 59 | 60 | ||
| 60 | enum spi_imx_devtype { | 61 | enum spi_imx_devtype { |
| 61 | IMX1_CSPI, | 62 | IMX1_CSPI, |
| @@ -63,7 +64,8 @@ enum spi_imx_devtype { | |||
| 63 | IMX27_CSPI, | 64 | IMX27_CSPI, |
| 64 | IMX31_CSPI, | 65 | IMX31_CSPI, |
| 65 | IMX35_CSPI, /* CSPI on all i.mx except above */ | 66 | IMX35_CSPI, /* CSPI on all i.mx except above */ |
| 66 | IMX51_ECSPI, /* ECSPI on i.mx51 and later */ | 67 | IMX51_ECSPI, /* ECSPI on i.mx51 */ |
| 68 | IMX53_ECSPI, /* ECSPI on i.mx53 and later */ | ||
| 67 | }; | 69 | }; |
| 68 | 70 | ||
| 69 | struct spi_imx_data; | 71 | struct spi_imx_data; |
| @@ -74,6 +76,9 @@ struct spi_imx_devtype_data { | |||
| 74 | void (*trigger)(struct spi_imx_data *); | 76 | void (*trigger)(struct spi_imx_data *); |
| 75 | int (*rx_available)(struct spi_imx_data *); | 77 | int (*rx_available)(struct spi_imx_data *); |
| 76 | void (*reset)(struct spi_imx_data *); | 78 | void (*reset)(struct spi_imx_data *); |
| 79 | bool has_dmamode; | ||
| 80 | unsigned int fifo_size; | ||
| 81 | bool dynamic_burst; | ||
| 77 | enum spi_imx_devtype devtype; | 82 | enum spi_imx_devtype devtype; |
| 78 | }; | 83 | }; |
| 79 | 84 | ||
| @@ -94,12 +99,14 @@ struct spi_imx_data { | |||
| 94 | unsigned int bits_per_word; | 99 | unsigned int bits_per_word; |
| 95 | unsigned int spi_drctl; | 100 | unsigned int spi_drctl; |
| 96 | 101 | ||
| 97 | unsigned int count; | 102 | unsigned int count, remainder; |
| 98 | void (*tx)(struct spi_imx_data *); | 103 | void (*tx)(struct spi_imx_data *); |
| 99 | void (*rx)(struct spi_imx_data *); | 104 | void (*rx)(struct spi_imx_data *); |
| 100 | void *rx_buf; | 105 | void *rx_buf; |
| 101 | const void *tx_buf; | 106 | const void *tx_buf; |
| 102 | unsigned int txfifo; /* number of words pushed in tx FIFO */ | 107 | unsigned int txfifo; /* number of words pushed in tx FIFO */ |
| 108 | unsigned int dynamic_burst, read_u32; | ||
| 109 | unsigned int word_mask; | ||
| 103 | 110 | ||
| 104 | /* DMA */ | 111 | /* DMA */ |
| 105 | bool usedma; | 112 | bool usedma; |
| @@ -125,9 +132,9 @@ static inline int is_imx51_ecspi(struct spi_imx_data *d) | |||
| 125 | return d->devtype_data->devtype == IMX51_ECSPI; | 132 | return d->devtype_data->devtype == IMX51_ECSPI; |
| 126 | } | 133 | } |
| 127 | 134 | ||
| 128 | static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d) | 135 | static inline int is_imx53_ecspi(struct spi_imx_data *d) |
| 129 | { | 136 | { |
| 130 | return is_imx51_ecspi(d) ? 64 : 8; | 137 | return d->devtype_data->devtype == IMX53_ECSPI; |
| 131 | } | 138 | } |
| 132 | 139 | ||
| 133 | #define MXC_SPI_BUF_RX(type) \ | 140 | #define MXC_SPI_BUF_RX(type) \ |
| @@ -219,7 +226,7 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, | |||
| 219 | if (bytes_per_word != 1 && bytes_per_word != 2 && bytes_per_word != 4) | 226 | if (bytes_per_word != 1 && bytes_per_word != 2 && bytes_per_word != 4) |
| 220 | return false; | 227 | return false; |
| 221 | 228 | ||
| 222 | for (i = spi_imx_get_fifosize(spi_imx) / 2; i > 0; i--) { | 229 | for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) { |
| 223 | if (!(transfer->len % (i * bytes_per_word))) | 230 | if (!(transfer->len % (i * bytes_per_word))) |
| 224 | break; | 231 | break; |
| 225 | } | 232 | } |
| @@ -228,6 +235,7 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, | |||
| 228 | return false; | 235 | return false; |
| 229 | 236 | ||
| 230 | spi_imx->wml = i; | 237 | spi_imx->wml = i; |
| 238 | spi_imx->dynamic_burst = 0; | ||
| 231 | 239 | ||
| 232 | return true; | 240 | return true; |
| 233 | } | 241 | } |
| @@ -242,6 +250,7 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, | |||
| 242 | #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 | 250 | #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 |
| 243 | #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) | 251 | #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) |
| 244 | #define MX51_ECSPI_CTRL_BL_OFFSET 20 | 252 | #define MX51_ECSPI_CTRL_BL_OFFSET 20 |
| 253 | #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20) | ||
| 245 | 254 | ||
| 246 | #define MX51_ECSPI_CONFIG 0x0c | 255 | #define MX51_ECSPI_CONFIG 0x0c |
| 247 | #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) | 256 | #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) |
| @@ -269,6 +278,106 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, | |||
| 269 | #define MX51_ECSPI_TESTREG 0x20 | 278 | #define MX51_ECSPI_TESTREG 0x20 |
| 270 | #define MX51_ECSPI_TESTREG_LBC BIT(31) | 279 | #define MX51_ECSPI_TESTREG_LBC BIT(31) |
| 271 | 280 | ||
| 281 | static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx) | ||
| 282 | { | ||
| 283 | unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); | ||
| 284 | #ifdef __LITTLE_ENDIAN | ||
| 285 | unsigned int bytes_per_word; | ||
| 286 | #endif | ||
| 287 | |||
| 288 | if (spi_imx->rx_buf) { | ||
| 289 | #ifdef __LITTLE_ENDIAN | ||
| 290 | bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); | ||
| 291 | if (bytes_per_word == 1) | ||
| 292 | val = cpu_to_be32(val); | ||
| 293 | else if (bytes_per_word == 2) | ||
| 294 | val = (val << 16) | (val >> 16); | ||
| 295 | #endif | ||
| 296 | val &= spi_imx->word_mask; | ||
| 297 | *(u32 *)spi_imx->rx_buf = val; | ||
| 298 | spi_imx->rx_buf += sizeof(u32); | ||
| 299 | } | ||
| 300 | } | ||
| 301 | |||
| 302 | static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx) | ||
| 303 | { | ||
| 304 | unsigned int bytes_per_word; | ||
| 305 | |||
| 306 | bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); | ||
| 307 | if (spi_imx->read_u32) { | ||
| 308 | spi_imx_buf_rx_swap_u32(spi_imx); | ||
| 309 | return; | ||
| 310 | } | ||
| 311 | |||
| 312 | if (bytes_per_word == 1) | ||
| 313 | spi_imx_buf_rx_u8(spi_imx); | ||
| 314 | else if (bytes_per_word == 2) | ||
| 315 | spi_imx_buf_rx_u16(spi_imx); | ||
| 316 | } | ||
| 317 | |||
| 318 | static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx) | ||
| 319 | { | ||
| 320 | u32 val = 0; | ||
| 321 | #ifdef __LITTLE_ENDIAN | ||
| 322 | unsigned int bytes_per_word; | ||
| 323 | #endif | ||
| 324 | |||
| 325 | if (spi_imx->tx_buf) { | ||
| 326 | val = *(u32 *)spi_imx->tx_buf; | ||
| 327 | val &= spi_imx->word_mask; | ||
| 328 | spi_imx->tx_buf += sizeof(u32); | ||
| 329 | } | ||
| 330 | |||
| 331 | spi_imx->count -= sizeof(u32); | ||
| 332 | #ifdef __LITTLE_ENDIAN | ||
| 333 | bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); | ||
| 334 | |||
| 335 | if (bytes_per_word == 1) | ||
| 336 | val = cpu_to_be32(val); | ||
| 337 | else if (bytes_per_word == 2) | ||
| 338 | val = (val << 16) | (val >> 16); | ||
| 339 | #endif | ||
| 340 | writel(val, spi_imx->base + MXC_CSPITXDATA); | ||
| 341 | } | ||
| 342 | |||
| 343 | static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx) | ||
| 344 | { | ||
| 345 | u32 ctrl, val; | ||
| 346 | unsigned int bytes_per_word; | ||
| 347 | |||
| 348 | if (spi_imx->count == spi_imx->remainder) { | ||
| 349 | ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); | ||
| 350 | ctrl &= ~MX51_ECSPI_CTRL_BL_MASK; | ||
| 351 | if (spi_imx->count > MX51_ECSPI_CTRL_MAX_BURST) { | ||
| 352 | spi_imx->remainder = spi_imx->count % | ||
| 353 | MX51_ECSPI_CTRL_MAX_BURST; | ||
| 354 | val = MX51_ECSPI_CTRL_MAX_BURST * 8 - 1; | ||
| 355 | } else if (spi_imx->count >= sizeof(u32)) { | ||
| 356 | spi_imx->remainder = spi_imx->count % sizeof(u32); | ||
| 357 | val = (spi_imx->count - spi_imx->remainder) * 8 - 1; | ||
| 358 | } else { | ||
| 359 | spi_imx->remainder = 0; | ||
| 360 | val = spi_imx->bits_per_word - 1; | ||
| 361 | spi_imx->read_u32 = 0; | ||
| 362 | } | ||
| 363 | |||
| 364 | ctrl |= (val << MX51_ECSPI_CTRL_BL_OFFSET); | ||
| 365 | writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); | ||
| 366 | } | ||
| 367 | |||
| 368 | if (spi_imx->count >= sizeof(u32)) { | ||
| 369 | spi_imx_buf_tx_swap_u32(spi_imx); | ||
| 370 | return; | ||
| 371 | } | ||
| 372 | |||
| 373 | bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); | ||
| 374 | |||
| 375 | if (bytes_per_word == 1) | ||
| 376 | spi_imx_buf_tx_u8(spi_imx); | ||
| 377 | else if (bytes_per_word == 2) | ||
| 378 | spi_imx_buf_tx_u16(spi_imx); | ||
| 379 | } | ||
| 380 | |||
| 272 | /* MX51 eCSPI */ | 381 | /* MX51 eCSPI */ |
| 273 | static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx, | 382 | static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx, |
| 274 | unsigned int fspi, unsigned int *fres) | 383 | unsigned int fspi, unsigned int *fres) |
| @@ -513,8 +622,8 @@ static int mx31_config(struct spi_device *spi) | |||
| 513 | reg |= MX31_CSPICTRL_POL; | 622 | reg |= MX31_CSPICTRL_POL; |
| 514 | if (spi->mode & SPI_CS_HIGH) | 623 | if (spi->mode & SPI_CS_HIGH) |
| 515 | reg |= MX31_CSPICTRL_SSPOL; | 624 | reg |= MX31_CSPICTRL_SSPOL; |
| 516 | if (spi->cs_gpio < 0) | 625 | if (!gpio_is_valid(spi->cs_gpio)) |
| 517 | reg |= (spi->cs_gpio + 32) << | 626 | reg |= (spi->chip_select) << |
| 518 | (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : | 627 | (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : |
| 519 | MX31_CSPICTRL_CS_SHIFT); | 628 | MX31_CSPICTRL_CS_SHIFT); |
| 520 | 629 | ||
| @@ -605,8 +714,8 @@ static int mx21_config(struct spi_device *spi) | |||
| 605 | reg |= MX21_CSPICTRL_POL; | 714 | reg |= MX21_CSPICTRL_POL; |
| 606 | if (spi->mode & SPI_CS_HIGH) | 715 | if (spi->mode & SPI_CS_HIGH) |
| 607 | reg |= MX21_CSPICTRL_SSPOL; | 716 | reg |= MX21_CSPICTRL_SSPOL; |
| 608 | if (spi->cs_gpio < 0) | 717 | if (!gpio_is_valid(spi->cs_gpio)) |
| 609 | reg |= (spi->cs_gpio + 32) << MX21_CSPICTRL_CS_SHIFT; | 718 | reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT; |
| 610 | 719 | ||
| 611 | writel(reg, spi_imx->base + MXC_CSPICTRL); | 720 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
| 612 | 721 | ||
| @@ -693,6 +802,9 @@ static struct spi_imx_devtype_data imx1_cspi_devtype_data = { | |||
| 693 | .trigger = mx1_trigger, | 802 | .trigger = mx1_trigger, |
| 694 | .rx_available = mx1_rx_available, | 803 | .rx_available = mx1_rx_available, |
| 695 | .reset = mx1_reset, | 804 | .reset = mx1_reset, |
| 805 | .fifo_size = 8, | ||
| 806 | .has_dmamode = false, | ||
| 807 | .dynamic_burst = false, | ||
| 696 | .devtype = IMX1_CSPI, | 808 | .devtype = IMX1_CSPI, |
| 697 | }; | 809 | }; |
| 698 | 810 | ||
| @@ -702,6 +814,9 @@ static struct spi_imx_devtype_data imx21_cspi_devtype_data = { | |||
| 702 | .trigger = mx21_trigger, | 814 | .trigger = mx21_trigger, |
| 703 | .rx_available = mx21_rx_available, | 815 | .rx_available = mx21_rx_available, |
| 704 | .reset = mx21_reset, | 816 | .reset = mx21_reset, |
| 817 | .fifo_size = 8, | ||
| 818 | .has_dmamode = false, | ||
| 819 | .dynamic_burst = false, | ||
| 705 | .devtype = IMX21_CSPI, | 820 | .devtype = IMX21_CSPI, |
| 706 | }; | 821 | }; |
| 707 | 822 | ||
| @@ -712,6 +827,9 @@ static struct spi_imx_devtype_data imx27_cspi_devtype_data = { | |||
| 712 | .trigger = mx21_trigger, | 827 | .trigger = mx21_trigger, |
| 713 | .rx_available = mx21_rx_available, | 828 | .rx_available = mx21_rx_available, |
| 714 | .reset = mx21_reset, | 829 | .reset = mx21_reset, |
| 830 | .fifo_size = 8, | ||
| 831 | .has_dmamode = false, | ||
| 832 | .dynamic_burst = false, | ||
| 715 | .devtype = IMX27_CSPI, | 833 | .devtype = IMX27_CSPI, |
| 716 | }; | 834 | }; |
| 717 | 835 | ||
| @@ -721,6 +839,9 @@ static struct spi_imx_devtype_data imx31_cspi_devtype_data = { | |||
| 721 | .trigger = mx31_trigger, | 839 | .trigger = mx31_trigger, |
| 722 | .rx_available = mx31_rx_available, | 840 | .rx_available = mx31_rx_available, |
| 723 | .reset = mx31_reset, | 841 | .reset = mx31_reset, |
| 842 | .fifo_size = 8, | ||
| 843 | .has_dmamode = false, | ||
| 844 | .dynamic_burst = false, | ||
| 724 | .devtype = IMX31_CSPI, | 845 | .devtype = IMX31_CSPI, |
| 725 | }; | 846 | }; |
| 726 | 847 | ||
| @@ -731,6 +852,9 @@ static struct spi_imx_devtype_data imx35_cspi_devtype_data = { | |||
| 731 | .trigger = mx31_trigger, | 852 | .trigger = mx31_trigger, |
| 732 | .rx_available = mx31_rx_available, | 853 | .rx_available = mx31_rx_available, |
| 733 | .reset = mx31_reset, | 854 | .reset = mx31_reset, |
| 855 | .fifo_size = 8, | ||
| 856 | .has_dmamode = true, | ||
| 857 | .dynamic_burst = false, | ||
| 734 | .devtype = IMX35_CSPI, | 858 | .devtype = IMX35_CSPI, |
| 735 | }; | 859 | }; |
| 736 | 860 | ||
| @@ -740,9 +864,23 @@ static struct spi_imx_devtype_data imx51_ecspi_devtype_data = { | |||
| 740 | .trigger = mx51_ecspi_trigger, | 864 | .trigger = mx51_ecspi_trigger, |
| 741 | .rx_available = mx51_ecspi_rx_available, | 865 | .rx_available = mx51_ecspi_rx_available, |
| 742 | .reset = mx51_ecspi_reset, | 866 | .reset = mx51_ecspi_reset, |
| 867 | .fifo_size = 64, | ||
| 868 | .has_dmamode = true, | ||
| 869 | .dynamic_burst = true, | ||
| 743 | .devtype = IMX51_ECSPI, | 870 | .devtype = IMX51_ECSPI, |
| 744 | }; | 871 | }; |
| 745 | 872 | ||
| 873 | static struct spi_imx_devtype_data imx53_ecspi_devtype_data = { | ||
| 874 | .intctrl = mx51_ecspi_intctrl, | ||
| 875 | .config = mx51_ecspi_config, | ||
| 876 | .trigger = mx51_ecspi_trigger, | ||
| 877 | .rx_available = mx51_ecspi_rx_available, | ||
| 878 | .reset = mx51_ecspi_reset, | ||
| 879 | .fifo_size = 64, | ||
| 880 | .has_dmamode = true, | ||
| 881 | .devtype = IMX53_ECSPI, | ||
| 882 | }; | ||
| 883 | |||
| 746 | static const struct platform_device_id spi_imx_devtype[] = { | 884 | static const struct platform_device_id spi_imx_devtype[] = { |
| 747 | { | 885 | { |
| 748 | .name = "imx1-cspi", | 886 | .name = "imx1-cspi", |
| @@ -763,6 +901,9 @@ static const struct platform_device_id spi_imx_devtype[] = { | |||
| 763 | .name = "imx51-ecspi", | 901 | .name = "imx51-ecspi", |
| 764 | .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data, | 902 | .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data, |
| 765 | }, { | 903 | }, { |
| 904 | .name = "imx53-ecspi", | ||
| 905 | .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data, | ||
| 906 | }, { | ||
| 766 | /* sentinel */ | 907 | /* sentinel */ |
| 767 | } | 908 | } |
| 768 | }; | 909 | }; |
| @@ -774,6 +915,7 @@ static const struct of_device_id spi_imx_dt_ids[] = { | |||
| 774 | { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, | 915 | { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, |
| 775 | { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, | 916 | { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, |
| 776 | { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, | 917 | { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, |
| 918 | { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, }, | ||
| 777 | { /* sentinel */ } | 919 | { /* sentinel */ } |
| 778 | }; | 920 | }; |
| 779 | MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); | 921 | MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); |
| @@ -783,6 +925,9 @@ static void spi_imx_chipselect(struct spi_device *spi, int is_active) | |||
| 783 | int active = is_active != BITBANG_CS_INACTIVE; | 925 | int active = is_active != BITBANG_CS_INACTIVE; |
| 784 | int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); | 926 | int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); |
| 785 | 927 | ||
| 928 | if (spi->mode & SPI_NO_CS) | ||
| 929 | return; | ||
| 930 | |||
| 786 | if (!gpio_is_valid(spi->cs_gpio)) | 931 | if (!gpio_is_valid(spi->cs_gpio)) |
| 787 | return; | 932 | return; |
| 788 | 933 | ||
| @@ -791,9 +936,11 @@ static void spi_imx_chipselect(struct spi_device *spi, int is_active) | |||
| 791 | 936 | ||
| 792 | static void spi_imx_push(struct spi_imx_data *spi_imx) | 937 | static void spi_imx_push(struct spi_imx_data *spi_imx) |
| 793 | { | 938 | { |
| 794 | while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) { | 939 | while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) { |
| 795 | if (!spi_imx->count) | 940 | if (!spi_imx->count) |
| 796 | break; | 941 | break; |
| 942 | if (spi_imx->txfifo && (spi_imx->count == spi_imx->remainder)) | ||
| 943 | break; | ||
| 797 | spi_imx->tx(spi_imx); | 944 | spi_imx->tx(spi_imx); |
| 798 | spi_imx->txfifo++; | 945 | spi_imx->txfifo++; |
| 799 | } | 946 | } |
| @@ -887,15 +1034,37 @@ static int spi_imx_setupxfer(struct spi_device *spi, | |||
| 887 | spi_imx->speed_hz = t->speed_hz; | 1034 | spi_imx->speed_hz = t->speed_hz; |
| 888 | 1035 | ||
| 889 | /* Initialize the functions for transfer */ | 1036 | /* Initialize the functions for transfer */ |
| 890 | if (spi_imx->bits_per_word <= 8) { | 1037 | if (spi_imx->devtype_data->dynamic_burst) { |
| 891 | spi_imx->rx = spi_imx_buf_rx_u8; | 1038 | u32 mask; |
| 892 | spi_imx->tx = spi_imx_buf_tx_u8; | 1039 | |
| 893 | } else if (spi_imx->bits_per_word <= 16) { | 1040 | spi_imx->dynamic_burst = 0; |
| 894 | spi_imx->rx = spi_imx_buf_rx_u16; | 1041 | spi_imx->remainder = 0; |
| 895 | spi_imx->tx = spi_imx_buf_tx_u16; | 1042 | spi_imx->read_u32 = 1; |
| 1043 | |||
| 1044 | mask = (1 << spi_imx->bits_per_word) - 1; | ||
| 1045 | spi_imx->rx = spi_imx_buf_rx_swap; | ||
| 1046 | spi_imx->tx = spi_imx_buf_tx_swap; | ||
| 1047 | spi_imx->dynamic_burst = 1; | ||
| 1048 | spi_imx->remainder = t->len; | ||
| 1049 | |||
| 1050 | if (spi_imx->bits_per_word <= 8) | ||
| 1051 | spi_imx->word_mask = mask << 24 | mask << 16 | ||
| 1052 | | mask << 8 | mask; | ||
| 1053 | else if (spi_imx->bits_per_word <= 16) | ||
| 1054 | spi_imx->word_mask = mask << 16 | mask; | ||
| 1055 | else | ||
| 1056 | spi_imx->word_mask = mask; | ||
| 896 | } else { | 1057 | } else { |
| 897 | spi_imx->rx = spi_imx_buf_rx_u32; | 1058 | if (spi_imx->bits_per_word <= 8) { |
| 898 | spi_imx->tx = spi_imx_buf_tx_u32; | 1059 | spi_imx->rx = spi_imx_buf_rx_u8; |
| 1060 | spi_imx->tx = spi_imx_buf_tx_u8; | ||
| 1061 | } else if (spi_imx->bits_per_word <= 16) { | ||
| 1062 | spi_imx->rx = spi_imx_buf_rx_u16; | ||
| 1063 | spi_imx->tx = spi_imx_buf_tx_u16; | ||
| 1064 | } else { | ||
| 1065 | spi_imx->rx = spi_imx_buf_rx_u32; | ||
| 1066 | spi_imx->tx = spi_imx_buf_tx_u32; | ||
| 1067 | } | ||
| 899 | } | 1068 | } |
| 900 | 1069 | ||
| 901 | if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t)) | 1070 | if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t)) |
| @@ -938,7 +1107,7 @@ static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx, | |||
| 938 | if (of_machine_is_compatible("fsl,imx6dl")) | 1107 | if (of_machine_is_compatible("fsl,imx6dl")) |
| 939 | return 0; | 1108 | return 0; |
| 940 | 1109 | ||
| 941 | spi_imx->wml = spi_imx_get_fifosize(spi_imx) / 2; | 1110 | spi_imx->wml = spi_imx->devtype_data->fifo_size / 2; |
| 942 | 1111 | ||
| 943 | /* Prepare for TX DMA: */ | 1112 | /* Prepare for TX DMA: */ |
| 944 | master->dma_tx = dma_request_slave_channel_reason(dev, "tx"); | 1113 | master->dma_tx = dma_request_slave_channel_reason(dev, "tx"); |
| @@ -1109,6 +1278,9 @@ static int spi_imx_setup(struct spi_device *spi) | |||
| 1109 | dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, | 1278 | dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, |
| 1110 | spi->mode, spi->bits_per_word, spi->max_speed_hz); | 1279 | spi->mode, spi->bits_per_word, spi->max_speed_hz); |
| 1111 | 1280 | ||
| 1281 | if (spi->mode & SPI_NO_CS) | ||
| 1282 | return 0; | ||
| 1283 | |||
| 1112 | if (gpio_is_valid(spi->cs_gpio)) | 1284 | if (gpio_is_valid(spi->cs_gpio)) |
| 1113 | gpio_direction_output(spi->cs_gpio, | 1285 | gpio_direction_output(spi->cs_gpio, |
| 1114 | spi->mode & SPI_CS_HIGH ? 0 : 1); | 1286 | spi->mode & SPI_CS_HIGH ? 0 : 1); |
| @@ -1208,8 +1380,10 @@ static int spi_imx_probe(struct platform_device *pdev) | |||
| 1208 | spi_imx->bitbang.master->cleanup = spi_imx_cleanup; | 1380 | spi_imx->bitbang.master->cleanup = spi_imx_cleanup; |
| 1209 | spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message; | 1381 | spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message; |
| 1210 | spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; | 1382 | spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; |
| 1211 | spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | 1383 | spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ |
| 1212 | if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx)) | 1384 | | SPI_NO_CS; |
| 1385 | if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) || | ||
| 1386 | is_imx53_ecspi(spi_imx)) | ||
| 1213 | spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY; | 1387 | spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY; |
| 1214 | 1388 | ||
| 1215 | spi_imx->spi_drctl = spi_drctl; | 1389 | spi_imx->spi_drctl = spi_drctl; |
| @@ -1262,7 +1436,7 @@ static int spi_imx_probe(struct platform_device *pdev) | |||
| 1262 | * Only validated on i.mx35 and i.mx6 now, can remove the constraint | 1436 | * Only validated on i.mx35 and i.mx6 now, can remove the constraint |
| 1263 | * if validated on other chips. | 1437 | * if validated on other chips. |
| 1264 | */ | 1438 | */ |
| 1265 | if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx)) { | 1439 | if (spi_imx->devtype_data->has_dmamode) { |
| 1266 | ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master); | 1440 | ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master); |
| 1267 | if (ret == -EPROBE_DEFER) | 1441 | if (ret == -EPROBE_DEFER) |
| 1268 | goto out_clk_put; | 1442 | goto out_clk_put; |
