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path: root/drivers/rtc/rtc-ds1307.c
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Diffstat (limited to 'drivers/rtc/rtc-ds1307.c')
-rw-r--r--drivers/rtc/rtc-ds1307.c707
1 files changed, 352 insertions, 355 deletions
diff --git a/drivers/rtc/rtc-ds1307.c b/drivers/rtc/rtc-ds1307.c
index 74b31dce484f..07530fe1da2a 100644
--- a/drivers/rtc/rtc-ds1307.c
+++ b/drivers/rtc/rtc-ds1307.c
@@ -114,6 +114,33 @@ enum ds_type {
114# define RX8025_BIT_VDET 0x40 114# define RX8025_BIT_VDET 0x40
115# define RX8025_BIT_XST 0x20 115# define RX8025_BIT_XST 0x20
116 116
117#define RX8130_REG_ALARM_MIN 0x17
118#define RX8130_REG_ALARM_HOUR 0x18
119#define RX8130_REG_ALARM_WEEK_OR_DAY 0x19
120#define RX8130_REG_EXTENSION 0x1c
121#define RX8130_REG_EXTENSION_WADA BIT(3)
122#define RX8130_REG_FLAG 0x1d
123#define RX8130_REG_FLAG_VLF BIT(1)
124#define RX8130_REG_FLAG_AF BIT(3)
125#define RX8130_REG_CONTROL0 0x1e
126#define RX8130_REG_CONTROL0_AIE BIT(3)
127
128#define MCP794XX_REG_CONTROL 0x07
129# define MCP794XX_BIT_ALM0_EN 0x10
130# define MCP794XX_BIT_ALM1_EN 0x20
131#define MCP794XX_REG_ALARM0_BASE 0x0a
132#define MCP794XX_REG_ALARM0_CTRL 0x0d
133#define MCP794XX_REG_ALARM1_BASE 0x11
134#define MCP794XX_REG_ALARM1_CTRL 0x14
135# define MCP794XX_BIT_ALMX_IF BIT(3)
136# define MCP794XX_BIT_ALMX_C0 BIT(4)
137# define MCP794XX_BIT_ALMX_C1 BIT(5)
138# define MCP794XX_BIT_ALMX_C2 BIT(6)
139# define MCP794XX_BIT_ALMX_POL BIT(7)
140# define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
141 MCP794XX_BIT_ALMX_C1 | \
142 MCP794XX_BIT_ALMX_C2)
143
117#define M41TXX_REG_CONTROL 0x07 144#define M41TXX_REG_CONTROL 0x07
118# define M41TXX_BIT_OUT BIT(7) 145# define M41TXX_BIT_OUT BIT(7)
119# define M41TXX_BIT_FT BIT(6) 146# define M41TXX_BIT_FT BIT(6)
@@ -158,289 +185,7 @@ struct chip_desc {
158 bool); 185 bool);
159}; 186};
160 187
161static int ds1307_get_time(struct device *dev, struct rtc_time *t); 188static const struct chip_desc chips[last_ds_type];
162static int ds1307_set_time(struct device *dev, struct rtc_time *t);
163static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t);
164static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t);
165static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled);
166static u8 do_trickle_setup_ds1339(struct ds1307 *, u32 ohms, bool diode);
167static irqreturn_t rx8130_irq(int irq, void *dev_id);
168static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t);
169static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t);
170static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled);
171static irqreturn_t mcp794xx_irq(int irq, void *dev_id);
172static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t);
173static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t);
174static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled);
175static int m41txx_rtc_read_offset(struct device *dev, long *offset);
176static int m41txx_rtc_set_offset(struct device *dev, long offset);
177
178static const struct rtc_class_ops rx8130_rtc_ops = {
179 .read_time = ds1307_get_time,
180 .set_time = ds1307_set_time,
181 .read_alarm = rx8130_read_alarm,
182 .set_alarm = rx8130_set_alarm,
183 .alarm_irq_enable = rx8130_alarm_irq_enable,
184};
185
186static const struct rtc_class_ops mcp794xx_rtc_ops = {
187 .read_time = ds1307_get_time,
188 .set_time = ds1307_set_time,
189 .read_alarm = mcp794xx_read_alarm,
190 .set_alarm = mcp794xx_set_alarm,
191 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
192};
193
194static const struct rtc_class_ops m41txx_rtc_ops = {
195 .read_time = ds1307_get_time,
196 .set_time = ds1307_set_time,
197 .read_alarm = ds1337_read_alarm,
198 .set_alarm = ds1337_set_alarm,
199 .alarm_irq_enable = ds1307_alarm_irq_enable,
200 .read_offset = m41txx_rtc_read_offset,
201 .set_offset = m41txx_rtc_set_offset,
202};
203
204static const struct chip_desc chips[last_ds_type] = {
205 [ds_1307] = {
206 .nvram_offset = 8,
207 .nvram_size = 56,
208 },
209 [ds_1308] = {
210 .nvram_offset = 8,
211 .nvram_size = 56,
212 },
213 [ds_1337] = {
214 .alarm = 1,
215 .century_reg = DS1307_REG_MONTH,
216 .century_bit = DS1337_BIT_CENTURY,
217 },
218 [ds_1338] = {
219 .nvram_offset = 8,
220 .nvram_size = 56,
221 },
222 [ds_1339] = {
223 .alarm = 1,
224 .century_reg = DS1307_REG_MONTH,
225 .century_bit = DS1337_BIT_CENTURY,
226 .bbsqi_bit = DS1339_BIT_BBSQI,
227 .trickle_charger_reg = 0x10,
228 .do_trickle_setup = &do_trickle_setup_ds1339,
229 },
230 [ds_1340] = {
231 .century_reg = DS1307_REG_HOUR,
232 .century_enable_bit = DS1340_BIT_CENTURY_EN,
233 .century_bit = DS1340_BIT_CENTURY,
234 .do_trickle_setup = &do_trickle_setup_ds1339,
235 .trickle_charger_reg = 0x08,
236 },
237 [ds_1341] = {
238 .century_reg = DS1307_REG_MONTH,
239 .century_bit = DS1337_BIT_CENTURY,
240 },
241 [ds_1388] = {
242 .offset = 1,
243 .trickle_charger_reg = 0x0a,
244 },
245 [ds_3231] = {
246 .alarm = 1,
247 .century_reg = DS1307_REG_MONTH,
248 .century_bit = DS1337_BIT_CENTURY,
249 .bbsqi_bit = DS3231_BIT_BBSQW,
250 },
251 [rx_8130] = {
252 .alarm = 1,
253 /* this is battery backed SRAM */
254 .nvram_offset = 0x20,
255 .nvram_size = 4, /* 32bit (4 word x 8 bit) */
256 .offset = 0x10,
257 .irq_handler = rx8130_irq,
258 .rtc_ops = &rx8130_rtc_ops,
259 },
260 [m41t0] = {
261 .rtc_ops = &m41txx_rtc_ops,
262 },
263 [m41t00] = {
264 .rtc_ops = &m41txx_rtc_ops,
265 },
266 [m41t11] = {
267 /* this is battery backed SRAM */
268 .nvram_offset = 8,
269 .nvram_size = 56,
270 .rtc_ops = &m41txx_rtc_ops,
271 },
272 [mcp794xx] = {
273 .alarm = 1,
274 /* this is battery backed SRAM */
275 .nvram_offset = 0x20,
276 .nvram_size = 0x40,
277 .irq_handler = mcp794xx_irq,
278 .rtc_ops = &mcp794xx_rtc_ops,
279 },
280};
281
282static const struct i2c_device_id ds1307_id[] = {
283 { "ds1307", ds_1307 },
284 { "ds1308", ds_1308 },
285 { "ds1337", ds_1337 },
286 { "ds1338", ds_1338 },
287 { "ds1339", ds_1339 },
288 { "ds1388", ds_1388 },
289 { "ds1340", ds_1340 },
290 { "ds1341", ds_1341 },
291 { "ds3231", ds_3231 },
292 { "m41t0", m41t0 },
293 { "m41t00", m41t00 },
294 { "m41t11", m41t11 },
295 { "mcp7940x", mcp794xx },
296 { "mcp7941x", mcp794xx },
297 { "pt7c4338", ds_1307 },
298 { "rx8025", rx_8025 },
299 { "isl12057", ds_1337 },
300 { "rx8130", rx_8130 },
301 { }
302};
303MODULE_DEVICE_TABLE(i2c, ds1307_id);
304
305#ifdef CONFIG_OF
306static const struct of_device_id ds1307_of_match[] = {
307 {
308 .compatible = "dallas,ds1307",
309 .data = (void *)ds_1307
310 },
311 {
312 .compatible = "dallas,ds1308",
313 .data = (void *)ds_1308
314 },
315 {
316 .compatible = "dallas,ds1337",
317 .data = (void *)ds_1337
318 },
319 {
320 .compatible = "dallas,ds1338",
321 .data = (void *)ds_1338
322 },
323 {
324 .compatible = "dallas,ds1339",
325 .data = (void *)ds_1339
326 },
327 {
328 .compatible = "dallas,ds1388",
329 .data = (void *)ds_1388
330 },
331 {
332 .compatible = "dallas,ds1340",
333 .data = (void *)ds_1340
334 },
335 {
336 .compatible = "dallas,ds1341",
337 .data = (void *)ds_1341
338 },
339 {
340 .compatible = "maxim,ds3231",
341 .data = (void *)ds_3231
342 },
343 {
344 .compatible = "st,m41t0",
345 .data = (void *)m41t0
346 },
347 {
348 .compatible = "st,m41t00",
349 .data = (void *)m41t00
350 },
351 {
352 .compatible = "st,m41t11",
353 .data = (void *)m41t11
354 },
355 {
356 .compatible = "microchip,mcp7940x",
357 .data = (void *)mcp794xx
358 },
359 {
360 .compatible = "microchip,mcp7941x",
361 .data = (void *)mcp794xx
362 },
363 {
364 .compatible = "pericom,pt7c4338",
365 .data = (void *)ds_1307
366 },
367 {
368 .compatible = "epson,rx8025",
369 .data = (void *)rx_8025
370 },
371 {
372 .compatible = "isil,isl12057",
373 .data = (void *)ds_1337
374 },
375 {
376 .compatible = "epson,rx8130",
377 .data = (void *)rx_8130
378 },
379 { }
380};
381MODULE_DEVICE_TABLE(of, ds1307_of_match);
382#endif
383
384#ifdef CONFIG_ACPI
385static const struct acpi_device_id ds1307_acpi_ids[] = {
386 { .id = "DS1307", .driver_data = ds_1307 },
387 { .id = "DS1308", .driver_data = ds_1308 },
388 { .id = "DS1337", .driver_data = ds_1337 },
389 { .id = "DS1338", .driver_data = ds_1338 },
390 { .id = "DS1339", .driver_data = ds_1339 },
391 { .id = "DS1388", .driver_data = ds_1388 },
392 { .id = "DS1340", .driver_data = ds_1340 },
393 { .id = "DS1341", .driver_data = ds_1341 },
394 { .id = "DS3231", .driver_data = ds_3231 },
395 { .id = "M41T0", .driver_data = m41t0 },
396 { .id = "M41T00", .driver_data = m41t00 },
397 { .id = "M41T11", .driver_data = m41t11 },
398 { .id = "MCP7940X", .driver_data = mcp794xx },
399 { .id = "MCP7941X", .driver_data = mcp794xx },
400 { .id = "PT7C4338", .driver_data = ds_1307 },
401 { .id = "RX8025", .driver_data = rx_8025 },
402 { .id = "ISL12057", .driver_data = ds_1337 },
403 { .id = "RX8130", .driver_data = rx_8130 },
404 { }
405};
406MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
407#endif
408
409/*
410 * The ds1337 and ds1339 both have two alarms, but we only use the first
411 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
412 * signal; ds1339 chips have only one alarm signal.
413 */
414static irqreturn_t ds1307_irq(int irq, void *dev_id)
415{
416 struct ds1307 *ds1307 = dev_id;
417 struct mutex *lock = &ds1307->rtc->ops_lock;
418 int stat, ret;
419
420 mutex_lock(lock);
421 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
422 if (ret)
423 goto out;
424
425 if (stat & DS1337_BIT_A1I) {
426 stat &= ~DS1337_BIT_A1I;
427 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
428
429 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
430 DS1337_BIT_A1IE, 0);
431 if (ret)
432 goto out;
433
434 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
435 }
436
437out:
438 mutex_unlock(lock);
439
440 return IRQ_HANDLED;
441}
442
443/*----------------------------------------------------------------------*/
444 189
445static int ds1307_get_time(struct device *dev, struct rtc_time *t) 190static int ds1307_get_time(struct device *dev, struct rtc_time *t)
446{ 191{
@@ -449,6 +194,20 @@ static int ds1307_get_time(struct device *dev, struct rtc_time *t)
449 const struct chip_desc *chip = &chips[ds1307->type]; 194 const struct chip_desc *chip = &chips[ds1307->type];
450 u8 regs[7]; 195 u8 regs[7];
451 196
197 if (ds1307->type == rx_8130) {
198 unsigned int regflag;
199 ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, &regflag);
200 if (ret) {
201 dev_err(dev, "%s error %d\n", "read", ret);
202 return ret;
203 }
204
205 if (regflag & RX8130_REG_FLAG_VLF) {
206 dev_warn_once(dev, "oscillator failed, set time!\n");
207 return -EINVAL;
208 }
209 }
210
452 /* read the RTC date and time registers all at once */ 211 /* read the RTC date and time registers all at once */
453 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs, 212 ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
454 sizeof(regs)); 213 sizeof(regs));
@@ -548,6 +307,17 @@ static int ds1307_set_time(struct device *dev, struct rtc_time *t)
548 dev_err(dev, "%s error %d\n", "write", result); 307 dev_err(dev, "%s error %d\n", "write", result);
549 return result; 308 return result;
550 } 309 }
310
311 if (ds1307->type == rx_8130) {
312 /* clear Voltage Loss Flag as data is available now */
313 result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
314 ~(u8)RX8130_REG_FLAG_VLF);
315 if (result) {
316 dev_err(dev, "%s error %d\n", "write", result);
317 return result;
318 }
319 }
320
551 return 0; 321 return 0;
552} 322}
553 323
@@ -666,29 +436,28 @@ static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
666 enabled ? DS1337_BIT_A1IE : 0); 436 enabled ? DS1337_BIT_A1IE : 0);
667} 437}
668 438
669static const struct rtc_class_ops ds13xx_rtc_ops = { 439static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
670 .read_time = ds1307_get_time, 440{
671 .set_time = ds1307_set_time, 441 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
672 .read_alarm = ds1337_read_alarm, 442 DS1307_TRICKLE_CHARGER_NO_DIODE;
673 .set_alarm = ds1337_set_alarm,
674 .alarm_irq_enable = ds1307_alarm_irq_enable,
675};
676
677/*----------------------------------------------------------------------*/
678
679/*
680 * Alarm support for rx8130 devices.
681 */
682 443
683#define RX8130_REG_ALARM_MIN 0x07 444 switch (ohms) {
684#define RX8130_REG_ALARM_HOUR 0x08 445 case 250:
685#define RX8130_REG_ALARM_WEEK_OR_DAY 0x09 446 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
686#define RX8130_REG_EXTENSION 0x0c 447 break;
687#define RX8130_REG_EXTENSION_WADA BIT(3) 448 case 2000:
688#define RX8130_REG_FLAG 0x0d 449 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
689#define RX8130_REG_FLAG_AF BIT(3) 450 break;
690#define RX8130_REG_CONTROL0 0x0e 451 case 4000:
691#define RX8130_REG_CONTROL0_AIE BIT(3) 452 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
453 break;
454 default:
455 dev_warn(ds1307->dev,
456 "Unsupported ohm value %u in dt\n", ohms);
457 return 0;
458 }
459 return setup;
460}
692 461
693static irqreturn_t rx8130_irq(int irq, void *dev_id) 462static irqreturn_t rx8130_irq(int irq, void *dev_id)
694{ 463{
@@ -785,8 +554,8 @@ static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
785 if (ret < 0) 554 if (ret < 0)
786 return ret; 555 return ret;
787 556
788 ctl[0] &= ~RX8130_REG_EXTENSION_WADA; 557 ctl[0] &= RX8130_REG_EXTENSION_WADA;
789 ctl[1] |= RX8130_REG_FLAG_AF; 558 ctl[1] &= ~RX8130_REG_FLAG_AF;
790 ctl[2] &= ~RX8130_REG_CONTROL0_AIE; 559 ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
791 560
792 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 561 ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
@@ -809,8 +578,7 @@ static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
809 578
810 ctl[2] |= RX8130_REG_CONTROL0_AIE; 579 ctl[2] |= RX8130_REG_CONTROL0_AIE;
811 580
812 return regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl, 581 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
813 sizeof(ctl));
814} 582}
815 583
816static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled) 584static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
@@ -833,28 +601,6 @@ static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
833 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg); 601 return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
834} 602}
835 603
836/*----------------------------------------------------------------------*/
837
838/*
839 * Alarm support for mcp794xx devices.
840 */
841
842#define MCP794XX_REG_CONTROL 0x07
843# define MCP794XX_BIT_ALM0_EN 0x10
844# define MCP794XX_BIT_ALM1_EN 0x20
845#define MCP794XX_REG_ALARM0_BASE 0x0a
846#define MCP794XX_REG_ALARM0_CTRL 0x0d
847#define MCP794XX_REG_ALARM1_BASE 0x11
848#define MCP794XX_REG_ALARM1_CTRL 0x14
849# define MCP794XX_BIT_ALMX_IF BIT(3)
850# define MCP794XX_BIT_ALMX_C0 BIT(4)
851# define MCP794XX_BIT_ALMX_C1 BIT(5)
852# define MCP794XX_BIT_ALMX_C2 BIT(6)
853# define MCP794XX_BIT_ALMX_POL BIT(7)
854# define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
855 MCP794XX_BIT_ALMX_C1 | \
856 MCP794XX_BIT_ALMX_C2)
857
858static irqreturn_t mcp794xx_irq(int irq, void *dev_id) 604static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
859{ 605{
860 struct ds1307 *ds1307 = dev_id; 606 struct ds1307 *ds1307 = dev_id;
@@ -1050,6 +796,281 @@ static int m41txx_rtc_set_offset(struct device *dev, long offset)
1050 ctrl_reg); 796 ctrl_reg);
1051} 797}
1052 798
799static const struct rtc_class_ops rx8130_rtc_ops = {
800 .read_time = ds1307_get_time,
801 .set_time = ds1307_set_time,
802 .read_alarm = rx8130_read_alarm,
803 .set_alarm = rx8130_set_alarm,
804 .alarm_irq_enable = rx8130_alarm_irq_enable,
805};
806
807static const struct rtc_class_ops mcp794xx_rtc_ops = {
808 .read_time = ds1307_get_time,
809 .set_time = ds1307_set_time,
810 .read_alarm = mcp794xx_read_alarm,
811 .set_alarm = mcp794xx_set_alarm,
812 .alarm_irq_enable = mcp794xx_alarm_irq_enable,
813};
814
815static const struct rtc_class_ops m41txx_rtc_ops = {
816 .read_time = ds1307_get_time,
817 .set_time = ds1307_set_time,
818 .read_alarm = ds1337_read_alarm,
819 .set_alarm = ds1337_set_alarm,
820 .alarm_irq_enable = ds1307_alarm_irq_enable,
821 .read_offset = m41txx_rtc_read_offset,
822 .set_offset = m41txx_rtc_set_offset,
823};
824
825static const struct chip_desc chips[last_ds_type] = {
826 [ds_1307] = {
827 .nvram_offset = 8,
828 .nvram_size = 56,
829 },
830 [ds_1308] = {
831 .nvram_offset = 8,
832 .nvram_size = 56,
833 },
834 [ds_1337] = {
835 .alarm = 1,
836 .century_reg = DS1307_REG_MONTH,
837 .century_bit = DS1337_BIT_CENTURY,
838 },
839 [ds_1338] = {
840 .nvram_offset = 8,
841 .nvram_size = 56,
842 },
843 [ds_1339] = {
844 .alarm = 1,
845 .century_reg = DS1307_REG_MONTH,
846 .century_bit = DS1337_BIT_CENTURY,
847 .bbsqi_bit = DS1339_BIT_BBSQI,
848 .trickle_charger_reg = 0x10,
849 .do_trickle_setup = &do_trickle_setup_ds1339,
850 },
851 [ds_1340] = {
852 .century_reg = DS1307_REG_HOUR,
853 .century_enable_bit = DS1340_BIT_CENTURY_EN,
854 .century_bit = DS1340_BIT_CENTURY,
855 .do_trickle_setup = &do_trickle_setup_ds1339,
856 .trickle_charger_reg = 0x08,
857 },
858 [ds_1341] = {
859 .century_reg = DS1307_REG_MONTH,
860 .century_bit = DS1337_BIT_CENTURY,
861 },
862 [ds_1388] = {
863 .offset = 1,
864 .trickle_charger_reg = 0x0a,
865 },
866 [ds_3231] = {
867 .alarm = 1,
868 .century_reg = DS1307_REG_MONTH,
869 .century_bit = DS1337_BIT_CENTURY,
870 .bbsqi_bit = DS3231_BIT_BBSQW,
871 },
872 [rx_8130] = {
873 .alarm = 1,
874 /* this is battery backed SRAM */
875 .nvram_offset = 0x20,
876 .nvram_size = 4, /* 32bit (4 word x 8 bit) */
877 .offset = 0x10,
878 .irq_handler = rx8130_irq,
879 .rtc_ops = &rx8130_rtc_ops,
880 },
881 [m41t0] = {
882 .rtc_ops = &m41txx_rtc_ops,
883 },
884 [m41t00] = {
885 .rtc_ops = &m41txx_rtc_ops,
886 },
887 [m41t11] = {
888 /* this is battery backed SRAM */
889 .nvram_offset = 8,
890 .nvram_size = 56,
891 .rtc_ops = &m41txx_rtc_ops,
892 },
893 [mcp794xx] = {
894 .alarm = 1,
895 /* this is battery backed SRAM */
896 .nvram_offset = 0x20,
897 .nvram_size = 0x40,
898 .irq_handler = mcp794xx_irq,
899 .rtc_ops = &mcp794xx_rtc_ops,
900 },
901};
902
903static const struct i2c_device_id ds1307_id[] = {
904 { "ds1307", ds_1307 },
905 { "ds1308", ds_1308 },
906 { "ds1337", ds_1337 },
907 { "ds1338", ds_1338 },
908 { "ds1339", ds_1339 },
909 { "ds1388", ds_1388 },
910 { "ds1340", ds_1340 },
911 { "ds1341", ds_1341 },
912 { "ds3231", ds_3231 },
913 { "m41t0", m41t0 },
914 { "m41t00", m41t00 },
915 { "m41t11", m41t11 },
916 { "mcp7940x", mcp794xx },
917 { "mcp7941x", mcp794xx },
918 { "pt7c4338", ds_1307 },
919 { "rx8025", rx_8025 },
920 { "isl12057", ds_1337 },
921 { "rx8130", rx_8130 },
922 { }
923};
924MODULE_DEVICE_TABLE(i2c, ds1307_id);
925
926#ifdef CONFIG_OF
927static const struct of_device_id ds1307_of_match[] = {
928 {
929 .compatible = "dallas,ds1307",
930 .data = (void *)ds_1307
931 },
932 {
933 .compatible = "dallas,ds1308",
934 .data = (void *)ds_1308
935 },
936 {
937 .compatible = "dallas,ds1337",
938 .data = (void *)ds_1337
939 },
940 {
941 .compatible = "dallas,ds1338",
942 .data = (void *)ds_1338
943 },
944 {
945 .compatible = "dallas,ds1339",
946 .data = (void *)ds_1339
947 },
948 {
949 .compatible = "dallas,ds1388",
950 .data = (void *)ds_1388
951 },
952 {
953 .compatible = "dallas,ds1340",
954 .data = (void *)ds_1340
955 },
956 {
957 .compatible = "dallas,ds1341",
958 .data = (void *)ds_1341
959 },
960 {
961 .compatible = "maxim,ds3231",
962 .data = (void *)ds_3231
963 },
964 {
965 .compatible = "st,m41t0",
966 .data = (void *)m41t0
967 },
968 {
969 .compatible = "st,m41t00",
970 .data = (void *)m41t00
971 },
972 {
973 .compatible = "st,m41t11",
974 .data = (void *)m41t11
975 },
976 {
977 .compatible = "microchip,mcp7940x",
978 .data = (void *)mcp794xx
979 },
980 {
981 .compatible = "microchip,mcp7941x",
982 .data = (void *)mcp794xx
983 },
984 {
985 .compatible = "pericom,pt7c4338",
986 .data = (void *)ds_1307
987 },
988 {
989 .compatible = "epson,rx8025",
990 .data = (void *)rx_8025
991 },
992 {
993 .compatible = "isil,isl12057",
994 .data = (void *)ds_1337
995 },
996 {
997 .compatible = "epson,rx8130",
998 .data = (void *)rx_8130
999 },
1000 { }
1001};
1002MODULE_DEVICE_TABLE(of, ds1307_of_match);
1003#endif
1004
1005#ifdef CONFIG_ACPI
1006static const struct acpi_device_id ds1307_acpi_ids[] = {
1007 { .id = "DS1307", .driver_data = ds_1307 },
1008 { .id = "DS1308", .driver_data = ds_1308 },
1009 { .id = "DS1337", .driver_data = ds_1337 },
1010 { .id = "DS1338", .driver_data = ds_1338 },
1011 { .id = "DS1339", .driver_data = ds_1339 },
1012 { .id = "DS1388", .driver_data = ds_1388 },
1013 { .id = "DS1340", .driver_data = ds_1340 },
1014 { .id = "DS1341", .driver_data = ds_1341 },
1015 { .id = "DS3231", .driver_data = ds_3231 },
1016 { .id = "M41T0", .driver_data = m41t0 },
1017 { .id = "M41T00", .driver_data = m41t00 },
1018 { .id = "M41T11", .driver_data = m41t11 },
1019 { .id = "MCP7940X", .driver_data = mcp794xx },
1020 { .id = "MCP7941X", .driver_data = mcp794xx },
1021 { .id = "PT7C4338", .driver_data = ds_1307 },
1022 { .id = "RX8025", .driver_data = rx_8025 },
1023 { .id = "ISL12057", .driver_data = ds_1337 },
1024 { .id = "RX8130", .driver_data = rx_8130 },
1025 { }
1026};
1027MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
1028#endif
1029
1030/*
1031 * The ds1337 and ds1339 both have two alarms, but we only use the first
1032 * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
1033 * signal; ds1339 chips have only one alarm signal.
1034 */
1035static irqreturn_t ds1307_irq(int irq, void *dev_id)
1036{
1037 struct ds1307 *ds1307 = dev_id;
1038 struct mutex *lock = &ds1307->rtc->ops_lock;
1039 int stat, ret;
1040
1041 mutex_lock(lock);
1042 ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
1043 if (ret)
1044 goto out;
1045
1046 if (stat & DS1337_BIT_A1I) {
1047 stat &= ~DS1337_BIT_A1I;
1048 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
1049
1050 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1051 DS1337_BIT_A1IE, 0);
1052 if (ret)
1053 goto out;
1054
1055 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
1056 }
1057
1058out:
1059 mutex_unlock(lock);
1060
1061 return IRQ_HANDLED;
1062}
1063
1064/*----------------------------------------------------------------------*/
1065
1066static const struct rtc_class_ops ds13xx_rtc_ops = {
1067 .read_time = ds1307_get_time,
1068 .set_time = ds1307_set_time,
1069 .read_alarm = ds1337_read_alarm,
1070 .set_alarm = ds1337_set_alarm,
1071 .alarm_irq_enable = ds1307_alarm_irq_enable,
1072};
1073
1053static ssize_t frequency_test_store(struct device *dev, 1074static ssize_t frequency_test_store(struct device *dev,
1054 struct device_attribute *attr, 1075 struct device_attribute *attr,
1055 const char *buf, size_t count) 1076 const char *buf, size_t count)
@@ -1137,30 +1158,6 @@ static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
1137 1158
1138/*----------------------------------------------------------------------*/ 1159/*----------------------------------------------------------------------*/
1139 1160
1140static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307,
1141 u32 ohms, bool diode)
1142{
1143 u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
1144 DS1307_TRICKLE_CHARGER_NO_DIODE;
1145
1146 switch (ohms) {
1147 case 250:
1148 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
1149 break;
1150 case 2000:
1151 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
1152 break;
1153 case 4000:
1154 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
1155 break;
1156 default:
1157 dev_warn(ds1307->dev,
1158 "Unsupported ohm value %u in dt\n", ohms);
1159 return 0;
1160 }
1161 return setup;
1162}
1163
1164static u8 ds1307_trickle_init(struct ds1307 *ds1307, 1161static u8 ds1307_trickle_init(struct ds1307 *ds1307,
1165 const struct chip_desc *chip) 1162 const struct chip_desc *chip)
1166{ 1163{
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-06 04:56:53 -0500