7 files changed, 181 insertions, 36 deletions

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c21da9fe51ec..2e01bd833ffd 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -109,7 +109,7 @@ config RESET_QCOM_PDC
 
 config RESET_SIMPLE
         bool "Simple Reset Controller Driver" if COMPILE_TEST
-        default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
+        default ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARCH_ASPEED
         help
           This enables a simple reset controller driver for reset lines that
           that can be asserted and deasserted by toggling bits in a contiguous,
@@ -128,6 +128,14 @@ config RESET_STM32MP157
         help
           This enables the RCC reset controller driver for STM32 MPUs.
 
+config RESET_SOCFPGA
+        bool "SoCFPGA Reset Driver" if COMPILE_TEST && !ARCH_SOCFPGA
+        default ARCH_SOCFPGA
+        select RESET_SIMPLE
+        help
+          This enables the reset driver for the SoCFPGA ARMv7 platforms. This
+          driver gets initialized early during platform init calls.
+
 config RESET_SUNXI
         bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
         default ARCH_SUNXI
@@ -163,15 +171,15 @@ config RESET_UNIPHIER
           Say Y if you want to control reset signals provided by System Control
           block, Media I/O block, Peripheral Block.
 
-config RESET_UNIPHIER_USB3
-        tristate "USB3 reset driver for UniPhier SoCs"
+config RESET_UNIPHIER_GLUE
+        tristate "Reset driver in glue layer for UniPhier SoCs"
         depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
         default ARCH_UNIPHIER
         select RESET_SIMPLE
         help
-          Support for the USB3 core reset on UniPhier SoCs.
-          Say Y if you want to control reset signals provided by
-          USB3 glue layer.
+          Support for peripheral core reset included in its own glue layer
+          on UniPhier SoCs. Say Y if you want to control reset signals
+          provided by the glue layer.
 
 config RESET_ZYNQ
         bool "ZYNQ Reset Driver" if COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index d08e8b90046a..dc7874df78d9 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -19,10 +19,11 @@ obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
 obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
 obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
 obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
+obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
 obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
 obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
-obj-$(CONFIG_RESET_UNIPHIER_USB3) += reset-uniphier-usb3.o
+obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o
 obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o
 
diff --git a/drivers/reset/core.c b/drivers/reset/core.c
index d1887c0ed5d3..9582efb70025 100644
--- a/drivers/reset/core.c
+++ b/drivers/reset/core.c
@@ -795,3 +795,45 @@ devm_reset_control_array_get(struct device *dev, bool shared, bool optional)
         return rstc;
 }
 EXPORT_SYMBOL_GPL(devm_reset_control_array_get);
+
+static int reset_control_get_count_from_lookup(struct device *dev)
+{
+        const struct reset_control_lookup *lookup;
+        const char *dev_id;
+        int count = 0;
+
+        if (!dev)
+                return -EINVAL;
+
+        dev_id = dev_name(dev);
+        mutex_lock(&reset_lookup_mutex);
+
+        list_for_each_entry(lookup, &reset_lookup_list, list) {
+                if (!strcmp(lookup->dev_id, dev_id))
+                        count++;
+        }
+
+        mutex_unlock(&reset_lookup_mutex);
+
+        if (count == 0)
+                count = -ENOENT;
+
+        return count;
+}
+
+/**
+ * reset_control_get_count - Count number of resets available with a device
+ *
+ * @dev: device for which to return the number of resets
+ *
+ * Returns positive reset count on success, or error number on failure and
+ * on count being zero.
+ */
+int reset_control_get_count(struct device *dev)
+{
+        if (dev->of_node)
+                return of_reset_control_get_count(dev->of_node);
+
+        return reset_control_get_count_from_lookup(dev);
+}
+EXPORT_SYMBOL_GPL(reset_control_get_count);
diff --git a/drivers/reset/reset-hsdk.c b/drivers/reset/reset-hsdk.c
index 8bce391c6943..4c7b8647b49c 100644
--- a/drivers/reset/reset-hsdk.c
+++ b/drivers/reset/reset-hsdk.c
@@ -86,6 +86,7 @@ static int hsdk_reset_reset(struct reset_controller_dev *rcdev,
 
 static const struct reset_control_ops hsdk_reset_ops = {
         .reset  = hsdk_reset_reset,
+        .deassert = hsdk_reset_reset,
 };
 
 static int hsdk_reset_probe(struct platform_device *pdev)
diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c
index a91107fc9e27..77fbba3100c8 100644
--- a/drivers/reset/reset-simple.c
+++ b/drivers/reset/reset-simple.c
@@ -109,7 +109,7 @@ struct reset_simple_devdata {
 #define SOCFPGA_NR_BANKS        8
 
 static const struct reset_simple_devdata reset_simple_socfpga = {
-        .reg_offset = 0x10,
+        .reg_offset = 0x20,
         .nr_resets = SOCFPGA_NR_BANKS * 32,
         .status_active_low = true,
 };
@@ -120,7 +120,8 @@ static const struct reset_simple_devdata reset_simple_active_low = {
 };
 
 static const struct of_device_id reset_simple_dt_ids[] = {
-        { .compatible = "altr,rst-mgr", .data = &reset_simple_socfpga },
+        { .compatible = "altr,stratix10-rst-mgr",
+                .data = &reset_simple_socfpga },
         { .compatible = "st,stm32-rcc", },
         { .compatible = "allwinner,sun6i-a31-clock-reset",
                 .data = &reset_simple_active_low },
@@ -166,14 +167,6 @@ static int reset_simple_probe(struct platform_device *pdev)
                 data->status_active_low = devdata->status_active_low;
         }
 
-        if (of_device_is_compatible(dev->of_node, "altr,rst-mgr") &&
-            of_property_read_u32(dev->of_node, "altr,modrst-offset",
-                                 &reg_offset)) {
-                dev_warn(dev,
-                         "missing altr,modrst-offset property, assuming 0x%x!\n",
-                         reg_offset);
-        }
-
         data->membase += reg_offset;
 
         return devm_reset_controller_register(dev, &data->rcdev);
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
new file mode 100644
index 000000000000..318cfc51c441
--- /dev/null
+++ b/drivers/reset/reset-socfpga.c
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018, Intel Corporation
+ * Copied from reset-sunxi.c
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#include "reset-simple.h"
+
+#define SOCFPGA_NR_BANKS        8
+void __init socfpga_reset_init(void);
+
+static int a10_reset_init(struct device_node *np)
+{
+        struct reset_simple_data *data;
+        struct resource res;
+        resource_size_t size;
+        int ret;
+        u32 reg_offset = 0x10;
+
+        data = kzalloc(sizeof(*data), GFP_KERNEL);
+        if (!data)
+                return -ENOMEM;
+
+        ret = of_address_to_resource(np, 0, &res);
+        if (ret)
+                goto err_alloc;
+
+        size = resource_size(&res);
+        if (!request_mem_region(res.start, size, np->name)) {
+                ret = -EBUSY;
+                goto err_alloc;
+        }
+
+        data->membase = ioremap(res.start, size);
+        if (!data->membase) {
+                ret = -ENOMEM;
+                goto err_alloc;
+        }
+
+        if (of_property_read_u32(np, "altr,modrst-offset", &reg_offset))
+                pr_warn("missing altr,modrst-offset property, assuming 0x10\n");
+        data->membase += reg_offset;
+
+        spin_lock_init(&data->lock);
+
+        data->rcdev.owner = THIS_MODULE;
+        data->rcdev.nr_resets = SOCFPGA_NR_BANKS * 32;
+        data->rcdev.ops = &reset_simple_ops;
+        data->rcdev.of_node = np;
+        data->status_active_low = true;
+
+        return reset_controller_register(&data->rcdev);
+
+err_alloc:
+        kfree(data);
+        return ret;
+};
+
+/*
+ * These are the reset controller we need to initialize early on in
+ * our system, before we can even think of using a regular device
+ * driver for it.
+ * The controllers that we can register through the regular device
+ * model are handled by the simple reset driver directly.
+ */
+static const struct of_device_id socfpga_early_reset_dt_ids[] __initconst = {
+        { .compatible = "altr,rst-mgr", },
+        { /* sentinel */ },
+};
+
+void __init socfpga_reset_init(void)
+{
+        struct device_node *np;
+
+        for_each_matching_node(np, socfpga_early_reset_dt_ids)
+                a10_reset_init(np);
+}
diff --git a/drivers/reset/reset-uniphier-usb3.c b/drivers/reset/reset-uniphier-glue.c
index ffa1b19b594d..a45923f4df6d 100644
--- a/drivers/reset/reset-uniphier-usb3.c
+++ b/drivers/reset/reset-uniphier-glue.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 //
-// reset-uniphier-usb3.c - USB3 reset driver for UniPhier
+// reset-uniphier-glue.c - Glue layer reset driver for UniPhier
 // Copyright 2018 Socionext Inc.
 // Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
 
@@ -15,24 +15,24 @@
 #define MAX_CLKS        2
 #define MAX_RSTS        2
 
-struct uniphier_usb3_reset_soc_data {
+struct uniphier_glue_reset_soc_data {
         int nclks;
         const char * const *clock_names;
         int nrsts;
         const char * const *reset_names;
 };
 
-struct uniphier_usb3_reset_priv {
+struct uniphier_glue_reset_priv {
         struct clk_bulk_data clk[MAX_CLKS];
         struct reset_control *rst[MAX_RSTS];
         struct reset_simple_data rdata;
-        const struct uniphier_usb3_reset_soc_data *data;
+        const struct uniphier_glue_reset_soc_data *data;
 };
 
-static int uniphier_usb3_reset_probe(struct platform_device *pdev)
+static int uniphier_glue_reset_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
-        struct uniphier_usb3_reset_priv *priv;
+        struct uniphier_glue_reset_priv *priv;
         struct resource *res;
         resource_size_t size;
         const char *name;
@@ -100,9 +100,9 @@ out_rst_assert:
         return ret;
 }
 
-static int uniphier_usb3_reset_remove(struct platform_device *pdev)
+static int uniphier_glue_reset_remove(struct platform_device *pdev)
 {
-        struct uniphier_usb3_reset_priv *priv = platform_get_drvdata(pdev);
+        struct uniphier_glue_reset_priv *priv = platform_get_drvdata(pdev);
         int i;
 
         for (i = 0; i < priv->data->nrsts; i++)
@@ -117,7 +117,7 @@ static const char * const uniphier_pro4_clock_reset_names[] = {
         "gio", "link",
 };
 
-static const struct uniphier_usb3_reset_soc_data uniphier_pro4_data = {
+static const struct uniphier_glue_reset_soc_data uniphier_pro4_data = {
         .nclks = ARRAY_SIZE(uniphier_pro4_clock_reset_names),
         .clock_names = uniphier_pro4_clock_reset_names,
         .nrsts = ARRAY_SIZE(uniphier_pro4_clock_reset_names),
@@ -128,14 +128,14 @@ static const char * const uniphier_pxs2_clock_reset_names[] = {
         "link",
 };
 
-static const struct uniphier_usb3_reset_soc_data uniphier_pxs2_data = {
+static const struct uniphier_glue_reset_soc_data uniphier_pxs2_data = {
         .nclks = ARRAY_SIZE(uniphier_pxs2_clock_reset_names),
         .clock_names = uniphier_pxs2_clock_reset_names,
         .nrsts = ARRAY_SIZE(uniphier_pxs2_clock_reset_names),
         .reset_names = uniphier_pxs2_clock_reset_names,
 };
 
-static const struct of_device_id uniphier_usb3_reset_match[] = {
+static const struct of_device_id uniphier_glue_reset_match[] = {
         {
                 .compatible = "socionext,uniphier-pro4-usb3-reset",
                 .data = &uniphier_pro4_data,
@@ -152,20 +152,32 @@ static const struct of_device_id uniphier_usb3_reset_match[] = {
                 .compatible = "socionext,uniphier-pxs3-usb3-reset",
                 .data = &uniphier_pxs2_data,
         },
+        {
+                .compatible = "socionext,uniphier-pro4-ahci-reset",
+                .data = &uniphier_pro4_data,
+        },
+        {
+                .compatible = "socionext,uniphier-pxs2-ahci-reset",
+                .data = &uniphier_pxs2_data,
+        },
+        {
+                .compatible = "socionext,uniphier-pxs3-ahci-reset",
+                .data = &uniphier_pxs2_data,
+        },
         { /* Sentinel */ }
 };
-MODULE_DEVICE_TABLE(of, uniphier_usb3_reset_match);
+MODULE_DEVICE_TABLE(of, uniphier_glue_reset_match);
 
-static struct platform_driver uniphier_usb3_reset_driver = {
-        .probe = uniphier_usb3_reset_probe,
-        .remove = uniphier_usb3_reset_remove,
+static struct platform_driver uniphier_glue_reset_driver = {
+        .probe = uniphier_glue_reset_probe,
+        .remove = uniphier_glue_reset_remove,
         .driver = {
-                .name = "uniphier-usb3-reset",
-                .of_match_table = uniphier_usb3_reset_match,
+                .name = "uniphier-glue-reset",
+                .of_match_table = uniphier_glue_reset_match,
         },
 };
-module_platform_driver(uniphier_usb3_reset_driver);
+module_platform_driver(uniphier_glue_reset_driver);
 
 MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
-MODULE_DESCRIPTION("UniPhier USB3 Reset Driver");
+MODULE_DESCRIPTION("UniPhier Glue layer reset driver");
 MODULE_LICENSE("GPL");