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path: root/drivers/pinctrl/pinctrl-exynos.c
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-rw-r--r--drivers/pinctrl/pinctrl-exynos.c579
1 files changed, 579 insertions, 0 deletions
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
new file mode 100644
index 000000000000..21362f48d370
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -0,0 +1,579 @@
1/*
2 * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2012 Linaro Ltd
7 * http://www.linaro.org
8 *
9 * Author: Thomas Abraham <thomas.ab@samsung.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This file contains the Samsung Exynos specific information required by the
17 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
18 * external gpio and wakeup interrupt support.
19 */
20
21#include <linux/module.h>
22#include <linux/device.h>
23#include <linux/interrupt.h>
24#include <linux/irqdomain.h>
25#include <linux/irq.h>
26#include <linux/of_irq.h>
27#include <linux/io.h>
28#include <linux/slab.h>
29#include <linux/err.h>
30
31#include <asm/mach/irq.h>
32
33#include "pinctrl-samsung.h"
34#include "pinctrl-exynos.h"
35
36/* list of external wakeup controllers supported */
37static const struct of_device_id exynos_wkup_irq_ids[] = {
38 { .compatible = "samsung,exynos4210-wakeup-eint", },
39};
40
41static void exynos_gpio_irq_unmask(struct irq_data *irqd)
42{
43 struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
44 struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
45 unsigned long reg_mask = d->ctrl->geint_mask + edata->eint_offset;
46 unsigned long mask;
47
48 mask = readl(d->virt_base + reg_mask);
49 mask &= ~(1 << edata->pin);
50 writel(mask, d->virt_base + reg_mask);
51}
52
53static void exynos_gpio_irq_mask(struct irq_data *irqd)
54{
55 struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
56 struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
57 unsigned long reg_mask = d->ctrl->geint_mask + edata->eint_offset;
58 unsigned long mask;
59
60 mask = readl(d->virt_base + reg_mask);
61 mask |= 1 << edata->pin;
62 writel(mask, d->virt_base + reg_mask);
63}
64
65static void exynos_gpio_irq_ack(struct irq_data *irqd)
66{
67 struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
68 struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
69 unsigned long reg_pend = d->ctrl->geint_pend + edata->eint_offset;
70
71 writel(1 << edata->pin, d->virt_base + reg_pend);
72}
73
74static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
75{
76 struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
77 struct samsung_pin_ctrl *ctrl = d->ctrl;
78 struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
79 struct samsung_pin_bank *bank = edata->bank;
80 unsigned int shift = EXYNOS_EINT_CON_LEN * edata->pin;
81 unsigned int con, trig_type;
82 unsigned long reg_con = ctrl->geint_con + edata->eint_offset;
83 unsigned int mask;
84
85 switch (type) {
86 case IRQ_TYPE_EDGE_RISING:
87 trig_type = EXYNOS_EINT_EDGE_RISING;
88 break;
89 case IRQ_TYPE_EDGE_FALLING:
90 trig_type = EXYNOS_EINT_EDGE_FALLING;
91 break;
92 case IRQ_TYPE_EDGE_BOTH:
93 trig_type = EXYNOS_EINT_EDGE_BOTH;
94 break;
95 case IRQ_TYPE_LEVEL_HIGH:
96 trig_type = EXYNOS_EINT_LEVEL_HIGH;
97 break;
98 case IRQ_TYPE_LEVEL_LOW:
99 trig_type = EXYNOS_EINT_LEVEL_LOW;
100 break;
101 default:
102 pr_err("unsupported external interrupt type\n");
103 return -EINVAL;
104 }
105
106 if (type & IRQ_TYPE_EDGE_BOTH)
107 __irq_set_handler_locked(irqd->irq, handle_edge_irq);
108 else
109 __irq_set_handler_locked(irqd->irq, handle_level_irq);
110
111 con = readl(d->virt_base + reg_con);
112 con &= ~(EXYNOS_EINT_CON_MASK << shift);
113 con |= trig_type << shift;
114 writel(con, d->virt_base + reg_con);
115
116 reg_con = bank->pctl_offset;
117 shift = edata->pin * bank->func_width;
118 mask = (1 << bank->func_width) - 1;
119
120 con = readl(d->virt_base + reg_con);
121 con &= ~(mask << shift);
122 con |= EXYNOS_EINT_FUNC << shift;
123 writel(con, d->virt_base + reg_con);
124
125 return 0;
126}
127
128/*
129 * irq_chip for gpio interrupts.
130 */
131static struct irq_chip exynos_gpio_irq_chip = {
132 .name = "exynos_gpio_irq_chip",
133 .irq_unmask = exynos_gpio_irq_unmask,
134 .irq_mask = exynos_gpio_irq_mask,
135 .irq_ack = exynos_gpio_irq_ack,
136 .irq_set_type = exynos_gpio_irq_set_type,
137};
138
139/*
140 * given a controller-local external gpio interrupt number, prepare the handler
141 * data for it.
142 */
143static struct exynos_geint_data *exynos_get_eint_data(irq_hw_number_t hw,
144 struct samsung_pinctrl_drv_data *d)
145{
146 struct samsung_pin_bank *bank = d->ctrl->pin_banks;
147 struct exynos_geint_data *eint_data;
148 unsigned int nr_banks = d->ctrl->nr_banks, idx;
149 unsigned int irq_base = 0, eint_offset = 0;
150
151 if (hw >= d->ctrl->nr_gint) {
152 dev_err(d->dev, "unsupported ext-gpio interrupt\n");
153 return NULL;
154 }
155
156 for (idx = 0; idx < nr_banks; idx++, bank++) {
157 if (bank->eint_type != EINT_TYPE_GPIO)
158 continue;
159 if ((hw >= irq_base) && (hw < (irq_base + bank->nr_pins)))
160 break;
161 irq_base += bank->nr_pins;
162 eint_offset += 4;
163 }
164
165 if (idx == nr_banks) {
166 dev_err(d->dev, "pin bank not found for ext-gpio interrupt\n");
167 return NULL;
168 }
169
170 eint_data = devm_kzalloc(d->dev, sizeof(*eint_data), GFP_KERNEL);
171 if (!eint_data) {
172 dev_err(d->dev, "no memory for eint-gpio data\n");
173 return NULL;
174 }
175
176 eint_data->bank = bank;
177 eint_data->pin = hw - irq_base;
178 eint_data->eint_offset = eint_offset;
179 return eint_data;
180}
181
182static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
183 irq_hw_number_t hw)
184{
185 struct samsung_pinctrl_drv_data *d = h->host_data;
186 struct exynos_geint_data *eint_data;
187
188 eint_data = exynos_get_eint_data(hw, d);
189 if (!eint_data)
190 return -EINVAL;
191
192 irq_set_handler_data(virq, eint_data);
193 irq_set_chip_data(virq, h->host_data);
194 irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip,
195 handle_level_irq);
196 set_irq_flags(virq, IRQF_VALID);
197 return 0;
198}
199
200static void exynos_gpio_irq_unmap(struct irq_domain *h, unsigned int virq)
201{
202 struct samsung_pinctrl_drv_data *d = h->host_data;
203 struct exynos_geint_data *eint_data;
204
205 eint_data = irq_get_handler_data(virq);
206 devm_kfree(d->dev, eint_data);
207}
208
209/*
210 * irq domain callbacks for external gpio interrupt controller.
211 */
212static const struct irq_domain_ops exynos_gpio_irqd_ops = {
213 .map = exynos_gpio_irq_map,
214 .unmap = exynos_gpio_irq_unmap,
215 .xlate = irq_domain_xlate_twocell,
216};
217
218static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
219{
220 struct samsung_pinctrl_drv_data *d = data;
221 struct samsung_pin_ctrl *ctrl = d->ctrl;
222 struct samsung_pin_bank *bank = ctrl->pin_banks;
223 unsigned int svc, group, pin, virq;
224
225 svc = readl(d->virt_base + ctrl->svc);
226 group = EXYNOS_SVC_GROUP(svc);
227 pin = svc & EXYNOS_SVC_NUM_MASK;
228
229 if (!group)
230 return IRQ_HANDLED;
231 bank += (group - 1);
232
233 virq = irq_linear_revmap(d->gpio_irqd, bank->irq_base + pin);
234 if (!virq)
235 return IRQ_NONE;
236 generic_handle_irq(virq);
237 return IRQ_HANDLED;
238}
239
240/*
241 * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
242 * @d: driver data of samsung pinctrl driver.
243 */
244static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
245{
246 struct device *dev = d->dev;
247 unsigned int ret;
248
249 if (!d->irq) {
250 dev_err(dev, "irq number not available\n");
251 return -EINVAL;
252 }
253
254 ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
255 0, dev_name(dev), d);
256 if (ret) {
257 dev_err(dev, "irq request failed\n");
258 return -ENXIO;
259 }
260
261 d->gpio_irqd = irq_domain_add_linear(dev->of_node, d->ctrl->nr_gint,
262 &exynos_gpio_irqd_ops, d);
263 if (!d->gpio_irqd) {
264 dev_err(dev, "gpio irq domain allocation failed\n");
265 return -ENXIO;
266 }
267
268 return 0;
269}
270
271static void exynos_wkup_irq_unmask(struct irq_data *irqd)
272{
273 struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
274 unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
275 unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
276 unsigned long reg_mask = d->ctrl->weint_mask + (bank << 2);
277 unsigned long mask;
278
279 mask = readl(d->virt_base + reg_mask);
280 mask &= ~(1 << pin);
281 writel(mask, d->virt_base + reg_mask);
282}
283
284static void exynos_wkup_irq_mask(struct irq_data *irqd)
285{
286 struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
287 unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
288 unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
289 unsigned long reg_mask = d->ctrl->weint_mask + (bank << 2);
290 unsigned long mask;
291
292 mask = readl(d->virt_base + reg_mask);
293 mask |= 1 << pin;
294 writel(mask, d->virt_base + reg_mask);
295}
296
297static void exynos_wkup_irq_ack(struct irq_data *irqd)
298{
299 struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
300 unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
301 unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
302 unsigned long pend = d->ctrl->weint_pend + (bank << 2);
303
304 writel(1 << pin, d->virt_base + pend);
305}
306
307static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
308{
309 struct samsung_pinctrl_drv_data *d = irq_data_get_irq_chip_data(irqd);
310 unsigned int bank = irqd->hwirq / EXYNOS_EINT_MAX_PER_BANK;
311 unsigned int pin = irqd->hwirq & (EXYNOS_EINT_MAX_PER_BANK - 1);
312 unsigned long reg_con = d->ctrl->weint_con + (bank << 2);
313 unsigned long shift = EXYNOS_EINT_CON_LEN * pin;
314 unsigned long con, trig_type;
315
316 switch (type) {
317 case IRQ_TYPE_EDGE_RISING:
318 trig_type = EXYNOS_EINT_EDGE_RISING;
319 break;
320 case IRQ_TYPE_EDGE_FALLING:
321 trig_type = EXYNOS_EINT_EDGE_FALLING;
322 break;
323 case IRQ_TYPE_EDGE_BOTH:
324 trig_type = EXYNOS_EINT_EDGE_BOTH;
325 break;
326 case IRQ_TYPE_LEVEL_HIGH:
327 trig_type = EXYNOS_EINT_LEVEL_HIGH;
328 break;
329 case IRQ_TYPE_LEVEL_LOW:
330 trig_type = EXYNOS_EINT_LEVEL_LOW;
331 break;
332 default:
333 pr_err("unsupported external interrupt type\n");
334 return -EINVAL;
335 }
336
337 if (type & IRQ_TYPE_EDGE_BOTH)
338 __irq_set_handler_locked(irqd->irq, handle_edge_irq);
339 else
340 __irq_set_handler_locked(irqd->irq, handle_level_irq);
341
342 con = readl(d->virt_base + reg_con);
343 con &= ~(EXYNOS_EINT_CON_MASK << shift);
344 con |= trig_type << shift;
345 writel(con, d->virt_base + reg_con);
346 return 0;
347}
348
349/*
350 * irq_chip for wakeup interrupts
351 */
352static struct irq_chip exynos_wkup_irq_chip = {
353 .name = "exynos_wkup_irq_chip",
354 .irq_unmask = exynos_wkup_irq_unmask,
355 .irq_mask = exynos_wkup_irq_mask,
356 .irq_ack = exynos_wkup_irq_ack,
357 .irq_set_type = exynos_wkup_irq_set_type,
358};
359
360/* interrupt handler for wakeup interrupts 0..15 */
361static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
362{
363 struct exynos_weint_data *eintd = irq_get_handler_data(irq);
364 struct irq_chip *chip = irq_get_chip(irq);
365 int eint_irq;
366
367 chained_irq_enter(chip, desc);
368 chip->irq_mask(&desc->irq_data);
369
370 if (chip->irq_ack)
371 chip->irq_ack(&desc->irq_data);
372
373 eint_irq = irq_linear_revmap(eintd->domain, eintd->irq);
374 generic_handle_irq(eint_irq);
375 chip->irq_unmask(&desc->irq_data);
376 chained_irq_exit(chip, desc);
377}
378
379static inline void exynos_irq_demux_eint(int irq_base, unsigned long pend,
380 struct irq_domain *domain)
381{
382 unsigned int irq;
383
384 while (pend) {
385 irq = fls(pend) - 1;
386 generic_handle_irq(irq_find_mapping(domain, irq_base + irq));
387 pend &= ~(1 << irq);
388 }
389}
390
391/* interrupt handler for wakeup interrupt 16 */
392static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
393{
394 struct irq_chip *chip = irq_get_chip(irq);
395 struct exynos_weint_data *eintd = irq_get_handler_data(irq);
396 struct samsung_pinctrl_drv_data *d = eintd->domain->host_data;
397 unsigned long pend;
398 unsigned long mask;
399
400 chained_irq_enter(chip, desc);
401 pend = readl(d->virt_base + d->ctrl->weint_pend + 0x8);
402 mask = readl(d->virt_base + d->ctrl->weint_mask + 0x8);
403 exynos_irq_demux_eint(16, pend & ~mask, eintd->domain);
404 pend = readl(d->virt_base + d->ctrl->weint_pend + 0xC);
405 mask = readl(d->virt_base + d->ctrl->weint_mask + 0xC);
406 exynos_irq_demux_eint(24, pend & ~mask, eintd->domain);
407 chained_irq_exit(chip, desc);
408}
409
410static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
411 irq_hw_number_t hw)
412{
413 irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip, handle_level_irq);
414 irq_set_chip_data(virq, h->host_data);
415 set_irq_flags(virq, IRQF_VALID);
416 return 0;
417}
418
419/*
420 * irq domain callbacks for external wakeup interrupt controller.
421 */
422static const struct irq_domain_ops exynos_wkup_irqd_ops = {
423 .map = exynos_wkup_irq_map,
424 .xlate = irq_domain_xlate_twocell,
425};
426
427/*
428 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
429 * @d: driver data of samsung pinctrl driver.
430 */
431static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
432{
433 struct device *dev = d->dev;
434 struct device_node *wkup_np = NULL;
435 struct device_node *np;
436 struct exynos_weint_data *weint_data;
437 int idx, irq;
438
439 for_each_child_of_node(dev->of_node, np) {
440 if (of_match_node(exynos_wkup_irq_ids, np)) {
441 wkup_np = np;
442 break;
443 }
444 }
445 if (!wkup_np)
446 return -ENODEV;
447
448 d->wkup_irqd = irq_domain_add_linear(wkup_np, d->ctrl->nr_wint,
449 &exynos_wkup_irqd_ops, d);
450 if (!d->wkup_irqd) {
451 dev_err(dev, "wakeup irq domain allocation failed\n");
452 return -ENXIO;
453 }
454
455 weint_data = devm_kzalloc(dev, sizeof(*weint_data) * 17, GFP_KERNEL);
456 if (!weint_data) {
457 dev_err(dev, "could not allocate memory for weint_data\n");
458 return -ENOMEM;
459 }
460
461 irq = irq_of_parse_and_map(wkup_np, 16);
462 if (irq) {
463 weint_data[16].domain = d->wkup_irqd;
464 irq_set_chained_handler(irq, exynos_irq_demux_eint16_31);
465 irq_set_handler_data(irq, &weint_data[16]);
466 } else {
467 dev_err(dev, "irq number for EINT16-32 not found\n");
468 }
469
470 for (idx = 0; idx < 16; idx++) {
471 weint_data[idx].domain = d->wkup_irqd;
472 weint_data[idx].irq = idx;
473
474 irq = irq_of_parse_and_map(wkup_np, idx);
475 if (irq) {
476 irq_set_handler_data(irq, &weint_data[idx]);
477 irq_set_chained_handler(irq, exynos_irq_eint0_15);
478 } else {
479 dev_err(dev, "irq number for eint-%x not found\n", idx);
480 }
481 }
482 return 0;
483}
484
485/* pin banks of exynos4210 pin-controller 0 */
486static struct samsung_pin_bank exynos4210_pin_banks0[] = {
487 EXYNOS_PIN_BANK_EINTG(0x000, EXYNOS4210_GPIO_A0, "gpa0"),
488 EXYNOS_PIN_BANK_EINTG(0x020, EXYNOS4210_GPIO_A1, "gpa1"),
489 EXYNOS_PIN_BANK_EINTG(0x040, EXYNOS4210_GPIO_B, "gpb"),
490 EXYNOS_PIN_BANK_EINTG(0x060, EXYNOS4210_GPIO_C0, "gpc0"),
491 EXYNOS_PIN_BANK_EINTG(0x080, EXYNOS4210_GPIO_C1, "gpc1"),
492 EXYNOS_PIN_BANK_EINTG(0x0A0, EXYNOS4210_GPIO_D0, "gpd0"),
493 EXYNOS_PIN_BANK_EINTG(0x0C0, EXYNOS4210_GPIO_D1, "gpd1"),
494 EXYNOS_PIN_BANK_EINTG(0x0E0, EXYNOS4210_GPIO_E0, "gpe0"),
495 EXYNOS_PIN_BANK_EINTG(0x100, EXYNOS4210_GPIO_E1, "gpe1"),
496 EXYNOS_PIN_BANK_EINTG(0x120, EXYNOS4210_GPIO_E2, "gpe2"),
497 EXYNOS_PIN_BANK_EINTG(0x140, EXYNOS4210_GPIO_E3, "gpe3"),
498 EXYNOS_PIN_BANK_EINTG(0x160, EXYNOS4210_GPIO_E4, "gpe4"),
499 EXYNOS_PIN_BANK_EINTG(0x180, EXYNOS4210_GPIO_F0, "gpf0"),
500 EXYNOS_PIN_BANK_EINTG(0x1A0, EXYNOS4210_GPIO_F1, "gpf1"),
501 EXYNOS_PIN_BANK_EINTG(0x1C0, EXYNOS4210_GPIO_F2, "gpf2"),
502 EXYNOS_PIN_BANK_EINTG(0x1E0, EXYNOS4210_GPIO_F3, "gpf3"),
503};
504
505/* pin banks of exynos4210 pin-controller 1 */
506static struct samsung_pin_bank exynos4210_pin_banks1[] = {
507 EXYNOS_PIN_BANK_EINTG(0x000, EXYNOS4210_GPIO_J0, "gpj0"),
508 EXYNOS_PIN_BANK_EINTG(0x020, EXYNOS4210_GPIO_J1, "gpj1"),
509 EXYNOS_PIN_BANK_EINTG(0x040, EXYNOS4210_GPIO_K0, "gpk0"),
510 EXYNOS_PIN_BANK_EINTG(0x060, EXYNOS4210_GPIO_K1, "gpk1"),
511 EXYNOS_PIN_BANK_EINTG(0x080, EXYNOS4210_GPIO_K2, "gpk2"),
512 EXYNOS_PIN_BANK_EINTG(0x0A0, EXYNOS4210_GPIO_K3, "gpk3"),
513 EXYNOS_PIN_BANK_EINTG(0x0C0, EXYNOS4210_GPIO_L0, "gpl0"),
514 EXYNOS_PIN_BANK_EINTG(0x0E0, EXYNOS4210_GPIO_L1, "gpl1"),
515 EXYNOS_PIN_BANK_EINTG(0x100, EXYNOS4210_GPIO_L2, "gpl2"),
516 EXYNOS_PIN_BANK_EINTN(0x120, EXYNOS4210_GPIO_Y0, "gpy0"),
517 EXYNOS_PIN_BANK_EINTN(0x140, EXYNOS4210_GPIO_Y1, "gpy1"),
518 EXYNOS_PIN_BANK_EINTN(0x160, EXYNOS4210_GPIO_Y2, "gpy2"),
519 EXYNOS_PIN_BANK_EINTN(0x180, EXYNOS4210_GPIO_Y3, "gpy3"),
520 EXYNOS_PIN_BANK_EINTN(0x1A0, EXYNOS4210_GPIO_Y4, "gpy4"),
521 EXYNOS_PIN_BANK_EINTN(0x1C0, EXYNOS4210_GPIO_Y5, "gpy5"),
522 EXYNOS_PIN_BANK_EINTN(0x1E0, EXYNOS4210_GPIO_Y6, "gpy6"),
523 EXYNOS_PIN_BANK_EINTN(0xC00, EXYNOS4210_GPIO_X0, "gpx0"),
524 EXYNOS_PIN_BANK_EINTN(0xC20, EXYNOS4210_GPIO_X1, "gpx1"),
525 EXYNOS_PIN_BANK_EINTN(0xC40, EXYNOS4210_GPIO_X2, "gpx2"),
526 EXYNOS_PIN_BANK_EINTN(0xC60, EXYNOS4210_GPIO_X3, "gpx3"),
527};
528
529/* pin banks of exynos4210 pin-controller 2 */
530static struct samsung_pin_bank exynos4210_pin_banks2[] = {
531 EXYNOS_PIN_BANK_EINTN(0x000, EXYNOS4210_GPIO_Z, "gpz"),
532};
533
534/*
535 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
536 * three gpio/pin-mux/pinconfig controllers.
537 */
538struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
539 {
540 /* pin-controller instance 0 data */
541 .pin_banks = exynos4210_pin_banks0,
542 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
543 .base = EXYNOS4210_GPIO_A0_START,
544 .nr_pins = EXYNOS4210_GPIOA_NR_PINS,
545 .nr_gint = EXYNOS4210_GPIOA_NR_GINT,
546 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
547 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
548 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
549 .svc = EXYNOS_SVC_OFFSET,
550 .eint_gpio_init = exynos_eint_gpio_init,
551 .label = "exynos4210-gpio-ctrl0",
552 }, {
553 /* pin-controller instance 1 data */
554 .pin_banks = exynos4210_pin_banks1,
555 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
556 .base = EXYNOS4210_GPIOA_NR_PINS,
557 .nr_pins = EXYNOS4210_GPIOB_NR_PINS,
558 .nr_gint = EXYNOS4210_GPIOB_NR_GINT,
559 .nr_wint = 32,
560 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
561 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
562 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
563 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
564 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
565 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
566 .svc = EXYNOS_SVC_OFFSET,
567 .eint_gpio_init = exynos_eint_gpio_init,
568 .eint_wkup_init = exynos_eint_wkup_init,
569 .label = "exynos4210-gpio-ctrl1",
570 }, {
571 /* pin-controller instance 2 data */
572 .pin_banks = exynos4210_pin_banks2,
573 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),
574 .base = EXYNOS4210_GPIOA_NR_PINS +
575 EXYNOS4210_GPIOB_NR_PINS,
576 .nr_pins = EXYNOS4210_GPIOC_NR_PINS,
577 .label = "exynos4210-gpio-ctrl2",
578 },
579};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 16:44:47 -0500